LLVM 19.0.0git
PPCSubtarget.cpp
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1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCSubtarget.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "PPCTargetMachine.h"
24#include "llvm/IR/Attributes.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/GlobalValue.h"
30#include <cstdlib>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "ppc-subtarget"
35
36#define GET_SUBTARGETINFO_TARGET_DESC
37#define GET_SUBTARGETINFO_CTOR
38#include "PPCGenSubtargetInfo.inc"
39
40static cl::opt<bool>
41 UseSubRegLiveness("ppc-track-subreg-liveness",
42 cl::desc("Enable subregister liveness tracking for PPC"),
43 cl::init(true), cl::Hidden);
44
45static cl::opt<bool>
46 EnableMachinePipeliner("ppc-enable-pipeliner",
47 cl::desc("Enable Machine Pipeliner for PPC"),
48 cl::init(false), cl::Hidden);
49
51 StringRef TuneCPU,
52 StringRef FS) {
53 initializeEnvironment();
54 initSubtargetFeatures(CPU, TuneCPU, FS);
55 return *this;
56}
57
58PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
59 const std::string &TuneCPU, const std::string &FS,
60 const PPCTargetMachine &TM)
61 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),
62 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
63 TargetTriple.getArch() == Triple::ppc64le),
64 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
65 InstrInfo(*this), TLInfo(TM, *this) {
67 Legalizer.reset(new PPCLegalizerInfo(*this));
68 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
69 RegBankInfo.reset(RBI);
70
72 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
73}
74
75void PPCSubtarget::initializeEnvironment() {
79}
80
81void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
82 StringRef FS) {
83 // Determine default and user specified characteristics
84 std::string CPUName = std::string(CPU);
85 if (CPUName.empty() || CPU == "generic") {
86 // If cross-compiling with -march=ppc64le without -mcpu
88 CPUName = "ppc64le";
90 CPUName = "e500";
91 else
92 CPUName = "generic";
93 }
94
95 // Determine the CPU to schedule for.
96 if (TuneCPU.empty()) TuneCPU = CPUName;
97
98 // Initialize scheduling itinerary for the specified CPU.
99 InstrItins = getInstrItineraryForCPU(CPUName);
100
101 // Parse features string.
102 ParseSubtargetFeatures(CPUName, TuneCPU, FS);
103
104 // If the user requested use of 64-bit regs, but the cpu selected doesn't
105 // support it, ignore.
106 if (IsPPC64 && has64BitSupport())
107 Use64BitRegs = true;
108
110 IsSecurePlt = true;
111
112 if (HasSPE && IsPPC64)
113 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
114 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
116 "SPE and traditional floating point cannot both be enabled.\n", false);
117
118 // If not SPE, set standard FPU
119 if (!HasSPE)
120 HasFPU = true;
121
123
124 // Determine endianness.
126
127 if (HasAIXSmallLocalExecTLS) {
128 if (!TargetTriple.isOSAIX() || !IsPPC64)
130 "The aix-small-local-exec-tls attribute is only supported on AIX in "
131 "64-bit mode.\n",
132 false);
133 // The aix-small-local-exec-tls attribute should only be used with
134 // -data-sections, as having data sections turned off with this option
135 // is not ideal for performance. Moreover, the small-local-exec-tls region
136 // is a limited resource, and should not be used for variables that may
137 // be replaced.
138 if (!TM.getDataSections())
140 "The aix-small-local-exec-tls attribute can only be specified with "
141 "-data-sections.\n",
142 false);
143 }
144}
145
146bool PPCSubtarget::enableMachineScheduler() const { return true; }
147
149 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
150}
151
152bool PPCSubtarget::useDFAforSMS() const { return false; }
153
154// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
155bool PPCSubtarget::enablePostRAScheduler() const { return true; }
156
157PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
158 return TargetSubtargetInfo::ANTIDEP_ALL;
159}
160
161void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
162 CriticalPathRCs.clear();
163 CriticalPathRCs.push_back(isPPC64() ?
164 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
165}
166
168 unsigned NumRegionInstrs) const {
169 // The GenericScheduler that we use defaults to scheduling bottom up only.
170 // We want to schedule from both the top and the bottom and so we set
171 // OnlyBottomUp to false.
172 // We want to do bi-directional scheduling since it provides a more balanced
173 // schedule leading to better performance.
174 Policy.OnlyBottomUp = false;
175 // Spilling is generally expensive on all PPC cores, so always enable
176 // register-pressure tracking.
177 Policy.ShouldTrackPressure = true;
178}
179
181 return true;
182}
183
185 return UseSubRegLiveness;
186}
187
189 // Large code model always uses the TOC even for local symbols.
191 return true;
192 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
193 return false;
194 return true;
195}
196
197bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
198bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
199
201 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
203}
204
205// GlobalISEL
207 return CallLoweringInfo.get();
208}
209
211 return RegBankInfo.get();
212}
213
215 return Legalizer.get();
216}
217
219 return InstSelector.get();
220}
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
static cl::opt< bool > UseSubRegLiveness("ppc-track-subreg-liveness", cl::desc("Enable subregister liveness tracking for PPC"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
const char LLVMTargetMachineRef TM
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:113
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
const CallLowering * getCallLowering() const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:112
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:101
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:146
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:96
AntiDepBreakMode getAntiDepBreakMode() const override
bool useAA() const override
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:188
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:155
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:103
bool enableMachineScheduler() const override
Scheduling customization.
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:152
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:110
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
bool getDataSections() const
Return true if data objects should be emitted into their own section, corresponds to -fdata-sections.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
SubArchType getSubArch() const
get the parsed subarchitecture type for this triple.
Definition: Triple.h:364
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:361
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:694
@ PPCSubArch_spe
Definition: Triple.h:158
bool isPPC32SecurePlt() const
Tests whether the target 32-bit PowerPC uses Secure PLT.
Definition: Triple.h:961
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.