LLVM  16.0.0git
PPCInstructionSelector.cpp
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1 //===- PPCInstructionSelector.cpp --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// PowerPC.
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
14 #include "PPCRegisterBankInfo.h"
15 #include "PPCSubtarget.h"
16 #include "PPCTargetMachine.h"
20 #include "llvm/IR/IntrinsicsPowerPC.h"
21 #include "llvm/Support/Debug.h"
22 
23 #define DEBUG_TYPE "ppc-gisel"
24 
25 using namespace llvm;
26 
27 namespace {
28 
29 #define GET_GLOBALISEL_PREDICATE_BITSET
30 #include "PPCGenGlobalISel.inc"
31 #undef GET_GLOBALISEL_PREDICATE_BITSET
32 
33 class PPCInstructionSelector : public InstructionSelector {
34 public:
35  PPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &STI,
36  const PPCRegisterBankInfo &RBI);
37 
38  bool select(MachineInstr &I) override;
39  static const char *getName() { return DEBUG_TYPE; }
40 
41 private:
42  /// tblgen generated 'select' implementation that is used as the initial
43  /// selector for the patterns that do not require complex C++.
44  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
45 
46  const PPCInstrInfo &TII;
47  const PPCRegisterInfo &TRI;
48  const PPCRegisterBankInfo &RBI;
49 
50 #define GET_GLOBALISEL_PREDICATES_DECL
51 #include "PPCGenGlobalISel.inc"
52 #undef GET_GLOBALISEL_PREDICATES_DECL
53 
54 #define GET_GLOBALISEL_TEMPORARIES_DECL
55 #include "PPCGenGlobalISel.inc"
56 #undef GET_GLOBALISEL_TEMPORARIES_DECL
57 };
58 
59 } // end anonymous namespace
60 
61 #define GET_GLOBALISEL_IMPL
62 #include "PPCGenGlobalISel.inc"
63 #undef GET_GLOBALISEL_IMPL
64 
65 PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,
66  const PPCSubtarget &STI,
67  const PPCRegisterBankInfo &RBI)
68  : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
70 #include "PPCGenGlobalISel.inc"
73 #include "PPCGenGlobalISel.inc"
75 {
76 }
77 
78 static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
79  if (RB->getID() == PPC::GPRRegBankID) {
80  if (Ty.getSizeInBits() == 64)
81  return &PPC::G8RCRegClass;
82  }
83  if (RB->getID() == PPC::FPRRegBankID) {
84  if (Ty.getSizeInBits() == 32)
85  return &PPC::F4RCRegClass;
86  if (Ty.getSizeInBits() == 64)
87  return &PPC::F8RCRegClass;
88  }
89 
90  llvm_unreachable("Unknown RegBank!");
91 }
92 
95  const RegisterBankInfo &RBI) {
96  Register DstReg = I.getOperand(0).getReg();
97 
98  if (DstReg.isPhysical())
99  return true;
100 
101  const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI);
102  const TargetRegisterClass *DstRC =
103  getRegClass(MRI.getType(DstReg), DstRegBank);
104 
105  // No need to constrain SrcReg. It will get constrained when we hit another of
106  // its use or its defs.
107  // Copies do not have constraints.
108  if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
109  LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
110  << " operand\n");
111  return false;
112  }
113 
114  return true;
115 }
116 
118  auto &MBB = *I.getParent();
119  auto &MF = *MBB.getParent();
120  auto &MRI = MF.getRegInfo();
121 
122  if (!isPreISelGenericOpcode(I.getOpcode())) {
123  if (I.isCopy())
124  return selectCopy(I, TII, MRI, TRI, RBI);
125 
126  return true;
127  }
128 
129  if (selectImpl(I, *CoverageInfo))
130  return true;
131  return false;
132 }
133 
134 namespace llvm {
137  const PPCSubtarget &Subtarget,
138  const PPCRegisterBankInfo &RBI) {
139  return new PPCInstructionSelector(TM, Subtarget, RBI);
140 }
141 } // end namespace llvm
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:20
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_PREDICATES_INIT
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:431
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:212
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
include
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRPrinter) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
Definition: CMakeLists.txt:1
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
PPCRegisterBankInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
PPCSubtarget.h
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
select
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C the select is being which prevents the dag combiner from turning select(load CPI1)
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
GET_GLOBALISEL_TEMPORARIES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
llvm::createPPCInstructionSelector
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
Definition: PPCInstructionSelector.cpp:136
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::RegisterBank::getID
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
llvm::RegisterBankInfo::constrainGenericRegister
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Definition: RegisterBankInfo.cpp:129
InstructionSelector.h
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
PPCInstrInfo.h
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
selectCopy
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Definition: PPCInstructionSelector.cpp:93
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
DEBUG_TYPE
#define DEBUG_TYPE
Definition: PPCInstructionSelector.cpp:23
InstructionSelectorImpl.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
getRegClass
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
Definition: AArch64InstrInfo.cpp:3228
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::PPCRegisterBankInfo
Definition: PPCRegisterBankInfo.h:61
MachineFunction.h
llvm::mca::selectImpl
static uint64_t selectImpl(uint64_t CandidateMask, uint64_t &NextInSequenceMask)
Definition: ResourceManager.cpp:26
Debug.h
PPCTargetMachine.h
llvm::LLT
Definition: LowLevelTypeImpl.h:39