LLVM  14.0.0git
PPCSubtarget.h
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1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
25 #include "llvm/IR/DataLayout.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
31 
32 // GCC #defines PPC on Linux but we use it as our namespace name
33 #undef PPC
34 
35 namespace llvm {
36 class StringRef;
37 
38 namespace PPC {
39  // -m directive values.
40 enum {
66 };
67 }
68 
69 class GlobalValue;
70 
72 public:
73  enum POPCNTDKind {
77  };
78 
79 protected:
80  /// TargetTriple - What processor and OS we're targeting.
82 
83  /// stackAlignment - The minimum alignment known to hold of the stack frame on
84  /// entry to the function and which must be maintained by every function.
86 
87  /// Selected instruction itineraries (one entry per itinerary class.)
89 
90  /// Which cpu directive was used.
91  unsigned CPUDirective;
92 
93  /// Used by the ISel to turn in optimizations for POWER4-derived architectures
94  bool HasMFOCRF;
97  bool UseCRBits;
99  bool IsPPC64;
101  bool HasFPU;
102  bool HasSPE;
103  bool HasEFPU2;
104  bool HasVSX;
114  bool HasMMA;
117  bool HasFCPSGN;
118  bool HasFSQRT;
121  bool HasSTFIWX;
122  bool HasLFIWAX;
123  bool HasFPRND;
124  bool HasFPCVT;
125  bool HasISEL;
126  bool HasBPERMD;
127  bool HasExtDiv;
128  bool HasCMPB;
129  bool HasLDBRX;
130  bool IsBookE;
132  bool IsE500;
133  bool IsPPC4xx;
134  bool IsPPC6xx;
139  bool HasICBT;
144  bool HasHTM;
146  bool HasFusion;
150  bool IsISA2_07;
151  bool IsISA3_0;
152  bool IsISA3_1;
154  bool SecurePlt;
161  bool IsAIX;
162 
164 
170 
171  /// GlobalISel related APIs.
172  std::unique_ptr<CallLowering> CallLoweringInfo;
173  std::unique_ptr<LegalizerInfo> Legalizer;
174  std::unique_ptr<RegisterBankInfo> RegBankInfo;
175  std::unique_ptr<InstructionSelector> InstSelector;
176 
177 public:
178  /// This constructor initializes the data members to match that
179  /// of the specified triple.
180  ///
181  PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
182  const PPCTargetMachine &TM);
183 
184  /// ParseSubtargetFeatures - Parses features string setting specified
185  /// subtarget options. Definition of function is auto generated by tblgen.
187 
188  /// getStackAlignment - Returns the minimum alignment known to hold of the
189  /// stack frame on entry to the function and which must be maintained by every
190  /// function for this subtarget.
192 
193  /// getCPUDirective - Returns the -m directive specified for the cpu.
194  ///
195  unsigned getCPUDirective() const { return CPUDirective; }
196 
197  /// getInstrItins - Return the instruction itineraries based on subtarget
198  /// selection.
199  const InstrItineraryData *getInstrItineraryData() const override {
200  return &InstrItins;
201  }
202 
203  const PPCFrameLowering *getFrameLowering() const override {
204  return &FrameLowering;
205  }
206  const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
207  const PPCTargetLowering *getTargetLowering() const override {
208  return &TLInfo;
209  }
210  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
211  return &TSInfo;
212  }
213  const PPCRegisterInfo *getRegisterInfo() const override {
214  return &getInstrInfo()->getRegisterInfo();
215  }
216  const PPCTargetMachine &getTargetMachine() const { return TM; }
217 
218  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
219  /// so that we can use initializer lists for subtarget initialization.
221 
222 private:
223  void initializeEnvironment();
224  void initSubtargetFeatures(StringRef CPU, StringRef FS);
225 
226 public:
227  /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
228  ///
229  bool isPPC64() const;
230 
231  /// has64BitSupport - Return true if the selected CPU supports 64-bit
232  /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
233  bool has64BitSupport() const { return Has64BitSupport; }
234  // useSoftFloat - Return true if soft-float option is turned on.
235  bool useSoftFloat() const {
236  if (isAIXABI() && !HasHardFloat)
237  report_fatal_error("soft-float is not yet supported on AIX.");
238  return !HasHardFloat;
239  }
240 
241  /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
242  /// registers in 32-bit mode when possible. This can only true if
243  /// has64BitSupport() returns true.
244  bool use64BitRegs() const { return Use64BitRegs; }
245 
246  /// useCRBits - Return true if we should store and manipulate i1 values in
247  /// the individual condition register bits.
248  bool useCRBits() const { return UseCRBits; }
249 
250  // isLittleEndian - True if generating little-endian code
251  bool isLittleEndian() const { return IsLittleEndian; }
252 
253  // Specific obvious features.
254  bool hasFCPSGN() const { return HasFCPSGN; }
255  bool hasFSQRT() const { return HasFSQRT; }
256  bool hasFRE() const { return HasFRE; }
257  bool hasFRES() const { return HasFRES; }
258  bool hasFRSQRTE() const { return HasFRSQRTE; }
259  bool hasFRSQRTES() const { return HasFRSQRTES; }
260  bool hasRecipPrec() const { return HasRecipPrec; }
261  bool hasSTFIWX() const { return HasSTFIWX; }
262  bool hasLFIWAX() const { return HasLFIWAX; }
263  bool hasFPRND() const { return HasFPRND; }
264  bool hasFPCVT() const { return HasFPCVT; }
265  bool hasAltivec() const { return HasAltivec; }
266  bool hasSPE() const { return HasSPE; }
267  bool hasEFPU2() const { return HasEFPU2; }
268  bool hasFPU() const { return HasFPU; }
269  bool hasVSX() const { return HasVSX; }
270  bool needsTwoConstNR() const { return NeedsTwoConstNR; }
271  bool hasP8Vector() const { return HasP8Vector; }
272  bool hasP8Altivec() const { return HasP8Altivec; }
273  bool hasP8Crypto() const { return HasP8Crypto; }
274  bool hasP9Vector() const { return HasP9Vector; }
275  bool hasP9Altivec() const { return HasP9Altivec; }
276  bool hasP10Vector() const { return HasP10Vector; }
277  bool hasPrefixInstrs() const { return HasPrefixInstrs; }
278  bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
279  bool hasMMA() const { return HasMMA; }
280  bool hasROPProtect() const { return HasROPProtect; }
281  bool hasPrivileged() const { return HasPrivileged; }
282  bool pairedVectorMemops() const { return PairedVectorMemops; }
283  bool hasMFOCRF() const { return HasMFOCRF; }
284  bool hasISEL() const { return HasISEL; }
285  bool hasBPERMD() const { return HasBPERMD; }
286  bool hasExtDiv() const { return HasExtDiv; }
287  bool hasCMPB() const { return HasCMPB; }
288  bool hasLDBRX() const { return HasLDBRX; }
289  bool isBookE() const { return IsBookE; }
290  bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
291  bool isPPC4xx() const { return IsPPC4xx; }
292  bool isPPC6xx() const { return IsPPC6xx; }
293  bool isSecurePlt() const {return SecurePlt; }
294  bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
295  bool isE500() const { return IsE500; }
296  bool isFeatureMFTB() const { return FeatureMFTB; }
298  bool isDeprecatedDST() const { return DeprecatedDST; }
299  bool hasICBT() const { return HasICBT; }
302  }
305  bool hasPartwordAtomics() const { return HasPartwordAtomics; }
306  bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
307  bool hasDirectMove() const { return HasDirectMove; }
308 
310  return Align(16);
311  }
312 
313  unsigned getRedZoneSize() const {
314  if (isPPC64())
315  // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
316  return 288;
317 
318  // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
319  // PPC32 SVR4ABI has no redzone.
320  return isAIXABI() ? 220 : 0;
321  }
322 
323  bool hasHTM() const { return HasHTM; }
324  bool hasFloat128() const { return HasFloat128; }
325  bool isISA2_07() const { return IsISA2_07; }
326  bool isISA3_0() const { return IsISA3_0; }
327  bool isISA3_1() const { return IsISA3_1; }
328  bool useLongCalls() const { return UseLongCalls; }
329  bool hasFusion() const { return HasFusion; }
330  bool hasStoreFusion() const { return HasStoreFusion; }
331  bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
332  bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
333  bool needsSwapsForVSXMemOps() const {
334  return hasVSX() && isLittleEndian() && !hasP9Vector();
335  }
336 
337  POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
338 
339  const Triple &getTargetTriple() const { return TargetTriple; }
340 
341  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
342  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
343  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
344 
345  bool isAIXABI() const { return TargetTriple.isOSAIX(); }
346  bool isSVR4ABI() const { return !isAIXABI(); }
347  bool isELFv2ABI() const;
348 
349  bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
350  bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
351  bool isUsingPCRelativeCalls() const;
352 
353  /// Originally, this function return hasISEL(). Now we always enable it,
354  /// but may expand the ISEL instruction later.
355  bool enableEarlyIfConversion() const override { return true; }
356 
357  /// Scheduling customization.
358  bool enableMachineScheduler() const override;
359  /// Pipeliner customization.
360  bool enableMachinePipeliner() const override;
361  /// Machine Pipeliner customization
362  bool useDFAforSMS() const override;
363  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
364  bool enablePostRAScheduler() const override;
365  AntiDepBreakMode getAntiDepBreakMode() const override;
366  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
367 
369  unsigned NumRegionInstrs) const override;
370  bool useAA() const override;
371 
372  bool enableSubRegLiveness() const override;
373 
374  /// True if the GV will be accessed via an indirect symbol.
375  bool isGVIndirectSymbol(const GlobalValue *GV) const;
376 
377  /// True if the ABI is descriptor based.
378  bool usesFunctionDescriptors() const {
379  // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
380  // v1 ABI uses descriptors.
381  return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
382  }
383 
384  unsigned descriptorTOCAnchorOffset() const {
386  "Should only be called when the target uses descriptors.");
387  return IsPPC64 ? 8 : 4;
388  }
389 
392  "Should only be called when the target uses descriptors.");
393  return IsPPC64 ? 16 : 8;
394  }
395 
398  "Should only be called when the target uses descriptors.");
399  return IsPPC64 ? PPC::X11 : PPC::R11;
400  }
401 
403  assert((is64BitELFABI() || isAIXABI()) &&
404  "Should only be called when the target is a TOC based ABI.");
405  return IsPPC64 ? PPC::X2 : PPC::R2;
406  }
407 
409  return IsPPC64 ? PPC::X1 : PPC::R1;
410  }
411 
412  bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
413 
416  }
417 
418  // Select allocation orders of GPRC and G8RC. It should be strictly consistent
419  // with corresponding AltOrders in PPCRegisterInfo.td.
420  unsigned getGPRAllocationOrderIdx() const {
421  if (is64BitELFABI())
422  return 1;
423  if (isAIXABI())
424  return 2;
425  return 0;
426  }
427 
428  // GlobalISEL
429  const CallLowering *getCallLowering() const override;
430  const RegisterBankInfo *getRegBankInfo() const override;
431  const LegalizerInfo *getLegalizerInfo() const override;
433 };
434 } // End llvm namespace
435 
436 #endif
llvm::PPCSubtarget::AllowsUnalignedFPAccess
bool AllowsUnalignedFPAccess
Definition: PPCSubtarget.h:136
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
llvm::PPC::DIR_PWR7
@ DIR_PWR7
Definition: PPCSubtarget.h:60
llvm::PPCSubtarget::PPCSubtarget
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
Definition: PPCSubtarget.cpp:54
llvm::PPCSubtarget::useCRBits
bool useCRBits() const
useCRBits - Return true if we should store and manipulate i1 values in the individual condition regis...
Definition: PPCSubtarget.h:248
llvm::PPCSubtarget::isE500
bool isE500() const
Definition: PPCSubtarget.h:295
llvm::PPCSubtarget::hasRecipPrec
bool hasRecipPrec() const
Definition: PPCSubtarget.h:260
llvm::PPCSubtarget::hasFloat128
bool hasFloat128() const
Definition: PPCSubtarget.h:324
llvm::PPCSubtarget::hasPOPCNTD
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:337
llvm::PPCSubtarget::IsISA2_07
bool IsISA2_07
Definition: PPCSubtarget.h:150
llvm::PPCSubtarget::isSecurePlt
bool isSecurePlt() const
Definition: PPCSubtarget.h:293
llvm::PPCSubtarget::getRegisterInfo
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:213
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::PPCSubtarget::TSInfo
SelectionDAGTargetInfo TSInfo
Definition: PPCSubtarget.h:169
llvm::PPCSubtarget::usesFunctionDescriptors
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
Definition: PPCSubtarget.h:378
llvm::PPCSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: PPCSubtarget.cpp:255
llvm::PPCSubtarget::hasPrefixInstrs
bool hasPrefixInstrs() const
Definition: PPCSubtarget.h:277
llvm::PPCSubtarget::HasExtDiv
bool HasExtDiv
Definition: PPCSubtarget.h:127
llvm::PPCSubtarget::hasAddisLoadFusion
bool hasAddisLoadFusion() const
Definition: PPCSubtarget.h:332
CallLowering.h
llvm::PPCSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
llvm::PPCSubtarget::getPlatformStackAlignment
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:309
llvm::PPCSubtarget::HasISEL
bool HasISEL
Definition: PPCSubtarget.h:125
llvm::PPCSubtarget::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Definition: PPCSubtarget.h:159
llvm::PPCSubtarget::hasMMA
bool hasMMA() const
Definition: PPCSubtarget.h:279
llvm::PPCSubtarget::HasLFIWAX
bool HasLFIWAX
Definition: PPCSubtarget.h:122
llvm::PPCSubtarget::HasDirectMove
bool HasDirectMove
Definition: PPCSubtarget.h:143
llvm::PPCSubtarget::HasInvariantFunctionDescriptors
bool HasInvariantFunctionDescriptors
Definition: PPCSubtarget.h:140
llvm::PPC::DIR_A2
@ DIR_A2
Definition: PPCSubtarget.h:50
llvm::PPC::DIR_601
@ DIR_601
Definition: PPCSubtarget.h:44
llvm::PPCSubtarget::HasROPProtect
bool HasROPProtect
Definition: PPCSubtarget.h:115
llvm::PPCSubtarget::POPCNTDKind
POPCNTDKind
Definition: PPCSubtarget.h:73
llvm::PPCSubtarget::hasP8Vector
bool hasP8Vector() const
Definition: PPCSubtarget.h:271
llvm::PPCSubtarget::isLittleEndian
bool isLittleEndian() const
Definition: PPCSubtarget.h:251
llvm::PPCSubtarget::hasROPProtect
bool hasROPProtect() const
Definition: PPCSubtarget.h:280
RegisterBankInfo.h
llvm::PPCSubtarget::getFrameLowering
const PPCFrameLowering * getFrameLowering() const override
Definition: PPCSubtarget.h:203
llvm::PPCSubtarget::hasVSX
bool hasVSX() const
Definition: PPCSubtarget.h:269
llvm::PPCSubtarget::isISA2_07
bool isISA2_07() const
Definition: PPCSubtarget.h:325
llvm::PPCSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: PPCSubtarget.h:339
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::PPC::DIR_PWR10
@ DIR_PWR10
Definition: PPCSubtarget.h:63
llvm::PPC::DIR_PWR5X
@ DIR_PWR5X
Definition: PPCSubtarget.h:57
llvm::PPCSubtarget::hasP9Vector
bool hasP9Vector() const
Definition: PPCSubtarget.h:274
llvm::PPCSubtarget::HasAltivec
bool HasAltivec
Definition: PPCSubtarget.h:100
llvm::PPCSubtarget::DeprecatedDST
bool DeprecatedDST
Definition: PPCSubtarget.h:137
llvm::PPCSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: PPCSubtarget.cpp:251
llvm::PPC::DIR_32
@ DIR_32
Definition: PPCSubtarget.h:42
llvm::PPCSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Scheduling customization.
Definition: PPCSubtarget.cpp:191
llvm::PPCSubtarget::hasBPERMD
bool hasBPERMD() const
Definition: PPCSubtarget.h:285
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:595
llvm::PPCSubtarget::getTargetMachine
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:216
llvm::PPCSubtarget::needsTwoConstNR
bool needsTwoConstNR() const
Definition: PPCSubtarget.h:270
llvm::PPCSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: PPCSubtarget.cpp:259
llvm::PPC::DIR_PWR6X
@ DIR_PWR6X
Definition: PPCSubtarget.h:59
llvm::PPCSubtarget::VectorsUseTwoUnits
bool VectorsUseTwoUnits
Definition: PPCSubtarget.h:155
llvm::PPCSubtarget::HasPrefixInstrs
bool HasPrefixInstrs
Definition: PPCSubtarget.h:112
llvm::PPCSubtarget::vectorsUseTwoUnits
bool vectorsUseTwoUnits() const
Definition: PPCSubtarget.h:294
llvm::PPCSubtarget::HasLDBRX
bool HasLDBRX
Definition: PPCSubtarget.h:129
llvm::PPCSubtarget::useAA
bool useAA() const override
Definition: PPCSubtarget.cpp:225
llvm::PPCSubtarget::hasFSQRT
bool hasFSQRT() const
Definition: PPCSubtarget.h:255
llvm::PPCSubtarget::getStackPointerRegister
MCRegister getStackPointerRegister() const
Definition: PPCSubtarget.h:408
llvm::PPCSubtarget::hasFRSQRTES
bool hasFRSQRTES() const
Definition: PPCSubtarget.h:259
llvm::PPCSubtarget::usePPCPostRASchedStrategy
bool usePPCPostRASchedStrategy() const
Definition: PPCSubtarget.h:304
LegalizerInfo.h
llvm::PPCSubtarget::is64BitELFABI
bool is64BitELFABI() const
Definition: PPCSubtarget.h:349
llvm::PPCSubtarget::HasFCPSGN
bool HasFCPSGN
Definition: PPCSubtarget.h:117
llvm::PPCSubtarget::hasPCRelativeMemops
bool hasPCRelativeMemops() const
Definition: PPCSubtarget.h:278
llvm::PPCSubtarget::HasVSX
bool HasVSX
Definition: PPCSubtarget.h:104
llvm::PPCSubtarget::HasPCRelativeMemops
bool HasPCRelativeMemops
Definition: PPCSubtarget.h:113
llvm::PPCSubtarget::IsBookE
bool IsBookE
Definition: PPCSubtarget.h:130
llvm::PPC::DIR_440
@ DIR_440
Definition: PPCSubtarget.h:43
llvm::PPCSubtarget::hasP8Altivec
bool hasP8Altivec() const
Definition: PPCSubtarget.h:272
llvm::PPCSubtarget::TM
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:165
R2
#define R2(n)
llvm::PPCSubtarget::HasFSQRT
bool HasFSQRT
Definition: PPCSubtarget.h:118
MCInstrItineraries.h
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:632
llvm::PPCSubtarget::HasSTFIWX
bool HasSTFIWX
Definition: PPCSubtarget.h:121
llvm::PPCSubtarget::hasFPRND
bool hasFPRND() const
Definition: PPCSubtarget.h:263
llvm::PPCSubtarget::FeatureMFTB
bool FeatureMFTB
Definition: PPCSubtarget.h:135
llvm::PPCSubtarget::CPUDirective
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:91
llvm::PPCSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
llvm::PPCSubtarget::hasFRES
bool hasFRES() const
Definition: PPCSubtarget.h:257
llvm::PPCSubtarget::HasFRE
bool HasFRE
Definition: PPCSubtarget.h:119
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCSubtarget::getTOCPointerRegister
MCRegister getTOCPointerRegister() const
Definition: PPCSubtarget.h:402
llvm::PPCSubtarget::isTargetELF
bool isTargetELF() const
Definition: PPCSubtarget.h:341
llvm::PPCSubtarget::IsE500
bool IsE500
Definition: PPCSubtarget.h:132
llvm::PPCFrameLowering
Definition: PPCFrameLowering.h:22
llvm::PPCSubtarget::isPPC4xx
bool isPPC4xx() const
Definition: PPCSubtarget.h:291
llvm::PPCSubtarget::HasBPERMD
bool HasBPERMD
Definition: PPCSubtarget.h:126
llvm::PPCSubtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: PPCSubtarget.cpp:212
llvm::PPCSubtarget::TLInfo
PPCTargetLowering TLInfo
Definition: PPCSubtarget.h:168
llvm::PPCSubtarget::isISA3_1
bool isISA3_1() const
Definition: PPCSubtarget.h:327
llvm::PPC::DIR_7400
@ DIR_7400
Definition: PPCSubtarget.h:47
llvm::PPCSubtarget::HasAddisLoadFusion
bool HasAddisLoadFusion
Definition: PPCSubtarget.h:149
llvm::PPCSubtarget::hasFPCVT
bool hasFPCVT() const
Definition: PPCSubtarget.h:264
llvm::PPCSubtarget::isISA3_0
bool isISA3_0() const
Definition: PPCSubtarget.h:326
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::PPCSubtarget::HasFPU
bool HasFPU
Definition: PPCSubtarget.h:101
llvm::PPCSubtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: PPCSubtarget.h:173
llvm::PPCSubtarget::hasEFPU2
bool hasEFPU2() const
Definition: PPCSubtarget.h:267
llvm::PPCSubtarget::isPPC6xx
bool isPPC6xx() const
Definition: PPCSubtarget.h:292
PPCFrameLowering.h
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:645
llvm::PPCSubtarget::hasHTM
bool hasHTM() const
Definition: PPCSubtarget.h:323
llvm::PPCSubtarget::descriptorTOCAnchorOffset
unsigned descriptorTOCAnchorOffset() const
Definition: PPCSubtarget.h:384
llvm::PPCSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
Definition: PPCSubtarget.cpp:200
llvm::PPCSubtarget::isPPC64
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Definition: PPCSubtarget.cpp:243
llvm::PPC::DIR_PWR4
@ DIR_PWR4
Definition: PPCSubtarget.h:55
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::PPC::DIR_PWR9
@ DIR_PWR9
Definition: PPCSubtarget.h:62
llvm::PPCSubtarget::HasFPRND
bool HasFPRND
Definition: PPCSubtarget.h:123
llvm::PPCSubtarget::hasPartwordAtomics
bool hasPartwordAtomics() const
Definition: PPCSubtarget.h:305
llvm::PPC::DIR_E500
@ DIR_E500
Definition: PPCSubtarget.h:51
llvm::PPCSubtarget::getRedZoneSize
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:313
llvm::PPCSubtarget::HasP8Crypto
bool HasP8Crypto
Definition: PPCSubtarget.h:108
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::PPCSubtarget::getInstrInfo
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:206
llvm::PPCSubtarget::UseLongCalls
bool UseLongCalls
Definition: PPCSubtarget.h:153
llvm::PPC::DIR_603
@ DIR_603
Definition: PPCSubtarget.h:46
llvm::PPCSubtarget::IsLittleEndian
bool IsLittleEndian
Definition: PPCSubtarget.h:138
llvm::PPCSubtarget::usePPCPreRASchedStrategy
bool usePPCPreRASchedStrategy() const
Definition: PPCSubtarget.h:303
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::Triple::isOSAIX
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:627
llvm::PPCSubtarget::hasFCPSGN
bool hasFCPSGN() const
Definition: PPCSubtarget.h:254
llvm::PPCSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::PPC::DIR_PWR_FUTURE
@ DIR_PWR_FUTURE
Definition: PPCSubtarget.h:64
llvm::PPCSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: PPCSubtarget.cpp:233
llvm::PPCSubtarget::hasOnlyMSYNC
bool hasOnlyMSYNC() const
Definition: PPCSubtarget.h:290
PPCGenSubtargetInfo
llvm::PPCSubtarget::isAIXABI
bool isAIXABI() const
Definition: PPCSubtarget.h:345
llvm::PPCSubtarget::hasLDBRX
bool hasLDBRX() const
Definition: PPCSubtarget.h:288
llvm::PPCSubtarget::isSVR4ABI
bool isSVR4ABI() const
Definition: PPCSubtarget.h:346
llvm::PPCSubtarget::hasMFOCRF
bool hasMFOCRF() const
Definition: PPCSubtarget.h:283
llvm::PPCSubtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: PPCSubtarget.h:210
llvm::PPCSubtarget::UsePPCPreRASchedStrategy
bool UsePPCPreRASchedStrategy
Definition: PPCSubtarget.h:156
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::PPCSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: PPCSubtarget.h:343
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::PPCSubtarget::HasMFOCRF
bool HasMFOCRF
Used by the ISel to turn in optimizations for POWER4-derived architectures.
Definition: PPCSubtarget.h:94
llvm::PPCSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: PPCSubtarget.cpp:229
llvm::PPCSubtarget::IsPPC6xx
bool IsPPC6xx
Definition: PPCSubtarget.h:134
llvm::PPCSubtarget::POPCNTD_Unavailable
@ POPCNTD_Unavailable
Definition: PPCSubtarget.h:74
llvm::PPCSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:174
llvm::PPCSubtarget::useDFAforSMS
bool useDFAforSMS() const override
Machine Pipeliner customization.
Definition: PPCSubtarget.cpp:197
llvm::PPCSubtarget::HasFRES
bool HasFRES
Definition: PPCSubtarget.h:119
llvm::PPCSubtarget::hasP9Altivec
bool hasP9Altivec() const
Definition: PPCSubtarget.h:275
llvm::PPCSubtarget::InstrInfo
PPCInstrInfo InstrInfo
Definition: PPCSubtarget.h:167
llvm::PPCSubtarget::HasQuadwordAtomics
bool HasQuadwordAtomics
Definition: PPCSubtarget.h:142
llvm::PPCSubtarget::is32BitELFABI
bool is32BitELFABI() const
Definition: PPCSubtarget.h:350
llvm::PPCSubtarget::needsSwapsForVSXMemOps
bool needsSwapsForVSXMemOps() const
Definition: PPCSubtarget.h:333
llvm::PPCSubtarget::IsPPC4xx
bool IsPPC4xx
Definition: PPCSubtarget.h:133
PPCInstrInfo.h
llvm::PPCSubtarget::HasFRSQRTES
bool HasFRSQRTES
Definition: PPCSubtarget.h:119
llvm::PPCSubtarget::hasSTFIWX
bool hasSTFIWX() const
Definition: PPCSubtarget.h:261
llvm::PPC::DIR_NONE
@ DIR_NONE
Definition: PPCSubtarget.h:41
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::PPCSubtarget::StackAlignment
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
llvm::PPCSubtarget::HasMMA
bool HasMMA
Definition: PPCSubtarget.h:114
llvm::PPC::DIR_602
@ DIR_602
Definition: PPCSubtarget.h:45
llvm::PPCSubtarget::hasExtDiv
bool hasExtDiv() const
Definition: PPCSubtarget.h:286
llvm::PPCSubtarget::HasOnlyMSYNC
bool HasOnlyMSYNC
Definition: PPCSubtarget.h:131
llvm::PPCSubtarget::HasP8Vector
bool HasP8Vector
Definition: PPCSubtarget.h:106
llvm::PPCSubtarget::IsPPC64
bool IsPPC64
Definition: PPCSubtarget.h:99
llvm::PPCSubtarget::isPredictableSelectIsExpensive
bool isPredictableSelectIsExpensive() const
Definition: PPCSubtarget.h:414
llvm::PPCSubtarget::FrameLowering
PPCFrameLowering FrameLowering
Definition: PPCSubtarget.h:166
llvm::PPC::DIR_PWR3
@ DIR_PWR3
Definition: PPCSubtarget.h:54
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::PPCSubtarget::HasRecipPrec
bool HasRecipPrec
Definition: PPCSubtarget.h:120
llvm::PPC::DIR_750
@ DIR_750
Definition: PPCSubtarget.h:48
llvm::PPCSubtarget::HasP9Altivec
bool HasP9Altivec
Definition: PPCSubtarget.h:110
llvm::PPCTargetLowering
Definition: PPCISelLowering.h:719
llvm::PPCSubtarget::hasP8Crypto
bool hasP8Crypto() const
Definition: PPCSubtarget.h:273
llvm::PPCSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: PPCSubtarget.h:199
llvm::PPC::DIR_PWR5
@ DIR_PWR5
Definition: PPCSubtarget.h:56
Triple.h
llvm::PPCSubtarget::hasDirectMove
bool hasDirectMove() const
Definition: PPCSubtarget.h:307
llvm::PPCSubtarget::hasStoreFusion
bool hasStoreFusion() const
Definition: PPCSubtarget.h:330
llvm::PPCSubtarget::HasAddiLoadFusion
bool HasAddiLoadFusion
Definition: PPCSubtarget.h:148
llvm::PPCSubtarget::hasFRE
bool hasFRE() const
Definition: PPCSubtarget.h:256
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::PPCSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:175
llvm::PPCSubtarget::getStackAlignment
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: PPCSubtarget.h:191
llvm::PPCSubtarget::hasFPU
bool hasFPU() const
Definition: PPCSubtarget.h:268
llvm::PPCSubtarget::HasFPCVT
bool HasFPCVT
Definition: PPCSubtarget.h:124
TargetSubtargetInfo.h
llvm::PPCSubtarget::has64BitSupport
bool has64BitSupport() const
has64BitSupport - Return true if the selected CPU supports 64-bit instructions, regardless of whether...
Definition: PPCSubtarget.h:233
llvm::PPCSubtarget::IsISA3_1
bool IsISA3_1
Definition: PPCSubtarget.h:152
llvm::PPCSubtarget::HasICBT
bool HasICBT
Definition: PPCSubtarget.h:139
llvm::PPCSubtarget::Use64BitRegs
bool Use64BitRegs
Definition: PPCSubtarget.h:96
llvm::PPCSubtarget::PairedVectorMemops
bool PairedVectorMemops
Definition: PPCSubtarget.h:158
llvm::PPCSubtarget::getAntiDepBreakMode
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: PPCSubtarget.cpp:202
llvm::PPCSubtarget::HasPOPCNTD
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:163
llvm::PPC::DIR_64
@ DIR_64
Definition: PPCSubtarget.h:65
llvm::PPCSubtarget::HasPartwordAtomics
bool HasPartwordAtomics
Definition: PPCSubtarget.h:141
llvm::PPCSubtarget::Has64BitSupport
bool Has64BitSupport
Definition: PPCSubtarget.h:95
llvm::PPC::DIR_E500mc
@ DIR_E500mc
Definition: PPCSubtarget.h:52
llvm::PPCSubtarget::HasP9Vector
bool HasP9Vector
Definition: PPCSubtarget.h:109
llvm::PPCSubtarget::hasInvariantFunctionDescriptors
bool hasInvariantFunctionDescriptors() const
Definition: PPCSubtarget.h:300
llvm::PPCSubtarget::getTargetLowering
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:207
llvm::PPCSubtarget::hasCMPB
bool hasCMPB() const
Definition: PPCSubtarget.h:287
llvm::PPC::DIR_970
@ DIR_970
Definition: PPCSubtarget.h:49
llvm::PPCInstrInfo::getRegisterInfo
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:289
llvm::PPCSubtarget::enableMachinePipeliner
bool enableMachinePipeliner() const override
Pipeliner customization.
Definition: PPCSubtarget.cpp:193
llvm::PPCSubtarget::hasPrivileged
bool hasPrivileged() const
Definition: PPCSubtarget.h:281
llvm::PPCSubtarget::useSoftFloat
bool useSoftFloat() const
Definition: PPCSubtarget.h:235
llvm::PPCSubtarget::initializeSubtargetDependencies
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: PPCSubtarget.cpp:47
llvm::PPCSubtarget::hasICBT
bool hasICBT() const
Definition: PPCSubtarget.h:299
llvm::PPCSubtarget::IsISA3_0
bool IsISA3_0
Definition: PPCSubtarget.h:151
llvm::PPCSubtarget::IsAIX
bool IsAIX
Definition: PPCSubtarget.h:161
llvm::PPCSubtarget::HasSPE
bool HasSPE
Definition: PPCSubtarget.h:102
llvm::PPCSubtarget::hasSPE
bool hasSPE() const
Definition: PPCSubtarget.h:266
llvm::PPCSubtarget::hasAddiLoadFusion
bool hasAddiLoadFusion() const
Definition: PPCSubtarget.h:331
PPCISelLowering.h
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::PPCSubtarget::getGPRAllocationOrderIdx
unsigned getGPRAllocationOrderIdx() const
Definition: PPCSubtarget.h:420
llvm::PPCSubtarget::HasModernAIXAs
bool HasModernAIXAs
Definition: PPCSubtarget.h:160
llvm::PPCSubtarget::HasHardFloat
bool HasHardFloat
Definition: PPCSubtarget.h:98
llvm::PPCSubtarget::UsePPCPostRASchedStrategy
bool UsePPCPostRASchedStrategy
Definition: PPCSubtarget.h:157
llvm::PPCSubtarget::NeedsTwoConstNR
bool NeedsTwoConstNR
Definition: PPCSubtarget.h:105
llvm::PPCSubtarget::HasStoreFusion
bool HasStoreFusion
Definition: PPCSubtarget.h:147
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:245
llvm::PPCSubtarget::HasFloat128
bool HasFloat128
Definition: PPCSubtarget.h:145
SelectionDAGTargetInfo.h
llvm::PPCSubtarget::HasFRSQRTE
bool HasFRSQRTE
Definition: PPCSubtarget.h:119
llvm::PPCSubtarget::hasAltivec
bool hasAltivec() const
Definition: PPCSubtarget.h:265
llvm::PPC::DIR_PWR6
@ DIR_PWR6
Definition: PPCSubtarget.h:58
llvm::PPCSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: PPCSubtarget.cpp:263
llvm::PPCSubtarget::HasP10Vector
bool HasP10Vector
Definition: PPCSubtarget.h:111
llvm::PPCSubtarget::getEnvironmentPointerRegister
MCRegister getEnvironmentPointerRegister() const
Definition: PPCSubtarget.h:396
llvm::PPCSubtarget::descriptorEnvironmentPointerOffset
unsigned descriptorEnvironmentPointerOffset() const
Definition: PPCSubtarget.h:390
llvm::PPC::DIR_E5500
@ DIR_E5500
Definition: PPCSubtarget.h:53
llvm::PPCSubtarget::HasEFPU2
bool HasEFPU2
Definition: PPCSubtarget.h:103
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::PPCSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: PPCSubtarget.h:412
llvm::PPC::DIR_PWR8
@ DIR_PWR8
Definition: PPCSubtarget.h:61
llvm::PPCSubtarget::hasFusion
bool hasFusion() const
Definition: PPCSubtarget.h:329
llvm::PPCSubtarget::isBookE
bool isBookE() const
Definition: PPCSubtarget.h:289
llvm::PPCSubtarget::HasPrivileged
bool HasPrivileged
Definition: PPCSubtarget.h:116
llvm::PPCSubtarget::SecurePlt
bool SecurePlt
Definition: PPCSubtarget.h:154
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1083
llvm::PPCSubtarget::POPCNTD_Fast
@ POPCNTD_Fast
Definition: PPCSubtarget.h:76
llvm::PPCSubtarget::isDeprecatedDST
bool isDeprecatedDST() const
Definition: PPCSubtarget.h:298
llvm::PPCSubtarget::useLongCalls
bool useLongCalls() const
Definition: PPCSubtarget.h:328
llvm::PPCSubtarget::getCriticalPathRCs
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
Definition: PPCSubtarget.cpp:206
llvm::PPCSubtarget::getCPUDirective
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:195
llvm::PPCSubtarget::hasQuadwordAtomics
bool hasQuadwordAtomics() const
Definition: PPCSubtarget.h:306
llvm::PPCSubtarget::allowsUnalignedFPAccess
bool allowsUnalignedFPAccess() const
Definition: PPCSubtarget.h:297
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:174
llvm::PPCSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:172
llvm::PPCSubtarget::hasLFIWAX
bool hasLFIWAX() const
Definition: PPCSubtarget.h:262
llvm::PPCSubtarget::HasHTM
bool HasHTM
Definition: PPCSubtarget.h:144
llvm::PPCSubtarget::UseCRBits
bool UseCRBits
Definition: PPCSubtarget.h:97
llvm::PPCSubtarget::HasCMPB
bool HasCMPB
Definition: PPCSubtarget.h:128
llvm::PPCSubtarget::POPCNTD_Slow
@ POPCNTD_Slow
Definition: PPCSubtarget.h:75
llvm::CallLowering
Definition: CallLowering.h:43
llvm::PPCSubtarget::isFeatureMFTB
bool isFeatureMFTB() const
Definition: PPCSubtarget.h:296
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::PPCSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: PPCSubtarget.h:342
llvm::PPCSubtarget::hasFRSQRTE
bool hasFRSQRTE() const
Definition: PPCSubtarget.h:258
llvm::PPCSubtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Originally, this function return hasISEL().
Definition: PPCSubtarget.h:355
llvm::PPCSubtarget::HasP8Altivec
bool HasP8Altivec
Definition: PPCSubtarget.h:107
llvm::PPCSubtarget::pairedVectorMemops
bool pairedVectorMemops() const
Definition: PPCSubtarget.h:282
llvm::PPCSubtarget::use64BitRegs
bool use64BitRegs() const
use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit registers in 32-bit mode when...
Definition: PPCSubtarget.h:244
llvm::PPCSubtarget::hasISEL
bool hasISEL() const
Definition: PPCSubtarget.h:284
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::PPCSubtarget::hasP10Vector
bool hasP10Vector() const
Definition: PPCSubtarget.h:276
llvm::PPCSubtarget::HasFusion
bool HasFusion
Definition: PPCSubtarget.h:146
llvm::PPCSubtarget::isELFv2ABI
bool isELFv2ABI() const
Definition: PPCSubtarget.cpp:242