LLVM 19.0.0git
PPCSubtarget.h
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1//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15
16#include "PPCFrameLowering.h"
17#include "PPCISelLowering.h"
18#include "PPCInstrInfo.h"
24#include "llvm/IR/DataLayout.h"
27#include <string>
28
29#define GET_SUBTARGETINFO_HEADER
30#include "PPCGenSubtargetInfo.inc"
31
32// GCC #defines PPC on Linux but we use it as our namespace name
33#undef PPC
34
35namespace llvm {
36class StringRef;
37
38namespace PPC {
39 // -m directive values.
40enum {
65 DIR_64
66};
67}
68
69class GlobalValue;
70
72public:
77 };
78
79protected:
80 /// TargetTriple - What processor and OS we're targeting.
82
83 /// stackAlignment - The minimum alignment known to hold of the stack frame on
84 /// entry to the function and which must be maintained by every function.
86
87 /// Selected instruction itineraries (one entry per itinerary class.)
89
90// Bool members corresponding to the SubtargetFeatures defined in tablegen.
91#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
92 bool ATTRIBUTE = DEFAULT;
93#include "PPCGenSubtargetInfo.inc"
94
95 /// Which cpu directive was used.
96 unsigned CPUDirective;
97
98 bool IsPPC64;
100
102
108
109 /// GlobalISel related APIs.
110 std::unique_ptr<CallLowering> CallLoweringInfo;
111 std::unique_ptr<LegalizerInfo> Legalizer;
112 std::unique_ptr<RegisterBankInfo> RegBankInfo;
113 std::unique_ptr<InstructionSelector> InstSelector;
114
115public:
116 /// This constructor initializes the data members to match that
117 /// of the specified triple.
118 ///
119 PPCSubtarget(const Triple &TT, const std::string &CPU,
120 const std::string &TuneCPU, const std::string &FS,
121 const PPCTargetMachine &TM);
122
123 /// ParseSubtargetFeatures - Parses features string setting specified
124 /// subtarget options. Definition of function is auto generated by tblgen.
126
127 /// getStackAlignment - Returns the minimum alignment known to hold of the
128 /// stack frame on entry to the function and which must be maintained by every
129 /// function for this subtarget.
131
132 /// getCPUDirective - Returns the -m directive specified for the cpu.
133 ///
134 unsigned getCPUDirective() const { return CPUDirective; }
135
136 /// getInstrItins - Return the instruction itineraries based on subtarget
137 /// selection.
139 return &InstrItins;
140 }
141
142 const PPCFrameLowering *getFrameLowering() const override {
143 return &FrameLowering;
144 }
145 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
146 const PPCTargetLowering *getTargetLowering() const override {
147 return &TLInfo;
148 }
150 return &TSInfo;
151 }
152 const PPCRegisterInfo *getRegisterInfo() const override {
153 return &getInstrInfo()->getRegisterInfo();
154 }
155 const PPCTargetMachine &getTargetMachine() const { return TM; }
156
157 /// initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and
158 /// feature string so that we can use initializer lists for subtarget
159 /// initialization.
161 StringRef TuneCPU,
162 StringRef FS);
163
164private:
165 void initializeEnvironment();
166 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
167
168public:
169 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
170 ///
171 bool isPPC64() const;
172
173 // useSoftFloat - Return true if soft-float option is turned on.
174 bool useSoftFloat() const {
175 if (isAIXABI() && !HasHardFloat)
176 report_fatal_error("soft-float is not yet supported on AIX.");
177 return !HasHardFloat;
178 }
179
180 // isLittleEndian - True if generating little-endian code
181 bool isLittleEndian() const { return IsLittleEndian; }
182
183// Getters for SubtargetFeatures defined in tablegen.
184#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
185 bool GETTER() const { return ATTRIBUTE; }
186#include "PPCGenSubtargetInfo.inc"
187
189 return Align(16);
190 }
191
192 unsigned getRedZoneSize() const {
193 if (isPPC64())
194 // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
195 return 288;
196
197 // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
198 // PPC32 SVR4ABI has no redzone.
199 return isAIXABI() ? 220 : 0;
200 }
201
203 return hasVSX() && isLittleEndian() && !hasP9Vector();
204 }
205
207
208 const Triple &getTargetTriple() const { return TargetTriple; }
209
210 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
212 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
213
214 bool isAIXABI() const { return TargetTriple.isOSAIX(); }
215 bool isSVR4ABI() const { return !isAIXABI(); }
216 bool isELFv2ABI() const;
217
218 bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
219 bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
220 bool isUsingPCRelativeCalls() const;
221
222 /// Originally, this function return hasISEL(). Now we always enable it,
223 /// but may expand the ISEL instruction later.
224 bool enableEarlyIfConversion() const override { return true; }
225
226 /// Scheduling customization.
227 bool enableMachineScheduler() const override;
228 /// Pipeliner customization.
229 bool enableMachinePipeliner() const override;
230 /// Machine Pipeliner customization
231 bool useDFAforSMS() const override;
232 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
233 bool enablePostRAScheduler() const override;
234 AntiDepBreakMode getAntiDepBreakMode() const override;
235 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
236
238 unsigned NumRegionInstrs) const override;
239 bool useAA() const override;
240
241 bool enableSubRegLiveness() const override;
242
243 bool enableSpillageCopyElimination() const override { return true; }
244
245 /// True if the GV will be accessed via an indirect symbol.
246 bool isGVIndirectSymbol(const GlobalValue *GV) const;
247
248 /// Calculates the effective code model for argument GV.
250 const GlobalValue *GV) const;
251
252 /// True if the ABI is descriptor based.
254 // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
255 // v1 ABI uses descriptors.
256 return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
257 }
258
259 unsigned descriptorTOCAnchorOffset() const {
261 "Should only be called when the target uses descriptors.");
262 return IsPPC64 ? 8 : 4;
263 }
264
267 "Should only be called when the target uses descriptors.");
268 return IsPPC64 ? 16 : 8;
269 }
270
273 "Should only be called when the target uses descriptors.");
274 return IsPPC64 ? PPC::X11 : PPC::R11;
275 }
276
278 assert((is64BitELFABI() || isAIXABI()) &&
279 "Should only be called when the target is a TOC based ABI.");
280 return IsPPC64 ? PPC::X2 : PPC::R2;
281 }
282
284 assert((is64BitELFABI() || isAIXABI()) &&
285 "Should only be called for targets with a thread pointer register.");
286 return IsPPC64 ? PPC::X13 : PPC::R13;
287 }
288
290 return IsPPC64 ? PPC::X1 : PPC::R1;
291 }
292
293 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
294
296 return PredictableSelectIsExpensive;
297 }
298
299 // Select allocation orders of GPRC and G8RC. It should be strictly consistent
300 // with corresponding AltOrders in PPCRegisterInfo.td.
301 unsigned getGPRAllocationOrderIdx() const {
302 if (is64BitELFABI())
303 return 1;
304 if (isAIXABI())
305 return 2;
306 return 0;
307 }
308
309 // GlobalISEL
310 const CallLowering *getCallLowering() const override;
311 const RegisterBankInfo *getRegBankInfo() const override;
312 const LegalizerInfo *getLegalizerInfo() const override;
314};
315} // End llvm namespace
316
317#endif
This file describes how to lower LLVM calls to machine code calls.
Interface for Targets to specify which operations they can successfully select and how the others sho...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Itinerary data supplied by a subtarget to be used by a target.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:274
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:113
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool is32BitELFABI() const
Definition: PPCSubtarget.h:219
std::unique_ptr< LegalizerInfo > Legalizer
Definition: PPCSubtarget.h:111
PPCTargetLowering TLInfo
Definition: PPCSubtarget.h:106
unsigned descriptorTOCAnchorOffset() const
Definition: PPCSubtarget.h:259
bool isTargetMachO() const
Definition: PPCSubtarget.h:211
PPCFrameLowering FrameLowering
Definition: PPCSubtarget.h:104
bool isAIXABI() const
Definition: PPCSubtarget.h:214
const CallLowering * getCallLowering() const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
const LegalizerInfo * getLegalizerInfo() const override
unsigned getGPRAllocationOrderIdx() const
Definition: PPCSubtarget.h:301
bool useSoftFloat() const
Definition: PPCSubtarget.h:174
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:112
bool isXRaySupported() const override
Definition: PPCSubtarget.h:293
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:101
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
const PPCFrameLowering * getFrameLowering() const override
Definition: PPCSubtarget.h:142
bool needsSwapsForVSXMemOps() const
Definition: PPCSubtarget.h:202
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
PPCInstrInfo InstrInfo
Definition: PPCSubtarget.h:105
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
Definition: PPCSubtarget.h:253
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:146
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: PPCSubtarget.h:138
SelectionDAGTargetInfo TSInfo
Definition: PPCSubtarget.h:107
InstructionSelector * getInstructionSelector() const override
bool enableEarlyIfConversion() const override
Originally, this function return hasISEL().
Definition: PPCSubtarget.h:224
MCRegister getEnvironmentPointerRegister() const
Definition: PPCSubtarget.h:271
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:96
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:145
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:192
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: PPCSubtarget.h:149
AntiDepBreakMode getAntiDepBreakMode() const override
MCRegister getThreadPointerRegister() const
Definition: PPCSubtarget.h:283
bool isSVR4ABI() const
Definition: PPCSubtarget.h:215
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:134
bool enableSpillageCopyElimination() const override
Definition: PPCSubtarget.h:243
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:206
bool isLittleEndian() const
Definition: PPCSubtarget.h:181
bool isTargetLinux() const
Definition: PPCSubtarget.h:212
MCRegister getTOCPointerRegister() const
Definition: PPCSubtarget.h:277
bool isTargetELF() const
Definition: PPCSubtarget.h:210
MCRegister getStackPointerRegister() const
Definition: PPCSubtarget.h:289
bool useAA() const override
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: PPCSubtarget.h:130
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
bool is64BitELFABI() const
Definition: PPCSubtarget.h:218
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:188
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:155
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:103
bool isPredictableSelectIsExpensive() const
Definition: PPCSubtarget.h:295
bool enableMachineScheduler() const override
Scheduling customization.
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:152
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
const Triple & getTargetTriple() const
Definition: PPCSubtarget.h:208
unsigned descriptorEnvironmentPointerOffset() const
Definition: PPCSubtarget.h:265
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:110
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:732
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:678
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:710
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
@ DIR_PWR_FUTURE
Definition: PPCSubtarget.h:64
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.