LLVM  14.0.0git
PPCTargetMachine.cpp
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1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCMacroFusion.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetObjectFile.h"
20 #include "PPCTargetTransformInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
33 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
45 #include "llvm/Transforms/Scalar.h"
46 #include <cassert>
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 
53 static cl::opt<bool>
54  EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
55  cl::desc("enable coalescing of duplicate branches for PPC"));
56 static cl::
57 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
58  cl::desc("Disable CTR loops for PPC"));
59 
60 static cl::
61 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
62  cl::desc("Disable PPC loop instr form prep"));
63 
64 static cl::opt<bool>
65 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
66  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
67 
68 static cl::
69 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
70  cl::desc("Disable VSX Swap Removal for PPC"));
71 
72 static cl::
73 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
74  cl::desc("Disable machine peepholes for PPC"));
75 
76 static cl::opt<bool>
77 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
78  cl::desc("Enable optimizations on complex GEPs"),
79  cl::init(true));
80 
81 static cl::opt<bool>
82 EnablePrefetch("enable-ppc-prefetching",
83  cl::desc("enable software prefetching on PPC"),
84  cl::init(false), cl::Hidden);
85 
86 static cl::opt<bool>
87 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
88  cl::desc("Add extra TOC register dependencies"),
89  cl::init(true), cl::Hidden);
90 
91 static cl::opt<bool>
92 EnableMachineCombinerPass("ppc-machine-combiner",
93  cl::desc("Enable the machine combiner pass"),
94  cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool>
97  ReduceCRLogical("ppc-reduce-cr-logicals",
98  cl::desc("Expand eligible cr-logical binary ops to branches"),
99  cl::init(true), cl::Hidden);
101  // Register the targets
106 
108 #ifndef NDEBUG
110 #endif
128 }
129 
130 static bool isLittleEndianTriple(const Triple &T) {
131  return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
132 }
133 
134 /// Return the datalayout string of a subtarget.
135 static std::string getDataLayoutString(const Triple &T) {
136  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
137  std::string Ret;
138 
139  // Most PPC* platforms are big endian, PPC(64)LE is little endian.
140  if (isLittleEndianTriple(T))
141  Ret = "e";
142  else
143  Ret = "E";
144 
146 
147  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
148  // pointers.
149  if (!is64Bit || T.getOS() == Triple::Lv2)
150  Ret += "-p:32:32";
151 
152  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
153  // documentation are wrong; these are correct (i.e. "what gcc does").
154  Ret += "-i64:64";
155 
156  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
157  if (is64Bit)
158  Ret += "-n32:64";
159  else
160  Ret += "-n32";
161 
162  // Specify the vector alignment explicitly. For v256i1 and v512i1, the
163  // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
164  // which is 256 and 512 bytes - way over aligned.
165  if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
166  Ret += "-S128-v256:256:256-v512:512:512";
167 
168  return Ret;
169 }
170 
172  const Triple &TT) {
173  std::string FullFS = std::string(FS);
174 
175  // Make sure 64-bit features are available when CPUname is generic
176  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
177  if (!FullFS.empty())
178  FullFS = "+64bit," + FullFS;
179  else
180  FullFS = "+64bit";
181  }
182 
183  if (OL >= CodeGenOpt::Default) {
184  if (!FullFS.empty())
185  FullFS = "+crbits," + FullFS;
186  else
187  FullFS = "+crbits";
188  }
189 
190  if (OL != CodeGenOpt::None) {
191  if (!FullFS.empty())
192  FullFS = "+invariant-function-descriptors," + FullFS;
193  else
194  FullFS = "+invariant-function-descriptors";
195  }
196 
197  if (TT.isOSAIX()) {
198  if (!FullFS.empty())
199  FullFS = "+aix," + FullFS;
200  else
201  FullFS = "+aix";
202  }
203 
204  return FullFS;
205 }
206 
207 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
208  if (TT.isOSAIX())
209  return std::make_unique<TargetLoweringObjectFileXCOFF>();
210 
211  return std::make_unique<PPC64LinuxTargetObjectFile>();
212 }
213 
215  const TargetOptions &Options) {
216  if (Options.MCOptions.getABIName().startswith("elfv1"))
218  else if (Options.MCOptions.getABIName().startswith("elfv2"))
220 
221  assert(Options.MCOptions.getABIName().empty() &&
222  "Unknown target-abi option!");
223 
224  if (TT.isMacOSX())
226 
227  switch (TT.getArch()) {
228  case Triple::ppc64le:
230  case Triple::ppc64:
232  default:
234  }
235 }
236 
239  assert((!TT.isOSAIX() || !RM.hasValue() || *RM == Reloc::PIC_) &&
240  "Invalid relocation model for AIX.");
241 
242  if (RM.hasValue())
243  return *RM;
244 
245  // Big Endian PPC and AIX default to PIC.
246  if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
247  return Reloc::PIC_;
248 
249  // Rest are static by default.
250  return Reloc::Static;
251 }
252 
255  bool JIT) {
256  if (CM) {
257  if (*CM == CodeModel::Tiny)
258  report_fatal_error("Target does not support the tiny CodeModel", false);
259  if (*CM == CodeModel::Kernel)
260  report_fatal_error("Target does not support the kernel CodeModel", false);
261  return *CM;
262  }
263 
264  if (JIT)
265  return CodeModel::Small;
266  if (TT.isOSAIX())
267  return CodeModel::Small;
268 
269  assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
270 
271  if (TT.isArch32Bit())
272  return CodeModel::Small;
273 
274  assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
275  return CodeModel::Medium;
276 }
277 
278 
280  const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
281  ScheduleDAGMILive *DAG =
282  new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
283  std::make_unique<PPCPreRASchedStrategy>(C) :
284  std::make_unique<GenericScheduler>(C));
285  // add DAG Mutations here.
286  DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
287  if (ST.hasStoreFusion())
288  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
289  if (ST.hasFusion())
290  DAG->addMutation(createPowerPCMacroFusionDAGMutation());
291 
292  return DAG;
293 }
294 
297  const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
298  ScheduleDAGMI *DAG =
299  new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
300  std::make_unique<PPCPostRASchedStrategy>(C) :
301  std::make_unique<PostGenericScheduler>(C), true);
302  // add DAG Mutations here.
303  if (ST.hasStoreFusion())
304  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
305  if (ST.hasFusion())
306  DAG->addMutation(createPowerPCMacroFusionDAGMutation());
307  return DAG;
308 }
309 
310 // The FeatureString here is a little subtle. We are modifying the feature
311 // string with what are (currently) non-function specific overrides as it goes
312 // into the LLVMTargetMachine constructor and then using the stored value in the
313 // Subtarget constructor below it.
315  StringRef CPU, StringRef FS,
316  const TargetOptions &Options,
319  CodeGenOpt::Level OL, bool JIT)
320  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
321  computeFSAdditions(FS, OL, TT), Options,
323  getEffectivePPCCodeModel(TT, CM, JIT), OL),
324  TLOF(createTLOF(getTargetTriple())),
325  TargetABI(computeTargetABI(TT, Options)),
326  Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
327  initAsmInfo();
328 }
329 
331 
332 const PPCSubtarget *
334  Attribute CPUAttr = F.getFnAttribute("target-cpu");
335  Attribute FSAttr = F.getFnAttribute("target-features");
336 
337  std::string CPU =
338  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
339  std::string FS =
340  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
341 
342  // FIXME: This is related to the code below to reset the target options,
343  // we need to know whether or not the soft float flag is set on the
344  // function before we can generate a subtarget. We also need to use
345  // it as a key for the subtarget since that can be the only difference
346  // between two functions.
347  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
348  // If the soft float attribute is set on the function turn on the soft float
349  // subtarget feature.
350  if (SoftFloat)
351  FS += FS.empty() ? "-hard-float" : ",-hard-float";
352 
353  auto &I = SubtargetMap[CPU + FS];
354  if (!I) {
355  // This needs to be done before we create a new subtarget since any
356  // creation will depend on the TM and the code generation flags on the
357  // function that reside in TargetOptions.
359  I = std::make_unique<PPCSubtarget>(
360  TargetTriple, CPU,
361  // FIXME: It would be good to have the subtarget additions here
362  // not necessary. Anything that turns them on/off (overrides) ends
363  // up being put at the end of the feature string, but the defaults
364  // shouldn't require adding them. Fixing this means pulling Feature64Bit
365  // out of most of the target cpus in the .td file and making it set only
366  // as part of initialization via the TargetTriple.
368  }
369  return I.get();
370 }
371 
372 //===----------------------------------------------------------------------===//
373 // Pass Pipeline Configuration
374 //===----------------------------------------------------------------------===//
375 
376 namespace {
377 
378 /// PPC Code Generator Pass Configuration Options.
379 class PPCPassConfig : public TargetPassConfig {
380 public:
381  PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
382  : TargetPassConfig(TM, PM) {
383  // At any optimization level above -O0 we use the Machine Scheduler and not
384  // the default Post RA List Scheduler.
385  if (TM.getOptLevel() != CodeGenOpt::None)
386  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
387  }
388 
389  PPCTargetMachine &getPPCTargetMachine() const {
390  return getTM<PPCTargetMachine>();
391  }
392 
393  void addIRPasses() override;
394  bool addPreISel() override;
395  bool addILPOpts() override;
396  bool addInstSelector() override;
397  void addMachineSSAOptimization() override;
398  void addPreRegAlloc() override;
399  void addPreSched2() override;
400  void addPreEmitPass() override;
401  void addPreEmitPass2() override;
402  // GlobalISEL
403  bool addIRTranslator() override;
404  bool addLegalizeMachineIR() override;
405  bool addRegBankSelect() override;
406  bool addGlobalInstructionSelect() override;
407 
409  createMachineScheduler(MachineSchedContext *C) const override {
411  }
413  createPostMachineScheduler(MachineSchedContext *C) const override {
415  }
416 };
417 
418 } // end anonymous namespace
419 
421  return new PPCPassConfig(*this, PM);
422 }
423 
424 void PPCPassConfig::addIRPasses() {
425  if (TM->getOptLevel() != CodeGenOpt::None)
426  addPass(createPPCBoolRetToIntPass());
427  addPass(createAtomicExpandPass());
428 
429  // Lower generic MASSV routines to PowerPC subtarget-specific entries.
431 
432  // If explicitly requested, add explicit data prefetch intrinsics.
434  addPass(createLoopDataPrefetchPass());
435 
436  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
437  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
438  // and lower a GEP with multiple indices to either arithmetic operations or
439  // multiple GEPs with single index.
441  // Call EarlyCSE pass to find and remove subexpressions in the lowered
442  // result.
443  addPass(createEarlyCSEPass());
444  // Do loop invariant code motion in case part of the lowered result is
445  // invariant.
446  addPass(createLICMPass());
447  }
448 
450 }
451 
452 bool PPCPassConfig::addPreISel() {
453  if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
454  addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
455 
456  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
457  addPass(createHardwareLoopsPass());
458 
459  return false;
460 }
461 
462 bool PPCPassConfig::addILPOpts() {
463  addPass(&EarlyIfConverterID);
464 
466  addPass(&MachineCombinerID);
467 
468  return true;
469 }
470 
471 bool PPCPassConfig::addInstSelector() {
472  // Install an instruction selector.
473  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
474 
475 #ifndef NDEBUG
476  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
477  addPass(createPPCCTRLoopsVerify());
478 #endif
479 
480  addPass(createPPCVSXCopyPass());
481  return false;
482 }
483 
484 void PPCPassConfig::addMachineSSAOptimization() {
485  // PPCBranchCoalescingPass need to be done before machine sinking
486  // since it merges empty blocks.
487  if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
490  // For little endian, remove where possible the vector swap instructions
491  // introduced at code generation to normalize vector element order.
492  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
494  addPass(createPPCVSXSwapRemovalPass());
495  // Reduce the number of cr-logical ops.
496  if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
498  // Target-specific peephole cleanups performed after instruction
499  // selection.
500  if (!DisableMIPeephole) {
501  addPass(createPPCMIPeepholePass());
503  }
504 }
505 
506 void PPCPassConfig::addPreRegAlloc() {
507  if (getOptLevel() != CodeGenOpt::None) {
511  }
512 
513  // FIXME: We probably don't need to run these for -fPIE.
514  if (getPPCTargetMachine().isPositionIndependent()) {
515  // FIXME: LiveVariables should not be necessary here!
516  // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
517  // LiveVariables. This (unnecessary) dependency has been removed now,
518  // however a stage-2 clang build fails without LiveVariables computed here.
519  addPass(&LiveVariablesID);
520  addPass(createPPCTLSDynamicCallPass());
521  }
523  addPass(createPPCTOCRegDepsPass());
524 
525  if (getOptLevel() != CodeGenOpt::None)
526  addPass(&MachinePipelinerID);
527 }
528 
529 void PPCPassConfig::addPreSched2() {
530  if (getOptLevel() != CodeGenOpt::None)
531  addPass(&IfConverterID);
532 }
533 
534 void PPCPassConfig::addPreEmitPass() {
535  addPass(createPPCPreEmitPeepholePass());
536  addPass(createPPCExpandISELPass());
537 
538  if (getOptLevel() != CodeGenOpt::None)
539  addPass(createPPCEarlyReturnPass());
540 }
541 
542 void PPCPassConfig::addPreEmitPass2() {
543  // Schedule the expansion of AMOs at the last possible moment, avoiding the
544  // possibility for other passes to break the requirements for forward
545  // progress in the LL/SC block.
547  // Must run branch selection immediately preceding the asm printer.
548  addPass(createPPCBranchSelectionPass());
549 }
550 
553  return TargetTransformInfo(PPCTTIImpl(this, F));
554 }
555 
557  assert(Endianness != Endian::NOT_DETECTED &&
558  "Unable to determine endianness");
559  return Endianness == Endian::LITTLE;
560 }
561 
563 PPCPreRASchedRegistry("ppc-prera",
564  "Run PowerPC PreRA specific scheduler",
566 
568 PPCPostRASchedRegistry("ppc-postra",
569  "Run PowerPC PostRA specific scheduler",
571 
572 // Global ISEL
573 bool PPCPassConfig::addIRTranslator() {
574  addPass(new IRTranslator());
575  return false;
576 }
577 
578 bool PPCPassConfig::addLegalizeMachineIR() {
579  addPass(new Legalizer());
580  return false;
581 }
582 
583 bool PPCPassConfig::addRegBankSelect() {
584  addPass(new RegBankSelect());
585  return false;
586 }
587 
588 bool PPCPassConfig::addGlobalInstructionSelect() {
589  addPass(new InstructionSelect(getOptLevel()));
590  return false;
591 }
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Definition: PPCTargetMachine.cpp:295
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---------------------— PointerInfo ------------------------------------—
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Definition: PPCTargetMachine.cpp:135
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Definition: Legalizer.h:31
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
isLittleEndianTriple
static bool isLittleEndianTriple(const Triple &T)
Definition: PPCTargetMachine.cpp:130
llvm::createCopyConstrainDAGMutation
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1794
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::Triple::ppc64
@ ppc64
Definition: Triple.h:69
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
EnableExtraTOCRegDeps
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::initializePPCBSelPass
void initializePPCBSelPass(PassRegistry &)
PPC.h
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:404
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:100
llvm::PPCTargetMachine::PPC_ABI_ELFv1
@ PPC_ABI_ELFv1
Definition: PPCTargetMachine.h:27
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
EnablePrefetch
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("enable software prefetching on PPC"), cl::init(false), cl::Hidden)
llvm::initializePPCTOCRegDepsPass
void initializePPCTOCRegDepsPass(PassRegistry &)
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
PPCMacroFusion.h
PPCTargetObjectFile.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::PPCTargetMachine::Endian
Endian
Definition: PPCTargetMachine.h:28
llvm::createPPCVSXCopyPass
FunctionPass * createPPCVSXCopyPass()
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::PPCTargetMachine::getSubtargetImpl
const PPCSubtarget * getSubtargetImpl() const =delete
DisableVSXSwapRemoval
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
PPCPreRASchedRegistry
static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", createPPCMachineScheduler)
llvm::Triple::ppc64le
@ ppc64le
Definition: Triple.h:70
LLVMInitializePowerPCTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget()
Definition: PPCTargetMachine.cpp:100
llvm::initializePPCMIPeepholePass
void initializePPCMIPeepholePass(PassRegistry &)
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:98
EnableBranchCoalescing
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
llvm::createPPCLowerMASSVEntriesPass
ModulePass * createPPCLowerMASSVEntriesPass()
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::PPCVSXFMAMutateID
char & PPCVSXFMAMutateID
Definition: PPCVSXFMAMutate.cpp:393
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EnableGEPOpt
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
llvm::PPCTTIImpl
Definition: PPCTargetTransformInfo.h:26
llvm::createPPCTLSDynamicCallPass
FunctionPass * createPPCTLSDynamicCallPass()
Definition: PPCTLSDynamicCall.cpp:239
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
I
#define I(x, y, z)
Definition: MD5.cpp:59
PowerPCTargetInfo.h
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:850
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
TargetPassConfig.h
Localizer.h
llvm::createPPCTOCRegDepsPass
FunctionPass * createPPCTOCRegDepsPass()
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
DisableCTRLoops
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
VSXFMAMutateEarly
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
getEffectivePPCCodeModel
static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
Definition: PPCTargetMachine.cpp:253
PPCPostRASchedRegistry
static MachineSchedRegistry PPCPostRASchedRegistry("ppc-postra", "Run PowerPC PostRA specific scheduler", createPPCPostMachineScheduler)
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::initializePPCCTRLoopsVerifyPass
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
llvm::createPPCBranchSelectionPass
FunctionPass * createPPCBranchSelectionPass()
llvm::createPPCPreEmitPeepholePass
FunctionPass * createPPCPreEmitPeepholePass()
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::initializePPCTLSDynamicCallPass
void initializePPCTLSDynamicCallPass(PassRegistry &)
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::createHardwareLoopsPass
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
Definition: HardwareLoops.cpp:546
llvm::Triple::ppcle
@ ppcle
Definition: Triple.h:68
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
IRTranslator.h
ReduceCRLogical
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(true), cl::Hidden)
EnableMachineCombinerPass
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::createPPCBranchCoalescingPass
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass
Definition: PPCBranchCoalescing.cpp:193
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::getThePPC64Target
Target & getThePPC64Target()
Definition: PowerPCTargetInfo.cpp:21
Attributes.h
llvm::createPPCMIPeepholePass
FunctionPass * createPPCMIPeepholePass()
Definition: PPCMIPeephole.cpp:1669
llvm::createPPCVSXSwapRemovalPass
FunctionPass * createPPCVSXSwapRemovalPass()
Definition: PPCVSXSwapRemoval.cpp:1072
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1287
llvm::createPPCReduceCRLogicalsPass
FunctionPass * createPPCReduceCRLogicalsPass()
Definition: PPCReduceCRLogicals.cpp:738
RegBankSelect.h
llvm::initializePPCExpandISELPass
void initializePPCExpandISELPass(PassRegistry &)
Function.h
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:393
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
PPCTargetTransformInfo.h
computeTargetABI
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
Definition: PPCTargetMachine.cpp:214
llvm::getThePPC32LETarget
Target & getThePPC32LETarget()
Definition: PowerPCTargetInfo.cpp:17
llvm::initializePPCEarlyReturnPass
void initializePPCEarlyReturnPass(PassRegistry &)
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:210
CodeGen.h
Legalizer.h
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:327
MachineScheduler.h
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
llvm::initializePPCBoolRetToIntPass
void initializePPCBoolRetToIntPass(PassRegistry &)
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:128
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: PPCTargetMachine.cpp:207
llvm::initializePPCBranchCoalescingPass
void initializePPCBranchCoalescingPass(PassRegistry &)
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:130
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1580
llvm::IRTranslator
Definition: IRTranslator.h:62
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
computeFSAdditions
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
Definition: PPCTargetMachine.cpp:171
llvm::createPPCISelDag
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG,...
Definition: PPCISelDAGToDAG.cpp:7284
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:241
llvm::cl::desc
Definition: CommandLine.h:414
llvm::PPCTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: PPCTargetMachine.cpp:552
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:436
TargetRegistry.h
llvm::initializePPCReduceCRLogicalsPass
void initializePPCReduceCRLogicalsPass(PassRegistry &)
InitializePasses.h
llvm::initializePPCVSXSwapRemovalPass
void initializePPCVSXSwapRemovalPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:99
PPCTargetMachine.h
llvm::createPPCExpandAtomicPseudoPass
FunctionPass * createPPCExpandAtomicPseudoPass()
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:155
llvm::getThePPC32Target
Target & getThePPC32Target()
Definition: PowerPCTargetInfo.cpp:13