LLVM 17.0.0git
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#include "Target/PowerPC/GISel/PPCRegisterBankInfo.h"
Additional Inherited Members | |
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using | InstructionMappings = SmallVector< const InstructionMapping *, 4 > |
Convenient type to represent the alternatives for mapping an instruction. | |
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static void | applyDefaultMapping (const OperandsMapper &OpdMapper) |
Helper method to apply something that is like the default mapping. | |
static const TargetRegisterClass * | constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) |
Constrain the (possibly generic) virtual register Reg to RC . | |
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static const unsigned | DefaultMappingID = UINT_MAX |
Identifier used when the related instruction mapping instance is generated by target independent code. | |
static const unsigned | InvalidMappingID = UINT_MAX - 1 |
Identifier used when the related instruction mapping instance is generated by the default constructor. | |
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enum | PartialMappingIdx { PMI_None = -1 , PMI_GPR32 = 1 , PMI_GPR64 = 2 , PMI_FPR32 = 3 , PMI_FPR64 = 4 , PMI_CR = 5 , PMI_Min = PMI_GPR32 } |
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RegisterBankInfo (RegisterBank **RegBanks, unsigned NumRegBanks) | |
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. | |
RegisterBankInfo () | |
This constructor is meaningless. | |
RegisterBank & | getRegBank (unsigned ID) |
Get the register bank identified by ID . | |
const TargetRegisterClass * | getMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const |
Get the MinimalPhysRegClass for Reg. | |
const InstructionMapping & | getInstrMappingImpl (const MachineInstr &MI) const |
Try to get the mapping of MI . | |
const PartialMapping & | getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
Get the uniquely generated PartialMapping for the given arguments. | |
const ValueMapping & | getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
The most common ValueMapping consists of a single PartialMapping. | |
const ValueMapping & | getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const |
Get the ValueMapping for the given arguments. | |
template<typename Iterator > | |
const ValueMapping * | getOperandsMapping (Iterator Begin, Iterator End) const |
Get the uniquely generated array of ValueMapping for the elements of between Begin and End . | |
const ValueMapping * | getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the elements of OpdsMapping . | |
const ValueMapping * | getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the given arguments. | |
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static const RegisterBankInfo::ValueMapping * | getValueMapping (PartialMappingIdx RBIdx) |
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx . | |
static const RegisterBankInfo::ValueMapping * | getCopyMapping (unsigned DstBankID, unsigned SrcBankID, unsigned Size) |
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register bank to the DstBankID register bank with a size of Size . | |
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RegisterBank ** | RegBanks |
Hold the set of supported register banks. | |
unsigned | NumRegBanks |
Total number of register banks. | |
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > | MapOfPartialMappings |
Keep dynamically allocated PartialMapping in a separate map. | |
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > | MapOfValueMappings |
Keep dynamically allocated ValueMapping in a separate map. | |
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > | MapOfOperandsMappings |
Keep dynamically allocated array of ValueMapping in a separate map. | |
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > | MapOfInstructionMappings |
Keep dynamically allocated InstructionMapping in a separate map. | |
DenseMap< unsigned, const TargetRegisterClass * > | PhysRegMinimalRCs |
Getting the minimal register class of a physreg is expensive. | |
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static RegisterBankInfo::PartialMapping | PartMappings [] |
static RegisterBankInfo::ValueMapping | ValMappings [] |
static PartialMappingIdx | BankIDToCopyMapIdx [] |
Definition at line 63 of file PPCRegisterBankInfo.h.
PPCRegisterBankInfo::PPCRegisterBankInfo | ( | const TargetRegisterInfo & | TRI | ) |
Definition at line 29 of file PPCRegisterBankInfo.cpp.
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overridevirtual |
Get the alternative mappings for MI
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Alternative in the sense different from getInstrMapping.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 315 of file PPCRegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstrAlternativeMappings(), and MI.
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overridevirtual |
Get the mapping of the different operands of MI
on the register bank.
This mapping should be the direct translation of MI
. In other words, when MI
is mapped with the returned mapping, only the register banks of the operands of MI
need to be updated. In particular, neither the opcode nor the type of MI
needs to be updated for this direct mapping.
The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.
For instance, if MI
is a vector add, the mapping should not be a scalarization of the add.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 60 of file PPCRegisterBankInfo.cpp.
References llvm::any_of(), assert(), Cost, llvm::RegisterBankInfo::DefaultMappingID, DefMI, llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getInvalidInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RegisterBankInfo::getSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::PPCGenRegisterBankInfo::getValueMapping(), llvm::isPreISelGenericOpcode(), llvm::RegisterBankInfo::InstructionMapping::isValid(), MI, MRI, llvm::PPCGenRegisterBankInfo::PMI_CR, llvm::PPCGenRegisterBankInfo::PMI_FPR32, llvm::PPCGenRegisterBankInfo::PMI_FPR64, llvm::PPCGenRegisterBankInfo::PMI_GPR32, llvm::PPCGenRegisterBankInfo::PMI_GPR64, Size, TRI, and UseMI.
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overridevirtual |
Get a register bank that covers RC
.
RC
is a user-defined register class (as opposed as one generated by TableGen).Reimplemented from llvm::RegisterBankInfo.
Definition at line 32 of file PPCRegisterBankInfo.cpp.
References llvm::TargetRegisterClass::getID(), llvm::RegisterBankInfo::getRegBank(), and llvm_unreachable.