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SparcInstrInfo.h
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1 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Sparc implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
14 #define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
15 
16 #include "SparcRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "SparcGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class SparcSubtarget;
25 
26 /// SPII - This namespace holds all of the target specific flags that
27 /// instruction info tracks.
28 ///
29 namespace SPII {
30  enum {
31  Pseudo = (1<<0),
32  Load = (1<<1),
33  Store = (1<<2),
34  DelaySlot = (1<<3)
35  };
36 }
37 
39  const SparcRegisterInfo RI;
40  const SparcSubtarget& Subtarget;
41  virtual void anchor();
42 public:
43  explicit SparcInstrInfo(SparcSubtarget &ST);
44 
45  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46  /// such, whenever a client has an instance of instruction info, it should
47  /// always be able to get register info as well (through this method).
48  ///
49  const SparcRegisterInfo &getRegisterInfo() const { return RI; }
50 
51  /// isLoadFromStackSlot - If the specified machine instruction is a direct
52  /// load from a stack slot, return the virtual or physical register number of
53  /// the destination along with the FrameIndex of the loaded stack slot. If
54  /// not, return 0. This predicate must return 0 if the instruction has
55  /// any side effects other than loading from the stack slot.
56  unsigned isLoadFromStackSlot(const MachineInstr &MI,
57  int &FrameIndex) const override;
58 
59  /// isStoreToStackSlot - If the specified machine instruction is a direct
60  /// store to a stack slot, return the virtual or physical register number of
61  /// the source reg along with the FrameIndex of the loaded stack slot. If
62  /// not, return 0. This predicate must return 0 if the instruction has
63  /// any side effects other than storing to the stack slot.
64  unsigned isStoreToStackSlot(const MachineInstr &MI,
65  int &FrameIndex) const override;
66 
68  MachineBasicBlock *&FBB,
70  bool AllowModify = false) const override;
71 
73  int *BytesRemoved = nullptr) const override;
74 
77  const DebugLoc &DL,
78  int *BytesAdded = nullptr) const override;
79 
80  bool
82 
84  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
85  bool KillSrc) const override;
86 
89  Register SrcReg, bool isKill, int FrameIndex,
90  const TargetRegisterClass *RC,
91  const TargetRegisterInfo *TRI) const override;
92 
95  Register DestReg, int FrameIndex,
96  const TargetRegisterClass *RC,
97  const TargetRegisterInfo *TRI) const override;
98 
100 
101  // Lower pseudo instructions after register allocation.
102  bool expandPostRAPseudo(MachineInstr &MI) const override;
103 };
104 
105 }
106 
107 #endif
llvm::SparcRegisterInfo
Definition: SparcRegisterInfo.h:22
SparcRegisterInfo.h
llvm::SparcInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SparcInstrInfo.cpp:273
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::SparcInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SparcInstrInfo.cpp:159
llvm::SparcInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition: SparcInstrInfo.cpp:43
llvm::SparcInstrInfo::getRegisterInfo
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: SparcInstrInfo.h:49
llvm::SparcInstrInfo::SparcInstrInfo
SparcInstrInfo(SparcSubtarget &ST)
Definition: SparcInstrInfo.cpp:34
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SparcInstrInfo
Definition: SparcInstrInfo.h:38
TargetInstrInfo.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SPII::Pseudo
@ Pseudo
Definition: SparcInstrInfo.h:31
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SparcSubtarget
Definition: SparcSubtarget.h:31
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SparcInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: SparcInstrInfo.cpp:62
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SparcInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SparcInstrInfo.cpp:395
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SparcInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SparcInstrInfo.cpp:242
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SparcInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SparcInstrInfo.cpp:305
SparcGenInstrInfo
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SPII::DelaySlot
@ DelaySlot
Definition: SparcInstrInfo.h:34
llvm::SparcInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SparcInstrInfo.cpp:493
llvm::SparcInstrInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction *MF) const
Definition: SparcInstrInfo.cpp:471
llvm::SparcInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SparcInstrInfo.cpp:434
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SparcInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SparcInstrInfo.cpp:297
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23