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28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "SparcGenInstrInfo.inc"
32 void SparcInstrInfo::anchor() {}
45 if (
MI.getOpcode() == SP::LDri ||
MI.getOpcode() == SP::LDXri ||
46 MI.getOpcode() == SP::LDFri ||
MI.getOpcode() == SP::LDDFri ||
47 MI.getOpcode() == SP::LDQFri) {
48 if (
MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() &&
49 MI.getOperand(2).getImm() == 0) {
51 return MI.getOperand(0).getReg();
64 if (
MI.getOpcode() == SP::STri ||
MI.getOpcode() == SP::STXri ||
65 MI.getOpcode() == SP::STFri ||
MI.getOpcode() == SP::STDFri ||
66 MI.getOpcode() == SP::STQFri) {
67 if (
MI.getOperand(0).isFI() &&
MI.getOperand(1).isImm() &&
68 MI.getOperand(1).getImm() == 0) {
70 return MI.getOperand(2).getReg();
146 return Opc == SP::FBCOND || Opc == SP::BCOND;
150 return Opc == SP::BINDrr || Opc == SP::BINDri;
163 bool AllowModify)
const {
168 if (!isUnpredicatedTerminator(*
I))
173 unsigned LastOpc = LastInst->
getOpcode();
176 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
191 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
198 LastInst = SecondLastInst;
200 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
205 SecondLastInst = &*
I;
206 SecondLastOpc = SecondLastInst->
getOpcode();
212 if (SecondLastInst &&
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
234 I->eraseFromParent();
247 int *BytesAdded)
const {
248 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
250 "Sparc branch conditions should have one component!");
251 assert(!BytesAdded &&
"code size not handled");
254 assert(!FBB &&
"Unconditional branch with multiple successors!");
260 unsigned CC =
Cond[0].getImm();
274 int *BytesRemoved)
const {
275 assert(!BytesRemoved &&
"code size not handled");
282 if (
I->isDebugInstr())
285 if (
I->getOpcode() != SP::BA
286 &&
I->getOpcode() != SP::BCOND
287 &&
I->getOpcode() != SP::FBCOND)
290 I->eraseFromParent();
309 unsigned numSubRegs = 0;
311 const unsigned *subRegIdx =
nullptr;
312 bool ExtraG0 =
false;
314 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
315 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
316 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
317 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
318 SP::sub_odd64_then_sub_even,
319 SP::sub_odd64_then_sub_odd };
321 if (SP::IntRegsRegClass.
contains(DestReg, SrcReg))
324 else if (SP::IntPairRegClass.
contains(DestReg, SrcReg)) {
325 subRegIdx = DW_SubRegsIdx;
329 }
else if (SP::FPRegsRegClass.
contains(DestReg, SrcReg))
332 else if (SP::DFPRegsRegClass.
contains(DestReg, SrcReg)) {
333 if (Subtarget.
isV9()) {
338 subRegIdx = DFP_FP_SubRegsIdx;
342 }
else if (SP::QFPRegsRegClass.
contains(DestReg, SrcReg)) {
343 if (Subtarget.
isV9()) {
349 subRegIdx = QFP_DFP_SubRegsIdx;
355 subRegIdx = QFP_FP_SubRegsIdx;
359 }
else if (SP::ASRRegsRegClass.
contains(DestReg) &&
360 SP::IntRegsRegClass.
contains(SrcReg)) {
364 }
else if (SP::IntRegsRegClass.
contains(DestReg) &&
365 SP::ASRRegsRegClass.
contains(SrcReg)) {
371 if (numSubRegs == 0 || subRegIdx ==
nullptr || movOpc == 0)
377 for (
unsigned i = 0;
i != numSubRegs; ++
i) {
380 assert(Dst && Src &&
"Bad sub-register");
396 Register SrcReg,
bool isKill,
int FI,
409 if (RC == &SP::I64RegsRegClass)
412 else if (RC == &SP::IntRegsRegClass)
415 else if (RC == &SP::IntPairRegClass)
418 else if (RC == &SP::FPRegsRegClass)
421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
447 if (RC == &SP::I64RegsRegClass)
450 else if (RC == &SP::IntRegsRegClass)
453 else if (RC == &SP::IntPairRegClass)
456 else if (RC == &SP::FPRegsRegClass)
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
483 Subtarget.
is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
494 switch (
MI.getOpcode()) {
495 case TargetOpcode::LOAD_STACK_GUARD: {
497 "Only Linux target is expected to contain LOAD_STACK_GUARD");
499 const int64_t Offset = Subtarget.
is64Bit() ? 0x28 : 0x14;
500 MI.setDesc(
get(Subtarget.
is64Bit() ? SP::LDXri : SP::LDri));
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
return AArch64::GPR64RegClass contains(Reg)
Target - Wrapper for Target specific information.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
SparcInstrInfo(SparcSubtarget &ST)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A description of a memory reference used in the backend.
static bool isCondBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
unsigned const TargetRegisterInfo * TRI
const MachineBasicBlock & front() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
static MachineOperand CreateImm(int64_t Val)
void setGlobalBaseReg(Register Reg)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineOperand & getOperand(unsigned i) const
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static bool isIndirectBranchOpcode(int Opc)
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock * getMBB() const
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator MBBI
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
@ MOLoad
The memory access reads data.
Wrapper class representing virtual and physical registers.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isTargetLinux() const
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
bool expandPostRAPseudo(MachineInstr &MI) const override
Should compile to something r4 addze r3 instead we get
Register getGlobalBaseReg(MachineFunction *MF) const
Register getGlobalBaseReg() const
@ MOStore
The memory access writes data.
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool IsIntegerCC(unsigned CC)
Wrapper class representing physical registers. Should be passed by value.