Go to the documentation of this file.
42 class X86AlignBranchKind {
44 uint8_t AlignBranchKind = 0;
47 void operator=(
const std::string &Val) {
67 <<
" to -x86-align-branch=; each element must be one of: fused, "
68 "jcc, jmp, call, ret, indirect.(plus separated)\n";
73 operator uint8_t()
const {
return AlignBranchKind; }
77 X86AlignBranchKind X86AlignBranchKindLoc;
80 "x86-align-branch-boundary",
cl::init(0),
82 "Control how the assembler should align branches with NOP. If the "
83 "boundary's size is not 0, it should be a power of 2 and no less "
84 "than 32. Branches will be aligned to prevent from being across or "
85 "against the boundary of specified size. The default value 0 does not "
91 "Specify types of branches to align (plus separated list of types):"
92 "\njcc indicates conditional jumps"
93 "\nfused indicates fused conditional jumps"
94 "\njmp indicates direct unconditional jumps"
95 "\ncall indicates direct and indirect calls"
96 "\nret indicates rets"
97 "\nindirect indicates indirect unconditional jumps"),
101 "x86-branches-within-32B-boundaries",
cl::init(
false),
103 "Align selected instructions to mitigate negative performance impact "
104 "of Intel's micro code update for errata skx102. May break "
105 "assumptions about labels corresponding to particular instructions, "
106 "and should be used with caution."));
109 "x86-pad-max-prefix-size",
cl::init(0),
110 cl::desc(
"Maximum number of prefixes to use for padding"));
114 cl::desc(
"Pad previous instructions to implement align directives"));
118 cl::desc(
"Pad previous instructions to implement branch alignment"));
122 std::unique_ptr<const MCInstrInfo> MCII;
123 X86AlignBranchKind AlignBranchType;
125 unsigned TargetPrefixMax = 0;
129 std::pair<MCFragment *, size_t> PrevInstPosition;
132 uint8_t determinePaddingPrefix(
const MCInst &Inst)
const;
134 bool needAlign(
const MCInst &Inst)
const;
142 if (X86AlignBranchWithin32BBoundaries) {
153 if (X86AlignBranchBoundary.getNumOccurrences())
155 if (X86AlignBranch.getNumOccurrences())
156 AlignBranchType = X86AlignBranchKindLoc;
157 if (X86PadMaxPrefixSize.getNumOccurrences())
158 TargetPrefixMax = X86PadMaxPrefixSize;
161 bool allowAutoPadding()
const override;
162 bool allowEnhancedRelaxation()
const override;
167 unsigned getNumFixupKinds()
const override {
183 bool mayNeedRelaxation(
const MCInst &Inst,
190 void relaxInstruction(
MCInst &Inst,
195 unsigned &RemainingSize)
const;
198 unsigned &RemainingSize)
const;
201 unsigned &RemainingSize)
const;
218 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
220 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
238 unsigned Opcode =
MI.getOpcode();
258 unsigned Opcode =
MI.getOpcode();
266 unsigned BaseReg =
MI.getOperand(BaseRegNum).getReg();
267 return (BaseReg == X86::RIP);
295 uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
297 "Prefixes can be added only in 32-bit or 64-bit mode.");
306 unsigned SegmentReg = 0;
343 if (BaseReg ==
X86::ESP || BaseReg == X86::EBP)
365 for (
auto &Operand :
MI) {
366 if (!Operand.isExpr())
368 const MCExpr &Expr = *Operand.getExpr();
376 bool X86AsmBackend::allowAutoPadding()
const {
380 bool X86AsmBackend::allowEnhancedRelaxation()
const {
381 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
408 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
413 for (; isa_and_nonnull<MCDataFragment>(
F);
F =
F->getPrevNode())
414 if (cast<MCDataFragment>(
F)->getContents().size() != 0)
427 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
428 return DF != PrevInstPosition.first ||
429 DF->getContents().size() != PrevInstPosition.second;
436 if (!
F || !
F->hasInstructions())
439 switch (
F->getKind()) {
443 return cast<MCDataFragment>(*F).getContents().size();
445 return cast<MCRelaxableFragment>(*F).getContents().size();
447 return cast<MCCompactEncodedInstFragment>(*F).getContents().size();
485 assert(allowAutoPadding() &&
"incorrect initialization!");
503 bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
518 CanPadInst = canPadInst(Inst, OS);
520 if (!canPadBranches(OS))
565 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
566 F->setAllowAutoPadding(CanPadInst);
568 if (!canPadBranches(OS))
571 if (!needAlign(Inst) || !PendingBA)
582 if (isa_and_nonnull<MCDataFragment>(CF))
596 #define ELF_RELOC(X, Y) .Case(#X, Y)
597 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
599 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
600 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
601 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
602 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
603 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
607 #define ELF_RELOC(X, Y) .Case(#X, Y)
608 #include "llvm/BinaryFormat/ELFRelocs/i386.def"
610 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
611 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
612 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
613 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
629 {
"reloc_signed_4byte", 0, 32, 0},
630 {
"reloc_signed_4byte_relax", 0, 32, 0},
631 {
"reloc_global_offset_table", 0, 32, 0},
632 {
"reloc_global_offset_table8", 0, 64, 0},
650 bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
700 assert(
Fixup.getOffset() + Size <=
Data.size() &&
"Invalid fixup offset!");
702 int64_t SignedValue =
static_cast<int64_t
>(
Value);
703 if ((
Target.isAbsolute() || IsResolved) &&
704 getFixupKindInfo(
Fixup.getKind()).Flags &
707 if (Size > 0 && !
isIntN(Size * 8, SignedValue))
708 Asm.getContext().reportError(
709 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
710 " is too large for field of " +
Twine(Size) +
711 ((
Size == 1) ?
" byte." :
" bytes."));
717 assert((Size == 0 ||
isIntN(Size * 8 + 1, SignedValue)) &&
718 "Value does not fit in the Fixup field");
721 for (
unsigned i = 0;
i !=
Size; ++
i)
725 bool X86AsmBackend::mayNeedRelaxation(
const MCInst &Inst,
745 bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &Fixup,
755 void X86AsmBackend::relaxInstruction(
MCInst &Inst,
783 unsigned &RemainingSize)
const {
797 const unsigned MaxPossiblePad =
std::min(15 - OldSize, RemainingSize);
798 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
802 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
809 unsigned ExistingPrefixSize =
Code.size();
810 if (TargetPrefixMax <= ExistingPrefixSize)
812 return TargetPrefixMax - ExistingPrefixSize;
814 const unsigned PrefixBytesToAdd =
815 std::min(MaxPossiblePad, RemainingPrefixSize);
816 if (PrefixBytesToAdd == 0)
828 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
831 RemainingSize -= PrefixBytesToAdd;
837 unsigned &RemainingSize)
const {
851 const unsigned NewSize =
Code.size();
852 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
853 unsigned Delta = NewSize - OldSize;
854 if (Delta > RemainingSize)
859 RemainingSize -= Delta;
865 unsigned &RemainingSize)
const {
866 bool Changed =
false;
867 if (RemainingSize != 0)
868 Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);
869 if (RemainingSize != 0)
870 Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);
882 if (!X86PadForAlign && !X86PadForBranchAlign)
890 LabeledFragments.
insert(
S.getFragment(
false));
900 if (LabeledFragments.
count(&
F))
909 auto &RF = cast<MCRelaxableFragment>(*
I);
910 Relaxable.push_back(&RF);
915 switch (
F.getKind()) {
919 return X86PadForAlign;
921 return X86PadForBranchAlign;
933 const uint64_t OrigSize =
Asm.computeFragmentSize(Layout,
F);
940 unsigned RemainingSize = OrigSize;
941 while (!Relaxable.empty() && RemainingSize != 0) {
946 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
947 FirstChangedFragment = &RF;
960 if (FirstChangedFragment) {
969 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
973 const uint64_t FinalSize =
Asm.computeFragmentSize(Layout,
F);
974 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
975 "can't move start of next fragment!");
976 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
982 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
983 const MCFragment *LastFragment = BF->getLastFragment();
986 while (&*
I != LastFragment)
996 Asm.computeFragmentSize(Layout, *
Section.getFragmentList().rbegin());
1000 unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
1022 static const char Nops32Bit[10][11] = {
1032 "\x0f\x1f\x44\x00\x00",
1034 "\x66\x0f\x1f\x44\x00\x00",
1036 "\x0f\x1f\x80\x00\x00\x00\x00",
1038 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1040 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1042 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1046 static const char Nops16Bit[4][11] = {
1057 const char(*Nops)[11] =
1065 const uint8_t ThisNopLength = (uint8_t)
std::min(Count, MaxNopLength);
1066 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1067 for (uint8_t
i = 0;
i < Prefixes;
i++)
1069 const uint8_t Rest = ThisNopLength - Prefixes;
1071 OS.
write(Nops[Rest - 1], Rest);
1072 Count -= ThisNopLength;
1073 }
while (Count != 0);
1082 class ELFX86AsmBackend :
public X86AsmBackend {
1086 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1089 class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1091 ELFX86_32AsmBackend(
const Target &
T, uint8_t OSABI,
1093 : ELFX86AsmBackend(
T, OSABI, STI) {}
1095 std::unique_ptr<MCObjectTargetWriter>
1096 createObjectTargetWriter()
const override {
1101 class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1103 ELFX86_X32AsmBackend(
const Target &
T, uint8_t OSABI,
1105 : ELFX86AsmBackend(
T, OSABI, STI) {}
1107 std::unique_ptr<MCObjectTargetWriter>
1108 createObjectTargetWriter()
const override {
1114 class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1116 ELFX86_IAMCUAsmBackend(
const Target &
T, uint8_t OSABI,
1118 : ELFX86AsmBackend(
T, OSABI, STI) {}
1120 std::unique_ptr<MCObjectTargetWriter>
1121 createObjectTargetWriter()
const override {
1127 class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1129 ELFX86_64AsmBackend(
const Target &
T, uint8_t OSABI,
1131 : ELFX86AsmBackend(
T, OSABI, STI) {}
1133 std::unique_ptr<MCObjectTargetWriter>
1134 createObjectTargetWriter()
const override {
1139 class WindowsX86AsmBackend :
public X86AsmBackend {
1145 : X86AsmBackend(
T, STI)
1157 std::unique_ptr<MCObjectTargetWriter>
1158 createObjectTargetWriter()
const override {
1169 UNWIND_MODE_BP_FRAME = 0x01000000,
1172 UNWIND_MODE_STACK_IMMD = 0x02000000,
1175 UNWIND_MODE_STACK_IND = 0x03000000,
1178 UNWIND_MODE_DWARF = 0x04000000,
1181 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1184 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1189 class DarwinX86AsmBackend :
public X86AsmBackend {
1193 enum { CU_NUM_SAVED_REGS = 6 };
1195 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1199 unsigned OffsetSize;
1200 unsigned MoveInstrSize;
1201 unsigned StackDivide;
1204 unsigned PushInstrSize(
unsigned Reg)
const {
1227 int getCompactUnwindRegNum(
unsigned Reg)
const {
1228 static const MCPhysReg CU32BitRegs[7] = {
1231 static const MCPhysReg CU64BitRegs[] = {
1232 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1234 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1235 for (
int Idx = 1; *CURegs; ++CURegs, ++Idx)
1244 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1249 for (
int i = 0, Idx = 0;
i != CU_NUM_SAVED_REGS; ++
i) {
1250 unsigned Reg = SavedRegs[
i];
1251 if (
Reg == 0)
break;
1253 int CURegNum = getCompactUnwindRegNum(
Reg);
1254 if (CURegNum == -1)
return ~0U;
1258 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
1261 assert((RegEnc & 0x3FFFF) == RegEnc &&
1262 "Invalid compact register encoding!");
1269 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1283 for (
unsigned i = 0;
i < RegCount; ++
i) {
1284 int CUReg = getCompactUnwindRegNum(SavedRegs[
i]);
1285 if (CUReg == -1)
return ~0U;
1286 SavedRegs[
i] = CUReg;
1290 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1292 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1293 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount;
i < CU_NUM_SAVED_REGS; ++
i){
1294 unsigned Countless = 0;
1295 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j <
i; ++
j)
1296 if (SavedRegs[
j] < SavedRegs[
i])
1299 RenumRegs[
i] = SavedRegs[
i] - Countless - 1;
1306 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1307 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1311 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1312 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1316 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1317 + 3 * RenumRegs[4] + RenumRegs[5];
1320 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1324 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1327 permutationEncoding |= RenumRegs[5];
1331 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1332 "Invalid compact register encoding!");
1333 return permutationEncoding;
1339 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1340 Is64Bit(
TT.isArch64Bit()) {
1341 memset(SavedRegs, 0,
sizeof(SavedRegs));
1342 OffsetSize = Is64Bit ? 8 : 4;
1343 MoveInstrSize = Is64Bit ? 3 : 2;
1344 StackDivide = Is64Bit ? 8 : 4;
1347 std::unique_ptr<MCObjectTargetWriter>
1348 createObjectTargetWriter()
const override {
1358 if (Instrs.
empty())
return 0;
1361 unsigned SavedRegIdx = 0;
1362 memset(SavedRegs, 0,
sizeof(SavedRegs));
1367 uint32_t CompactUnwindEncoding = 0;
1369 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1370 unsigned InstrOffset = 0;
1371 unsigned StackAdjust = 0;
1372 unsigned StackSize = 0;
1376 switch (Inst.getOperation()) {
1392 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1393 (Is64Bit ? X86::RBP : X86::EBP))
1397 memset(SavedRegs, 0,
sizeof(SavedRegs));
1401 InstrOffset += MoveInstrSize;
1419 StackSize = Inst.getOffset() / StackDivide;
1435 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1438 return CU::UNWIND_MODE_DWARF;
1440 unsigned Reg = *
MRI.getLLVMRegNum(Inst.getRegister(),
true);
1441 SavedRegs[SavedRegIdx++] =
Reg;
1442 StackAdjust += OffsetSize;
1443 MinAbsOffset =
std::min(MinAbsOffset,
abs(Inst.getOffset()));
1444 InstrOffset += PushInstrSize(
Reg);
1450 StackAdjust /= StackDivide;
1453 if ((StackAdjust & 0xFF) != StackAdjust)
1455 return CU::UNWIND_MODE_DWARF;
1459 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1460 return CU::UNWIND_MODE_DWARF;
1463 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1464 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1466 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1467 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1468 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1470 SubtractInstrIdx += InstrOffset;
1473 if ((StackSize & 0xFF) == StackSize) {
1475 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1478 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1480 if ((StackAdjust & 0x7) != StackAdjust)
1482 return CU::UNWIND_MODE_DWARF;
1485 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1489 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1492 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1497 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1501 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1502 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1505 CompactUnwindEncoding |=
1506 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1509 return CompactUnwindEncoding;
1521 return new DarwinX86AsmBackend(
T,
MRI, STI);
1524 return new WindowsX86AsmBackend(
T,
false, STI);
1529 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1531 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1540 return new DarwinX86AsmBackend(
T,
MRI, STI);
1543 return new WindowsX86AsmBackend(
T,
true, STI);
1547 if (TheTriple.
isX32())
1548 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1549 return new ELFX86_64AsmBackend(
T, OSABI, STI);
StringSwitch & Case(StringLiteral S, T Value)
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
This is an optimization pass for GlobalISel generic memory operations.
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
@ FK_PCRel_8
A eight-byte pc relative fixup.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
LocationClass< Ty > location(Ty &L)
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
LLVM_NODISCARD R Default(T Value)
static bool is64Bit(const char *name)
unsigned getRelaxedOpcodeArith(unsigned ShortOp)
Get the relaxed instruction opcode for a given short opcode.
Target - Wrapper for Target specific information.
virtual void emitPrefix(const MCInst &Inst, raw_ostream &OS, const MCSubtargetInfo &STI) const
Emit the prefixes of given instruction on the output stream.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
Triple - Helper class for working with autoconf configuration names.
static MCInstrInfo * createMCInstrInfo()
The instances of the Type class are immutable: once they are created, they are never changed.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
static unsigned getRelaxedOpcodeArith(const MCInst &Inst)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD T pop_back_val()
Instances of this class represent a single low-level machine instruction.
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
SmallVectorImpl< MCFixup > & getFixups()
std::pair< iterator, bool > insert(const ValueT &V)
bool getAllowAutoPadding() const
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
unsigned getNumOperands() const
bool empty() const
empty - Check if the array is empty.
@ FK_PCRel_1
A one-byte pc relative fixup.
Expected< uint32_t > getCPUType(const Triple &T)
@ reloc_signed_4byte_relax
void setOpcode(unsigned Op)
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_4
A four-byte fixup.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Generic interface to target specific assembler backends.
CompactUnwindEncodings
Compact unwind encoding values.
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
@ FK_SecRel_4
A four-byte section relative fixup.
bool hasFeature(unsigned Feature) const
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
const Triple & getTargetTriple() const
static size_t getSizeForInstFragment(const MCFragment *F)
static unsigned getFixupKindSize(unsigned Kind)
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ FK_SecRel_2
A two-byte section relative fixup.
Streaming object file generation interface.
void setInst(const MCInst &Value)
Describe properties that are true of each instruction in the target description file.
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
const FeatureBitset & getFeatureBits() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & write(unsigned char C)
const MCInst & getInst() const
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
MCFragment * getCurrentFragment() const
Expected< uint32_t > getCPUSubType(const Triple &T)
This struct is a compact representation of a valid (non-zero power of two) alignment.
ArchType getArch() const
Get the parsed architecture type of this triple.
MCSection * getCurrentSectionOnly() const
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
constexpr bool isInt< 8 >(int64_t x)
Implements a dense probed hash-table based set.
static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
bool isCall() const
Return true if the instruction is a call.
OSType getOS() const
Get the parsed operating system type of this triple.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
initializer< Ty > init(const Ty &Val)
void insert(MCFragment *F)
virtual Optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isFullyRelaxed(const MCRelaxableFragment &RF)
Return true if this instruction has been fully relaxed into it's most general available form.
Target independent information on a fixup kind.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
void setLastFragment(const MCFragment *F)
@ reloc_global_offset_table
MCAssembler & getAssembler()
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
unsigned getAlignment() const
PowerPC TLS Dynamic Call Fixup
StringRef - Represent a constant reference to a string, i.e.
static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool Is16BitMode)
bool isPrefix(uint64_t TSFlags)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
@ reloc_global_offset_table8
Instances of this class represent a uniqued identifier for a section in the current translation unit.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const Symbol *GOTSymbol)
Apply fixup expression for edge to block content.
@ FK_SecRel_1
A one-byte section relative fixup.
unsigned const MachineRegisterInfo * MRI
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
@ reloc_riprel_4byte_relax
bool isOSWindows() const
Tests whether the OS is Windows.
void setAlignment(Align Value)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Interface to description of machine instruction set.
Encapsulates the layout of an assembly file at a particular point in time.
MCCodeEmitter - Generic instruction encoding interface.
Iterator for intrusive lists based on ilist_node.
uint64_t value() const
This is a hole in the type system and should not be abused.
@ reloc_riprel_4byte_movq_load
@ FK_SecRel_8
A eight-byte section relative fixup.
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
unsigned getOpcode() const
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
SecondMacroFusionInstKind
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
bool getAllowAutoPadding() const
SectionKind getKind() const
MCFixupKind
Extensible enumeration to represent the type of a fixup.
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
@ FK_Data_8
A eight-byte fixup.
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
@ SymbolRef
References to labels and assigned expressions.
static unsigned getRelaxedOpcode(const MCInst &Inst, bool Is16BitMode)
const MCOperand & getOperand(unsigned i) const
bool isX32() const
Tests whether the target is X32.
Align max(MaybeAlign Lhs, Align Rhs)
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
A raw_ostream that writes to an SmallVector or SmallString.
static bool hasInterruptDelaySlot(const MCInst &Inst)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
A switch()-like statement whose cases are string literals.
bool isReturn() const
Return true if the instruction is a return.
This represents an "assembler immediate".
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
@ reloc_riprel_4byte_relax_rex
@ FK_Data_2
A two-byte fixup.
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Fragment for data and encoded instructions.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
bool isBundlingEnabled() const
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
@ reloc_branch_4byte_pcrel
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
SmallVectorImpl< char > & getContents()
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
unsigned getReg() const
Returns the register number.
Represents required padding such that a particular other set of fragments does not cross a particular...