35 #define DEBUG_TYPE "mccodeemitter"
45 : MCII(mcii), Ctx(ctx) {}
46 X86MCCodeEmitter(
const X86MCCodeEmitter &) =
delete;
47 X86MCCodeEmitter &operator=(
const X86MCCodeEmitter &) =
delete;
48 ~X86MCCodeEmitter()
override =
default;
58 unsigned getX86RegNum(
const MCOperand &MO)
const;
60 unsigned getX86RegEncoding(
const MCInst &
MI,
unsigned OpNum)
const;
66 bool isREXExtendedReg(
const MCInst &
MI,
unsigned OpNum)
const;
68 void emitImmediate(
const MCOperand &Disp,
SMLoc Loc,
unsigned ImmSize,
72 void emitRegModRMByte(
const MCOperand &ModRMReg,
unsigned RegOpcodeFld,
75 void emitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
78 void emitMemModRMByte(
const MCInst &
MI,
unsigned Op,
unsigned RegOpcodeField,
79 uint64_t TSFlags,
bool HasREX, uint64_t StartByte,
82 bool ForceSIB =
false)
const;
84 bool emitPrefixImpl(
unsigned &CurOp,
const MCInst &
MI,
87 void emitVEXOpcodePrefix(
int MemOperand,
const MCInst &
MI,
90 void emitSegmentOverridePrefix(
unsigned SegOperand,
const MCInst &
MI,
93 bool emitOpcodePrefix(
int MemOperand,
const MCInst &
MI,
96 bool emitREXPrefix(
int MemOperand,
const MCInst &
MI,
102 static uint8_t
modRMByte(
unsigned Mod,
unsigned RegOpcode,
unsigned RM) {
103 assert(
Mod < 4 && RegOpcode < 8 &&
RM < 8 &&
"ModRM Fields out of range!");
104 return RM | (RegOpcode << 3) | (
Mod << 6);
111 for (
unsigned i = 0;
i !=
Size; ++
i) {
125 if (!HasEVEX || CD8_Scale == 0)
129 if (
Value & (CD8_Scale - 1))
132 int CDisp8 =
Value / CD8_Scale;
137 ImmOffset = CDisp8 -
Value;
166 unsigned BaseReg = Base.
getReg();
167 unsigned IndexReg =
Index.getReg();
169 if (STI.
hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0)
172 X86MCRegisterClasses[X86::GR16RegClassID].
contains(BaseReg)) ||
174 X86MCRegisterClasses[X86::GR16RegClassID].
contains(IndexReg)))
186 if ((BaseReg.
getReg() != 0 &&
187 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.
getReg())) ||
188 (IndexReg.
getReg() != 0 &&
189 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.
getReg())))
191 if (BaseReg.
getReg() == X86::EIP) {
192 assert(IndexReg.
getReg() == 0 &&
"Invalid eip-based address.");
195 if (IndexReg.
getReg() == X86::EIZ)
208 if ((BaseReg.
getReg() != 0 &&
209 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.
getReg())) ||
210 (IndexReg.
getReg() != 0 &&
211 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.
getReg())))
226 const MCExpr *RHS =
nullptr;
238 if (
S.getName() !=
"_GLOBAL_OFFSET_TABLE_")
254 unsigned Opcode =
MI.getOpcode();
256 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
257 Opcode != X86::JCC_4) ||
270 unsigned X86MCCodeEmitter::getX86RegNum(
const MCOperand &MO)
const {
271 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg()) & 0x7;
274 unsigned X86MCCodeEmitter::getX86RegEncoding(
const MCInst &
MI,
275 unsigned OpNum)
const {
276 return Ctx.getRegisterInfo()->getEncodingValue(
MI.getOperand(OpNum).getReg());
283 bool X86MCCodeEmitter::isREXExtendedReg(
const MCInst &
MI,
284 unsigned OpNum)
const {
285 return (getX86RegEncoding(
MI, OpNum) >> 3) & 1;
288 void X86MCCodeEmitter::emitImmediate(
const MCOperand &DispOp,
SMLoc Loc,
292 int ImmOffset)
const {
293 const MCExpr *Expr =
nullptr;
294 if (DispOp.
isImm()) {
322 ImmOffset =
static_cast<int>(OS.
tell() - StartByte);
366 void X86MCCodeEmitter::emitRegModRMByte(
const MCOperand &ModRMReg,
367 unsigned RegOpcodeFld,
372 void X86MCCodeEmitter::emitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
378 void X86MCCodeEmitter::emitMemModRMByte(
const MCInst &
MI,
unsigned Op,
379 unsigned RegOpcodeField,
380 uint64_t TSFlags,
bool HasREX,
384 bool ForceSIB)
const {
389 unsigned BaseReg = Base.
getReg();
392 if (BaseReg == X86::RIP ||
393 BaseReg == X86::EIP) {
395 "Rip-relative addressing requires 64-bit mode");
397 "Invalid rip-relative address");
400 unsigned Opcode =
MI.getOpcode();
404 if (!(Disp.
isExpr() && isa<MCSymbolRefExpr>(Disp.
getExpr())))
430 case X86::TAILJMPm64:
461 unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
478 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
479 unsigned RMfield = R16Table[BaseRegNo];
481 assert(RMfield &&
"invalid 16-bit base register");
484 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
486 assert(IndexReg16 &&
"invalid 16-bit index register");
488 assert(((IndexReg16 ^ RMfield) & 2) &&
489 "invalid 16-bit base/index register combination");
491 "invalid scale for 16-bit memory reference");
495 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
497 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
501 if (Disp.
getImm() == 0 && RMfield != 6) {
514 assert(IndexReg.
getReg() == 0 &&
"Unexpected index register!");
529 bool AllowNoDisp = !UseDisp8 && !UseDisp32;
531 bool AllowDisp8 = !UseDisp32;
536 !ForceSIB && IndexReg.
getReg() == 0 &&
543 (!STI.
hasFeature(X86::Mode64Bit) || BaseReg != 0)) {
556 if (Disp.
isImm() && Disp.
getImm() == 0 && AllowNoDisp) {
563 auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.
getExpr());
578 if (Disp.
isImm() && AllowDisp8) {
592 unsigned Opcode =
MI.getOpcode();
602 "Cannot use ESP as index reg!");
604 bool ForceDisp32 =
false;
605 bool ForceDisp8 =
false;
613 }
else if (Disp.
isImm() && Disp.
getImm() == 0 && AllowNoDisp &&
621 }
else if (Disp.
isImm() && AllowDisp8 &&
635 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
636 unsigned SS = SSTable[Scale.
getImm()];
638 unsigned IndexRegNo = IndexReg.
getReg() ? getX86RegNum(IndexReg) : 4;
640 emitSIBByte(
SS, IndexRegNo, BaseRegNo, OS);
646 else if (ForceDisp32)
654 bool X86MCCodeEmitter::emitPrefixImpl(
unsigned &CurOp,
const MCInst &
MI,
657 uint64_t TSFlags = MCII.get(
MI.getOpcode()).TSFlags;
661 if (MemoryOperand != -1) {
662 MemoryOperand += CurOp;
667 unsigned Flags =
MI.getFlags();
674 bool NeedAddressOverride;
679 NeedAddressOverride =
true;
680 }
else if (MemoryOperand < 0) {
681 NeedAddressOverride =
false;
694 if (NeedAddressOverride)
701 emitVEXOpcodePrefix(MemoryOperand,
MI, OS);
703 HasREX = emitOpcodePrefix(MemoryOperand,
MI, STI, OS);
710 unsigned siReg =
MI.getOperand(1).getReg();
713 (siReg == X86::RSI &&
MI.getOperand(0).getReg() == X86::RDI)) &&
714 "SI and DI register sizes do not match");
716 if (
MI.getOperand(2).getReg() !=
X86::DS)
717 emitSegmentOverridePrefix(2,
MI, OS);
726 unsigned siReg =
MI.getOperand(0).getReg();
728 if (
MI.getOperand(1).getReg() !=
X86::DS)
729 emitSegmentOverridePrefix(1,
MI, OS);
738 unsigned siReg =
MI.getOperand(0).getReg();
741 (STI.
hasFeature(X86::Mode32Bit) && siReg == X86::DI))
748 emitSegmentOverridePrefix(1,
MI, OS);
757 void X86MCCodeEmitter::emitVEXOpcodePrefix(
int MemOperand,
const MCInst &
MI,
760 uint64_t TSFlags = Desc.
TSFlags;
776 uint8_t EVEX_R2 = 0x1;
833 uint8_t EVEX_V2 = 0x1;
870 uint8_t EVEX_z = (HasEVEX_K && (TSFlags &
X86II::EVEX_Z)) ? 1 : 0;
879 uint8_t EVEX_aaa = 0;
881 bool EncodeRC =
false;
902 VEX_B = ~(BaseRegEnc >> 3) & 1;
903 unsigned IndexRegEnc =
905 VEX_X = ~(IndexRegEnc >> 3) & 1;
907 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
912 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
915 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
917 EVEX_V2 = ~(VRegEnc >> 4) & 1;
920 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
921 VEX_R = ~(RegEnc >> 3) & 1;
922 EVEX_R2 = ~(RegEnc >> 4) & 1;
935 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
936 VEX_R = ~(RegEnc >> 3) & 1;
937 EVEX_R2 = ~(RegEnc >> 4) & 1;
940 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
943 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
945 EVEX_V2 = ~(VRegEnc >> 4) & 1;
949 VEX_B = ~(BaseRegEnc >> 3) & 1;
950 unsigned IndexRegEnc =
952 VEX_X = ~(IndexRegEnc >> 3) & 1;
954 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
961 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
962 VEX_R = ~(RegEnc >> 3) & 1;
965 VEX_B = ~(BaseRegEnc >> 3) & 1;
966 unsigned IndexRegEnc =
968 VEX_X = ~(IndexRegEnc >> 3) & 1;
975 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
976 VEX_R = ~(RegEnc >> 3) & 1;
978 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
982 VEX_B = ~(BaseRegEnc >> 3) & 1;
983 unsigned IndexRegEnc =
985 VEX_X = ~(IndexRegEnc >> 3) & 1;
1000 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1002 EVEX_V2 = ~(VRegEnc >> 4) & 1;
1006 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
1009 VEX_B = ~(BaseRegEnc >> 3) & 1;
1010 unsigned IndexRegEnc =
1012 VEX_X = ~(IndexRegEnc >> 3) & 1;
1014 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
1026 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1027 VEX_R = ~(RegEnc >> 3) & 1;
1028 EVEX_R2 = ~(RegEnc >> 4) & 1;
1031 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
1034 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1036 EVEX_V2 = ~(VRegEnc >> 4) & 1;
1039 RegEnc = getX86RegEncoding(
MI, CurOp++);
1040 VEX_B = ~(RegEnc >> 3) & 1;
1041 VEX_X = ~(RegEnc >> 4) & 1;
1045 unsigned RcOperand = NumOps - 1;
1046 assert(RcOperand >= CurOp);
1047 EVEX_rc =
MI.getOperand(RcOperand).getImm();
1048 assert(EVEX_rc <= 3 &&
"Invalid rounding control!");
1057 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1058 VEX_R = ~(RegEnc >> 3) & 1;
1060 RegEnc = getX86RegEncoding(
MI, CurOp++);
1061 VEX_B = ~(RegEnc >> 3) & 1;
1063 VEX_4V = ~getX86RegEncoding(
MI, CurOp++) & 0xf;
1068 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1069 VEX_R = ~(RegEnc >> 3) & 1;
1071 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1077 RegEnc = getX86RegEncoding(
MI, CurOp++);
1078 VEX_B = ~(RegEnc >> 3) & 1;
1079 VEX_X = ~(RegEnc >> 4) & 1;
1087 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1088 VEX_B = ~(RegEnc >> 3) & 1;
1089 VEX_X = ~(RegEnc >> 4) & 1;
1092 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
1095 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1097 EVEX_V2 = ~(VRegEnc >> 4) & 1;
1100 RegEnc = getX86RegEncoding(
MI, CurOp++);
1101 VEX_R = ~(RegEnc >> 3) & 1;
1102 EVEX_R2 = ~(RegEnc >> 4) & 1;
1111 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1112 VEX_R = ~(RegEnc >> 3) & 1;
1113 EVEX_R2 = ~(RegEnc >> 4) & 1;
1127 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1129 EVEX_V2 = ~(VRegEnc >> 4) & 1;
1132 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
1134 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1135 VEX_B = ~(RegEnc >> 3) & 1;
1136 VEX_X = ~(RegEnc >> 4) & 1;
1157 uint8_t LastByte = VEX_PP | (
VEX_L << 2) | (
VEX_4V << 3);
1161 VEX_B && VEX_X && !
VEX_W && (VEX_5M == 1)) {
1163 emitByte(LastByte | (VEX_R << 7), OS);
1169 emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, OS);
1179 "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
1182 emitByte((VEX_R << 7) | (VEX_X << 6) | (VEX_B << 5) | (EVEX_R2 << 4) |
1187 emitByte((EVEX_z << 7) | (EVEX_rc << 5) | (EVEX_b << 4) | (EVEX_V2 << 3) |
1192 (EVEX_V2 << 3) | EVEX_aaa,
1203 bool X86MCCodeEmitter::emitREXPrefix(
int MemOperand,
const MCInst &
MI,
1206 uint8_t REX = [&, MemOperand]() {
1208 bool UsesHighByteReg =
false;
1211 uint64_t TSFlags = Desc.
TSFlags;
1216 if (
MI.getNumOperands() == 0)
1219 unsigned NumOps =
MI.getNumOperands();
1223 for (
unsigned i = CurOp;
i != NumOps; ++
i) {
1229 UsesHighByteReg =
true;
1234 }
else if (MO.
isExpr() &&
1241 const auto *
Ref = dyn_cast<MCSymbolRefExpr>(MO.
getExpr());
1251 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1255 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1256 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1260 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1266 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1267 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1273 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1298 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1301 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1306 if (REX && UsesHighByteReg)
1308 "Cannot encode high byte register in REX-prefixed instruction");
1320 void X86MCCodeEmitter::emitSegmentOverridePrefix(
unsigned SegOperand,
1324 if (
unsigned Reg =
MI.getOperand(SegOperand).getReg())
1334 bool X86MCCodeEmitter::emitOpcodePrefix(
int MemOperand,
const MCInst &
MI,
1338 uint64_t TSFlags = Desc.
TSFlags;
1367 "REX.W requires 64bit mode.");
1369 ? emitREXPrefix(MemOperand,
MI, STI, OS)
1396 unsigned Opcode =
MI.getOpcode();
1398 uint64_t TSFlags = Desc.
TSFlags;
1406 emitPrefixImpl(CurOp,
MI, STI, OS);
1412 unsigned Opcode =
MI.getOpcode();
1414 uint64_t TSFlags = Desc.
TSFlags;
1423 uint64_t StartByte = OS.
tell();
1425 bool HasREX = emitPrefixImpl(CurOp,
MI, STI, OS);
1436 unsigned I8RegNum = 0;
1443 unsigned OpcodeOffset = 0;
1448 errs() <<
"FORM: " <<
Form <<
"\n";
1460 OpcodeOffset =
MI.getOperand(NumOps - 1).getImm();
1461 assert(OpcodeOffset < 16 &&
"Unexpected opcode offset!");
1465 emitByte(BaseOpcode + OpcodeOffset, OS);
1478 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1485 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1488 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(), 1,
FK_Data_1, StartByte,
1493 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1496 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(), 2,
FK_Data_2, StartByte,
1501 emitByte(BaseOpcode + getX86RegNum(
MI.getOperand(CurOp++)), OS);
1506 unsigned SrcRegNum = CurOp + 1;
1514 emitRegModRMByte(
MI.getOperand(CurOp),
1515 getX86RegNum(
MI.getOperand(SrcRegNum)), OS);
1516 CurOp = SrcRegNum + 1;
1531 emitMemModRMByte(
MI, CurOp, getX86RegNum(
MI.getOperand(SrcRegNum)), TSFlags,
1532 HasREX, StartByte, OS,
Fixups, STI, ForceSIB);
1533 CurOp = SrcRegNum + 1;
1538 unsigned SrcRegNum = CurOp + 1;
1546 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1547 getX86RegNum(
MI.getOperand(CurOp)), OS);
1548 CurOp = SrcRegNum + 1;
1550 I8RegNum = getX86RegEncoding(
MI, CurOp++);
1558 unsigned SrcRegNum = CurOp + 1;
1560 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1561 getX86RegNum(
MI.getOperand(CurOp)), OS);
1562 CurOp = SrcRegNum + 1;
1568 unsigned SrcRegNum = CurOp + 1;
1574 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1575 I8RegNum = getX86RegEncoding(
MI, SrcRegNum++);
1577 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1578 getX86RegNum(
MI.getOperand(CurOp)), OS);
1579 CurOp = SrcRegNum + 1;
1583 unsigned FirstOp = CurOp++;
1584 unsigned SecondOp = CurOp++;
1586 unsigned CC =
MI.getOperand(CurOp++).getImm();
1589 emitRegModRMByte(
MI.getOperand(SecondOp),
1590 getX86RegNum(
MI.getOperand(FirstOp)), OS);
1595 unsigned FirstMemOp = CurOp + 1;
1606 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1607 TSFlags, HasREX, StartByte, OS,
Fixups, STI, ForceSIB);
1610 I8RegNum = getX86RegEncoding(
MI, CurOp++);
1614 unsigned FirstMemOp = CurOp + 1;
1618 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1619 TSFlags, HasREX, StartByte, OS,
Fixups, STI);
1625 unsigned FirstMemOp = CurOp + 1;
1630 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1631 I8RegNum = getX86RegEncoding(
MI, FirstMemOp++);
1635 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1636 TSFlags, HasREX, StartByte, OS,
Fixups, STI);
1641 unsigned RegOp = CurOp++;
1642 unsigned FirstMemOp = CurOp;
1645 unsigned CC =
MI.getOperand(CurOp++).getImm();
1648 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(RegOp)),
1649 TSFlags, HasREX, StartByte, OS,
Fixups, STI);
1654 unsigned RegOp = CurOp++;
1656 unsigned CC =
MI.getOperand(CurOp++).getImm();
1658 emitRegModRMByte(
MI.getOperand(RegOp), 0, OS);
1676 emitRegModRMByte(
MI.getOperand(CurOp++),
1685 unsigned FirstMemOp = CurOp;
1688 unsigned CC =
MI.getOperand(CurOp++).getImm();
1691 emitMemModRMByte(
MI, FirstMemOp, 0, TSFlags, HasREX, StartByte, OS,
Fixups,
1710 emitMemModRMByte(
MI, CurOp,
1712 HasREX, StartByte, OS,
Fixups, STI);
1800 assert(I8RegNum < 16 &&
"Register encoding out of range");
1802 if (CurOp != NumOps) {
1803 unsigned Val =
MI.getOperand(CurOp++).getImm();
1804 assert(Val < 16 &&
"Immediate operand value out of range");
1813 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1814 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1824 "The size of instruction must be no longer than 15.");
1827 if ( CurOp != NumOps) {
1828 errs() <<
"Cannot encode all operands of: ";
1839 return new X86MCCodeEmitter(MCII, Ctx);