35#define DEBUG_TYPE "mccodeemitter"
39enum PrefixKind {
None, REX, XOP, VEX2, VEX3, EVEX };
43class X86OpcodePrefixHelper {
127 unsigned EVEX_R2 : 1;
129 unsigned EVEX_L2 : 1;
131 unsigned EVEX_V2 : 1;
132 unsigned EVEX_aaa : 3;
133 PrefixKind Kind =
None;
136 unsigned getRegEncoding(
const MCInst &
MI,
unsigned OpNum)
const {
137 return MRI.getEncodingValue(
MI.getOperand(OpNum).getReg());
140 void setR(
unsigned Encoding) { R = Encoding >> 3 & 1; }
141 void setR2(
unsigned Encoding) { EVEX_R2 = Encoding >> 4 & 1; }
142 void set4V(
unsigned Encoding) { VEX_4V = Encoding & 0xf; }
143 void setV2(
unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }
146 void setW(
bool V) { W = V; }
147 void setR(
const MCInst &
MI,
unsigned OpNum) {
148 setR(getRegEncoding(
MI, OpNum));
150 void setX(
const MCInst &
MI,
unsigned OpNum,
unsigned Shift = 3) {
151 X = getRegEncoding(
MI, OpNum) >> Shift & 1;
153 void setB(
const MCInst &
MI,
unsigned OpNum) {
154 B = getRegEncoding(
MI, OpNum) >> 3 & 1;
156 void set4V(
const MCInst &
MI,
unsigned OpNum) {
157 set4V(getRegEncoding(
MI, OpNum));
159 void setL(
bool V) { VEX_L = V; }
160 void setPP(
unsigned V) { VEX_PP = V; }
161 void set5M(
unsigned V) { VEX_5M = V; }
162 void setR2(
const MCInst &
MI,
unsigned OpNum) {
163 setR2(getRegEncoding(
MI, OpNum));
165 void setRR2(
const MCInst &
MI,
unsigned OpNum) {
166 unsigned Encoding = getRegEncoding(
MI, OpNum);
170 void setZ(
bool V) { EVEX_z = V; }
171 void setL2(
bool V) { EVEX_L2 = V; }
172 void setEVEX_b(
bool V) { EVEX_b = V; }
173 void setV2(
const MCInst &
MI,
unsigned OpNum) {
174 setV2(getRegEncoding(
MI, OpNum));
176 void set4VV2(
const MCInst &
MI,
unsigned OpNum) {
177 unsigned Encoding = getRegEncoding(
MI, OpNum);
181 void setAAA(
const MCInst &
MI,
unsigned OpNum) {
182 EVEX_aaa = getRegEncoding(
MI, OpNum);
186 : W(0), R(0), X(0), B(0), VEX_4V(0), VEX_L(0), VEX_PP(0), VEX_5M(0),
187 EVEX_R2(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0), EVEX_aaa(0),
190 void setLowerBound(PrefixKind K) { Kind = K; }
192 PrefixKind determineOptimalKind() {
195 Kind = (W | R | X | B) ? REX :
None;
203 Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
210 uint8_t FirstPayload =
211 ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
212 uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
217 emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, CB);
221 emitByte(((~R) & 1) << 7 | LastPayload, CB);
225 emitByte(Kind == VEX3 ? 0xC4 : 0x8F, CB);
226 emitByte(FirstPayload | VEX_5M, CB);
227 emitByte(W << 7 | LastPayload, CB);
230 assert(VEX_5M && !(VEX_5M & 0x8) &&
"invalid mmm fields for EVEX!");
232 emitByte(FirstPayload | ((~EVEX_R2) & 0x1) << 4 | VEX_5M, CB);
233 emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | 1 << 2 | VEX_PP, CB);
234 emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
235 ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
248 : MCII(mcii), Ctx(ctx) {}
249 X86MCCodeEmitter(
const X86MCCodeEmitter &) =
delete;
250 X86MCCodeEmitter &
operator=(
const X86MCCodeEmitter &) =
delete;
251 ~X86MCCodeEmitter()
override =
default;
261 unsigned getX86RegNum(
const MCOperand &MO)
const;
263 unsigned getX86RegEncoding(
const MCInst &
MI,
unsigned OpNum)
const;
265 void emitImmediate(
const MCOperand &Disp,
SMLoc Loc,
unsigned ImmSize,
270 void emitRegModRMByte(
const MCOperand &ModRMReg,
unsigned RegOpcodeFld,
273 void emitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
276 void emitMemModRMByte(
const MCInst &
MI,
unsigned Op,
unsigned RegOpcodeField,
281 bool ForceSIB =
false)
const;
283 PrefixKind emitPrefixImpl(
unsigned &CurOp,
const MCInst &
MI,
287 PrefixKind emitVEXOpcodePrefix(
int MemOperand,
const MCInst &
MI,
291 void emitSegmentOverridePrefix(
unsigned SegOperand,
const MCInst &
MI,
294 PrefixKind emitOpcodePrefix(
int MemOperand,
const MCInst &
MI,
298 PrefixKind emitREXPrefix(
int MemOperand,
const MCInst &
MI,
305static uint8_t
modRMByte(
unsigned Mod,
unsigned RegOpcode,
unsigned RM) {
306 assert(
Mod < 4 && RegOpcode < 8 && RM < 8 &&
"ModRM Fields out of range!");
307 return RM | (RegOpcode << 3) | (
Mod << 6);
313 for (
unsigned i = 0; i !=
Size; ++i) {
314 emitByte(Val & 255, CB);
327 CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;
328 if (!HasEVEX || !CD8_Scale)
329 return isInt<8>(
Value);
332 if (
Value & (CD8_Scale - 1))
335 int CDisp8 =
Value /
static_cast<int>(CD8_Scale);
336 if (!isInt<8>(CDisp8))
340 ImmOffset = CDisp8 -
Value;
382 if (S.
getName() !=
"_GLOBAL_OFFSET_TABLE_")
398 unsigned Opcode =
MI.getOpcode();
400 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
401 Opcode != X86::JCC_4) ||
414unsigned X86MCCodeEmitter::getX86RegNum(
const MCOperand &MO)
const {
415 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg()) & 0x7;
418unsigned X86MCCodeEmitter::getX86RegEncoding(
const MCInst &
MI,
419 unsigned OpNum)
const {
420 return Ctx.getRegisterInfo()->getEncodingValue(
MI.getOperand(OpNum).getReg());
423void X86MCCodeEmitter::emitImmediate(
const MCOperand &DispOp,
SMLoc Loc,
428 int ImmOffset)
const {
429 const MCExpr *Expr =
nullptr;
430 if (DispOp.
isImm()) {
458 ImmOffset =
static_cast<int>(CB.
size() - StartByte);
498 Expr, FixupKind, Loc));
502void X86MCCodeEmitter::emitRegModRMByte(
const MCOperand &ModRMReg,
503 unsigned RegOpcodeFld,
505 emitByte(
modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CB);
508void X86MCCodeEmitter::emitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
514void X86MCCodeEmitter::emitMemModRMByte(
518 bool ForceSIB)
const {
523 unsigned BaseReg =
Base.getReg();
526 if (BaseReg == X86::RIP ||
527 BaseReg == X86::EIP) {
529 "Rip-relative addressing requires 64-bit mode");
531 "Invalid rip-relative address");
532 emitByte(
modRMByte(0, RegOpcodeField, 5), CB);
534 unsigned Opcode =
MI.getOpcode();
538 if (!(Disp.
isExpr() && isa<MCSymbolRefExpr>(Disp.
getExpr())))
564 case X86::TAILJMPm64:
590 emitImmediate(Disp,
MI.getLoc(), 4,
MCFixupKind(FixupKind), StartByte, CB,
595 unsigned BaseRegNo = BaseReg ? getX86RegNum(
Base) : -1U;
612 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
613 unsigned RMfield = R16Table[BaseRegNo];
615 assert(RMfield &&
"invalid 16-bit base register");
618 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
620 assert(IndexReg16 &&
"invalid 16-bit index register");
622 assert(((IndexReg16 ^ RMfield) & 2) &&
623 "invalid 16-bit base/index register combination");
625 "invalid scale for 16-bit memory reference");
629 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
631 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
635 if (Disp.
getImm() == 0 && RMfield != 6) {
637 emitByte(
modRMByte(0, RegOpcodeField, RMfield), CB);
641 emitByte(
modRMByte(1, RegOpcodeField, RMfield), CB);
642 emitImmediate(Disp,
MI.getLoc(), 1,
FK_Data_1, StartByte, CB, Fixups);
646 emitByte(
modRMByte(2, RegOpcodeField, RMfield), CB);
648 assert(IndexReg.
getReg() == 0 &&
"Unexpected index register!");
650 emitByte(
modRMByte(0, RegOpcodeField, 6), CB);
654 emitImmediate(Disp,
MI.getLoc(), 2,
FK_Data_2, StartByte, CB, Fixups);
663 bool AllowNoDisp = !UseDisp8 && !UseDisp32;
665 bool AllowDisp8 = !UseDisp32;
670 !ForceSIB && IndexReg.
getReg() == 0 &&
677 (!STI.
hasFeature(X86::Is64Bit) || BaseReg != 0)) {
680 emitByte(
modRMByte(0, RegOpcodeField, 5), CB);
681 emitImmediate(Disp,
MI.getLoc(), 4,
FK_Data_4, StartByte, CB, Fixups);
690 if (Disp.
isImm() && Disp.
getImm() == 0 && AllowNoDisp) {
691 emitByte(
modRMByte(0, RegOpcodeField, BaseRegNo), CB);
697 auto *
Sym = dyn_cast<MCSymbolRefExpr>(Disp.
getExpr());
702 emitByte(
modRMByte(0, RegOpcodeField, BaseRegNo), CB);
712 if (Disp.
isImm() && AllowDisp8) {
715 emitByte(
modRMByte(1, RegOpcodeField, BaseRegNo), CB);
716 emitImmediate(Disp,
MI.getLoc(), 1,
FK_Data_1, StartByte, CB, Fixups,
725 emitByte(
modRMByte(2, RegOpcodeField, BaseRegNo), CB);
726 unsigned Opcode =
MI.getOpcode();
729 emitImmediate(Disp,
MI.getLoc(), 4,
MCFixupKind(FixupKind), StartByte, CB,
736 "Cannot use ESP as index reg!");
738 bool ForceDisp32 =
false;
739 bool ForceDisp8 =
false;
745 emitByte(
modRMByte(0, RegOpcodeField, 4), CB);
747 }
else if (Disp.
isImm() && Disp.
getImm() == 0 && AllowNoDisp &&
754 emitByte(
modRMByte(0, RegOpcodeField, 4), CB);
755 }
else if (Disp.
isImm() && AllowDisp8 &&
760 emitByte(
modRMByte(1, RegOpcodeField, 4), CB);
764 emitByte(
modRMByte(2, RegOpcodeField, 4), CB);
769 static const unsigned SSTable[] = {~0
U, 0, 1, ~0
U, 2, ~0
U, ~0
U, ~0
U, 3};
770 unsigned SS = SSTable[Scale.
getImm()];
772 unsigned IndexRegNo = IndexReg.
getReg() ? getX86RegNum(IndexReg) : 4;
774 emitSIBByte(SS, IndexRegNo, BaseRegNo, CB);
778 emitImmediate(Disp,
MI.getLoc(), 1,
FK_Data_1, StartByte, CB, Fixups,
780 else if (ForceDisp32)
782 StartByte, CB, Fixups);
789PrefixKind X86MCCodeEmitter::emitPrefixImpl(
unsigned &CurOp,
const MCInst &
MI,
796 if (MemoryOperand != -1) {
797 MemoryOperand += CurOp;
802 unsigned Flags =
MI.getFlags();
819 if (
MI.getOperand(2).getReg() != X86::DS)
820 emitSegmentOverridePrefix(2,
MI, CB);
826 if (
MI.getOperand(1).getReg() != X86::DS)
827 emitSegmentOverridePrefix(1,
MI, CB);
837 emitSegmentOverridePrefix(1,
MI, CB);
845 ? emitVEXOpcodePrefix(MemoryOperand,
MI, STI, CB)
846 : emitOpcodePrefix(MemoryOperand,
MI, STI, CB);
863X86MCCodeEmitter::emitVEXOpcodePrefix(
int MemOperand,
const MCInst &
MI,
871 X86OpcodePrefixHelper
Prefix(*Ctx.getRegisterInfo());
876 Prefix.setLowerBound(XOP);
883 Prefix.setLowerBound(EVEX);
942 bool EncodeRC =
false;
1072 unsigned NumOps =
Desc.getNumOperands();
1073 unsigned RcOperand = NumOps - 1;
1074 assert(RcOperand >= CurOp);
1075 EVEX_rc =
MI.getOperand(RcOperand).getImm();
1076 assert(EVEX_rc <= 3 &&
"Invalid rounding control!");
1152 Prefix.setL(EVEX_rc & 0x1);
1153 Prefix.setL2(EVEX_rc & 0x2);
1155 PrefixKind
Kind =
Prefix.determineOptimalKind();
1166PrefixKind X86MCCodeEmitter::emitREXPrefix(
int MemOperand,
const MCInst &
MI,
1171 X86OpcodePrefixHelper
Prefix(*Ctx.getRegisterInfo());
1175 unsigned NumOps =
MI.getNumOperands();
1176 bool UsesHighByteReg =
false;
1178 bool HasRegOp =
false;
1181 for (
unsigned i = CurOp; i != NumOps; ++i) {
1188 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1189 UsesHighByteReg =
true;
1192 Prefix.setLowerBound(REX);
1199 const auto *
Ref = dyn_cast<MCSymbolRefExpr>(MO.
getExpr());
1202 Prefix.setLowerBound(REX);
1208 assert(!HasRegOp &&
"Unexpected form in emitREXPrefix!");
1267 PrefixKind
Kind =
Prefix.determineOptimalKind();
1268 if (Kind && UsesHighByteReg)
1270 "Cannot encode high byte register in REX-prefixed instruction");
1276void X86MCCodeEmitter::emitSegmentOverridePrefix(
1279 if (
unsigned Reg =
MI.getOperand(SegOperand).getReg())
1289PrefixKind X86MCCodeEmitter::emitOpcodePrefix(
int MemOperand,
const MCInst &
MI,
1322 "REX.W requires 64bit mode.");
1323 PrefixKind
Kind = emitREXPrefix(MemOperand,
MI, STI, CB);
1349 unsigned Opcode =
MI.getOpcode();
1359 emitPrefixImpl(CurOp,
MI, STI, CB);
1362void X86MCCodeEmitter::encodeInstruction(
const MCInst &
MI,
1366 unsigned Opcode =
MI.getOpcode();
1374 unsigned NumOps =
Desc.getNumOperands();
1379 PrefixKind
Kind = emitPrefixImpl(CurOp,
MI, STI, CB);
1390 unsigned I8RegNum = 0;
1397 unsigned OpcodeOffset = 0;
1402 errs() <<
"FORM: " <<
Form <<
"\n";
1410 emitByte(BaseOpcode, CB);
1414 OpcodeOffset =
MI.getOperand(NumOps - 1).getImm();
1415 assert(OpcodeOffset < 16 &&
"Unexpected opcode offset!");
1419 emitByte(BaseOpcode + OpcodeOffset, CB);
1431 emitByte(BaseOpcode, CB);
1432 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1434 StartByte, CB, Fixups);
1438 emitByte(BaseOpcode, CB);
1439 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1441 StartByte, CB, Fixups);
1442 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(), 1,
FK_Data_1, StartByte,
1446 emitByte(BaseOpcode, CB);
1447 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1449 StartByte, CB, Fixups);
1450 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(), 2,
FK_Data_2, StartByte,
1455 emitByte(BaseOpcode + getX86RegNum(
MI.getOperand(CurOp++)), CB);
1459 emitByte(BaseOpcode, CB);
1460 unsigned SrcRegNum = CurOp + 1;
1468 emitRegModRMByte(
MI.getOperand(CurOp),
1469 getX86RegNum(
MI.getOperand(SrcRegNum)), CB);
1470 CurOp = SrcRegNum + 1;
1474 unsigned CC =
MI.getOperand(8).getImm();
1475 emitByte(BaseOpcode +
CC, CB);
1477 emitMemModRMByte(
MI, CurOp + 1, getX86RegNum(
MI.getOperand(0)),
TSFlags,
1478 Kind, StartByte, CB, Fixups, STI,
false);
1479 CurOp = SrcRegNum + 3;
1484 emitByte(BaseOpcode, CB);
1494 emitMemModRMByte(
MI, CurOp, getX86RegNum(
MI.getOperand(SrcRegNum)),
TSFlags,
1495 Kind, StartByte, CB, Fixups, STI, ForceSIB);
1496 CurOp = SrcRegNum + 1;
1500 emitByte(BaseOpcode, CB);
1501 unsigned SrcRegNum = CurOp + 1;
1509 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1510 getX86RegNum(
MI.getOperand(CurOp)), CB);
1511 CurOp = SrcRegNum + 1;
1513 I8RegNum = getX86RegEncoding(
MI, CurOp++);
1520 emitByte(BaseOpcode, CB);
1521 unsigned SrcRegNum = CurOp + 1;
1523 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1524 getX86RegNum(
MI.getOperand(CurOp)), CB);
1525 CurOp = SrcRegNum + 1;
1530 emitByte(BaseOpcode, CB);
1531 unsigned SrcRegNum = CurOp + 1;
1537 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1538 I8RegNum = getX86RegEncoding(
MI, SrcRegNum++);
1540 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1541 getX86RegNum(
MI.getOperand(CurOp)), CB);
1542 CurOp = SrcRegNum + 1;
1546 unsigned FirstOp = CurOp++;
1547 unsigned SecondOp = CurOp++;
1549 unsigned CC =
MI.getOperand(CurOp++).getImm();
1550 emitByte(BaseOpcode +
CC, CB);
1552 emitRegModRMByte(
MI.getOperand(SecondOp),
1553 getX86RegNum(
MI.getOperand(FirstOp)), CB);
1558 unsigned FirstMemOp = CurOp + 1;
1566 emitByte(BaseOpcode, CB);
1569 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1570 TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);
1573 I8RegNum = getX86RegEncoding(
MI, CurOp++);
1577 unsigned FirstMemOp = CurOp + 1;
1579 emitByte(BaseOpcode, CB);
1581 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1582 TSFlags, Kind, StartByte, CB, Fixups, STI);
1588 unsigned FirstMemOp = CurOp + 1;
1593 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1594 I8RegNum = getX86RegEncoding(
MI, FirstMemOp++);
1596 emitByte(BaseOpcode, CB);
1598 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1599 TSFlags, Kind, StartByte, CB, Fixups, STI);
1604 unsigned RegOp = CurOp++;
1605 unsigned FirstMemOp = CurOp;
1608 unsigned CC =
MI.getOperand(CurOp++).getImm();
1609 emitByte(BaseOpcode +
CC, CB);
1611 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(RegOp)),
1612 TSFlags, Kind, StartByte, CB, Fixups, STI);
1617 unsigned RegOp = CurOp++;
1619 unsigned CC =
MI.getOperand(CurOp++).getImm();
1620 emitByte(BaseOpcode +
CC, CB);
1621 emitRegModRMByte(
MI.getOperand(RegOp), 0, CB);
1638 emitByte(BaseOpcode, CB);
1639 emitRegModRMByte(
MI.getOperand(CurOp++),
1643 emitByte(BaseOpcode, CB);
1644 emitByte(
modRMByte(3, getX86RegNum(
MI.getOperand(CurOp++)), 0), CB);
1648 unsigned FirstMemOp = CurOp;
1651 unsigned CC =
MI.getOperand(CurOp++).getImm();
1652 emitByte(BaseOpcode +
CC, CB);
1654 emitMemModRMByte(
MI, FirstMemOp, 0,
TSFlags, Kind, StartByte, CB, Fixups,
1672 emitByte(BaseOpcode, CB);
1673 emitMemModRMByte(
MI, CurOp,
1675 Kind, StartByte, CB, Fixups, STI);
1687 emitByte(BaseOpcode, CB);
1755 emitByte(BaseOpcode, CB);
1763 assert(I8RegNum < 16 &&
"Register encoding out of range");
1765 if (CurOp != NumOps) {
1766 unsigned Val =
MI.getOperand(CurOp++).getImm();
1767 assert(Val < 16 &&
"Immediate operand value out of range");
1771 StartByte, CB, Fixups);
1776 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1777 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1779 StartByte, CB, Fixups);
1787 "The size of instruction must be no longer than 15.");
1790 if ( CurOp != NumOps) {
1791 errs() <<
"Cannot encode all operands of: ";
1801 return new X86MCCodeEmitter(MCII, Ctx);
unsigned const MachineRegisterInfo * MRI
static bool isPCRel(unsigned Kind)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII)
static GlobalOffsetTableExprKind startsWithGlobalOffsetTable(const MCExpr *Expr)
Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is of the form GLOBAL_OFFSET_TABLE...
static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM)
static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset)
Determine if this immediate can fit in a disp8 or a compressed disp8 for EVEX instructions.
GlobalOffsetTableExprKind
static void emitConstant(uint64_t Val, unsigned Size, SmallVectorImpl< char > &CB)
static bool hasSecRelSymbolRef(const MCExpr *Expr)
This class represents an Operation in the Expression.
Binary assembler expressions.
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
virtual void emitPrefix(const MCInst &Inst, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI) const
Append the prefixes of given instruction to the code buffer.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
@ Binary
Binary expressions.
static MCFixupKind getKindForSize(unsigned Size, bool IsPCRel)
Return the generic fixup kind for a value with the given size.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
Represents a location in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
bool isX32() const
Tests whether the target is X32.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
bool hasImm(uint64_t TSFlags)
bool isX86_64NonExtLowByteReg(unsigned reg)
bool isPseudo(uint64_t TSFlags)
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
@ MRM_C0
MRM_XX - A mod/rm byte of exactly 0xXX.
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
@ MRMDestMem4VOp3CC
MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
@ MRMr0
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte,...
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
@ XOP
XOP - Opcode prefix used by XOP instructions.
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!...
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
bool isImmPCRel(uint64_t TSFlags)
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
bool isImmSigned(uint64_t TSFlags)
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
@ reloc_global_offset_table8
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Ref
The access may reference the value stored in memory.
Description of the encoding of one expression Op.