llvm::AMDGPU::RegBankLegalizeRules Class Reference

#include "Target/AMDGPU/AMDGPURegBankLegalizeRules.h"

Public Member Functions
	RegBankLegalizeRules (const GCNSubtarget &ST, MachineRegisterInfo &MRI)
void	refreshRefs (const GCNSubtarget &_ST, MachineRegisterInfo &_MRI)
const SetOfRulesForOpcode &	getRulesForOpc (MachineInstr &MI) const

Detailed Description

Definition at line 296 of file AMDGPURegBankLegalizeRules.h.

Constructor & Destructor Documentation

RegBankLegalizeRules()

RegBankLegalizeRules::RegBankLegalizeRules	(	const GCNSubtarget &	ST,
		MachineRegisterInfo &	MRI )

Definition at line 465 of file AMDGPURegBankLegalizeRules.cpp.

References llvm::AMDGPU::_, llvm::AMDGPU::B128, llvm::AMDGPU::B32, llvm::AMDGPU::B64, llvm::AMDGPU::B96, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPU::DivB128, llvm::AMDGPU::DivB256, llvm::AMDGPU::DivB32, llvm::AMDGPU::DivB512, llvm::AMDGPU::DivB64, llvm::AMDGPU::DivB96, llvm::AMDGPU::DivP1, llvm::AMDGPU::DivPtr128, llvm::AMDGPU::DivPtr32, llvm::AMDGPU::DivPtr64, llvm::AMDGPU::DivS1, llvm::AMDGPU::DivS128, llvm::AMDGPU::DivS16, llvm::AMDGPU::DivS32, llvm::AMDGPU::DivS64, llvm::AMDGPU::DivV2S16, llvm::AMDGPU::Ext32To64, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::MachineMemOperand::getSize(), llvm::LocationSize::getValue(), llvm::AMDGPU::IntrId, llvm::AMDGPU::isUniformMMO(), MI, llvm::MONoClobber, llvm::AMDGPU::None, llvm::AMDGPU::P0, llvm::AMDGPU::P1, llvm::AMDGPU::P3, llvm::AMDGPU::P4, llvm::AMDGPU::P5, llvm::AMDGPU::Ptr128, llvm::AMDGPU::Ptr32, llvm::AMDGPU::S1, llvm::AMDGPU::S16, llvm::AMDGPU::S32, llvm::AMDGPU::S64, llvm::AMDGPU::S_BFE, llvm::AMDGPU::Sgpr128, llvm::AMDGPU::Sgpr16, llvm::AMDGPU::Sgpr32, llvm::AMDGPU::Sgpr32_WF, llvm::AMDGPU::Sgpr32AExt, llvm::AMDGPU::Sgpr32AExtBoolInReg, llvm::AMDGPU::Sgpr32SExt, llvm::AMDGPU::Sgpr32Trunc, llvm::AMDGPU::Sgpr32ZExt, llvm::AMDGPU::Sgpr64, llvm::AMDGPU::SgprB128, llvm::AMDGPU::SgprB256, llvm::AMDGPU::SgprB32, llvm::AMDGPU::SgprB512, llvm::AMDGPU::SgprB64, llvm::AMDGPU::SgprB96, llvm::AMDGPU::SgprP1, llvm::AMDGPU::SgprP3, llvm::AMDGPU::SgprP4, llvm::AMDGPU::SgprP5, llvm::AMDGPU::SgprPtr128, llvm::AMDGPU::SgprPtr32, llvm::AMDGPU::SgprPtr64, llvm::AMDGPU::SgprV2S16, llvm::AMDGPU::SgprV2S32, llvm::AMDGPU::SgprV4S32, llvm::AMDGPU::SgprV4S32_WF, llvm::AMDGPU::SplitLoad, llvm::AMDGPU::SplitTo32, llvm::AMDGPU::SplitTo32Select, llvm::AMDGPU::SplitTo32SExtInReg, llvm::AMDGPU::Standard, llvm::AMDGPU::StandardB, llvm::AMDGPU::UniB128, llvm::AMDGPU::UniB256, llvm::AMDGPU::UniB32, llvm::AMDGPU::UniB512, llvm::AMDGPU::UniB64, llvm::AMDGPU::UniB96, llvm::AMDGPU::UniCstExt, llvm::AMDGPU::UniExtToSel, llvm::AMDGPU::UniInVcc, llvm::AMDGPU::UniInVgprB128, llvm::AMDGPU::UniInVgprB256, llvm::AMDGPU::UniInVgprB32, llvm::AMDGPU::UniInVgprB512, llvm::AMDGPU::UniInVgprB64, llvm::AMDGPU::UniInVgprB96, llvm::AMDGPU::UniInVgprS16, llvm::AMDGPU::UniInVgprS32, llvm::AMDGPU::UniP1, llvm::AMDGPU::UniP5, llvm::AMDGPU::UniPtr128, llvm::AMDGPU::UniPtr32, llvm::AMDGPU::UniPtr64, llvm::AMDGPU::UniS1, llvm::AMDGPU::UniS128, llvm::AMDGPU::UniS16, llvm::AMDGPU::UniS32, llvm::AMDGPU::UniS64, llvm::AMDGPU::UniV2S16, llvm::AMDGPU::UnpackBitShift, llvm::AMDGPU::V2S16, llvm::AMDGPU::V2S32, llvm::AMDGPU::V_BFE, llvm::AMDGPU::Vcc, llvm::AMDGPU::VccExtToSel, llvm::AMDGPU::Vgpr128, llvm::AMDGPU::Vgpr16, llvm::AMDGPU::Vgpr32, llvm::AMDGPU::Vgpr32SExt, llvm::AMDGPU::Vgpr32ZExt, llvm::AMDGPU::Vgpr64, llvm::AMDGPU::VgprB128, llvm::AMDGPU::VgprB256, llvm::AMDGPU::VgprB32, llvm::AMDGPU::VgprB512, llvm::AMDGPU::VgprB64, llvm::AMDGPU::VgprB96, llvm::AMDGPU::VgprP0, llvm::AMDGPU::VgprP1, llvm::AMDGPU::VgprP3, llvm::AMDGPU::VgprP4, llvm::AMDGPU::VgprP5, llvm::AMDGPU::VgprPtr128, llvm::AMDGPU::VgprPtr32, llvm::AMDGPU::VgprPtr64, llvm::AMDGPU::VgprToVccCopy, llvm::AMDGPU::VgprV2S16, llvm::AMDGPU::VgprV2S32, llvm::AMDGPU::WidenLoad, and llvm::AMDGPU::WidenMMOToS32.

Member Function Documentation

getRulesForOpc()

const SetOfRulesForOpcode & RegBankLegalizeRules::getRulesForOpc

(

MachineInstr &

MI

)

const

Definition at line 353 of file AMDGPURegBankLegalizeRules.cpp.

References llvm::cast(), llvm::dbgs(), LLVM_DEBUG, llvm_unreachable, MI, and Opc.

refreshRefs()

void llvm::AMDGPU::RegBankLegalizeRules::refreshRefs ( const GCNSubtarget & _ST, MachineRegisterInfo & _MRI )

inline

Definition at line 372 of file AMDGPURegBankLegalizeRules.h.

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The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
• lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp