LLVM 18.0.0git
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1//===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
10#include "GCNSubtarget.h"
14#include "llvm/IR/Constants.h"
16using namespace llvm;
17using namespace MIPatternMatch;
19std::pair<Register, unsigned>
23 if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
24 unsigned Offset;
25 const MachineOperand &Op = Def->getOperand(1);
26 if (Op.isImm())
27 Offset = Op.getImm();
28 else
29 Offset = Op.getCImm()->getZExtValue();
31 return std::pair(Register(), Offset);
32 }
34 int64_t Offset;
35 if (Def->getOpcode() == TargetOpcode::G_ADD) {
36 // TODO: Handle G_OR used for add case
37 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
38 return std::pair(Def->getOperand(1).getReg(), Offset);
40 // FIXME: matcher should ignore copies
41 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
42 return std::pair(Def->getOperand(1).getReg(), Offset);
43 }
46 if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
47 KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
48 return std::pair(Base, Offset);
50 // Handle G_PTRTOINT (G_PTR_ADD base, const) case
51 if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
53 if (mi_match(Def->getOperand(1).getReg(), MRI,
55 // If Base was int converted to pointer, simply return int and offset.
56 if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
57 return std::pair(Base->getOperand(1).getReg(), Offset);
59 // Register returned here will be of pointer type.
60 return std::pair(Base->getOperand(0).getReg(), Offset);
61 }
62 }
64 return std::pair(Reg, 0);
68 const LLT &Ty) {
69 if (Ty == LLT::scalar(32))
70 return Subtarget.hasAtomicFaddRtnInsts();
71 if (Ty == LLT::fixed_vector(2, 16) || Ty == LLT::scalar(64))
72 return Subtarget.hasGFX90AInsts();
73 return false;
unsigned const MachineRegisterInfo * MRI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
AMD GCN specific subclass of TargetSubtarget.
Provides analysis for querying information about KnownBits during GISel passes.
Implement a low-level type suitable for MachineInstr level instruction selection.
Contains matchers for matching SSA Machine Instructions.
Class for arbitrary precision integers.
Definition: APInt.h:76
This class represents an Operation in the Expression.
bool hasGFX90AInsts() const
bool hasAtomicFaddRtnInsts() const
Definition: GCNSubtarget.h:774
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:92
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr)
Returns base register and constant offset.
bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty)
operand_type_match m_Reg()
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
ConstantMatch< APInt > m_ICst(APInt &Cst)
BinaryOp_match< LHS, RHS, TargetOpcode::G_OR, true > m_GOr(const LHS &L, const RHS &R)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:465