LLVM  14.0.0git
AMDGPUGlobalISelUtils.cpp
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1 //===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/IR/Constants.h"
12 
13 using namespace llvm;
14 using namespace MIPatternMatch;
15 
16 std::pair<Register, unsigned>
19  if (!Def)
20  return std::make_pair(Reg, 0);
21 
22  if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
23  unsigned Offset;
24  const MachineOperand &Op = Def->getOperand(1);
25  if (Op.isImm())
26  Offset = Op.getImm();
27  else
28  Offset = Op.getCImm()->getZExtValue();
29 
30  return std::make_pair(Register(), Offset);
31  }
32 
33  int64_t Offset;
34  if (Def->getOpcode() == TargetOpcode::G_ADD) {
35  // TODO: Handle G_OR used for add case
36  if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
37  return std::make_pair(Def->getOperand(1).getReg(), Offset);
38 
39  // FIXME: matcher should ignore copies
40  if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
41  return std::make_pair(Def->getOperand(1).getReg(), Offset);
42  }
43 
44  // Handle G_PTRTOINT (G_PTR_ADD base, const) case
45  if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
47  if (mi_match(Def->getOperand(1).getReg(), MRI,
49  // If Base was int converted to pointer, simply return int and offset.
50  if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
51  return std::make_pair(Base->getOperand(1).getReg(), Offset);
52 
53  // Register returned here will be of pointer type.
54  return std::make_pair(Base->getOperand(0).getReg(), Offset);
55  }
56  }
57 
58  return std::make_pair(Reg, 0);
59 }
60 
62  assert(Mask.size() == 2);
63 
64  // If one half is undef, the other is trivially in the same reg.
65  if (Mask[0] == -1 || Mask[1] == -1)
66  return true;
67  return (Mask[0] & 2) == (Mask[1] & 2);
68 }
MIPatternMatch.h
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:404
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Constants.h
llvm::MIPatternMatch::m_GPtrAdd
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, true > m_GPtrAdd(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:303
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MIPatternMatch::m_MInstr
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
Definition: MIPatternMatch.h:227
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::AMDGPU::getBaseWithConstantOffset
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
Returns base register and constant offset.
Definition: AMDGPUGlobalISelUtils.cpp:17
AMDGPUGlobalISelUtils.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ArrayRef< int >
llvm::MIPatternMatch::m_Copy
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
Definition: MIPatternMatch.h:463
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MIPatternMatch::m_ICst
ConstantMatch m_ICst(int64_t &Cst)
Definition: MIPatternMatch.h:74
llvm::AMDGPU::isLegalVOP3PShuffleMask
bool isLegalVOP3PShuffleMask(ArrayRef< int > Mask)
Definition: AMDGPUGlobalISelUtils.cpp:61
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:24
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58