LLVM  15.0.0git
AMDGPUGlobalISelUtils.cpp
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1 //===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "GCNSubtarget.h"
12 #include "llvm/IR/Constants.h"
14 
15 using namespace llvm;
16 using namespace MIPatternMatch;
17 
18 std::pair<Register, unsigned>
21  if (!Def)
22  return std::make_pair(Reg, 0);
23 
24  if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
25  unsigned Offset;
26  const MachineOperand &Op = Def->getOperand(1);
27  if (Op.isImm())
28  Offset = Op.getImm();
29  else
30  Offset = Op.getCImm()->getZExtValue();
31 
32  return std::make_pair(Register(), Offset);
33  }
34 
35  int64_t Offset;
36  if (Def->getOpcode() == TargetOpcode::G_ADD) {
37  // TODO: Handle G_OR used for add case
38  if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
39  return std::make_pair(Def->getOperand(1).getReg(), Offset);
40 
41  // FIXME: matcher should ignore copies
42  if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
43  return std::make_pair(Def->getOperand(1).getReg(), Offset);
44  }
45 
46  // Handle G_PTRTOINT (G_PTR_ADD base, const) case
47  if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
49  if (mi_match(Def->getOperand(1).getReg(), MRI,
50  m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
51  // If Base was int converted to pointer, simply return int and offset.
52  if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
53  return std::make_pair(Base->getOperand(1).getReg(), Offset);
54 
55  // Register returned here will be of pointer type.
56  return std::make_pair(Base->getOperand(0).getReg(), Offset);
57  }
58  }
59 
60  return std::make_pair(Reg, 0);
61 }
62 
64  assert(Mask.size() == 2);
65 
66  // If one half is undef, the other is trivially in the same reg.
67  if (Mask[0] == -1 || Mask[1] == -1)
68  return true;
69  return (Mask[0] & 2) == (Mask[1] & 2);
70 }
71 
73  const LLT &Ty) {
74  if (Ty == LLT::scalar(32))
75  return Subtarget.hasAtomicFaddRtnInsts();
76  if (Ty == LLT::fixed_vector(2, 16) || Ty == LLT::scalar(64))
77  return Subtarget.hasGFX90AInsts();
78  return false;
79 }
MIPatternMatch.h
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:459
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MIPatternMatch::m_GPtrAdd
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:428
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Constants.h
GCNSubtarget.h
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MIPatternMatch::m_MInstr
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
Definition: MIPatternMatch.h:352
LowLevelTypeImpl.h
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AMDGPU::getBaseWithConstantOffset
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
Returns base register and constant offset.
Definition: AMDGPUGlobalISelUtils.cpp:19
AMDGPUGlobalISelUtils.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::GCNSubtarget::hasGFX90AInsts
bool hasGFX90AInsts() const
Definition: GCNSubtarget.h:1019
llvm::ArrayRef< int >
llvm::MIPatternMatch::m_Copy
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
Definition: MIPatternMatch.h:588
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GCNSubtarget::hasAtomicFaddRtnInsts
bool hasAtomicFaddRtnInsts() const
Definition: GCNSubtarget.h:731
llvm::MIPatternMatch::m_ICst
ConstantMatch< APInt > m_ICst(APInt &Cst)
Definition: MIPatternMatch.h:90
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::AMDGPU::isLegalVOP3PShuffleMask
bool isLegalVOP3PShuffleMask(ArrayRef< int > Mask)
Definition: AMDGPUGlobalISelUtils.cpp:63
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:25
llvm::AMDGPU::hasAtomicFaddRtnForTy
bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty)
Definition: AMDGPUGlobalISelUtils.cpp:72
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::LLT
Definition: LowLevelTypeImpl.h:39