LLVM  16.0.0git
AMDGPUGlobalISelUtils.cpp
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1 //===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "GCNSubtarget.h"
13 #include "llvm/IR/Constants.h"
15 
16 using namespace llvm;
17 using namespace MIPatternMatch;
18 
19 std::pair<Register, unsigned>
23  if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
24  unsigned Offset;
25  const MachineOperand &Op = Def->getOperand(1);
26  if (Op.isImm())
27  Offset = Op.getImm();
28  else
29  Offset = Op.getCImm()->getZExtValue();
30 
31  return std::make_pair(Register(), Offset);
32  }
33 
34  int64_t Offset;
35  if (Def->getOpcode() == TargetOpcode::G_ADD) {
36  // TODO: Handle G_OR used for add case
37  if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
38  return std::make_pair(Def->getOperand(1).getReg(), Offset);
39 
40  // FIXME: matcher should ignore copies
41  if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
42  return std::make_pair(Def->getOperand(1).getReg(), Offset);
43  }
44 
45  Register Base;
46  if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
47  KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
48  return std::make_pair(Base, Offset);
49 
50  // Handle G_PTRTOINT (G_PTR_ADD base, const) case
51  if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
53  if (mi_match(Def->getOperand(1).getReg(), MRI,
54  m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
55  // If Base was int converted to pointer, simply return int and offset.
56  if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
57  return std::make_pair(Base->getOperand(1).getReg(), Offset);
58 
59  // Register returned here will be of pointer type.
60  return std::make_pair(Base->getOperand(0).getReg(), Offset);
61  }
62  }
63 
64  return std::make_pair(Reg, 0);
65 }
66 
68  const LLT &Ty) {
69  if (Ty == LLT::scalar(32))
70  return Subtarget.hasAtomicFaddRtnInsts();
71  if (Ty == LLT::fixed_vector(2, 16) || Ty == LLT::scalar(64))
72  return Subtarget.hasGFX90AInsts();
73  return false;
74 }
MIPatternMatch.h
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:462
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::MIPatternMatch::m_Reg
operand_type_match m_Reg()
Definition: MIPatternMatch.h:268
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
GISelKnownBits.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MIPatternMatch::m_GPtrAdd
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:468
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
Constants.h
GCNSubtarget.h
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MIPatternMatch::m_MInstr
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
Definition: MIPatternMatch.h:368
LowLevelTypeImpl.h
llvm::MIPatternMatch::m_GOr
BinaryOp_match< LHS, RHS, TargetOpcode::G_OR, true > m_GOr(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:515
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AMDGPU::getBaseWithConstantOffset
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr)
Returns base register and constant offset.
Definition: AMDGPUGlobalISelUtils.cpp:20
AMDGPUGlobalISelUtils.h
llvm::GCNSubtarget::hasGFX90AInsts
bool hasGFX90AInsts() const
Definition: GCNSubtarget.h:1050
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MIPatternMatch::m_Copy
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
Definition: MIPatternMatch.h:628
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GCNSubtarget::hasAtomicFaddRtnInsts
bool hasAtomicFaddRtnInsts() const
Definition: GCNSubtarget.h:746
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MIPatternMatch::m_ICst
ConstantMatch< APInt > m_ICst(APInt &Cst)
Definition: MIPatternMatch.h:92
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:25
llvm::AMDGPU::hasAtomicFaddRtnForTy
bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty)
Definition: AMDGPUGlobalISelUtils.cpp:67
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::LLT
Definition: LowLevelTypeImpl.h:39