467 : ST(&_ST), MRI(&_MRI) {
469 addRulesForGOpcs({G_ADD, G_SUB},
Standard)
477 addRulesForGOpcs({G_XOR, G_OR, G_AND},
StandardB)
497 addRulesForGOpcs({G_LSHR},
Standard)
507 addRulesForGOpcs({G_ASHR},
Standard)
519 addRulesForGOpcs({G_UBFX, G_SBFX},
Standard)
525 addRulesForGOpcs({G_SMIN, G_SMAX},
Standard)
533 addRulesForGOpcs({G_UMIN, G_UMAX},
Standard)
544 addRulesForGOpcs({G_CONSTANT})
548 addRulesForGOpcs({G_ICMP})
553 addRulesForGOpcs({G_FCMP})
557 addRulesForGOpcs({G_BRCOND})
561 addRulesForGOpcs({G_BR}).
Any({{
_}, {{}, {
None}}});
571 addRulesForGOpcs({G_ANYEXT})
585 addRulesForGOpcs({G_TRUNC})
600 addRulesForGOpcs({G_ZEXT})
615 addRulesForGOpcs({G_SEXT})
630 addRulesForGOpcs({G_SEXT_INREG})
636 addRulesForGOpcs({G_ASSERT_ZEXT, G_ASSERT_SEXT},
Standard)
642 bool hasSMRDx3 = ST->hasScalarDwordx3Loads();
643 bool hasSMRDSmall = ST->hasScalarSubwordLoads();
644 bool usesTrue16 = ST->useRealTrue16Insts();
647 return (*
MI.memoperands_begin())->getAlign() >=
Align(16);
651 return (*
MI.memoperands_begin())->getAlign() >=
Align(4);
655 return (*
MI.memoperands_begin())->isAtomic();
671 return (*
MI.memoperands_begin())->isVolatile();
675 return (*
MI.memoperands_begin())->isInvariant();
690 return MemSize == 16 || MemSize == 8;
698 auto isUL = !isAtomicMMO && isUniMMO && (isConst || !isVolatileMMO) &&
699 (isConst || isInvMMO || isNoClobberMMO);
703 addRulesForGOpcs({G_LOAD})
810 addRulesForGOpcs({G_ZEXTLOAD, G_SEXTLOAD})
830 addRulesForGOpcs({G_STORE})
865 addRulesForGOpcs({G_AMDGPU_BUFFER_LOAD, G_AMDGPU_BUFFER_LOAD_FORMAT,
866 G_AMDGPU_TBUFFER_LOAD_FORMAT},
877 addRulesForGOpcs({G_AMDGPU_BUFFER_STORE})
880 addRulesForGOpcs({G_PTR_ADD})
886 addRulesForGOpcs({G_INTTOPTR})
894 addRulesForGOpcs({G_PTRTOINT})
906 bool hasSALUFloat = ST->hasSALUFloatInsts();
908 addRulesForGOpcs({G_FADD},
Standard)
913 addRulesForGOpcs({G_FPTOUI})
917 addRulesForGOpcs({G_UITOFP})
929 addRulesForIOpcs({amdgcn_if_break},
Standard)
932 addRulesForIOpcs({amdgcn_mbcnt_lo, amdgcn_mbcnt_hi},
Standard)
935 addRulesForIOpcs({amdgcn_readfirstlane})