LLVM  9.0.0svn
AMDGPUInstructionSelector.cpp
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1 //===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
15 #include "AMDGPUInstrInfo.h"
16 #include "AMDGPURegisterBankInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "SIMachineFunctionInfo.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
33 
34 #define DEBUG_TYPE "amdgpu-isel"
35 
36 using namespace llvm;
37 
38 #define GET_GLOBALISEL_IMPL
39 #define AMDGPUSubtarget GCNSubtarget
40 #include "AMDGPUGenGlobalISel.inc"
41 #undef GET_GLOBALISEL_IMPL
42 #undef AMDGPUSubtarget
43 
45  const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI,
46  const AMDGPUTargetMachine &TM)
47  : InstructionSelector(), TII(*STI.getInstrInfo()),
48  TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
49  STI(STI),
50  EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
52 #include "AMDGPUGenGlobalISel.inc"
55 #include "AMDGPUGenGlobalISel.inc"
57 {
58 }
59 
60 const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
61 
62 bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
63  MachineBasicBlock *BB = I.getParent();
64  MachineFunction *MF = BB->getParent();
66  I.setDesc(TII.get(TargetOpcode::COPY));
67  for (const MachineOperand &MO : I.operands()) {
69  continue;
70 
71  const TargetRegisterClass *RC =
73  if (!RC)
74  continue;
75  RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
76  }
77  return true;
78 }
79 
81 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
82  unsigned SubIdx) const {
83 
84  MachineInstr *MI = MO.getParent();
86  MachineFunction *MF = BB->getParent();
88  unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
89 
90  if (MO.isReg()) {
91  unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
92  unsigned Reg = MO.getReg();
93  BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
94  .addReg(Reg, 0, ComposedSubIdx);
95 
96  return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
97  MO.isKill(), MO.isDead(), MO.isUndef(),
98  MO.isEarlyClobber(), 0, MO.isDebug(),
99  MO.isInternalRead());
100  }
101 
102  assert(MO.isImm());
103 
104  APInt Imm(64, MO.getImm());
105 
106  switch (SubIdx) {
107  default:
108  llvm_unreachable("do not know to split immediate with this sub index.");
109  case AMDGPU::sub0:
110  return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
111  case AMDGPU::sub1:
112  return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
113  }
114 }
115 
116 static int64_t getConstant(const MachineInstr *MI) {
117  return MI->getOperand(1).getCImm()->getSExtValue();
118 }
119 
120 bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
121  MachineBasicBlock *BB = I.getParent();
122  MachineFunction *MF = BB->getParent();
124  unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
125  unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
126  unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
127 
128  if (Size != 64)
129  return false;
130 
131  DebugLoc DL = I.getDebugLoc();
132 
133  MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
134  MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
135 
136  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
137  .add(Lo1)
138  .add(Lo2);
139 
140  MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
141  MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
142 
143  BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
144  .add(Hi1)
145  .add(Hi2);
146 
147  BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
148  .addReg(DstLo)
149  .addImm(AMDGPU::sub0)
150  .addReg(DstHi)
151  .addImm(AMDGPU::sub1);
152 
153  for (MachineOperand &MO : I.explicit_operands()) {
155  continue;
156  RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
157  }
158 
159  I.eraseFromParent();
160  return true;
161 }
162 
163 bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
164  MachineBasicBlock *BB = I.getParent();
165  MachineFunction *MF = BB->getParent();
167  assert(I.getOperand(2).getImm() % 32 == 0);
168  unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(2).getImm() / 32);
169  const DebugLoc &DL = I.getDebugLoc();
170  MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY),
171  I.getOperand(0).getReg())
172  .addReg(I.getOperand(1).getReg(), 0, SubReg);
173 
174  for (const MachineOperand &MO : Copy->operands()) {
175  const TargetRegisterClass *RC =
177  if (!RC)
178  continue;
179  RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
180  }
181  I.eraseFromParent();
182  return true;
183 }
184 
185 bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
186  return selectG_ADD(I);
187 }
188 
189 bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
190  MachineBasicBlock *BB = I.getParent();
191  MachineFunction *MF = BB->getParent();
193  const MachineOperand &MO = I.getOperand(0);
194  const TargetRegisterClass *RC =
196  if (RC)
197  RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
198  I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
199  return true;
200 }
201 
202 bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
203  MachineBasicBlock *BB = I.getParent();
204  MachineFunction *MF = BB->getParent();
206  unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(3).getImm() / 32);
207  DebugLoc DL = I.getDebugLoc();
208  MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG))
209  .addDef(I.getOperand(0).getReg())
210  .addReg(I.getOperand(1).getReg())
211  .addReg(I.getOperand(2).getReg())
212  .addImm(SubReg);
213 
214  for (const MachineOperand &MO : Ins->operands()) {
215  if (!MO.isReg())
216  continue;
218  continue;
219 
220  const TargetRegisterClass *RC =
222  if (!RC)
223  continue;
224  RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
225  }
226  I.eraseFromParent();
227  return true;
228 }
229 
230 bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
231  CodeGenCoverage &CoverageInfo) const {
232  unsigned IntrinsicID = I.getOperand(1).getIntrinsicID();
233 
234  switch (IntrinsicID) {
235  default:
236  break;
237  case Intrinsic::maxnum:
238  case Intrinsic::minnum:
239  case Intrinsic::amdgcn_cvt_pkrtz:
240  return selectImpl(I, CoverageInfo);
241 
242  case Intrinsic::amdgcn_kernarg_segment_ptr: {
243  MachineFunction *MF = I.getParent()->getParent();
246  const ArgDescriptor *InputPtrReg;
247  const TargetRegisterClass *RC;
248  const DebugLoc &DL = I.getDebugLoc();
249 
250  std::tie(InputPtrReg, RC)
252  if (!InputPtrReg)
253  report_fatal_error("missing kernarg segment ptr");
254 
255  BuildMI(*I.getParent(), &I, DL, TII.get(AMDGPU::COPY))
256  .add(I.getOperand(0))
257  .addReg(MRI.getLiveInVirtReg(InputPtrReg->getRegister()));
258  I.eraseFromParent();
259  return true;
260  }
261  }
262  return false;
263 }
264 
265 static MachineInstr *
266 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt,
267  unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3,
268  unsigned VM, bool Compr, unsigned Enabled, bool Done) {
269  const DebugLoc &DL = Insert->getDebugLoc();
270  MachineBasicBlock &BB = *Insert->getParent();
271  unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP;
272  return BuildMI(BB, Insert, DL, TII.get(Opcode))
273  .addImm(Tgt)
274  .addReg(Reg0)
275  .addReg(Reg1)
276  .addReg(Reg2)
277  .addReg(Reg3)
278  .addImm(VM)
279  .addImm(Compr)
280  .addImm(Enabled);
281 }
282 
283 bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
284  MachineInstr &I,
285  CodeGenCoverage &CoverageInfo) const {
286  MachineBasicBlock *BB = I.getParent();
287  MachineFunction *MF = BB->getParent();
289 
290  unsigned IntrinsicID = I.getOperand(0).getIntrinsicID();
291  switch (IntrinsicID) {
292  case Intrinsic::amdgcn_exp: {
293  int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg()));
294  int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg()));
295  int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(7).getReg()));
296  int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(8).getReg()));
297 
298  MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(),
299  I.getOperand(4).getReg(),
300  I.getOperand(5).getReg(),
301  I.getOperand(6).getReg(),
302  VM, false, Enabled, Done);
303 
304  I.eraseFromParent();
305  return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
306  }
307  case Intrinsic::amdgcn_exp_compr: {
308  const DebugLoc &DL = I.getDebugLoc();
309  int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg()));
310  int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg()));
311  unsigned Reg0 = I.getOperand(3).getReg();
312  unsigned Reg1 = I.getOperand(4).getReg();
313  unsigned Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
314  int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(5).getReg()));
315  int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(6).getReg()));
316 
317  BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef);
318  MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM,
319  true, Enabled, Done);
320 
321  I.eraseFromParent();
322  return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
323  }
324  }
325  return false;
326 }
327 
328 bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
329  MachineBasicBlock *BB = I.getParent();
330  MachineFunction *MF = BB->getParent();
332  DebugLoc DL = I.getDebugLoc();
333  unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
334  unsigned Opcode;
335 
336  // FIXME: Select store instruction based on address space
337  switch (StoreSize) {
338  default:
339  return false;
340  case 32:
341  Opcode = AMDGPU::FLAT_STORE_DWORD;
342  break;
343  case 64:
344  Opcode = AMDGPU::FLAT_STORE_DWORDX2;
345  break;
346  case 96:
347  Opcode = AMDGPU::FLAT_STORE_DWORDX3;
348  break;
349  case 128:
350  Opcode = AMDGPU::FLAT_STORE_DWORDX4;
351  break;
352  }
353 
354  MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
355  .add(I.getOperand(1))
356  .add(I.getOperand(0))
357  .addImm(0) // offset
358  .addImm(0) // glc
359  .addImm(0); // slc
360 
361 
362  // Now that we selected an opcode, we need to constrain the register
363  // operands to use appropriate classes.
364  bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
365 
366  I.eraseFromParent();
367  return Ret;
368 }
369 
370 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
371  MachineBasicBlock *BB = I.getParent();
372  MachineFunction *MF = BB->getParent();
374  MachineOperand &ImmOp = I.getOperand(1);
375 
376  // The AMDGPU backend only supports Imm operands and not CImm or FPImm.
377  if (ImmOp.isFPImm()) {
378  const APInt &Imm = ImmOp.getFPImm()->getValueAPF().bitcastToAPInt();
379  ImmOp.ChangeToImmediate(Imm.getZExtValue());
380  } else if (ImmOp.isCImm()) {
381  ImmOp.ChangeToImmediate(ImmOp.getCImm()->getZExtValue());
382  }
383 
384  unsigned DstReg = I.getOperand(0).getReg();
385  unsigned Size;
386  bool IsSgpr;
387  const RegisterBank *RB = MRI.getRegBankOrNull(I.getOperand(0).getReg());
388  if (RB) {
389  IsSgpr = RB->getID() == AMDGPU::SGPRRegBankID;
390  Size = MRI.getType(DstReg).getSizeInBits();
391  } else {
392  const TargetRegisterClass *RC = TRI.getRegClassForReg(MRI, DstReg);
393  IsSgpr = TRI.isSGPRClass(RC);
394  Size = TRI.getRegSizeInBits(*RC);
395  }
396 
397  if (Size != 32 && Size != 64)
398  return false;
399 
400  unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
401  if (Size == 32) {
402  I.setDesc(TII.get(Opcode));
404  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
405  }
406 
407  DebugLoc DL = I.getDebugLoc();
408  const TargetRegisterClass *RC = IsSgpr ? &AMDGPU::SReg_32_XM0RegClass :
409  &AMDGPU::VGPR_32RegClass;
410  unsigned LoReg = MRI.createVirtualRegister(RC);
411  unsigned HiReg = MRI.createVirtualRegister(RC);
412  const APInt &Imm = APInt(Size, I.getOperand(1).getImm());
413 
414  BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
415  .addImm(Imm.trunc(32).getZExtValue());
416 
417  BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
418  .addImm(Imm.ashr(32).getZExtValue());
419 
420  const MachineInstr *RS =
421  BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
422  .addReg(LoReg)
423  .addImm(AMDGPU::sub0)
424  .addReg(HiReg)
425  .addImm(AMDGPU::sub1);
426 
427  // We can't call constrainSelectedInstRegOperands here, because it doesn't
428  // work for target independent opcodes
429  I.eraseFromParent();
430  const TargetRegisterClass *DstRC =
431  TRI.getConstrainedRegClassForOperand(RS->getOperand(0), MRI);
432  if (!DstRC)
433  return true;
434  return RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
435 }
436 
437 static bool isConstant(const MachineInstr &MI) {
438  return MI.getOpcode() == TargetOpcode::G_CONSTANT;
439 }
440 
441 void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
442  const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
443 
444  const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
445 
446  assert(PtrMI);
447 
448  if (PtrMI->getOpcode() != TargetOpcode::G_GEP)
449  return;
450 
451  GEPInfo GEPInfo(*PtrMI);
452 
453  for (unsigned i = 1, e = 3; i < e; ++i) {
454  const MachineOperand &GEPOp = PtrMI->getOperand(i);
455  const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
456  assert(OpDef);
457  if (isConstant(*OpDef)) {
458  // FIXME: Is it possible to have multiple Imm parts? Maybe if we
459  // are lacking other optimizations.
460  assert(GEPInfo.Imm == 0);
461  GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
462  continue;
463  }
464  const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
465  if (OpBank->getID() == AMDGPU::SGPRRegBankID)
466  GEPInfo.SgprParts.push_back(GEPOp.getReg());
467  else
468  GEPInfo.VgprParts.push_back(GEPOp.getReg());
469  }
470 
471  AddrInfo.push_back(GEPInfo);
472  getAddrModeInfo(*PtrMI, MRI, AddrInfo);
473 }
474 
475 bool AMDGPUInstructionSelector::isInstrUniform(const MachineInstr &MI) const {
476  if (!MI.hasOneMemOperand())
477  return false;
478 
479  const MachineMemOperand *MMO = *MI.memoperands_begin();
480  const Value *Ptr = MMO->getValue();
481 
482  // UndefValue means this is a load of a kernel input. These are uniform.
483  // Sometimes LDS instructions have constant pointers.
484  // If Ptr is null, then that means this mem operand contains a
485  // PseudoSourceValue like GOT.
486  if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
487  isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
488  return true;
489 
491  return true;
492 
493  const Instruction *I = dyn_cast<Instruction>(Ptr);
494  return I && I->getMetadata("amdgpu.uniform");
495 }
496 
497 bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
498  for (const GEPInfo &GEPInfo : AddrInfo) {
499  if (!GEPInfo.VgprParts.empty())
500  return true;
501  }
502  return false;
503 }
504 
505 bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
506  MachineBasicBlock *BB = I.getParent();
507  MachineFunction *MF = BB->getParent();
508  MachineRegisterInfo &MRI = MF->getRegInfo();
509  DebugLoc DL = I.getDebugLoc();
510  unsigned DstReg = I.getOperand(0).getReg();
511  unsigned PtrReg = I.getOperand(1).getReg();
512  unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
513  unsigned Opcode;
514 
515  SmallVector<GEPInfo, 4> AddrInfo;
516 
517  getAddrModeInfo(I, MRI, AddrInfo);
518 
519  switch (LoadSize) {
520  default:
521  llvm_unreachable("Load size not supported\n");
522  case 32:
523  Opcode = AMDGPU::FLAT_LOAD_DWORD;
524  break;
525  case 64:
526  Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
527  break;
528  }
529 
530  MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
531  .add(I.getOperand(0))
532  .addReg(PtrReg)
533  .addImm(0) // offset
534  .addImm(0) // glc
535  .addImm(0); // slc
536 
537  bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
538  I.eraseFromParent();
539  return Ret;
540 }
541 
543  CodeGenCoverage &CoverageInfo) const {
544 
545  if (!isPreISelGenericOpcode(I.getOpcode())) {
546  if (I.isCopy())
547  return selectCOPY(I);
548  return true;
549  }
550 
551  switch (I.getOpcode()) {
552  default:
553  return selectImpl(I, CoverageInfo);
554  case TargetOpcode::G_ADD:
555  return selectG_ADD(I);
556  case TargetOpcode::G_INTTOPTR:
557  case TargetOpcode::G_BITCAST:
558  return selectCOPY(I);
559  case TargetOpcode::G_CONSTANT:
560  case TargetOpcode::G_FCONSTANT:
561  return selectG_CONSTANT(I);
562  case TargetOpcode::G_EXTRACT:
563  return selectG_EXTRACT(I);
564  case TargetOpcode::G_GEP:
565  return selectG_GEP(I);
566  case TargetOpcode::G_IMPLICIT_DEF:
567  return selectG_IMPLICIT_DEF(I);
568  case TargetOpcode::G_INSERT:
569  return selectG_INSERT(I);
570  case TargetOpcode::G_INTRINSIC:
571  return selectG_INTRINSIC(I, CoverageInfo);
572  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
573  return selectG_INTRINSIC_W_SIDE_EFFECTS(I, CoverageInfo);
574  case TargetOpcode::G_LOAD:
575  if (selectImpl(I, CoverageInfo))
576  return true;
577  return selectG_LOAD(I);
578  case TargetOpcode::G_STORE:
579  return selectG_STORE(I);
580  }
581  return false;
582 }
583 
585 AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const {
586  return {{
587  [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
588  }};
589 
590 }
591 
592 ///
593 /// This will select either an SGPR or VGPR operand and will save us from
594 /// having to write an extra tablegen pattern.
596 AMDGPUInstructionSelector::selectVSRC0(MachineOperand &Root) const {
597  return {{
598  [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
599  }};
600 }
601 
603 AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
604  return {{
605  [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
606  [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
607  [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
608  [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
609  }};
610 }
612 AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const {
613  return {{
614  [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
615  [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
616  [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
617  }};
618 }
619 
621 AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {
622  return {{
623  [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
624  [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods
625  }};
626 }
627 
629 AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const {
630  MachineRegisterInfo &MRI =
631  Root.getParent()->getParent()->getParent()->getRegInfo();
632 
633  SmallVector<GEPInfo, 4> AddrInfo;
634  getAddrModeInfo(*Root.getParent(), MRI, AddrInfo);
635 
636  if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
637  return None;
638 
639  const GEPInfo &GEPInfo = AddrInfo[0];
640 
641  if (!AMDGPU::isLegalSMRDImmOffset(STI, GEPInfo.Imm))
642  return None;
643 
644  unsigned PtrReg = GEPInfo.SgprParts[0];
645  int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
646  return {{
647  [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
648  [=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
649  }};
650 }
651 
653 AMDGPUInstructionSelector::selectSmrdImm32(MachineOperand &Root) const {
654  MachineRegisterInfo &MRI =
655  Root.getParent()->getParent()->getParent()->getRegInfo();
656 
657  SmallVector<GEPInfo, 4> AddrInfo;
658  getAddrModeInfo(*Root.getParent(), MRI, AddrInfo);
659 
660  if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
661  return None;
662 
663  const GEPInfo &GEPInfo = AddrInfo[0];
664  unsigned PtrReg = GEPInfo.SgprParts[0];
665  int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
666  if (!isUInt<32>(EncodedImm))
667  return None;
668 
669  return {{
670  [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
671  [=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
672  }};
673 }
674 
676 AMDGPUInstructionSelector::selectSmrdSgpr(MachineOperand &Root) const {
677  MachineInstr *MI = Root.getParent();
678  MachineBasicBlock *MBB = MI->getParent();
679  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
680 
681  SmallVector<GEPInfo, 4> AddrInfo;
682  getAddrModeInfo(*MI, MRI, AddrInfo);
683 
684  // FIXME: We should shrink the GEP if the offset is known to be <= 32-bits,
685  // then we can select all ptr + 32-bit offsets not just immediate offsets.
686  if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
687  return None;
688 
689  const GEPInfo &GEPInfo = AddrInfo[0];
690  if (!GEPInfo.Imm || !isUInt<32>(GEPInfo.Imm))
691  return None;
692 
693  // If we make it this far we have a load with an 32-bit immediate offset.
694  // It is OK to select this using a sgpr offset, because we have already
695  // failed trying to select this load into one of the _IMM variants since
696  // the _IMM Patterns are considered before the _SGPR patterns.
697  unsigned PtrReg = GEPInfo.SgprParts[0];
698  unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
699  BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
700  .addImm(GEPInfo.Imm);
701  return {{
702  [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
703  [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
704  }};
705 }
static MachineInstr * buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, unsigned VM, bool Compr, unsigned Enabled, bool Done)
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
static unsigned getSubRegFromChannel(unsigned Channel)
static bool isConstant(const MachineInstr &MI)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
unsigned getAddrSpace() const
AMDGPU specific subclass of TargetSubtarget.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:464
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getSubReg() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
static const char * getName()
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isInternalRead() const
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
bool isEarlyClobber() const
bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
A description of a memory reference used in the backend.
This file declares the targeting of the InstructionSelector class for AMDGPU.
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
Address space for 32-bit constant memory.
Definition: AMDGPU.h:258
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned SubReg
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isSGPRClass(const TargetRegisterClass *RC) const
#define GET_GLOBALISEL_PREDICATES_INIT
static int64_t getConstant(const MachineInstr *MI)
TargetRegisterInfo interface that is implemented by all hw codegen targets.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:234
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
#define DEBUG_TYPE
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
unsigned const MachineRegisterInfo * MRI
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:548
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
The AMDGPU TargetMachine interface definition for hw codgen targets.
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isCopy() const
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1237
const APFloat & getValueAPF() const
Definition: Constants.h:302
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:946
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
Intrinsic::ID getIntrinsicID() const
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:87
This class implements the register bank concept.
Definition: RegisterBank.h:28
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static bool Enabled
Definition: Statistic.cpp:50
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
Class for arbitrary precision integers.
Definition: APInt.h:69
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
#define GET_GLOBALISEL_TEMPORARIES_INIT
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
std::pair< const ArgDescriptor *, const TargetRegisterClass * > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
Provides the logic to select generic machine instructions.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
LLVM Value Representation.
Definition: Value.h:72
IRTranslator LLVM IR MI
APInt bitcastToAPInt() const
Definition: APFloat.h:1093
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:156
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
const ConstantInt * getCImm() const
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1226
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
bool isImplicit() const