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27 #define DEBUG_TYPE "bpf-mi-checking"
45 bool processAtomicInsts();
53 return processAtomicInsts();
109 &BPFMCRegisterClasses[BPF::GPRRegClassID];
110 std::vector<unsigned> GPR32LiveDefs;
111 std::vector<unsigned> GPR64DeadDefs;
116 if (!MO.isReg() || MO.isUse())
119 RegIsGPR64 = GPR64RegClass->
contains(MO.getReg());
127 GPR32LiveDefs.push_back(MO.getReg());
134 GPR64DeadDefs.push_back(MO.getReg());
138 if (GPR32LiveDefs.empty())
143 if (GPR64DeadDefs.empty())
147 for (
auto I : GPR32LiveDefs)
155 bool BPFMIPreEmitChecking::processAtomicInsts() {
158 if (
MI.getOpcode() != BPF::XADDW &&
159 MI.getOpcode() != BPF::XADDD &&
160 MI.getOpcode() != BPF::XADDW32)
164 if (hasLiveDefs(
MI,
TRI)) {
169 ": Invalid usage of the XADD return value",
false);
180 bool Changed =
false;
189 if (
MI.getOpcode() != BPF::XFADDW32 &&
MI.getOpcode() != BPF::XFADDD &&
190 MI.getOpcode() != BPF::XFANDW32 &&
MI.getOpcode() != BPF::XFANDD &&
191 MI.getOpcode() != BPF::XFXORW32 &&
MI.getOpcode() != BPF::XFXORD &&
192 MI.getOpcode() != BPF::XFORW32 &&
MI.getOpcode() != BPF::XFORD)
195 if (hasLiveDefs(
MI,
TRI))
200 switch (
MI.getOpcode()) {
202 newOpcode = BPF::XADDW32;
205 newOpcode = BPF::XADDD;
208 newOpcode = BPF::XANDW32;
211 newOpcode = BPF::XANDD;
214 newOpcode = BPF::XXORW32;
217 newOpcode = BPF::XXORD;
220 newOpcode = BPF::XORW32;
223 newOpcode = BPF::XORD;
230 .
add(
MI.getOperand(0))
231 .
add(
MI.getOperand(1))
232 .
add(
MI.getOperand(2))
233 .
add(
MI.getOperand(3));
246 "BPF PreEmit Checking",
false,
false)
248 char BPFMIPreEmitChecking::
ID = 0;
251 return new BPFMIPreEmitChecking();
This is an optimization pass for GlobalISel generic memory operations.
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringLiteral > StandardNames)
Initialize the set of available library functions based on the specified target triple.
unsigned const TargetRegisterInfo * TRI
MCRegisterClass - Base class of TargetRegisterClass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createBPFMIPreEmitCheckingPass()
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void initializeBPFMIPreEmitCheckingPass(PassRegistry &)
Representation of each machine instruction.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
MCSuperRegIterator enumerates all super-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
std::string to_string(const T &Value)
FunctionPass class - This class is used to implement most global optimizations.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.