LLVM 19.0.0git
GIMatchTableExecutor.cpp
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1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.cpp -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the GIMatchTableExecutor class.
11//
12//===----------------------------------------------------------------------===//
13
19
20#define DEBUG_TYPE "gi-match-table-executor"
21
22using namespace llvm;
23
25 : Renderers(MaxRenderers) {}
26
28
30 int64_t Value,
32 bool Splat) const {
33 if (MO.isReg() && MO.getReg()) {
34 if (auto VRegVal = getIConstantVRegValWithLookThrough(MO.getReg(), MRI))
35 return VRegVal->Value.getSExtValue() == Value;
36
37 if (Splat) {
38 if (auto VRegVal = getIConstantSplatVal(MO.getReg(), MRI))
39 return VRegVal->getSExtValue() == Value;
40 }
41 }
42 return false;
43}
44
46 const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
47 if (!Root.isReg())
48 return false;
49
50 MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
51 if (RootI->getOpcode() != TargetOpcode::G_PTR_ADD)
52 return false;
53
54 MachineOperand &RHS = RootI->getOperand(2);
55 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
56 if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
57 return false;
58
59 return true;
60}
61
63 MachineInstr &IntoMI) const {
64 // Immediate neighbours are already folded.
65 if (MI.getParent() == IntoMI.getParent() &&
66 std::next(MI.getIterator()) == IntoMI.getIterator())
67 return true;
68
69 // Convergent instructions cannot be moved in the CFG.
70 if (MI.isConvergent() && MI.getParent() != IntoMI.getParent())
71 return false;
72
73 return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
74 !MI.hasUnmodeledSideEffects() && MI.implicit_operands().empty();
75}
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
Value * RHS
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:564
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:341
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:574
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM Value Representation.
Definition: Value.h:74
self_iterator getIterator()
Definition: ilist_node.h:109
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1386
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:426