LLVM 18.0.0git
Utils.cpp
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1//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file This file implements the utility functions used by the GlobalISel
9/// pipeline.
10//===----------------------------------------------------------------------===//
11
13#include "llvm/ADT/APFloat.h"
14#include "llvm/ADT/APInt.h"
32#include "llvm/IR/Constants.h"
35#include <numeric>
36#include <optional>
37
38#define DEBUG_TYPE "globalisel-utils"
39
40using namespace llvm;
41using namespace MIPatternMatch;
42
44 const TargetInstrInfo &TII,
45 const RegisterBankInfo &RBI, Register Reg,
46 const TargetRegisterClass &RegClass) {
47 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
48 return MRI.createVirtualRegister(&RegClass);
49
50 return Reg;
51}
52
54 const MachineFunction &MF, const TargetRegisterInfo &TRI,
56 const RegisterBankInfo &RBI, MachineInstr &InsertPt,
57 const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
58 Register Reg = RegMO.getReg();
59 // Assume physical registers are properly constrained.
60 assert(Reg.isVirtual() && "PhysReg not implemented");
61
62 // Save the old register class to check whether
63 // the change notifications will be required.
64 // TODO: A better approach would be to pass
65 // the observers to constrainRegToClass().
66 auto *OldRegClass = MRI.getRegClassOrNull(Reg);
67 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
68 // If we created a new virtual register because the class is not compatible
69 // then create a copy between the new and the old register.
70 if (ConstrainedReg != Reg) {
71 MachineBasicBlock::iterator InsertIt(&InsertPt);
72 MachineBasicBlock &MBB = *InsertPt.getParent();
73 // FIXME: The copy needs to have the classes constrained for its operands.
74 // Use operand's regbank to get the class for old register (Reg).
75 if (RegMO.isUse()) {
76 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
77 TII.get(TargetOpcode::COPY), ConstrainedReg)
78 .addReg(Reg);
79 } else {
80 assert(RegMO.isDef() && "Must be a definition");
81 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
82 TII.get(TargetOpcode::COPY), Reg)
83 .addReg(ConstrainedReg);
84 }
85 if (GISelChangeObserver *Observer = MF.getObserver()) {
86 Observer->changingInstr(*RegMO.getParent());
87 }
88 RegMO.setReg(ConstrainedReg);
89 if (GISelChangeObserver *Observer = MF.getObserver()) {
90 Observer->changedInstr(*RegMO.getParent());
91 }
92 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) {
93 if (GISelChangeObserver *Observer = MF.getObserver()) {
94 if (!RegMO.isDef()) {
95 MachineInstr *RegDef = MRI.getVRegDef(Reg);
96 Observer->changedInstr(*RegDef);
97 }
98 Observer->changingAllUsesOfReg(MRI, Reg);
99 Observer->finishedChangingAllUsesOfReg();
100 }
101 }
102 return ConstrainedReg;
103}
104
106 const MachineFunction &MF, const TargetRegisterInfo &TRI,
108 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
109 MachineOperand &RegMO, unsigned OpIdx) {
110 Register Reg = RegMO.getReg();
111 // Assume physical registers are properly constrained.
112 assert(Reg.isVirtual() && "PhysReg not implemented");
113
114 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
115 // Some of the target independent instructions, like COPY, may not impose any
116 // register class constraints on some of their operands: If it's a use, we can
117 // skip constraining as the instruction defining the register would constrain
118 // it.
119
120 if (OpRC) {
121 // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
122 // can have multiple regbanks for a superclass that combine different
123 // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
124 // resolved by targets during regbankselect should not be overridden.
125 if (const auto *SubRC = TRI.getCommonSubClass(
126 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))
127 OpRC = SubRC;
128
129 OpRC = TRI.getAllocatableClass(OpRC);
130 }
131
132 if (!OpRC) {
133 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
134 "Register class constraint is required unless either the "
135 "instruction is target independent or the operand is a use");
136 // FIXME: Just bailing out like this here could be not enough, unless we
137 // expect the users of this function to do the right thing for PHIs and
138 // COPY:
139 // v1 = COPY v0
140 // v2 = COPY v1
141 // v1 here may end up not being constrained at all. Please notice that to
142 // reproduce the issue we likely need a destination pattern of a selection
143 // rule producing such extra copies, not just an input GMIR with them as
144 // every existing target using selectImpl handles copies before calling it
145 // and they never reach this function.
146 return Reg;
147 }
148 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
149 RegMO);
150}
151
153 const TargetInstrInfo &TII,
154 const TargetRegisterInfo &TRI,
155 const RegisterBankInfo &RBI) {
156 assert(!isPreISelGenericOpcode(I.getOpcode()) &&
157 "A selected instruction is expected");
158 MachineBasicBlock &MBB = *I.getParent();
161
162 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
163 MachineOperand &MO = I.getOperand(OpI);
164
165 // There's nothing to be done on non-register operands.
166 if (!MO.isReg())
167 continue;
168
169 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
170 assert(MO.isReg() && "Unsupported non-reg operand");
171
172 Register Reg = MO.getReg();
173 // Physical registers don't need to be constrained.
174 if (Reg.isPhysical())
175 continue;
176
177 // Register operands with a value of 0 (e.g. predicate operands) don't need
178 // to be constrained.
179 if (Reg == 0)
180 continue;
181
182 // If the operand is a vreg, we should constrain its regclass, and only
183 // insert COPYs if that's impossible.
184 // constrainOperandRegClass does that for us.
185 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
186
187 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
188 // done.
189 if (MO.isUse()) {
190 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
191 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
192 I.tieOperands(DefIdx, OpI);
193 }
194 }
195 return true;
196}
197
200 // Give up if either DstReg or SrcReg is a physical register.
201 if (DstReg.isPhysical() || SrcReg.isPhysical())
202 return false;
203 // Give up if the types don't match.
204 if (MRI.getType(DstReg) != MRI.getType(SrcReg))
205 return false;
206 // Replace if either DstReg has no constraints or the register
207 // constraints match.
208 const auto &DstRBC = MRI.getRegClassOrRegBank(DstReg);
209 if (!DstRBC || DstRBC == MRI.getRegClassOrRegBank(SrcReg))
210 return true;
211
212 // Otherwise match if the Src is already a regclass that is covered by the Dst
213 // RegBank.
214 return DstRBC.is<const RegisterBank *>() && MRI.getRegClassOrNull(SrcReg) &&
215 DstRBC.get<const RegisterBank *>()->covers(
216 *MRI.getRegClassOrNull(SrcReg));
217}
218
220 const MachineRegisterInfo &MRI) {
221 // FIXME: This logical is mostly duplicated with
222 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
223 // MachineInstr::isLabel?
224
225 // Don't delete frame allocation labels.
226 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
227 return false;
228 // LIFETIME markers should be preserved even if they seem dead.
229 if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
230 MI.getOpcode() == TargetOpcode::LIFETIME_END)
231 return false;
232
233 // If we can move an instruction, we can remove it. Otherwise, it has
234 // a side-effect of some sort.
235 bool SawStore = false;
236 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
237 return false;
238
239 // Instructions without side-effects are dead iff they only define dead vregs.
240 for (const auto &MO : MI.all_defs()) {
241 Register Reg = MO.getReg();
242 if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
243 return false;
244 }
245 return true;
246}
247
249 MachineFunction &MF,
250 const TargetPassConfig &TPC,
253 bool IsFatal = Severity == DS_Error &&
255 // Print the function name explicitly if we don't have a debug location (which
256 // makes the diagnostic less useful) or if we're going to emit a raw error.
257 if (!R.getLocation().isValid() || IsFatal)
258 R << (" (in function: " + MF.getName() + ")").str();
259
260 if (IsFatal)
261 report_fatal_error(Twine(R.getMsg()));
262 else
263 MORE.emit(R);
264}
265
270}
271
275 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
276 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
277}
278
281 const char *PassName, StringRef Msg,
282 const MachineInstr &MI) {
283 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
284 MI.getDebugLoc(), MI.getParent());
285 R << Msg;
286 // Printing MI is expensive; only do it if expensive remarks are enabled.
287 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
288 R << ": " << ore::MNV("Inst", MI);
289 reportGISelFailure(MF, TPC, MORE, R);
290}
291
292std::optional<APInt> llvm::getIConstantVRegVal(Register VReg,
293 const MachineRegisterInfo &MRI) {
294 std::optional<ValueAndVReg> ValAndVReg = getIConstantVRegValWithLookThrough(
295 VReg, MRI, /*LookThroughInstrs*/ false);
296 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
297 "Value found while looking through instrs");
298 if (!ValAndVReg)
299 return std::nullopt;
300 return ValAndVReg->Value;
301}
302
303std::optional<int64_t>
305 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI);
306 if (Val && Val->getBitWidth() <= 64)
307 return Val->getSExtValue();
308 return std::nullopt;
309}
310
311namespace {
312
313typedef std::function<bool(const MachineInstr *)> IsOpcodeFn;
314typedef std::function<std::optional<APInt>(const MachineInstr *MI)> GetAPCstFn;
315
316std::optional<ValueAndVReg> getConstantVRegValWithLookThrough(
317 Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode,
318 GetAPCstFn getAPCstValue, bool LookThroughInstrs = true,
319 bool LookThroughAnyExt = false) {
322
323 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
324 LookThroughInstrs) {
325 switch (MI->getOpcode()) {
326 case TargetOpcode::G_ANYEXT:
327 if (!LookThroughAnyExt)
328 return std::nullopt;
329 [[fallthrough]];
330 case TargetOpcode::G_TRUNC:
331 case TargetOpcode::G_SEXT:
332 case TargetOpcode::G_ZEXT:
333 SeenOpcodes.push_back(std::make_pair(
334 MI->getOpcode(),
335 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
336 VReg = MI->getOperand(1).getReg();
337 break;
338 case TargetOpcode::COPY:
339 VReg = MI->getOperand(1).getReg();
340 if (VReg.isPhysical())
341 return std::nullopt;
342 break;
343 case TargetOpcode::G_INTTOPTR:
344 VReg = MI->getOperand(1).getReg();
345 break;
346 default:
347 return std::nullopt;
348 }
349 }
350 if (!MI || !IsConstantOpcode(MI))
351 return std::nullopt;
352
353 std::optional<APInt> MaybeVal = getAPCstValue(MI);
354 if (!MaybeVal)
355 return std::nullopt;
356 APInt &Val = *MaybeVal;
357 while (!SeenOpcodes.empty()) {
358 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
359 switch (OpcodeAndSize.first) {
360 case TargetOpcode::G_TRUNC:
361 Val = Val.trunc(OpcodeAndSize.second);
362 break;
363 case TargetOpcode::G_ANYEXT:
364 case TargetOpcode::G_SEXT:
365 Val = Val.sext(OpcodeAndSize.second);
366 break;
367 case TargetOpcode::G_ZEXT:
368 Val = Val.zext(OpcodeAndSize.second);
369 break;
370 }
371 }
372
373 return ValueAndVReg{Val, VReg};
374}
375
376bool isIConstant(const MachineInstr *MI) {
377 if (!MI)
378 return false;
379 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
380}
381
382bool isFConstant(const MachineInstr *MI) {
383 if (!MI)
384 return false;
385 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
386}
387
388bool isAnyConstant(const MachineInstr *MI) {
389 if (!MI)
390 return false;
391 unsigned Opc = MI->getOpcode();
392 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
393}
394
395std::optional<APInt> getCImmAsAPInt(const MachineInstr *MI) {
396 const MachineOperand &CstVal = MI->getOperand(1);
397 if (CstVal.isCImm())
398 return CstVal.getCImm()->getValue();
399 return std::nullopt;
400}
401
402std::optional<APInt> getCImmOrFPImmAsAPInt(const MachineInstr *MI) {
403 const MachineOperand &CstVal = MI->getOperand(1);
404 if (CstVal.isCImm())
405 return CstVal.getCImm()->getValue();
406 if (CstVal.isFPImm())
407 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
408 return std::nullopt;
409}
410
411} // end anonymous namespace
412
414 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
415 return getConstantVRegValWithLookThrough(VReg, MRI, isIConstant,
416 getCImmAsAPInt, LookThroughInstrs);
417}
418
420 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
421 bool LookThroughAnyExt) {
422 return getConstantVRegValWithLookThrough(
423 VReg, MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
424 LookThroughAnyExt);
425}
426
427std::optional<FPValueAndVReg> llvm::getFConstantVRegValWithLookThrough(
428 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
429 auto Reg = getConstantVRegValWithLookThrough(
430 VReg, MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
431 if (!Reg)
432 return std::nullopt;
434 Reg->VReg};
435}
436
437const ConstantFP *
439 MachineInstr *MI = MRI.getVRegDef(VReg);
440 if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
441 return nullptr;
442 return MI->getOperand(1).getFPImm();
443}
444
445std::optional<DefinitionAndSourceRegister>
447 Register DefSrcReg = Reg;
448 auto *DefMI = MRI.getVRegDef(Reg);
449 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
450 if (!DstTy.isValid())
451 return std::nullopt;
452 unsigned Opc = DefMI->getOpcode();
453 while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
454 Register SrcReg = DefMI->getOperand(1).getReg();
455 auto SrcTy = MRI.getType(SrcReg);
456 if (!SrcTy.isValid())
457 break;
458 DefMI = MRI.getVRegDef(SrcReg);
459 DefSrcReg = SrcReg;
460 Opc = DefMI->getOpcode();
461 }
462 return DefinitionAndSourceRegister{DefMI, DefSrcReg};
463}
464
466 const MachineRegisterInfo &MRI) {
467 std::optional<DefinitionAndSourceRegister> DefSrcReg =
469 return DefSrcReg ? DefSrcReg->MI : nullptr;
470}
471
473 const MachineRegisterInfo &MRI) {
474 std::optional<DefinitionAndSourceRegister> DefSrcReg =
476 return DefSrcReg ? DefSrcReg->Reg : Register();
477}
478
480 const MachineRegisterInfo &MRI) {
482 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
483}
484
485APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
486 if (Size == 32)
487 return APFloat(float(Val));
488 if (Size == 64)
489 return APFloat(Val);
490 if (Size != 16)
491 llvm_unreachable("Unsupported FPConstant size");
492 bool Ignored;
493 APFloat APF(Val);
494 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
495 return APF;
496}
497
498std::optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode,
499 const Register Op1,
500 const Register Op2,
501 const MachineRegisterInfo &MRI) {
502 auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
503 if (!MaybeOp2Cst)
504 return std::nullopt;
505
506 auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
507 if (!MaybeOp1Cst)
508 return std::nullopt;
509
510 const APInt &C1 = MaybeOp1Cst->Value;
511 const APInt &C2 = MaybeOp2Cst->Value;
512 switch (Opcode) {
513 default:
514 break;
515 case TargetOpcode::G_ADD:
516 case TargetOpcode::G_PTR_ADD:
517 return C1 + C2;
518 case TargetOpcode::G_AND:
519 return C1 & C2;
520 case TargetOpcode::G_ASHR:
521 return C1.ashr(C2);
522 case TargetOpcode::G_LSHR:
523 return C1.lshr(C2);
524 case TargetOpcode::G_MUL:
525 return C1 * C2;
526 case TargetOpcode::G_OR:
527 return C1 | C2;
528 case TargetOpcode::G_SHL:
529 return C1 << C2;
530 case TargetOpcode::G_SUB:
531 return C1 - C2;
532 case TargetOpcode::G_XOR:
533 return C1 ^ C2;
534 case TargetOpcode::G_UDIV:
535 if (!C2.getBoolValue())
536 break;
537 return C1.udiv(C2);
538 case TargetOpcode::G_SDIV:
539 if (!C2.getBoolValue())
540 break;
541 return C1.sdiv(C2);
542 case TargetOpcode::G_UREM:
543 if (!C2.getBoolValue())
544 break;
545 return C1.urem(C2);
546 case TargetOpcode::G_SREM:
547 if (!C2.getBoolValue())
548 break;
549 return C1.srem(C2);
550 case TargetOpcode::G_SMIN:
551 return APIntOps::smin(C1, C2);
552 case TargetOpcode::G_SMAX:
553 return APIntOps::smax(C1, C2);
554 case TargetOpcode::G_UMIN:
555 return APIntOps::umin(C1, C2);
556 case TargetOpcode::G_UMAX:
557 return APIntOps::umax(C1, C2);
558 }
559
560 return std::nullopt;
561}
562
563std::optional<APFloat>
564llvm::ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
565 const Register Op2, const MachineRegisterInfo &MRI) {
566 const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
567 if (!Op2Cst)
568 return std::nullopt;
569
570 const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
571 if (!Op1Cst)
572 return std::nullopt;
573
574 APFloat C1 = Op1Cst->getValueAPF();
575 const APFloat &C2 = Op2Cst->getValueAPF();
576 switch (Opcode) {
577 case TargetOpcode::G_FADD:
578 C1.add(C2, APFloat::rmNearestTiesToEven);
579 return C1;
580 case TargetOpcode::G_FSUB:
581 C1.subtract(C2, APFloat::rmNearestTiesToEven);
582 return C1;
583 case TargetOpcode::G_FMUL:
584 C1.multiply(C2, APFloat::rmNearestTiesToEven);
585 return C1;
586 case TargetOpcode::G_FDIV:
587 C1.divide(C2, APFloat::rmNearestTiesToEven);
588 return C1;
589 case TargetOpcode::G_FREM:
590 C1.mod(C2);
591 return C1;
592 case TargetOpcode::G_FCOPYSIGN:
593 C1.copySign(C2);
594 return C1;
595 case TargetOpcode::G_FMINNUM:
596 return minnum(C1, C2);
597 case TargetOpcode::G_FMAXNUM:
598 return maxnum(C1, C2);
599 case TargetOpcode::G_FMINIMUM:
600 return minimum(C1, C2);
601 case TargetOpcode::G_FMAXIMUM:
602 return maximum(C1, C2);
603 case TargetOpcode::G_FMINNUM_IEEE:
604 case TargetOpcode::G_FMAXNUM_IEEE:
605 // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
606 // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
607 // and currently there isn't a nice wrapper in APFloat for the version with
608 // correct snan handling.
609 break;
610 default:
611 break;
612 }
613
614 return std::nullopt;
615}
616
618llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
619 const Register Op2,
620 const MachineRegisterInfo &MRI) {
621 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
622 if (!SrcVec2)
623 return SmallVector<APInt>();
624
625 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
626 if (!SrcVec1)
627 return SmallVector<APInt>();
628
629 SmallVector<APInt> FoldedElements;
630 for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
631 auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
632 SrcVec2->getSourceReg(Idx), MRI);
633 if (!MaybeCst)
634 return SmallVector<APInt>();
635 FoldedElements.push_back(*MaybeCst);
636 }
637 return FoldedElements;
638}
639
641 bool SNaN) {
642 const MachineInstr *DefMI = MRI.getVRegDef(Val);
643 if (!DefMI)
644 return false;
645
646 const TargetMachine& TM = DefMI->getMF()->getTarget();
647 if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
648 return true;
649
650 // If the value is a constant, we can obviously see if it is a NaN or not.
651 if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
652 return !FPVal->getValueAPF().isNaN() ||
653 (SNaN && !FPVal->getValueAPF().isSignaling());
654 }
655
656 if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
657 for (const auto &Op : DefMI->uses())
658 if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
659 return false;
660 return true;
661 }
662
663 switch (DefMI->getOpcode()) {
664 default:
665 break;
666 case TargetOpcode::G_FADD:
667 case TargetOpcode::G_FSUB:
668 case TargetOpcode::G_FMUL:
669 case TargetOpcode::G_FDIV:
670 case TargetOpcode::G_FREM:
671 case TargetOpcode::G_FSIN:
672 case TargetOpcode::G_FCOS:
673 case TargetOpcode::G_FMA:
674 case TargetOpcode::G_FMAD:
675 if (SNaN)
676 return true;
677
678 // TODO: Need isKnownNeverInfinity
679 return false;
680 case TargetOpcode::G_FMINNUM_IEEE:
681 case TargetOpcode::G_FMAXNUM_IEEE: {
682 if (SNaN)
683 return true;
684 // This can return a NaN if either operand is an sNaN, or if both operands
685 // are NaN.
686 return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
690 }
691 case TargetOpcode::G_FMINNUM:
692 case TargetOpcode::G_FMAXNUM: {
693 // Only one needs to be known not-nan, since it will be returned if the
694 // other ends up being one.
695 return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
697 }
698 }
699
700 if (SNaN) {
701 // FP operations quiet. For now, just handle the ones inserted during
702 // legalization.
703 switch (DefMI->getOpcode()) {
704 case TargetOpcode::G_FPEXT:
705 case TargetOpcode::G_FPTRUNC:
706 case TargetOpcode::G_FCANONICALIZE:
707 return true;
708 default:
709 return false;
710 }
711 }
712
713 return false;
714}
715
717 const MachinePointerInfo &MPO) {
718 auto PSV = dyn_cast_if_present<const PseudoSourceValue *>(MPO.V);
719 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
720 MachineFrameInfo &MFI = MF.getFrameInfo();
721 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
722 MPO.Offset);
723 }
724
725 if (const Value *V = dyn_cast_if_present<const Value *>(MPO.V)) {
726 const Module *M = MF.getFunction().getParent();
727 return V->getPointerAlignment(M->getDataLayout());
728 }
729
730 return Align(1);
731}
732
734 const TargetInstrInfo &TII,
735 MCRegister PhysReg,
736 const TargetRegisterClass &RC,
737 const DebugLoc &DL, LLT RegTy) {
738 MachineBasicBlock &EntryMBB = MF.front();
740 Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
741 if (LiveIn) {
742 MachineInstr *Def = MRI.getVRegDef(LiveIn);
743 if (Def) {
744 // FIXME: Should the verifier check this is in the entry block?
745 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
746 return LiveIn;
747 }
748
749 // It's possible the incoming argument register and copy was added during
750 // lowering, but later deleted due to being/becoming dead. If this happens,
751 // re-insert the copy.
752 } else {
753 // The live in register was not present, so add it.
754 LiveIn = MF.addLiveIn(PhysReg, &RC);
755 if (RegTy.isValid())
756 MRI.setType(LiveIn, RegTy);
757 }
758
759 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
760 .addReg(PhysReg);
761 if (!EntryMBB.isLiveIn(PhysReg))
762 EntryMBB.addLiveIn(PhysReg);
763 return LiveIn;
764}
765
766std::optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode,
767 const Register Op1, uint64_t Imm,
768 const MachineRegisterInfo &MRI) {
769 auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
770 if (MaybeOp1Cst) {
771 switch (Opcode) {
772 default:
773 break;
774 case TargetOpcode::G_SEXT_INREG: {
775 LLT Ty = MRI.getType(Op1);
776 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
777 }
778 }
779 }
780 return std::nullopt;
781}
782
783std::optional<APInt> llvm::ConstantFoldCastOp(unsigned Opcode, LLT DstTy,
784 const Register Op0,
785 const MachineRegisterInfo &MRI) {
786 std::optional<APInt> Val = getIConstantVRegVal(Op0, MRI);
787 if (!Val)
788 return Val;
789
790 const unsigned DstSize = DstTy.getScalarSizeInBits();
791
792 switch (Opcode) {
793 case TargetOpcode::G_SEXT:
794 return Val->sext(DstSize);
795 case TargetOpcode::G_ZEXT:
796 case TargetOpcode::G_ANYEXT:
797 // TODO: DAG considers target preference when constant folding any_extend.
798 return Val->zext(DstSize);
799 default:
800 break;
801 }
802
803 llvm_unreachable("unexpected cast opcode to constant fold");
804}
805
806std::optional<APFloat>
807llvm::ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
808 const MachineRegisterInfo &MRI) {
809 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
810 if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
811 APFloat DstVal(getFltSemanticForLLT(DstTy));
812 DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
813 APFloat::rmNearestTiesToEven);
814 return DstVal;
815 }
816 return std::nullopt;
817}
818
819std::optional<SmallVector<unsigned>>
821 LLT Ty = MRI.getType(Src);
822 SmallVector<unsigned> FoldedCTLZs;
823 auto tryFoldScalar = [&](Register R) -> std::optional<unsigned> {
824 auto MaybeCst = getIConstantVRegVal(R, MRI);
825 if (!MaybeCst)
826 return std::nullopt;
827 return MaybeCst->countl_zero();
828 };
829 if (Ty.isVector()) {
830 // Try to constant fold each element.
831 auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
832 if (!BV)
833 return std::nullopt;
834 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
835 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
836 FoldedCTLZs.emplace_back(*MaybeFold);
837 continue;
838 }
839 return std::nullopt;
840 }
841 return FoldedCTLZs;
842 }
843 if (auto MaybeCst = tryFoldScalar(Src)) {
844 FoldedCTLZs.emplace_back(*MaybeCst);
845 return FoldedCTLZs;
846 }
847 return std::nullopt;
848}
849
851 GISelKnownBits *KB) {
852 std::optional<DefinitionAndSourceRegister> DefSrcReg =
854 if (!DefSrcReg)
855 return false;
856
857 const MachineInstr &MI = *DefSrcReg->MI;
858 const LLT Ty = MRI.getType(Reg);
859
860 switch (MI.getOpcode()) {
861 case TargetOpcode::G_CONSTANT: {
862 unsigned BitWidth = Ty.getScalarSizeInBits();
863 const ConstantInt *CI = MI.getOperand(1).getCImm();
864 return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
865 }
866 case TargetOpcode::G_SHL: {
867 // A left-shift of a constant one will have exactly one bit set because
868 // shifting the bit off the end is undefined.
869
870 // TODO: Constant splat
871 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
872 if (*ConstLHS == 1)
873 return true;
874 }
875
876 break;
877 }
878 case TargetOpcode::G_LSHR: {
879 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
880 if (ConstLHS->isSignMask())
881 return true;
882 }
883
884 break;
885 }
886 case TargetOpcode::G_BUILD_VECTOR: {
887 // TODO: Probably should have a recursion depth guard since you could have
888 // bitcasted vector elements.
889 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
890 if (!isKnownToBeAPowerOfTwo(MO.getReg(), MRI, KB))
891 return false;
892
893 return true;
894 }
895 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
896 // Only handle constants since we would need to know if number of leading
897 // zeros is greater than the truncation amount.
898 const unsigned BitWidth = Ty.getScalarSizeInBits();
899 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
900 auto Const = getIConstantVRegVal(MO.getReg(), MRI);
901 if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
902 return false;
903 }
904
905 return true;
906 }
907 default:
908 break;
909 }
910
911 if (!KB)
912 return false;
913
914 // More could be done here, though the above checks are enough
915 // to handle some common cases.
916
917 // Fall back to computeKnownBits to catch other known cases.
918 KnownBits Known = KB->getKnownBits(Reg);
919 return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
920}
921
924}
925
926LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
927 const unsigned OrigSize = OrigTy.getSizeInBits();
928 const unsigned TargetSize = TargetTy.getSizeInBits();
929
930 if (OrigSize == TargetSize)
931 return OrigTy;
932
933 if (OrigTy.isVector()) {
934 const LLT OrigElt = OrigTy.getElementType();
935
936 if (TargetTy.isVector()) {
937 const LLT TargetElt = TargetTy.getElementType();
938
939 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
940 int GCDElts =
941 std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements());
942 // Prefer the original element type.
943 ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
944 return LLT::vector(Mul.divideCoefficientBy(GCDElts),
945 OrigTy.getElementType());
946 }
947 } else {
948 if (OrigElt.getSizeInBits() == TargetSize)
949 return OrigTy;
950 }
951
952 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
953 return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
954 }
955
956 if (TargetTy.isVector()) {
957 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
958 return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
959 }
960
961 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
962
963 // Preserve pointer types.
964 if (LCMSize == OrigSize)
965 return OrigTy;
966 if (LCMSize == TargetSize)
967 return TargetTy;
968
969 return LLT::scalar(LCMSize);
970}
971
972LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
973 if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
974 (OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
975 return getLCMType(OrigTy, TargetTy);
976
977 unsigned OrigTyNumElts = OrigTy.getNumElements();
978 unsigned TargetTyNumElts = TargetTy.getNumElements();
979 if (OrigTyNumElts % TargetTyNumElts == 0)
980 return OrigTy;
981
982 unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);
984 OrigTy.getElementType());
985}
986
987LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
988 const unsigned OrigSize = OrigTy.getSizeInBits();
989 const unsigned TargetSize = TargetTy.getSizeInBits();
990
991 if (OrigSize == TargetSize)
992 return OrigTy;
993
994 if (OrigTy.isVector()) {
995 LLT OrigElt = OrigTy.getElementType();
996 if (TargetTy.isVector()) {
997 LLT TargetElt = TargetTy.getElementType();
998 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
999 int GCD = std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements());
1000 return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
1001 }
1002 } else {
1003 // If the source is a vector of pointers, return a pointer element.
1004 if (OrigElt.getSizeInBits() == TargetSize)
1005 return OrigElt;
1006 }
1007
1008 unsigned GCD = std::gcd(OrigSize, TargetSize);
1009 if (GCD == OrigElt.getSizeInBits())
1010 return OrigElt;
1011
1012 // If we can't produce the original element type, we have to use a smaller
1013 // scalar.
1014 if (GCD < OrigElt.getSizeInBits())
1015 return LLT::scalar(GCD);
1016 return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
1017 }
1018
1019 if (TargetTy.isVector()) {
1020 // Try to preserve the original element type.
1021 LLT TargetElt = TargetTy.getElementType();
1022 if (TargetElt.getSizeInBits() == OrigSize)
1023 return OrigTy;
1024 }
1025
1026 unsigned GCD = std::gcd(OrigSize, TargetSize);
1027 return LLT::scalar(GCD);
1028}
1029
1031 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1032 "Only G_SHUFFLE_VECTOR can have a splat index!");
1033 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
1034 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
1035
1036 // If all elements are undefined, this shuffle can be considered a splat.
1037 // Return 0 for better potential for callers to simplify.
1038 if (FirstDefinedIdx == Mask.end())
1039 return 0;
1040
1041 // Make sure all remaining elements are either undef or the same
1042 // as the first non-undef value.
1043 int SplatValue = *FirstDefinedIdx;
1044 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
1045 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1046 return std::nullopt;
1047
1048 return SplatValue;
1049}
1050
1051static bool isBuildVectorOp(unsigned Opcode) {
1052 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1053 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1054}
1055
1056namespace {
1057
1058std::optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
1059 const MachineRegisterInfo &MRI,
1060 bool AllowUndef) {
1062 if (!MI)
1063 return std::nullopt;
1064
1065 bool isConcatVectorsOp = MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1066 if (!isBuildVectorOp(MI->getOpcode()) && !isConcatVectorsOp)
1067 return std::nullopt;
1068
1069 std::optional<ValueAndVReg> SplatValAndReg;
1070 for (MachineOperand &Op : MI->uses()) {
1071 Register Element = Op.getReg();
1072 // If we have a G_CONCAT_VECTOR, we recursively look into the
1073 // vectors that we're concatenating to see if they're splats.
1074 auto ElementValAndReg =
1075 isConcatVectorsOp
1076 ? getAnyConstantSplat(Element, MRI, AllowUndef)
1078
1079 // If AllowUndef, treat undef as value that will result in a constant splat.
1080 if (!ElementValAndReg) {
1081 if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1082 continue;
1083 return std::nullopt;
1084 }
1085
1086 // Record splat value
1087 if (!SplatValAndReg)
1088 SplatValAndReg = ElementValAndReg;
1089
1090 // Different constant than the one already recorded, not a constant splat.
1091 if (SplatValAndReg->Value != ElementValAndReg->Value)
1092 return std::nullopt;
1093 }
1094
1095 return SplatValAndReg;
1096}
1097
1098} // end anonymous namespace
1099
1101 const MachineRegisterInfo &MRI,
1102 int64_t SplatValue, bool AllowUndef) {
1103 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
1104 return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
1105 return false;
1106}
1107
1109 const MachineRegisterInfo &MRI,
1110 int64_t SplatValue, bool AllowUndef) {
1111 return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1112 AllowUndef);
1113}
1114
1115std::optional<APInt>
1117 if (auto SplatValAndReg =
1118 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false)) {
1119 std::optional<ValueAndVReg> ValAndVReg =
1120 getIConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1121 return ValAndVReg->Value;
1122 }
1123
1124 return std::nullopt;
1125}
1126
1127std::optional<APInt>
1129 const MachineRegisterInfo &MRI) {
1130 return getIConstantSplatVal(MI.getOperand(0).getReg(), MRI);
1131}
1132
1133std::optional<int64_t>
1135 const MachineRegisterInfo &MRI) {
1136 if (auto SplatValAndReg =
1137 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false))
1138 return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1139 return std::nullopt;
1140}
1141
1142std::optional<int64_t>
1144 const MachineRegisterInfo &MRI) {
1145 return getIConstantSplatSExtVal(MI.getOperand(0).getReg(), MRI);
1146}
1147
1148std::optional<FPValueAndVReg>
1150 bool AllowUndef) {
1151 if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1152 return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1153 return std::nullopt;
1154}
1155
1157 const MachineRegisterInfo &MRI,
1158 bool AllowUndef) {
1159 return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1160}
1161
1163 const MachineRegisterInfo &MRI,
1164 bool AllowUndef) {
1165 return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1166}
1167
1168std::optional<RegOrConstant>
1170 unsigned Opc = MI.getOpcode();
1171 if (!isBuildVectorOp(Opc))
1172 return std::nullopt;
1173 if (auto Splat = getIConstantSplatSExtVal(MI, MRI))
1174 return RegOrConstant(*Splat);
1175 auto Reg = MI.getOperand(1).getReg();
1176 if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
1177 [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1178 return std::nullopt;
1179 return RegOrConstant(Reg);
1180}
1181
1183 const MachineRegisterInfo &MRI,
1184 bool AllowFP = true,
1185 bool AllowOpaqueConstants = true) {
1186 switch (MI.getOpcode()) {
1187 case TargetOpcode::G_CONSTANT:
1188 case TargetOpcode::G_IMPLICIT_DEF:
1189 return true;
1190 case TargetOpcode::G_FCONSTANT:
1191 return AllowFP;
1192 case TargetOpcode::G_GLOBAL_VALUE:
1193 case TargetOpcode::G_FRAME_INDEX:
1194 case TargetOpcode::G_BLOCK_ADDR:
1195 case TargetOpcode::G_JUMP_TABLE:
1196 return AllowOpaqueConstants;
1197 default:
1198 return false;
1199 }
1200}
1201
1203 const MachineRegisterInfo &MRI) {
1204 Register Def = MI.getOperand(0).getReg();
1205 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1206 return true;
1207 GBuildVector *BV = dyn_cast<GBuildVector>(&MI);
1208 if (!BV)
1209 return false;
1210 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1212 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI))
1213 continue;
1214 return false;
1215 }
1216 return true;
1217}
1218
1220 const MachineRegisterInfo &MRI,
1221 bool AllowFP, bool AllowOpaqueConstants) {
1222 if (isConstantScalar(MI, MRI, AllowFP, AllowOpaqueConstants))
1223 return true;
1224
1225 if (!isBuildVectorOp(MI.getOpcode()))
1226 return false;
1227
1228 const unsigned NumOps = MI.getNumOperands();
1229 for (unsigned I = 1; I != NumOps; ++I) {
1230 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg());
1231 if (!isConstantScalar(*ElementDef, MRI, AllowFP, AllowOpaqueConstants))
1232 return false;
1233 }
1234
1235 return true;
1236}
1237
1238std::optional<APInt>
1240 const MachineRegisterInfo &MRI) {
1241 Register Def = MI.getOperand(0).getReg();
1242 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1243 return C->Value;
1244 auto MaybeCst = getIConstantSplatSExtVal(MI, MRI);
1245 if (!MaybeCst)
1246 return std::nullopt;
1247 const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1248 return APInt(ScalarSize, *MaybeCst, true);
1249}
1250
1252 const MachineRegisterInfo &MRI, bool AllowUndefs) {
1253 switch (MI.getOpcode()) {
1254 case TargetOpcode::G_IMPLICIT_DEF:
1255 return AllowUndefs;
1256 case TargetOpcode::G_CONSTANT:
1257 return MI.getOperand(1).getCImm()->isNullValue();
1258 case TargetOpcode::G_FCONSTANT: {
1259 const ConstantFP *FPImm = MI.getOperand(1).getFPImm();
1260 return FPImm->isZero() && !FPImm->isNegative();
1261 }
1262 default:
1263 if (!AllowUndefs) // TODO: isBuildVectorAllZeros assumes undef is OK already
1264 return false;
1265 return isBuildVectorAllZeros(MI, MRI);
1266 }
1267}
1268
1270 const MachineRegisterInfo &MRI,
1271 bool AllowUndefs) {
1272 switch (MI.getOpcode()) {
1273 case TargetOpcode::G_IMPLICIT_DEF:
1274 return AllowUndefs;
1275 case TargetOpcode::G_CONSTANT:
1276 return MI.getOperand(1).getCImm()->isAllOnesValue();
1277 default:
1278 if (!AllowUndefs) // TODO: isBuildVectorAllOnes assumes undef is OK already
1279 return false;
1280 return isBuildVectorAllOnes(MI, MRI);
1281 }
1282}
1283
1285 const MachineRegisterInfo &MRI, Register Reg,
1286 std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1287
1288 const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
1289 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1290 return Match(nullptr);
1291
1292 // TODO: Also handle fconstant
1293 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1294 return Match(Def->getOperand(1).getCImm());
1295
1296 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1297 return false;
1298
1299 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1300 Register SrcElt = Def->getOperand(I).getReg();
1301 const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1302 if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1303 if (!Match(nullptr))
1304 return false;
1305 continue;
1306 }
1307
1308 if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1309 !Match(SrcDef->getOperand(1).getCImm()))
1310 return false;
1311 }
1312
1313 return true;
1314}
1315
1316bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1317 bool IsFP) {
1318 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1319 case TargetLowering::UndefinedBooleanContent:
1320 return Val & 0x1;
1321 case TargetLowering::ZeroOrOneBooleanContent:
1322 return Val == 1;
1323 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1324 return Val == -1;
1325 }
1326 llvm_unreachable("Invalid boolean contents");
1327}
1328
1329bool llvm::isConstFalseVal(const TargetLowering &TLI, int64_t Val,
1330 bool IsVector, bool IsFP) {
1331 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1332 case TargetLowering::UndefinedBooleanContent:
1333 return ~Val & 0x1;
1334 case TargetLowering::ZeroOrOneBooleanContent:
1335 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1336 return Val == 0;
1337 }
1338 llvm_unreachable("Invalid boolean contents");
1339}
1340
1341int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1342 bool IsFP) {
1343 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1344 case TargetLowering::UndefinedBooleanContent:
1345 case TargetLowering::ZeroOrOneBooleanContent:
1346 return 1;
1347 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1348 return -1;
1349 }
1350 llvm_unreachable("Invalid boolean contents");
1351}
1352
1355 const auto &F = MBB.getParent()->getFunction();
1356 return F.hasOptSize() || F.hasMinSize() ||
1358}
1359
1361 LostDebugLocObserver *LocObserver,
1362 SmallInstListTy &DeadInstChain) {
1363 for (MachineOperand &Op : MI.uses()) {
1364 if (Op.isReg() && Op.getReg().isVirtual())
1365 DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1366 }
1367 LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1368 DeadInstChain.remove(&MI);
1369 MI.eraseFromParent();
1370 if (LocObserver)
1371 LocObserver->checkpoint(false);
1372}
1373
1376 LostDebugLocObserver *LocObserver) {
1377 SmallInstListTy DeadInstChain;
1378 for (MachineInstr *MI : DeadInstrs)
1379 saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1380
1381 while (!DeadInstChain.empty()) {
1382 MachineInstr *Inst = DeadInstChain.pop_back_val();
1383 if (!isTriviallyDead(*Inst, MRI))
1384 continue;
1385 saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1386 }
1387}
1388
1390 LostDebugLocObserver *LocObserver) {
1391 return eraseInstrs({&MI}, MRI, LocObserver);
1392}
1393
1395 for (auto &Def : MI.defs()) {
1396 assert(Def.isReg() && "Must be a reg");
1397
1399 for (auto &MOUse : MRI.use_operands(Def.getReg())) {
1400 MachineInstr *DbgValue = MOUse.getParent();
1401 // Ignore partially formed DBG_VALUEs.
1402 if (DbgValue->isNonListDebugValue() && DbgValue->getNumOperands() == 4) {
1403 DbgUsers.push_back(&MOUse);
1404 }
1405 }
1406
1407 if (!DbgUsers.empty()) {
1409 }
1410 }
1411}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
basic Basic Alias true
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:248
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:1051
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Definition: Utils.cpp:1182
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Tracks DebugLocs between checkpoints and verifies that they are transferred.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Contains matchers for matching SSA Machine Instructions.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
static const char PassName[]
BinaryOperator * Mul
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1067
void copySign(const APFloat &RHS)
Definition: APFloat.h:1161
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:5196
opStatus subtract(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1049
opStatus add(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1040
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition: APFloat.h:1191
opStatus multiply(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1058
APInt bitcastToAPInt() const
Definition: APFloat.h:1208
opStatus mod(const APFloat &RHS)
Definition: APFloat.h:1085
Class for arbitrary precision integers.
Definition: APInt.h:76
APInt udiv(const APInt &RHS) const
Unsigned division operation.
Definition: APInt.cpp:1579
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:981
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:1002
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:906
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1672
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
Definition: APInt.cpp:1650
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:805
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
Definition: APInt.cpp:1742
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:954
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:418
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:829
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
const APFloat & getValueAPF() const
Definition: Constants.h:296
bool isNegative() const
Return true if the sign bit is set.
Definition: Constants.h:303
bool isZero() const
Return true if the value is positive or negative zero.
Definition: Constants.h:300
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:136
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:291
Represents a G_BUILD_VECTOR.
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:74
MachineInstr * pop_back_val()
bool empty() const
Definition: GISelWorkList.h:38
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:83
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:249
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelType.h:56
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr bool isValid() const
Definition: LowLevelType.h:137
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:149
constexpr bool isVector() const
Definition: LowLevelType.h:145
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:175
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:272
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:166
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:92
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
Definition: LowLevelType.h:116
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:230
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionProperties & set(Property P)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:326
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:376
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:707
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:472
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Diagnostic information for missed-optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Analysis providing profile information.
Represents a value which can be a Register or a constant.
Definition: Utils.h:360
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
bool empty() const
Definition: SmallVector.h:94
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Definition: APInt.h:2171
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition: APInt.h:2176
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition: APInt.h:2181
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition: APInt.h:2186
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:733
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:330
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1156
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:53
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:479
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:438
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:292
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:807
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1116
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1269
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:564
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: Utils.cpp:1394
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:152
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:766
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1169
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
Definition: APFloat.h:1428
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1239
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1251
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:465
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1284
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1316
bool isKnownNeverNaN(const Value *V, const DataLayout &DL, const TargetLibraryInfo *TLI, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:926
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:304
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:498
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1353
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1404
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1219
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:198
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1360
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:272
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:419
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1162
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:618
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1149
std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:783
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:922
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:972
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1393
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:427
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Definition: Utils.cpp:1329
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:184
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:485
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1100
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1389
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
@ DS_Warning
@ DS_Error
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:43
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1341
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:413
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1754
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:309
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:446
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1374
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:472
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:987
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
Definition: APFloat.h:1415
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1134
std::optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:820
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:219
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:716
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:266
#define MORE()
Definition: regcomp.c:252
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:223
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:280
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:277
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:182