LLVM  14.0.0git
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file This file implements the utility functions used by the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/Optional.h"
32 #include "llvm/IR/Constants.h"
34 
35 #define DEBUG_TYPE "globalisel-utils"
36 
37 using namespace llvm;
38 using namespace MIPatternMatch;
39 
41  const TargetInstrInfo &TII,
42  const RegisterBankInfo &RBI, Register Reg,
43  const TargetRegisterClass &RegClass) {
44  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
45  return MRI.createVirtualRegister(&RegClass);
46 
47  return Reg;
48 }
49 
51  const MachineFunction &MF, const TargetRegisterInfo &TRI,
53  const RegisterBankInfo &RBI, MachineInstr &InsertPt,
54  const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
55  Register Reg = RegMO.getReg();
56  // Assume physical registers are properly constrained.
57  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
58 
59  Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
60  // If we created a new virtual register because the class is not compatible
61  // then create a copy between the new and the old register.
62  if (ConstrainedReg != Reg) {
63  MachineBasicBlock::iterator InsertIt(&InsertPt);
64  MachineBasicBlock &MBB = *InsertPt.getParent();
65  // FIXME: The copy needs to have the classes constrained for its operands.
66  // Use operand's regbank to get the class for old register (Reg).
67  if (RegMO.isUse()) {
68  BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
69  TII.get(TargetOpcode::COPY), ConstrainedReg)
70  .addReg(Reg);
71  } else {
72  assert(RegMO.isDef() && "Must be a definition");
73  BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
74  TII.get(TargetOpcode::COPY), Reg)
75  .addReg(ConstrainedReg);
76  }
77  if (GISelChangeObserver *Observer = MF.getObserver()) {
78  Observer->changingInstr(*RegMO.getParent());
79  }
80  RegMO.setReg(ConstrainedReg);
81  if (GISelChangeObserver *Observer = MF.getObserver()) {
82  Observer->changedInstr(*RegMO.getParent());
83  }
84  } else {
85  if (GISelChangeObserver *Observer = MF.getObserver()) {
86  if (!RegMO.isDef()) {
87  MachineInstr *RegDef = MRI.getVRegDef(Reg);
88  Observer->changedInstr(*RegDef);
89  }
90  Observer->changingAllUsesOfReg(MRI, Reg);
91  Observer->finishedChangingAllUsesOfReg();
92  }
93  }
94  return ConstrainedReg;
95 }
96 
98  const MachineFunction &MF, const TargetRegisterInfo &TRI,
100  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
101  MachineOperand &RegMO, unsigned OpIdx) {
102  Register Reg = RegMO.getReg();
103  // Assume physical registers are properly constrained.
104  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
105 
106  const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
107  // Some of the target independent instructions, like COPY, may not impose any
108  // register class constraints on some of their operands: If it's a use, we can
109  // skip constraining as the instruction defining the register would constrain
110  // it.
111 
112  if (OpRC) {
113  // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
114  // can have multiple regbanks for a superclass that combine different
115  // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
116  // resolved by targets during regbankselect should not be overridden.
117  if (const auto *SubRC = TRI.getCommonSubClass(
119  OpRC = SubRC;
120 
121  OpRC = TRI.getAllocatableClass(OpRC);
122  }
123 
124  if (!OpRC) {
125  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
126  "Register class constraint is required unless either the "
127  "instruction is target independent or the operand is a use");
128  // FIXME: Just bailing out like this here could be not enough, unless we
129  // expect the users of this function to do the right thing for PHIs and
130  // COPY:
131  // v1 = COPY v0
132  // v2 = COPY v1
133  // v1 here may end up not being constrained at all. Please notice that to
134  // reproduce the issue we likely need a destination pattern of a selection
135  // rule producing such extra copies, not just an input GMIR with them as
136  // every existing target using selectImpl handles copies before calling it
137  // and they never reach this function.
138  return Reg;
139  }
140  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
141  RegMO);
142 }
143 
145  const TargetInstrInfo &TII,
146  const TargetRegisterInfo &TRI,
147  const RegisterBankInfo &RBI) {
148  assert(!isPreISelGenericOpcode(I.getOpcode()) &&
149  "A selected instruction is expected");
150  MachineBasicBlock &MBB = *I.getParent();
151  MachineFunction &MF = *MBB.getParent();
153 
154  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
155  MachineOperand &MO = I.getOperand(OpI);
156 
157  // There's nothing to be done on non-register operands.
158  if (!MO.isReg())
159  continue;
160 
161  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
162  assert(MO.isReg() && "Unsupported non-reg operand");
163 
164  Register Reg = MO.getReg();
165  // Physical registers don't need to be constrained.
167  continue;
168 
169  // Register operands with a value of 0 (e.g. predicate operands) don't need
170  // to be constrained.
171  if (Reg == 0)
172  continue;
173 
174  // If the operand is a vreg, we should constrain its regclass, and only
175  // insert COPYs if that's impossible.
176  // constrainOperandRegClass does that for us.
177  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
178 
179  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
180  // done.
181  if (MO.isUse()) {
182  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
183  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
184  I.tieOperands(DefIdx, OpI);
185  }
186  }
187  return true;
188 }
189 
192  // Give up if either DstReg or SrcReg is a physical register.
193  if (DstReg.isPhysical() || SrcReg.isPhysical())
194  return false;
195  // Give up if the types don't match.
196  if (MRI.getType(DstReg) != MRI.getType(SrcReg))
197  return false;
198  // Replace if either DstReg has no constraints or the register
199  // constraints match.
200  return !MRI.getRegClassOrRegBank(DstReg) ||
202 }
203 
205  const MachineRegisterInfo &MRI) {
206  // FIXME: This logical is mostly duplicated with
207  // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
208  // MachineInstr::isLabel?
209 
210  // Don't delete frame allocation labels.
211  if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
212  return false;
213  // LIFETIME markers should be preserved even if they seem dead.
214  if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
215  MI.getOpcode() == TargetOpcode::LIFETIME_END)
216  return false;
217 
218  // If we can move an instruction, we can remove it. Otherwise, it has
219  // a side-effect of some sort.
220  bool SawStore = false;
221  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
222  return false;
223 
224  // Instructions without side-effects are dead iff they only define dead vregs.
225  for (auto &MO : MI.operands()) {
226  if (!MO.isReg() || !MO.isDef())
227  continue;
228 
229  Register Reg = MO.getReg();
231  return false;
232  }
233  return true;
234 }
235 
237  MachineFunction &MF,
238  const TargetPassConfig &TPC,
241  bool IsFatal = Severity == DS_Error &&
243  // Print the function name explicitly if we don't have a debug location (which
244  // makes the diagnostic less useful) or if we're going to emit a raw error.
245  if (!R.getLocation().isValid() || IsFatal)
246  R << (" (in function: " + MF.getName() + ")").str();
247 
248  if (IsFatal)
249  report_fatal_error(Twine(R.getMsg()));
250  else
251  MORE.emit(R);
252 }
253 
257  reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R);
258 }
259 
264  reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
265 }
266 
269  const char *PassName, StringRef Msg,
270  const MachineInstr &MI) {
271  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
272  MI.getDebugLoc(), MI.getParent());
273  R << Msg;
274  // Printing MI is expensive; only do it if expensive remarks are enabled.
275  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
276  R << ": " << ore::MNV("Inst", MI);
277  reportGISelFailure(MF, TPC, MORE, R);
278 }
279 
281  const MachineRegisterInfo &MRI) {
283  VReg, MRI, /*LookThroughInstrs*/ false);
284  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
285  "Value found while looking through instrs");
286  if (!ValAndVReg)
287  return None;
288  return ValAndVReg->Value;
289 }
290 
294  if (Val && Val->getBitWidth() <= 64)
295  return Val->getSExtValue();
296  return None;
297 }
298 
299 namespace {
300 
301 typedef std::function<bool(const MachineInstr *)> IsOpcodeFn;
302 typedef std::function<Optional<APInt>(const MachineInstr *MI)> GetAPCstFn;
303 
304 Optional<ValueAndVReg> getConstantVRegValWithLookThrough(
305  Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode,
306  GetAPCstFn getAPCstValue, bool LookThroughInstrs = true,
307  bool LookThroughAnyExt = false) {
309  MachineInstr *MI;
310 
311  while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
312  LookThroughInstrs) {
313  switch (MI->getOpcode()) {
314  case TargetOpcode::G_ANYEXT:
315  if (!LookThroughAnyExt)
316  return None;
318  case TargetOpcode::G_TRUNC:
319  case TargetOpcode::G_SEXT:
320  case TargetOpcode::G_ZEXT:
321  SeenOpcodes.push_back(std::make_pair(
322  MI->getOpcode(),
323  MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
324  VReg = MI->getOperand(1).getReg();
325  break;
326  case TargetOpcode::COPY:
327  VReg = MI->getOperand(1).getReg();
329  return None;
330  break;
331  case TargetOpcode::G_INTTOPTR:
332  VReg = MI->getOperand(1).getReg();
333  break;
334  default:
335  return None;
336  }
337  }
338  if (!MI || !IsConstantOpcode(MI))
339  return None;
340 
341  Optional<APInt> MaybeVal = getAPCstValue(MI);
342  if (!MaybeVal)
343  return None;
344  APInt &Val = *MaybeVal;
345  while (!SeenOpcodes.empty()) {
346  std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
347  switch (OpcodeAndSize.first) {
348  case TargetOpcode::G_TRUNC:
349  Val = Val.trunc(OpcodeAndSize.second);
350  break;
351  case TargetOpcode::G_ANYEXT:
352  case TargetOpcode::G_SEXT:
353  Val = Val.sext(OpcodeAndSize.second);
354  break;
355  case TargetOpcode::G_ZEXT:
356  Val = Val.zext(OpcodeAndSize.second);
357  break;
358  }
359  }
360 
361  return ValueAndVReg{Val, VReg};
362 }
363 
364 bool isIConstant(const MachineInstr *MI) {
365  if (!MI)
366  return false;
367  return MI->getOpcode() == TargetOpcode::G_CONSTANT;
368 }
369 
370 bool isFConstant(const MachineInstr *MI) {
371  if (!MI)
372  return false;
373  return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
374 }
375 
376 bool isAnyConstant(const MachineInstr *MI) {
377  if (!MI)
378  return false;
379  unsigned Opc = MI->getOpcode();
380  return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
381 }
382 
383 Optional<APInt> getCImmAsAPInt(const MachineInstr *MI) {
384  const MachineOperand &CstVal = MI->getOperand(1);
385  if (CstVal.isCImm())
386  return CstVal.getCImm()->getValue();
387  return None;
388 }
389 
390 Optional<APInt> getCImmOrFPImmAsAPInt(const MachineInstr *MI) {
391  const MachineOperand &CstVal = MI->getOperand(1);
392  if (CstVal.isCImm())
393  return CstVal.getCImm()->getValue();
394  if (CstVal.isFPImm())
395  return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
396  return None;
397 }
398 
399 } // end anonymous namespace
400 
402  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
403  return getConstantVRegValWithLookThrough(VReg, MRI, isIConstant,
404  getCImmAsAPInt, LookThroughInstrs);
405 }
406 
408  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
409  bool LookThroughAnyExt) {
410  return getConstantVRegValWithLookThrough(
411  VReg, MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
412  LookThroughAnyExt);
413 }
414 
416  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
417  auto Reg = getConstantVRegValWithLookThrough(
418  VReg, MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
419  if (!Reg)
420  return None;
422  Reg->VReg};
423 }
424 
425 const ConstantFP *
427  MachineInstr *MI = MRI.getVRegDef(VReg);
428  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
429  return nullptr;
430  return MI->getOperand(1).getFPImm();
431 }
432 
435  Register DefSrcReg = Reg;
436  auto *DefMI = MRI.getVRegDef(Reg);
437  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
438  if (!DstTy.isValid())
439  return None;
440  unsigned Opc = DefMI->getOpcode();
441  while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
442  Register SrcReg = DefMI->getOperand(1).getReg();
443  auto SrcTy = MRI.getType(SrcReg);
444  if (!SrcTy.isValid())
445  break;
446  DefMI = MRI.getVRegDef(SrcReg);
447  DefSrcReg = SrcReg;
448  Opc = DefMI->getOpcode();
449  }
450  return DefinitionAndSourceRegister{DefMI, DefSrcReg};
451 }
452 
454  const MachineRegisterInfo &MRI) {
457  return DefSrcReg ? DefSrcReg->MI : nullptr;
458 }
459 
461  const MachineRegisterInfo &MRI) {
464  return DefSrcReg ? DefSrcReg->Reg : Register();
465 }
466 
468  const MachineRegisterInfo &MRI) {
470  return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
471 }
472 
473 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
474  if (Size == 32)
475  return APFloat(float(Val));
476  if (Size == 64)
477  return APFloat(Val);
478  if (Size != 16)
479  llvm_unreachable("Unsupported FPConstant size");
480  bool Ignored;
481  APFloat APF(Val);
483  return APF;
484 }
485 
487  const Register Op2,
488  const MachineRegisterInfo &MRI) {
489  auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
490  if (!MaybeOp2Cst)
491  return None;
492 
493  auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
494  if (!MaybeOp1Cst)
495  return None;
496 
497  const APInt &C1 = MaybeOp1Cst->Value;
498  const APInt &C2 = MaybeOp2Cst->Value;
499  switch (Opcode) {
500  default:
501  break;
502  case TargetOpcode::G_ADD:
503  return C1 + C2;
504  case TargetOpcode::G_AND:
505  return C1 & C2;
506  case TargetOpcode::G_ASHR:
507  return C1.ashr(C2);
508  case TargetOpcode::G_LSHR:
509  return C1.lshr(C2);
510  case TargetOpcode::G_MUL:
511  return C1 * C2;
512  case TargetOpcode::G_OR:
513  return C1 | C2;
514  case TargetOpcode::G_SHL:
515  return C1 << C2;
516  case TargetOpcode::G_SUB:
517  return C1 - C2;
518  case TargetOpcode::G_XOR:
519  return C1 ^ C2;
520  case TargetOpcode::G_UDIV:
521  if (!C2.getBoolValue())
522  break;
523  return C1.udiv(C2);
524  case TargetOpcode::G_SDIV:
525  if (!C2.getBoolValue())
526  break;
527  return C1.sdiv(C2);
528  case TargetOpcode::G_UREM:
529  if (!C2.getBoolValue())
530  break;
531  return C1.urem(C2);
532  case TargetOpcode::G_SREM:
533  if (!C2.getBoolValue())
534  break;
535  return C1.srem(C2);
536  }
537 
538  return None;
539 }
540 
542  const Register Op2,
543  const MachineRegisterInfo &MRI) {
544  const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
545  if (!Op2Cst)
546  return None;
547 
548  const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
549  if (!Op1Cst)
550  return None;
551 
552  APFloat C1 = Op1Cst->getValueAPF();
553  const APFloat &C2 = Op2Cst->getValueAPF();
554  switch (Opcode) {
555  case TargetOpcode::G_FADD:
557  return C1;
558  case TargetOpcode::G_FSUB:
559  C1.subtract(C2, APFloat::rmNearestTiesToEven);
560  return C1;
561  case TargetOpcode::G_FMUL:
562  C1.multiply(C2, APFloat::rmNearestTiesToEven);
563  return C1;
564  case TargetOpcode::G_FDIV:
565  C1.divide(C2, APFloat::rmNearestTiesToEven);
566  return C1;
567  case TargetOpcode::G_FREM:
568  C1.mod(C2);
569  return C1;
570  case TargetOpcode::G_FCOPYSIGN:
571  C1.copySign(C2);
572  return C1;
573  case TargetOpcode::G_FMINNUM:
574  return minnum(C1, C2);
575  case TargetOpcode::G_FMAXNUM:
576  return maxnum(C1, C2);
577  case TargetOpcode::G_FMINIMUM:
578  return minimum(C1, C2);
579  case TargetOpcode::G_FMAXIMUM:
580  return maximum(C1, C2);
581  case TargetOpcode::G_FMINNUM_IEEE:
582  case TargetOpcode::G_FMAXNUM_IEEE:
583  // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
584  // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
585  // and currently there isn't a nice wrapper in APFloat for the version with
586  // correct snan handling.
587  break;
588  default:
589  break;
590  }
591 
592  return None;
593 }
594 
596 llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
597  const Register Op2,
598  const MachineRegisterInfo &MRI,
599  MachineIRBuilder &MIB) {
600  auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
601  if (!SrcVec1)
602  return None;
603  auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
604  if (!SrcVec2)
605  return None;
606 
607  const LLT EltTy = MRI.getType(SrcVec1->getSourceReg(0));
608 
609  SmallVector<Register, 16> FoldedElements;
610  for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
611  auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
612  SrcVec2->getSourceReg(Idx), MRI);
613  if (!MaybeCst)
614  return None;
615  auto FoldedCstReg = MIB.buildConstant(EltTy, *MaybeCst).getReg(0);
616  FoldedElements.emplace_back(FoldedCstReg);
617  }
618  // Create the new vector constant.
619  auto CstVec =
620  MIB.buildBuildVector(MRI.getType(SrcVec1->getReg(0)), FoldedElements);
621  return &*CstVec;
622 }
623 
625  bool SNaN) {
626  const MachineInstr *DefMI = MRI.getVRegDef(Val);
627  if (!DefMI)
628  return false;
629 
630  const TargetMachine& TM = DefMI->getMF()->getTarget();
631  if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
632  return true;
633 
634  // If the value is a constant, we can obviously see if it is a NaN or not.
635  if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
636  return !FPVal->getValueAPF().isNaN() ||
637  (SNaN && !FPVal->getValueAPF().isSignaling());
638  }
639 
640  if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
641  for (const auto &Op : DefMI->uses())
642  if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
643  return false;
644  return true;
645  }
646 
647  switch (DefMI->getOpcode()) {
648  default:
649  break;
650  case TargetOpcode::G_FMINNUM_IEEE:
651  case TargetOpcode::G_FMAXNUM_IEEE: {
652  if (SNaN)
653  return true;
654  // This can return a NaN if either operand is an sNaN, or if both operands
655  // are NaN.
656  return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
660  }
661  case TargetOpcode::G_FMINNUM:
662  case TargetOpcode::G_FMAXNUM: {
663  // Only one needs to be known not-nan, since it will be returned if the
664  // other ends up being one.
665  return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
666  isKnownNeverNaN(DefMI->getOperand(2).getReg(), MRI, SNaN);
667  }
668  }
669 
670  if (SNaN) {
671  // FP operations quiet. For now, just handle the ones inserted during
672  // legalization.
673  switch (DefMI->getOpcode()) {
674  case TargetOpcode::G_FPEXT:
675  case TargetOpcode::G_FPTRUNC:
676  case TargetOpcode::G_FCANONICALIZE:
677  return true;
678  default:
679  return false;
680  }
681  }
682 
683  return false;
684 }
685 
687  const MachinePointerInfo &MPO) {
688  auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>();
689  if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
690  MachineFrameInfo &MFI = MF.getFrameInfo();
691  return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
692  MPO.Offset);
693  }
694 
695  if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
696  const Module *M = MF.getFunction().getParent();
697  return V->getPointerAlignment(M->getDataLayout());
698  }
699 
700  return Align(1);
701 }
702 
704  const TargetInstrInfo &TII,
705  MCRegister PhysReg,
706  const TargetRegisterClass &RC,
707  const DebugLoc &DL, LLT RegTy) {
708  MachineBasicBlock &EntryMBB = MF.front();
710  Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
711  if (LiveIn) {
712  MachineInstr *Def = MRI.getVRegDef(LiveIn);
713  if (Def) {
714  // FIXME: Should the verifier check this is in the entry block?
715  assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
716  return LiveIn;
717  }
718 
719  // It's possible the incoming argument register and copy was added during
720  // lowering, but later deleted due to being/becoming dead. If this happens,
721  // re-insert the copy.
722  } else {
723  // The live in register was not present, so add it.
724  LiveIn = MF.addLiveIn(PhysReg, &RC);
725  if (RegTy.isValid())
726  MRI.setType(LiveIn, RegTy);
727  }
728 
729  BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
730  .addReg(PhysReg);
731  if (!EntryMBB.isLiveIn(PhysReg))
732  EntryMBB.addLiveIn(PhysReg);
733  return LiveIn;
734 }
735 
737  uint64_t Imm,
738  const MachineRegisterInfo &MRI) {
739  auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
740  if (MaybeOp1Cst) {
741  switch (Opcode) {
742  default:
743  break;
744  case TargetOpcode::G_SEXT_INREG: {
745  LLT Ty = MRI.getType(Op1);
746  return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
747  }
748  }
749  }
750  return None;
751 }
752 
754  Register Src,
755  const MachineRegisterInfo &MRI) {
756  assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
757  if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
758  APFloat DstVal(getFltSemanticForLLT(DstTy));
759  DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
761  return DstVal;
762  }
763  return None;
764 }
765 
768  LLT Ty = MRI.getType(Src);
769  SmallVector<unsigned> FoldedCTLZs;
770  auto tryFoldScalar = [&](Register R) -> Optional<unsigned> {
771  auto MaybeCst = getIConstantVRegVal(R, MRI);
772  if (!MaybeCst)
773  return None;
774  return MaybeCst->countLeadingZeros();
775  };
776  if (Ty.isVector()) {
777  // Try to constant fold each element.
778  auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
779  if (!BV)
780  return None;
781  for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
782  if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
783  FoldedCTLZs.emplace_back(*MaybeFold);
784  continue;
785  }
786  return None;
787  }
788  return FoldedCTLZs;
789  }
790  if (auto MaybeCst = tryFoldScalar(Src)) {
791  FoldedCTLZs.emplace_back(*MaybeCst);
792  return FoldedCTLZs;
793  }
794  return None;
795 }
796 
798  GISelKnownBits *KB) {
801  if (!DefSrcReg)
802  return false;
803 
804  const MachineInstr &MI = *DefSrcReg->MI;
805  const LLT Ty = MRI.getType(Reg);
806 
807  switch (MI.getOpcode()) {
808  case TargetOpcode::G_CONSTANT: {
809  unsigned BitWidth = Ty.getScalarSizeInBits();
810  const ConstantInt *CI = MI.getOperand(1).getCImm();
811  return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
812  }
813  case TargetOpcode::G_SHL: {
814  // A left-shift of a constant one will have exactly one bit set because
815  // shifting the bit off the end is undefined.
816 
817  // TODO: Constant splat
818  if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
819  if (*ConstLHS == 1)
820  return true;
821  }
822 
823  break;
824  }
825  case TargetOpcode::G_LSHR: {
826  if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
827  if (ConstLHS->isSignMask())
828  return true;
829  }
830 
831  break;
832  }
833  case TargetOpcode::G_BUILD_VECTOR: {
834  // TODO: Probably should have a recursion depth guard since you could have
835  // bitcasted vector elements.
836  for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
837  if (!isKnownToBeAPowerOfTwo(MO.getReg(), MRI, KB))
838  return false;
839 
840  return true;
841  }
842  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
843  // Only handle constants since we would need to know if number of leading
844  // zeros is greater than the truncation amount.
845  const unsigned BitWidth = Ty.getScalarSizeInBits();
846  for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
847  auto Const = getIConstantVRegVal(MO.getReg(), MRI);
848  if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
849  return false;
850  }
851 
852  return true;
853  }
854  default:
855  break;
856  }
857 
858  if (!KB)
859  return false;
860 
861  // More could be done here, though the above checks are enough
862  // to handle some common cases.
863 
864  // Fall back to computeKnownBits to catch other known cases.
865  KnownBits Known = KB->getKnownBits(Reg);
866  return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
867 }
868 
871 }
872 
873 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) {
874  unsigned Mul = OrigSize * TargetSize;
875  unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize);
876  return Mul / GCDSize;
877 }
878 
879 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
880  const unsigned OrigSize = OrigTy.getSizeInBits();
881  const unsigned TargetSize = TargetTy.getSizeInBits();
882 
883  if (OrigSize == TargetSize)
884  return OrigTy;
885 
886  if (OrigTy.isVector()) {
887  const LLT OrigElt = OrigTy.getElementType();
888 
889  if (TargetTy.isVector()) {
890  const LLT TargetElt = TargetTy.getElementType();
891 
892  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
893  int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(),
894  TargetTy.getNumElements());
895  // Prefer the original element type.
896  ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
897  return LLT::vector(Mul.divideCoefficientBy(GCDElts),
898  OrigTy.getElementType());
899  }
900  } else {
901  if (OrigElt.getSizeInBits() == TargetSize)
902  return OrigTy;
903  }
904 
905  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
906  return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
907  }
908 
909  if (TargetTy.isVector()) {
910  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
911  return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
912  }
913 
914  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
915 
916  // Preserve pointer types.
917  if (LCMSize == OrigSize)
918  return OrigTy;
919  if (LCMSize == TargetSize)
920  return TargetTy;
921 
922  return LLT::scalar(LCMSize);
923 }
924 
925 LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
926  if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
927  (OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
928  return getLCMType(OrigTy, TargetTy);
929 
930  unsigned OrigTyNumElts = OrigTy.getNumElements();
931  unsigned TargetTyNumElts = TargetTy.getNumElements();
932  if (OrigTyNumElts % TargetTyNumElts == 0)
933  return OrigTy;
934 
935  unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);
937  OrigTy.getElementType());
938 }
939 
940 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
941  const unsigned OrigSize = OrigTy.getSizeInBits();
942  const unsigned TargetSize = TargetTy.getSizeInBits();
943 
944  if (OrigSize == TargetSize)
945  return OrigTy;
946 
947  if (OrigTy.isVector()) {
948  LLT OrigElt = OrigTy.getElementType();
949  if (TargetTy.isVector()) {
950  LLT TargetElt = TargetTy.getElementType();
951  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
952  int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
953  TargetTy.getNumElements());
954  return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
955  }
956  } else {
957  // If the source is a vector of pointers, return a pointer element.
958  if (OrigElt.getSizeInBits() == TargetSize)
959  return OrigElt;
960  }
961 
962  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
963  if (GCD == OrigElt.getSizeInBits())
964  return OrigElt;
965 
966  // If we can't produce the original element type, we have to use a smaller
967  // scalar.
968  if (GCD < OrigElt.getSizeInBits())
969  return LLT::scalar(GCD);
970  return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
971  }
972 
973  if (TargetTy.isVector()) {
974  // Try to preserve the original element type.
975  LLT TargetElt = TargetTy.getElementType();
976  if (TargetElt.getSizeInBits() == OrigSize)
977  return OrigTy;
978  }
979 
980  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
981  return LLT::scalar(GCD);
982 }
983 
985  assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
986  "Only G_SHUFFLE_VECTOR can have a splat index!");
987  ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
988  auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
989 
990  // If all elements are undefined, this shuffle can be considered a splat.
991  // Return 0 for better potential for callers to simplify.
992  if (FirstDefinedIdx == Mask.end())
993  return 0;
994 
995  // Make sure all remaining elements are either undef or the same
996  // as the first non-undef value.
997  int SplatValue = *FirstDefinedIdx;
998  if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
999  [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1000  return None;
1001 
1002  return SplatValue;
1003 }
1004 
1005 static bool isBuildVectorOp(unsigned Opcode) {
1006  return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1007  Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1008 }
1009 
1010 namespace {
1011 
1012 Optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
1013  const MachineRegisterInfo &MRI,
1014  bool AllowUndef) {
1016  if (!MI)
1017  return None;
1018 
1019  if (!isBuildVectorOp(MI->getOpcode()))
1020  return None;
1021 
1022  Optional<ValueAndVReg> SplatValAndReg = None;
1023  for (MachineOperand &Op : MI->uses()) {
1024  Register Element = Op.getReg();
1025  auto ElementValAndReg =
1026  getAnyConstantVRegValWithLookThrough(Element, MRI, true, true);
1027 
1028  // If AllowUndef, treat undef as value that will result in a constant splat.
1029  if (!ElementValAndReg) {
1030  if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1031  continue;
1032  return None;
1033  }
1034 
1035  // Record splat value
1036  if (!SplatValAndReg)
1037  SplatValAndReg = ElementValAndReg;
1038 
1039  // Different constant then the one already recorded, not a constant splat.
1040  if (SplatValAndReg->Value != ElementValAndReg->Value)
1041  return None;
1042  }
1043 
1044  return SplatValAndReg;
1045 }
1046 
1047 } // end anonymous namespace
1048 
1050  const MachineRegisterInfo &MRI,
1051  int64_t SplatValue, bool AllowUndef) {
1052  if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
1053  return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
1054  return false;
1055 }
1056 
1058  const MachineRegisterInfo &MRI,
1059  int64_t SplatValue, bool AllowUndef) {
1060  return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1061  AllowUndef);
1062 }
1063 
1066  const MachineRegisterInfo &MRI) {
1067  if (auto SplatValAndReg =
1068  getAnyConstantSplat(MI.getOperand(0).getReg(), MRI, false))
1069  return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1070  return None;
1071 }
1072 
1074  const MachineRegisterInfo &MRI,
1075  bool AllowUndef) {
1076  if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1077  return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1078  return None;
1079 }
1080 
1082  const MachineRegisterInfo &MRI,
1083  bool AllowUndef) {
1084  return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1085 }
1086 
1088  const MachineRegisterInfo &MRI,
1089  bool AllowUndef) {
1090  return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1091 }
1092 
1094  const MachineRegisterInfo &MRI) {
1095  unsigned Opc = MI.getOpcode();
1096  if (!isBuildVectorOp(Opc))
1097  return None;
1098  if (auto Splat = getBuildVectorConstantSplat(MI, MRI))
1099  return RegOrConstant(*Splat);
1100  auto Reg = MI.getOperand(1).getReg();
1101  if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
1102  [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1103  return None;
1104  return RegOrConstant(Reg);
1105 }
1106 
1108  const MachineRegisterInfo &MRI) {
1109  Register Def = MI.getOperand(0).getReg();
1111  return true;
1112  GBuildVector *BV = dyn_cast<GBuildVector>(&MI);
1113  if (!BV)
1114  return false;
1115  for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1117  getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI))
1118  continue;
1119  return false;
1120  }
1121  return true;
1122 }
1123 
1126  const MachineRegisterInfo &MRI) {
1127  Register Def = MI.getOperand(0).getReg();
1129  return C->Value;
1130  auto MaybeCst = getBuildVectorConstantSplat(MI, MRI);
1131  if (!MaybeCst)
1132  return None;
1133  const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1134  return APInt(ScalarSize, *MaybeCst, true);
1135 }
1136 
1139  std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1140 
1142  if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1143  return Match(nullptr);
1144 
1145  // TODO: Also handle fconstant
1146  if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1147  return Match(Def->getOperand(1).getCImm());
1148 
1149  if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1150  return false;
1151 
1152  for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1153  Register SrcElt = Def->getOperand(I).getReg();
1154  const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1155  if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1156  if (!Match(nullptr))
1157  return false;
1158  continue;
1159  }
1160 
1161  if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1162  !Match(SrcDef->getOperand(1).getCImm()))
1163  return false;
1164  }
1165 
1166  return true;
1167 }
1168 
1169 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1170  bool IsFP) {
1171  switch (TLI.getBooleanContents(IsVector, IsFP)) {
1173  return Val & 0x1;
1175  return Val == 1;
1177  return Val == -1;
1178  }
1179  llvm_unreachable("Invalid boolean contents");
1180 }
1181 
1182 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1183  bool IsFP) {
1184  switch (TLI.getBooleanContents(IsVector, IsFP)) {
1187  return 1;
1189  return -1;
1190  }
1191  llvm_unreachable("Invalid boolean contents");
1192 }
1193 
1196  const auto &F = MBB.getParent()->getFunction();
1197  return F.hasOptSize() || F.hasMinSize() ||
1199 }
1200 
1202  LostDebugLocObserver *LocObserver,
1203  SmallInstListTy &DeadInstChain) {
1204  for (MachineOperand &Op : MI.uses()) {
1205  if (Op.isReg() && Op.getReg().isVirtual())
1206  DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1207  }
1208  LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1209  DeadInstChain.remove(&MI);
1210  MI.eraseFromParent();
1211  if (LocObserver)
1212  LocObserver->checkpoint(false);
1213 }
1214 
1217  LostDebugLocObserver *LocObserver) {
1218  SmallInstListTy DeadInstChain;
1219  for (MachineInstr *MI : DeadInstrs)
1220  saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1221 
1222  while (!DeadInstChain.empty()) {
1223  MachineInstr *Inst = DeadInstChain.pop_back_val();
1224  if (!isTriviallyDead(*Inst, MRI))
1225  continue;
1226  saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1227  }
1228 }
1229 
1231  LostDebugLocObserver *LocObserver) {
1232  return eraseInstrs({&MI}, MRI, LocObserver);
1233 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MIPatternMatch.h
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:497
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:292
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1086
StackProtector.h
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1201
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:666
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:453
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::GBuildVector
Represents a G_BUILD_VECTOR.
Definition: GenericMachineInstrs.h:191
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:321
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:579
Optional.h
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:206
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:212
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1182
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ElementCount
Definition: TypeSize.h:385
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:177
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:473
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1181
llvm::greatestCommonDivisor
T greatestCommonDivisor(T A, T B)
Return the greatest common divisor of the values using Euclid's algorithm.
Definition: MathExtras.h:621
llvm::ore::MNV
DiagnosticInfoMIROptimization::MachineArgument MNV
Definition: MachineOptimizationRemarkEmitter.h:141
llvm::APInt::isPowerOf2
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:425
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:467
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::MachineFunction::getObserver
GISelChangeObserver * getObserver() const
Definition: MachineFunction.h:590
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1479
GISelKnownBits.h
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:460
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:150
llvm::APInt::zextOrTrunc
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:970
RegisterBankInfo.h
MachineSizeOpts.h
reportGISelDiagnostic
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:236
llvm::minimum
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
Definition: APFloat.h:1318
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1194
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1412
TargetInstrInfo.h
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1215
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:452
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:541
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:325
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:666
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:297
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
GenericMachineInstrs.h
llvm::Optional
Definition: APInt.h:33
llvm::LLT::vector
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:56
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:672
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:869
MachineIRBuilder.h
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:644
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:254
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
Definition: TargetLowering.h:844
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:352
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:178
getLCMSize
static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize)
Definition: Utils.cpp:873
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:144
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:297
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1182
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::getFltSemanticForLLT
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
Definition: LowLevelType.cpp:73
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:45
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:179
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:703
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:940
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:835
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::GISelKnownBits::getKnownBits
KnownBits getKnownBits(Register R)
Definition: GISelKnownBits.cpp:57
Constants.h
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:182
llvm::maximum
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
Definition: APFloat.h:1331
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::DS_Warning
@ DS_Warning
Definition: DiagnosticInfo.h:47
llvm::APFloatBase::IEEEhalf
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:164
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3277
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::StackProtector
Definition: StackProtector.h:37
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LostDebugLocObserver::checkpoint
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Definition: LostDebugLocObserver.cpp:70
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:233
Utils.h
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:732
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:736
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:180
llvm::DiagnosticSeverity
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Definition: DiagnosticInfo.h:45
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1526
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:753
llvm::isConstantOrConstantSplatVector
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1125
llvm::MIPatternMatch::m_SpecificICst
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
Definition: MIPatternMatch.h:128
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1130
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::RegisterBankInfo::constrainGenericRegister
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Definition: RegisterBankInfo.cpp:132
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::maxnum
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1307
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1137
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:879
llvm::isConstantOrConstantVector
bool isConstantOrConstantVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a build vector of constant integers.
Definition: Utils.cpp:1107
llvm::APFloat
Definition: APFloat.h:701
llvm::FPValueAndVReg
Definition: Utils.h:195
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1230
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:542
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:578
llvm::MachineOptimizationRemarkMissed
Diagnostic information for missed-optimization remarks.
Definition: MachineOptimizationRemarkEmitter.h:82
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1169
llvm::GMergeLikeOp::getSourceReg
Register getSourceReg(unsigned I) const
Returns the I'th source register.
Definition: GenericMachineInstrs.h:160
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:151
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:686
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::getCoverTy
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:925
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
TargetPassConfig.h
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:547
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:546
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
isBuildVectorOp
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:1005
llvm::KnownBits::countMaxPopulation
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:291
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:280
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:204
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:668
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:658
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:407
llvm::GISelWorkList::pop_back_val
MachineInstr * pop_back_val()
Definition: GISelWorkList.h:98
llvm::ArrayRef< int >
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:42
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:68
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:40
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1656
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:401
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:431
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::GISelWorkList::remove
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:81
llvm::ConstantFoldVectorBinop
Optional< MachineInstr * > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI, MachineIRBuilder &MIB)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:596
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3641
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:371
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1676
llvm::APInt::zext
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:952
llvm::GISelWorkList::insert
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:74
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:767
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1087
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::minnum
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1296
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::APInt::trunc
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:883
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::KnownBits::countMinPopulation
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:286
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::getBuildVectorConstantSplat
Optional< int64_t > getBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
Definition: Utils.cpp:1065
llvm::isTargetSpecificOpcode
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:218
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:190
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:301
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1093
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:415
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:928
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:260
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::GMergeLikeOp::getNumSources
unsigned getNumSources() const
Returns the number of source registers.
Definition: GenericMachineInstrs.h:158
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:327
llvm::APFloatBase::rmNearestTiesToEven
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:190
llvm::APFloat::convert
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4836
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:344
llvm::GISelWorkList
Definition: GISelWorkList.h:27
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:272
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1073
llvm::LLT::getElementCount
ElementCount getElementCount() const
Definition: LowLevelTypeImpl.h:143
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:50
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::LLT::scalarOrVector
static LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
Definition: LowLevelTypeImpl.h:97
llvm::isBuildVectorConstantSplat
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1049
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:426
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::APFloat::convertFromAPInt
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition: APFloat.h:1113
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:24
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:303
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:220
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
GISelChangeObserver.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:236
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:219
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:434
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::GISelWorkList::empty
bool empty() const
Definition: GISelWorkList.h:38
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:46
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:670
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1081
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:917
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:231
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:486
llvm::LLT
Definition: LowLevelTypeImpl.h:39