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36 #define DEBUG_TYPE "globalisel-utils"
39 using namespace MIPatternMatch;
68 if (ConstrainedReg !=
Reg) {
75 TII.get(TargetOpcode::COPY), ConstrainedReg)
80 TII.get(TargetOpcode::COPY),
Reg)
84 Observer->changingInstr(*RegMO.
getParent());
86 RegMO.
setReg(ConstrainedReg);
88 Observer->changedInstr(*RegMO.
getParent());
94 Observer->changedInstr(*RegDef);
96 Observer->changingAllUsesOfReg(
MRI,
Reg);
97 Observer->finishedChangingAllUsesOfReg();
100 return ConstrainedReg;
132 "Register class constraint is required unless either the "
133 "instruction is target independent or the operand is a use");
155 "A selected instruction is expected");
160 for (
unsigned OpI = 0, OpE =
I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
168 assert(MO.
isReg() &&
"Unsupported non-reg operand");
188 int DefIdx =
I.getDesc().getOperandConstraint(OpI,
MCOI::TIED_TO);
189 if (DefIdx != -1 && !
I.isRegTiedToUseOperand(DefIdx))
190 I.tieOperands(DefIdx, OpI);
217 if (
MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
226 bool SawStore =
false;
227 if (!
MI.isSafeToMove(
nullptr, SawStore) && !
MI.isPHI())
231 for (
auto &MO :
MI.operands()) {
232 if (!MO.isReg() || !MO.isDef())
247 bool IsFatal = Severity ==
DS_Error &&
251 if (!R.getLocation().isValid() || IsFatal)
252 R << (
" (in function: " + MF.
getName() +
")").str();
278 MI.getDebugLoc(),
MI.getParent());
290 assert((!ValAndVReg || ValAndVReg->
VReg == VReg) &&
291 "Value found while looking through instrs");
294 return ValAndVReg->
Value;
308 typedef std::function<Optional<APInt>(
const MachineInstr *
MI)> GetAPCstFn;
312 GetAPCstFn getAPCstValue,
bool LookThroughInstrs =
true,
313 bool LookThroughAnyExt =
false) {
319 switch (
MI->getOpcode()) {
320 case TargetOpcode::G_ANYEXT:
321 if (!LookThroughAnyExt)
324 case TargetOpcode::G_TRUNC:
325 case TargetOpcode::G_SEXT:
326 case TargetOpcode::G_ZEXT:
327 SeenOpcodes.push_back(std::make_pair(
330 VReg =
MI->getOperand(1).getReg();
332 case TargetOpcode::COPY:
333 VReg =
MI->getOperand(1).getReg();
337 case TargetOpcode::G_INTTOPTR:
338 VReg =
MI->getOperand(1).getReg();
344 if (!
MI || !IsConstantOpcode(
MI))
350 APInt &Val = *MaybeVal;
351 while (!SeenOpcodes.empty()) {
352 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.
pop_back_val();
353 switch (OpcodeAndSize.first) {
354 case TargetOpcode::G_TRUNC:
355 Val = Val.
trunc(OpcodeAndSize.second);
357 case TargetOpcode::G_ANYEXT:
358 case TargetOpcode::G_SEXT:
359 Val = Val.
sext(OpcodeAndSize.second);
361 case TargetOpcode::G_ZEXT:
362 Val = Val.
zext(OpcodeAndSize.second);
373 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
379 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
385 unsigned Opc =
MI->getOpcode();
386 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
409 return getConstantVRegValWithLookThrough(VReg,
MRI, isIConstant,
410 getCImmAsAPInt, LookThroughInstrs);
415 bool LookThroughAnyExt) {
416 return getConstantVRegValWithLookThrough(
417 VReg,
MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
423 auto Reg = getConstantVRegValWithLookThrough(
424 VReg,
MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
434 if (TargetOpcode::G_FCONSTANT !=
MI->getOpcode())
436 return MI->getOperand(1).getFPImm();
444 if (!DstTy.isValid())
450 if (!SrcTy.isValid())
463 return DefSrcReg ? DefSrcReg->
MI :
nullptr;
503 const APInt &
C1 = MaybeOp1Cst->Value;
504 const APInt &C2 = MaybeOp2Cst->Value;
508 case TargetOpcode::G_ADD:
509 case TargetOpcode::G_PTR_ADD:
511 case TargetOpcode::G_AND:
513 case TargetOpcode::G_ASHR:
515 case TargetOpcode::G_LSHR:
517 case TargetOpcode::G_MUL:
519 case TargetOpcode::G_OR:
521 case TargetOpcode::G_SHL:
523 case TargetOpcode::G_SUB:
525 case TargetOpcode::G_XOR:
527 case TargetOpcode::G_UDIV:
528 if (!C2.getBoolValue())
531 case TargetOpcode::G_SDIV:
532 if (!C2.getBoolValue())
535 case TargetOpcode::G_UREM:
536 if (!C2.getBoolValue())
539 case TargetOpcode::G_SREM:
540 if (!C2.getBoolValue())
543 case TargetOpcode::G_SMIN:
545 case TargetOpcode::G_SMAX:
547 case TargetOpcode::G_UMIN:
549 case TargetOpcode::G_UMAX:
570 case TargetOpcode::G_FADD:
573 case TargetOpcode::G_FSUB:
576 case TargetOpcode::G_FMUL:
579 case TargetOpcode::G_FDIV:
582 case TargetOpcode::G_FREM:
585 case TargetOpcode::G_FCOPYSIGN:
588 case TargetOpcode::G_FMINNUM:
590 case TargetOpcode::G_FMAXNUM:
592 case TargetOpcode::G_FMINIMUM:
594 case TargetOpcode::G_FMAXIMUM:
596 case TargetOpcode::G_FMINNUM_IEEE:
597 case TargetOpcode::G_FMAXNUM_IEEE:
614 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2,
MRI);
618 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1,
MRI);
623 for (
unsigned Idx = 0,
E = SrcVec1->getNumSources(); Idx <
E; ++Idx) {
625 SrcVec2->getSourceReg(Idx),
MRI);
628 FoldedElements.push_back(*MaybeCst);
630 return FoldedElements;
645 return !FPVal->getValueAPF().isNaN() ||
646 (SNaN && !FPVal->getValueAPF().isSignaling());
659 case TargetOpcode::G_FMINNUM_IEEE:
660 case TargetOpcode::G_FMAXNUM_IEEE: {
670 case TargetOpcode::G_FMINNUM:
671 case TargetOpcode::G_FMAXNUM: {
683 case TargetOpcode::G_FPEXT:
684 case TargetOpcode::G_FPTRUNC:
685 case TargetOpcode::G_FCANONICALIZE:
698 if (
auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
706 return V->getPointerAlignment(
M->getDataLayout());
724 assert(
Def->getParent() == &EntryMBB &&
"live-in copy not in entry block");
753 case TargetOpcode::G_SEXT_INREG: {
765 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
783 return MaybeCst->countLeadingZeros();
787 auto *BV = getOpcodeDef<GBuildVector>(Src,
MRI);
790 for (
unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
791 if (
auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
799 if (
auto MaybeCst = tryFoldScalar(Src)) {
816 switch (
MI.getOpcode()) {
817 case TargetOpcode::G_CONSTANT: {
822 case TargetOpcode::G_SHL: {
834 case TargetOpcode::G_LSHR: {
836 if (ConstLHS->isSignMask())
842 case TargetOpcode::G_BUILD_VECTOR: {
851 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
857 if (!Const || !Const->zextOrTrunc(
BitWidth).isPowerOf2())
882 static unsigned getLCMSize(
unsigned OrigSize,
unsigned TargetSize) {
883 unsigned Mul = OrigSize * TargetSize;
885 return Mul / GCDSize;
892 if (OrigSize == TargetSize)
914 unsigned LCMSize =
getLCMSize(OrigSize, TargetSize);
919 unsigned LCMSize =
getLCMSize(OrigSize, TargetSize);
923 unsigned LCMSize =
getLCMSize(OrigSize, TargetSize);
926 if (LCMSize == OrigSize)
928 if (LCMSize == TargetSize)
941 if (OrigTyNumElts % TargetTyNumElts == 0)
944 unsigned NumElts =
alignTo(OrigTyNumElts, TargetTyNumElts);
953 if (OrigSize == TargetSize)
994 assert(
MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
995 "Only G_SHUFFLE_VECTOR can have a splat index!");
997 auto FirstDefinedIdx =
find_if(
Mask, [](
int Elt) {
return Elt >= 0; });
1001 if (FirstDefinedIdx ==
Mask.end())
1006 int SplatValue = *FirstDefinedIdx;
1008 [&SplatValue](
int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1015 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1016 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1034 auto ElementValAndReg =
1038 if (!ElementValAndReg) {
1039 if (AllowUndef && isa<GImplicitDef>(
MRI.
getVRegDef(Element)))
1045 if (!SplatValAndReg)
1046 SplatValAndReg = ElementValAndReg;
1049 if (SplatValAndReg->
Value != ElementValAndReg->Value)
1053 return SplatValAndReg;
1060 int64_t SplatValue,
bool AllowUndef) {
1061 if (
auto SplatValAndReg = getAnyConstantSplat(
Reg,
MRI, AllowUndef))
1068 int64_t SplatValue,
bool AllowUndef) {
1075 if (
auto SplatValAndReg =
1076 getAnyConstantSplat(
Reg,
MRI,
false)) {
1079 return ValAndVReg->
Value;
1093 if (
auto SplatValAndReg =
1094 getAnyConstantSplat(
Reg,
MRI,
false))
1108 if (
auto SplatValAndReg = getAnyConstantSplat(VReg,
MRI, AllowUndef))
1127 unsigned Opc =
MI.getOpcode();
1132 auto Reg =
MI.getOperand(1).getReg();
1141 bool AllowFP =
true,
1142 bool AllowOpaqueConstants =
true) {
1143 switch (
MI.getOpcode()) {
1144 case TargetOpcode::G_CONSTANT:
1145 case TargetOpcode::G_IMPLICIT_DEF:
1147 case TargetOpcode::G_FCONSTANT:
1149 case TargetOpcode::G_GLOBAL_VALUE:
1150 case TargetOpcode::G_FRAME_INDEX:
1151 case TargetOpcode::G_BLOCK_ADDR:
1152 case TargetOpcode::G_JUMP_TABLE:
1153 return AllowOpaqueConstants;
1167 for (
unsigned SrcIdx = 0; SrcIdx < BV->
getNumSources(); ++SrcIdx) {
1178 bool AllowFP,
bool AllowOpaqueConstants) {
1185 const unsigned NumOps =
MI.getNumOperands();
1186 for (
unsigned I = 1;
I != NumOps; ++
I) {
1205 return APInt(ScalarSize, *MaybeCst,
true);
1210 switch (
MI.getOpcode()) {
1211 case TargetOpcode::G_IMPLICIT_DEF:
1213 case TargetOpcode::G_CONSTANT:
1214 return MI.getOperand(1).getCImm()->isNullValue();
1215 case TargetOpcode::G_FCONSTANT: {
1229 switch (
MI.getOpcode()) {
1230 case TargetOpcode::G_IMPLICIT_DEF:
1232 case TargetOpcode::G_CONSTANT:
1233 return MI.getOperand(1).getCImm()->isAllOnesValue();
1246 if (AllowUndefs &&
Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1247 return Match(
nullptr);
1250 if (
Def->getOpcode() == TargetOpcode::G_CONSTANT)
1251 return Match(
Def->getOperand(1).getCImm());
1253 if (
Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1256 for (
unsigned I = 1,
E =
Def->getNumOperands();
I !=
E; ++
I) {
1259 if (AllowUndefs && SrcDef->
getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1260 if (!
Match(
nullptr))
1265 if (SrcDef->
getOpcode() != TargetOpcode::G_CONSTANT ||
1301 return F.hasOptSize() ||
F.hasMinSize() ||
1309 if (
Op.isReg() &&
Op.getReg().isVirtual())
1314 MI.eraseFromParent();
1326 while (!DeadInstChain.
empty()) {
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
unsigned getOpcode() const
Return the opcode number for this descriptor.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Represents a G_BUILD_VECTOR.
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getScalarSizeInBits() const
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Simple struct used to hold a constant integer value and a virtual register.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
@ LIFETIME_START
This corresponds to the llvm.lifetime.
T greatestCommonDivisor(T A, T B)
Return the greatest common divisor of the values using Euclid's algorithm.
DiagnosticInfoMIROptimization::MachineArgument MNV
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
instcombine should handle this C2 when C1
const APInt & getValue() const
Return the constant as an APInt value reference.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
GISelChangeObserver * getObserver() const
int64_t getSExtValue() const
Get sign extended value.
Reg
All possible values of the reg field in the ModR/M byte.
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isZero() const
Return true if the value is positive or negative zero.
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
unsigned getBitWidth() const
Return the number of bits in the APInt.
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const APFloat & getValueAPF() const
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
LLVM_NODISCARD T pop_back_val()
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
Represents a value which can be a Register or a constant.
unsigned const TargetRegisterInfo * TRI
static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize)
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
int64_t Offset
Offset - This is an offset from the base Value*.
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
This is the shared class of boolean and integer constants.
const MachineBasicBlock & front() const
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
TargetInstrInfo - Interface to description of machine instruction set.
KnownBits getKnownBits(Register R)
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static const fltSemantics & IEEEhalf() LLVM_READNONE
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Represent the analysis usage information of a pass.
@ ZeroOrNegativeOneBooleanContent
const MachineFunctionProperties & getProperties() const
Get the function properties.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
MachineFunctionProperties & set(Property P)
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ConstantFP - Floating Point Values [float, double].
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
Special value supplied for machine level alias analysis.
APInt bitcastToAPInt() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static ElementCount getFixed(ScalarTy MinVal)
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Analysis providing profile information.
Target-Independent Code Generator Pass Configuration Options.
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Holds all the information related to register banks.
This is an important base class in LLVM.
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const ConstantInt * getCImm() const
Representation of each machine instruction.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Module * getParent()
Get the module that this global value is contained inside of...
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Register getSourceReg(unsigned I) const
Returns the I'th source register.
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
This class contains a discriminated union of information about pointers in memory operands,...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
const ConstantFP * getFPImm() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool isNegative() const
Return true if the sign bit is set.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
static bool isBuildVectorOp(unsigned Opcode)
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
print Print MemDeps of function
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
A Module instance is used to store all the information related to an LLVM module.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Class for arbitrary precision integers.
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
MachineInstr * pop_back_val()
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
StringRef - Represent a constant reference to a string, i.e.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MachineBasicBlock * getParent() const
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Abstract class that contains various methods for clients to notify about changes.
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
unsigned const MachineRegisterInfo * MRI
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
const CustomOperand< const MCSubtargetInfo & > Msg[]
APInt zext(unsigned width) const
Zero extend to a new width.
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
APInt trunc(unsigned width) const
Truncate to new width.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned countMinPopulation() const
Returns the number of bits known to be one.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Simple struct used to hold a Register value and the instruction which defines it.
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
constexpr unsigned BitWidth
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
@ ZeroOrOneBooleanContent
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
APInt sext(unsigned width) const
Sign extend to a new width.
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
unsigned getNumSources() const
Returns the number of source registers.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
static constexpr roundingMode rmNearestTiesToEven
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
ElementCount getElementCount() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstrBuilder MachineInstrBuilder & DefMI
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
static LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
const char LLVMTargetMachineRef TM
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
LLVM Value Representation.
static const char PassName[]
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
reference emplace_back(ArgTypes &&... Args)
Wrapper class representing physical registers. Should be passed by value.
@ UndefinedBooleanContent
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)