LLVM  15.0.0git
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file This file implements the utility functions used by the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/Optional.h"
32 #include "llvm/IR/Constants.h"
35 
36 #define DEBUG_TYPE "globalisel-utils"
37 
38 using namespace llvm;
39 using namespace MIPatternMatch;
40 
42  const TargetInstrInfo &TII,
43  const RegisterBankInfo &RBI, Register Reg,
44  const TargetRegisterClass &RegClass) {
45  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
46  return MRI.createVirtualRegister(&RegClass);
47 
48  return Reg;
49 }
50 
52  const MachineFunction &MF, const TargetRegisterInfo &TRI,
54  const RegisterBankInfo &RBI, MachineInstr &InsertPt,
55  const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
56  Register Reg = RegMO.getReg();
57  // Assume physical registers are properly constrained.
58  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
59 
60  // Save the old register class to check whether
61  // the change notifications will be required.
62  // TODO: A better approach would be to pass
63  // the observers to constrainRegToClass().
64  auto *OldRegClass = MRI.getRegClassOrNull(Reg);
65  Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
66  // If we created a new virtual register because the class is not compatible
67  // then create a copy between the new and the old register.
68  if (ConstrainedReg != Reg) {
69  MachineBasicBlock::iterator InsertIt(&InsertPt);
70  MachineBasicBlock &MBB = *InsertPt.getParent();
71  // FIXME: The copy needs to have the classes constrained for its operands.
72  // Use operand's regbank to get the class for old register (Reg).
73  if (RegMO.isUse()) {
74  BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
75  TII.get(TargetOpcode::COPY), ConstrainedReg)
76  .addReg(Reg);
77  } else {
78  assert(RegMO.isDef() && "Must be a definition");
79  BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
80  TII.get(TargetOpcode::COPY), Reg)
81  .addReg(ConstrainedReg);
82  }
83  if (GISelChangeObserver *Observer = MF.getObserver()) {
84  Observer->changingInstr(*RegMO.getParent());
85  }
86  RegMO.setReg(ConstrainedReg);
87  if (GISelChangeObserver *Observer = MF.getObserver()) {
88  Observer->changedInstr(*RegMO.getParent());
89  }
90  } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) {
91  if (GISelChangeObserver *Observer = MF.getObserver()) {
92  if (!RegMO.isDef()) {
93  MachineInstr *RegDef = MRI.getVRegDef(Reg);
94  Observer->changedInstr(*RegDef);
95  }
96  Observer->changingAllUsesOfReg(MRI, Reg);
97  Observer->finishedChangingAllUsesOfReg();
98  }
99  }
100  return ConstrainedReg;
101 }
102 
104  const MachineFunction &MF, const TargetRegisterInfo &TRI,
106  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
107  MachineOperand &RegMO, unsigned OpIdx) {
108  Register Reg = RegMO.getReg();
109  // Assume physical registers are properly constrained.
110  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
111 
112  const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
113  // Some of the target independent instructions, like COPY, may not impose any
114  // register class constraints on some of their operands: If it's a use, we can
115  // skip constraining as the instruction defining the register would constrain
116  // it.
117 
118  if (OpRC) {
119  // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
120  // can have multiple regbanks for a superclass that combine different
121  // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
122  // resolved by targets during regbankselect should not be overridden.
123  if (const auto *SubRC = TRI.getCommonSubClass(
125  OpRC = SubRC;
126 
127  OpRC = TRI.getAllocatableClass(OpRC);
128  }
129 
130  if (!OpRC) {
131  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
132  "Register class constraint is required unless either the "
133  "instruction is target independent or the operand is a use");
134  // FIXME: Just bailing out like this here could be not enough, unless we
135  // expect the users of this function to do the right thing for PHIs and
136  // COPY:
137  // v1 = COPY v0
138  // v2 = COPY v1
139  // v1 here may end up not being constrained at all. Please notice that to
140  // reproduce the issue we likely need a destination pattern of a selection
141  // rule producing such extra copies, not just an input GMIR with them as
142  // every existing target using selectImpl handles copies before calling it
143  // and they never reach this function.
144  return Reg;
145  }
146  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
147  RegMO);
148 }
149 
151  const TargetInstrInfo &TII,
152  const TargetRegisterInfo &TRI,
153  const RegisterBankInfo &RBI) {
154  assert(!isPreISelGenericOpcode(I.getOpcode()) &&
155  "A selected instruction is expected");
156  MachineBasicBlock &MBB = *I.getParent();
157  MachineFunction &MF = *MBB.getParent();
159 
160  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
161  MachineOperand &MO = I.getOperand(OpI);
162 
163  // There's nothing to be done on non-register operands.
164  if (!MO.isReg())
165  continue;
166 
167  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
168  assert(MO.isReg() && "Unsupported non-reg operand");
169 
170  Register Reg = MO.getReg();
171  // Physical registers don't need to be constrained.
173  continue;
174 
175  // Register operands with a value of 0 (e.g. predicate operands) don't need
176  // to be constrained.
177  if (Reg == 0)
178  continue;
179 
180  // If the operand is a vreg, we should constrain its regclass, and only
181  // insert COPYs if that's impossible.
182  // constrainOperandRegClass does that for us.
183  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
184 
185  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
186  // done.
187  if (MO.isUse()) {
188  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
189  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
190  I.tieOperands(DefIdx, OpI);
191  }
192  }
193  return true;
194 }
195 
198  // Give up if either DstReg or SrcReg is a physical register.
199  if (DstReg.isPhysical() || SrcReg.isPhysical())
200  return false;
201  // Give up if the types don't match.
202  if (MRI.getType(DstReg) != MRI.getType(SrcReg))
203  return false;
204  // Replace if either DstReg has no constraints or the register
205  // constraints match.
206  return !MRI.getRegClassOrRegBank(DstReg) ||
208 }
209 
211  const MachineRegisterInfo &MRI) {
212  // FIXME: This logical is mostly duplicated with
213  // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
214  // MachineInstr::isLabel?
215 
216  // Don't delete frame allocation labels.
217  if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
218  return false;
219  // LIFETIME markers should be preserved even if they seem dead.
220  if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
221  MI.getOpcode() == TargetOpcode::LIFETIME_END)
222  return false;
223 
224  // If we can move an instruction, we can remove it. Otherwise, it has
225  // a side-effect of some sort.
226  bool SawStore = false;
227  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
228  return false;
229 
230  // Instructions without side-effects are dead iff they only define dead vregs.
231  for (auto &MO : MI.operands()) {
232  if (!MO.isReg() || !MO.isDef())
233  continue;
234 
235  Register Reg = MO.getReg();
237  return false;
238  }
239  return true;
240 }
241 
243  MachineFunction &MF,
244  const TargetPassConfig &TPC,
247  bool IsFatal = Severity == DS_Error &&
249  // Print the function name explicitly if we don't have a debug location (which
250  // makes the diagnostic less useful) or if we're going to emit a raw error.
251  if (!R.getLocation().isValid() || IsFatal)
252  R << (" (in function: " + MF.getName() + ")").str();
253 
254  if (IsFatal)
255  report_fatal_error(Twine(R.getMsg()));
256  else
257  MORE.emit(R);
258 }
259 
263  reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R);
264 }
265 
270  reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
271 }
272 
275  const char *PassName, StringRef Msg,
276  const MachineInstr &MI) {
277  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
278  MI.getDebugLoc(), MI.getParent());
279  R << Msg;
280  // Printing MI is expensive; only do it if expensive remarks are enabled.
281  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
282  R << ": " << ore::MNV("Inst", MI);
283  reportGISelFailure(MF, TPC, MORE, R);
284 }
285 
287  const MachineRegisterInfo &MRI) {
289  VReg, MRI, /*LookThroughInstrs*/ false);
290  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
291  "Value found while looking through instrs");
292  if (!ValAndVReg)
293  return None;
294  return ValAndVReg->Value;
295 }
296 
300  if (Val && Val->getBitWidth() <= 64)
301  return Val->getSExtValue();
302  return None;
303 }
304 
305 namespace {
306 
307 typedef std::function<bool(const MachineInstr *)> IsOpcodeFn;
308 typedef std::function<Optional<APInt>(const MachineInstr *MI)> GetAPCstFn;
309 
310 Optional<ValueAndVReg> getConstantVRegValWithLookThrough(
311  Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode,
312  GetAPCstFn getAPCstValue, bool LookThroughInstrs = true,
313  bool LookThroughAnyExt = false) {
315  MachineInstr *MI;
316 
317  while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
318  LookThroughInstrs) {
319  switch (MI->getOpcode()) {
320  case TargetOpcode::G_ANYEXT:
321  if (!LookThroughAnyExt)
322  return None;
324  case TargetOpcode::G_TRUNC:
325  case TargetOpcode::G_SEXT:
326  case TargetOpcode::G_ZEXT:
327  SeenOpcodes.push_back(std::make_pair(
328  MI->getOpcode(),
329  MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
330  VReg = MI->getOperand(1).getReg();
331  break;
332  case TargetOpcode::COPY:
333  VReg = MI->getOperand(1).getReg();
335  return None;
336  break;
337  case TargetOpcode::G_INTTOPTR:
338  VReg = MI->getOperand(1).getReg();
339  break;
340  default:
341  return None;
342  }
343  }
344  if (!MI || !IsConstantOpcode(MI))
345  return None;
346 
347  Optional<APInt> MaybeVal = getAPCstValue(MI);
348  if (!MaybeVal)
349  return None;
350  APInt &Val = *MaybeVal;
351  while (!SeenOpcodes.empty()) {
352  std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
353  switch (OpcodeAndSize.first) {
354  case TargetOpcode::G_TRUNC:
355  Val = Val.trunc(OpcodeAndSize.second);
356  break;
357  case TargetOpcode::G_ANYEXT:
358  case TargetOpcode::G_SEXT:
359  Val = Val.sext(OpcodeAndSize.second);
360  break;
361  case TargetOpcode::G_ZEXT:
362  Val = Val.zext(OpcodeAndSize.second);
363  break;
364  }
365  }
366 
367  return ValueAndVReg{Val, VReg};
368 }
369 
370 bool isIConstant(const MachineInstr *MI) {
371  if (!MI)
372  return false;
373  return MI->getOpcode() == TargetOpcode::G_CONSTANT;
374 }
375 
376 bool isFConstant(const MachineInstr *MI) {
377  if (!MI)
378  return false;
379  return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
380 }
381 
382 bool isAnyConstant(const MachineInstr *MI) {
383  if (!MI)
384  return false;
385  unsigned Opc = MI->getOpcode();
386  return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
387 }
388 
389 Optional<APInt> getCImmAsAPInt(const MachineInstr *MI) {
390  const MachineOperand &CstVal = MI->getOperand(1);
391  if (CstVal.isCImm())
392  return CstVal.getCImm()->getValue();
393  return None;
394 }
395 
396 Optional<APInt> getCImmOrFPImmAsAPInt(const MachineInstr *MI) {
397  const MachineOperand &CstVal = MI->getOperand(1);
398  if (CstVal.isCImm())
399  return CstVal.getCImm()->getValue();
400  if (CstVal.isFPImm())
401  return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
402  return None;
403 }
404 
405 } // end anonymous namespace
406 
408  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
409  return getConstantVRegValWithLookThrough(VReg, MRI, isIConstant,
410  getCImmAsAPInt, LookThroughInstrs);
411 }
412 
414  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
415  bool LookThroughAnyExt) {
416  return getConstantVRegValWithLookThrough(
417  VReg, MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
418  LookThroughAnyExt);
419 }
420 
422  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
423  auto Reg = getConstantVRegValWithLookThrough(
424  VReg, MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
425  if (!Reg)
426  return None;
428  Reg->VReg};
429 }
430 
431 const ConstantFP *
433  MachineInstr *MI = MRI.getVRegDef(VReg);
434  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
435  return nullptr;
436  return MI->getOperand(1).getFPImm();
437 }
438 
441  Register DefSrcReg = Reg;
442  auto *DefMI = MRI.getVRegDef(Reg);
443  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
444  if (!DstTy.isValid())
445  return None;
446  unsigned Opc = DefMI->getOpcode();
447  while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
448  Register SrcReg = DefMI->getOperand(1).getReg();
449  auto SrcTy = MRI.getType(SrcReg);
450  if (!SrcTy.isValid())
451  break;
452  DefMI = MRI.getVRegDef(SrcReg);
453  DefSrcReg = SrcReg;
454  Opc = DefMI->getOpcode();
455  }
456  return DefinitionAndSourceRegister{DefMI, DefSrcReg};
457 }
458 
460  const MachineRegisterInfo &MRI) {
463  return DefSrcReg ? DefSrcReg->MI : nullptr;
464 }
465 
467  const MachineRegisterInfo &MRI) {
470  return DefSrcReg ? DefSrcReg->Reg : Register();
471 }
472 
474  const MachineRegisterInfo &MRI) {
476  return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
477 }
478 
479 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
480  if (Size == 32)
481  return APFloat(float(Val));
482  if (Size == 64)
483  return APFloat(Val);
484  if (Size != 16)
485  llvm_unreachable("Unsupported FPConstant size");
486  bool Ignored;
487  APFloat APF(Val);
489  return APF;
490 }
491 
493  const Register Op2,
494  const MachineRegisterInfo &MRI) {
495  auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
496  if (!MaybeOp2Cst)
497  return None;
498 
499  auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
500  if (!MaybeOp1Cst)
501  return None;
502 
503  const APInt &C1 = MaybeOp1Cst->Value;
504  const APInt &C2 = MaybeOp2Cst->Value;
505  switch (Opcode) {
506  default:
507  break;
508  case TargetOpcode::G_ADD:
509  case TargetOpcode::G_PTR_ADD:
510  return C1 + C2;
511  case TargetOpcode::G_AND:
512  return C1 & C2;
513  case TargetOpcode::G_ASHR:
514  return C1.ashr(C2);
515  case TargetOpcode::G_LSHR:
516  return C1.lshr(C2);
517  case TargetOpcode::G_MUL:
518  return C1 * C2;
519  case TargetOpcode::G_OR:
520  return C1 | C2;
521  case TargetOpcode::G_SHL:
522  return C1 << C2;
523  case TargetOpcode::G_SUB:
524  return C1 - C2;
525  case TargetOpcode::G_XOR:
526  return C1 ^ C2;
527  case TargetOpcode::G_UDIV:
528  if (!C2.getBoolValue())
529  break;
530  return C1.udiv(C2);
531  case TargetOpcode::G_SDIV:
532  if (!C2.getBoolValue())
533  break;
534  return C1.sdiv(C2);
535  case TargetOpcode::G_UREM:
536  if (!C2.getBoolValue())
537  break;
538  return C1.urem(C2);
539  case TargetOpcode::G_SREM:
540  if (!C2.getBoolValue())
541  break;
542  return C1.srem(C2);
543  case TargetOpcode::G_SMIN:
544  return APIntOps::smin(C1, C2);
545  case TargetOpcode::G_SMAX:
546  return APIntOps::smax(C1, C2);
547  case TargetOpcode::G_UMIN:
548  return APIntOps::umin(C1, C2);
549  case TargetOpcode::G_UMAX:
550  return APIntOps::umax(C1, C2);
551  }
552 
553  return None;
554 }
555 
557  const Register Op2,
558  const MachineRegisterInfo &MRI) {
559  const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
560  if (!Op2Cst)
561  return None;
562 
563  const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
564  if (!Op1Cst)
565  return None;
566 
567  APFloat C1 = Op1Cst->getValueAPF();
568  const APFloat &C2 = Op2Cst->getValueAPF();
569  switch (Opcode) {
570  case TargetOpcode::G_FADD:
572  return C1;
573  case TargetOpcode::G_FSUB:
574  C1.subtract(C2, APFloat::rmNearestTiesToEven);
575  return C1;
576  case TargetOpcode::G_FMUL:
577  C1.multiply(C2, APFloat::rmNearestTiesToEven);
578  return C1;
579  case TargetOpcode::G_FDIV:
580  C1.divide(C2, APFloat::rmNearestTiesToEven);
581  return C1;
582  case TargetOpcode::G_FREM:
583  C1.mod(C2);
584  return C1;
585  case TargetOpcode::G_FCOPYSIGN:
586  C1.copySign(C2);
587  return C1;
588  case TargetOpcode::G_FMINNUM:
589  return minnum(C1, C2);
590  case TargetOpcode::G_FMAXNUM:
591  return maxnum(C1, C2);
592  case TargetOpcode::G_FMINIMUM:
593  return minimum(C1, C2);
594  case TargetOpcode::G_FMAXIMUM:
595  return maximum(C1, C2);
596  case TargetOpcode::G_FMINNUM_IEEE:
597  case TargetOpcode::G_FMAXNUM_IEEE:
598  // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
599  // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
600  // and currently there isn't a nice wrapper in APFloat for the version with
601  // correct snan handling.
602  break;
603  default:
604  break;
605  }
606 
607  return None;
608 }
609 
611 llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
612  const Register Op2,
613  const MachineRegisterInfo &MRI) {
614  auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
615  if (!SrcVec2)
616  return SmallVector<APInt>();
617 
618  auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
619  if (!SrcVec1)
620  return SmallVector<APInt>();
621 
622  SmallVector<APInt> FoldedElements;
623  for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
624  auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
625  SrcVec2->getSourceReg(Idx), MRI);
626  if (!MaybeCst)
627  return SmallVector<APInt>();
628  FoldedElements.push_back(*MaybeCst);
629  }
630  return FoldedElements;
631 }
632 
634  bool SNaN) {
635  const MachineInstr *DefMI = MRI.getVRegDef(Val);
636  if (!DefMI)
637  return false;
638 
639  const TargetMachine& TM = DefMI->getMF()->getTarget();
640  if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
641  return true;
642 
643  // If the value is a constant, we can obviously see if it is a NaN or not.
644  if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
645  return !FPVal->getValueAPF().isNaN() ||
646  (SNaN && !FPVal->getValueAPF().isSignaling());
647  }
648 
649  if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
650  for (const auto &Op : DefMI->uses())
651  if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
652  return false;
653  return true;
654  }
655 
656  switch (DefMI->getOpcode()) {
657  default:
658  break;
659  case TargetOpcode::G_FMINNUM_IEEE:
660  case TargetOpcode::G_FMAXNUM_IEEE: {
661  if (SNaN)
662  return true;
663  // This can return a NaN if either operand is an sNaN, or if both operands
664  // are NaN.
665  return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
669  }
670  case TargetOpcode::G_FMINNUM:
671  case TargetOpcode::G_FMAXNUM: {
672  // Only one needs to be known not-nan, since it will be returned if the
673  // other ends up being one.
674  return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
675  isKnownNeverNaN(DefMI->getOperand(2).getReg(), MRI, SNaN);
676  }
677  }
678 
679  if (SNaN) {
680  // FP operations quiet. For now, just handle the ones inserted during
681  // legalization.
682  switch (DefMI->getOpcode()) {
683  case TargetOpcode::G_FPEXT:
684  case TargetOpcode::G_FPTRUNC:
685  case TargetOpcode::G_FCANONICALIZE:
686  return true;
687  default:
688  return false;
689  }
690  }
691 
692  return false;
693 }
694 
696  const MachinePointerInfo &MPO) {
697  auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>();
698  if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
699  MachineFrameInfo &MFI = MF.getFrameInfo();
700  return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
701  MPO.Offset);
702  }
703 
704  if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
705  const Module *M = MF.getFunction().getParent();
706  return V->getPointerAlignment(M->getDataLayout());
707  }
708 
709  return Align(1);
710 }
711 
713  const TargetInstrInfo &TII,
714  MCRegister PhysReg,
715  const TargetRegisterClass &RC,
716  const DebugLoc &DL, LLT RegTy) {
717  MachineBasicBlock &EntryMBB = MF.front();
719  Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
720  if (LiveIn) {
721  MachineInstr *Def = MRI.getVRegDef(LiveIn);
722  if (Def) {
723  // FIXME: Should the verifier check this is in the entry block?
724  assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
725  return LiveIn;
726  }
727 
728  // It's possible the incoming argument register and copy was added during
729  // lowering, but later deleted due to being/becoming dead. If this happens,
730  // re-insert the copy.
731  } else {
732  // The live in register was not present, so add it.
733  LiveIn = MF.addLiveIn(PhysReg, &RC);
734  if (RegTy.isValid())
735  MRI.setType(LiveIn, RegTy);
736  }
737 
738  BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
739  .addReg(PhysReg);
740  if (!EntryMBB.isLiveIn(PhysReg))
741  EntryMBB.addLiveIn(PhysReg);
742  return LiveIn;
743 }
744 
746  uint64_t Imm,
747  const MachineRegisterInfo &MRI) {
748  auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
749  if (MaybeOp1Cst) {
750  switch (Opcode) {
751  default:
752  break;
753  case TargetOpcode::G_SEXT_INREG: {
754  LLT Ty = MRI.getType(Op1);
755  return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
756  }
757  }
758  }
759  return None;
760 }
761 
763  Register Src,
764  const MachineRegisterInfo &MRI) {
765  assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
766  if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
767  APFloat DstVal(getFltSemanticForLLT(DstTy));
768  DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
770  return DstVal;
771  }
772  return None;
773 }
774 
777  LLT Ty = MRI.getType(Src);
778  SmallVector<unsigned> FoldedCTLZs;
779  auto tryFoldScalar = [&](Register R) -> Optional<unsigned> {
780  auto MaybeCst = getIConstantVRegVal(R, MRI);
781  if (!MaybeCst)
782  return None;
783  return MaybeCst->countLeadingZeros();
784  };
785  if (Ty.isVector()) {
786  // Try to constant fold each element.
787  auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
788  if (!BV)
789  return None;
790  for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
791  if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
792  FoldedCTLZs.emplace_back(*MaybeFold);
793  continue;
794  }
795  return None;
796  }
797  return FoldedCTLZs;
798  }
799  if (auto MaybeCst = tryFoldScalar(Src)) {
800  FoldedCTLZs.emplace_back(*MaybeCst);
801  return FoldedCTLZs;
802  }
803  return None;
804 }
805 
807  GISelKnownBits *KB) {
810  if (!DefSrcReg)
811  return false;
812 
813  const MachineInstr &MI = *DefSrcReg->MI;
814  const LLT Ty = MRI.getType(Reg);
815 
816  switch (MI.getOpcode()) {
817  case TargetOpcode::G_CONSTANT: {
818  unsigned BitWidth = Ty.getScalarSizeInBits();
819  const ConstantInt *CI = MI.getOperand(1).getCImm();
820  return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
821  }
822  case TargetOpcode::G_SHL: {
823  // A left-shift of a constant one will have exactly one bit set because
824  // shifting the bit off the end is undefined.
825 
826  // TODO: Constant splat
827  if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
828  if (*ConstLHS == 1)
829  return true;
830  }
831 
832  break;
833  }
834  case TargetOpcode::G_LSHR: {
835  if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
836  if (ConstLHS->isSignMask())
837  return true;
838  }
839 
840  break;
841  }
842  case TargetOpcode::G_BUILD_VECTOR: {
843  // TODO: Probably should have a recursion depth guard since you could have
844  // bitcasted vector elements.
845  for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
846  if (!isKnownToBeAPowerOfTwo(MO.getReg(), MRI, KB))
847  return false;
848 
849  return true;
850  }
851  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
852  // Only handle constants since we would need to know if number of leading
853  // zeros is greater than the truncation amount.
854  const unsigned BitWidth = Ty.getScalarSizeInBits();
855  for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
856  auto Const = getIConstantVRegVal(MO.getReg(), MRI);
857  if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
858  return false;
859  }
860 
861  return true;
862  }
863  default:
864  break;
865  }
866 
867  if (!KB)
868  return false;
869 
870  // More could be done here, though the above checks are enough
871  // to handle some common cases.
872 
873  // Fall back to computeKnownBits to catch other known cases.
874  KnownBits Known = KB->getKnownBits(Reg);
875  return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
876 }
877 
880 }
881 
882 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) {
883  unsigned Mul = OrigSize * TargetSize;
884  unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize);
885  return Mul / GCDSize;
886 }
887 
888 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
889  const unsigned OrigSize = OrigTy.getSizeInBits();
890  const unsigned TargetSize = TargetTy.getSizeInBits();
891 
892  if (OrigSize == TargetSize)
893  return OrigTy;
894 
895  if (OrigTy.isVector()) {
896  const LLT OrigElt = OrigTy.getElementType();
897 
898  if (TargetTy.isVector()) {
899  const LLT TargetElt = TargetTy.getElementType();
900 
901  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
902  int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(),
903  TargetTy.getNumElements());
904  // Prefer the original element type.
905  ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
906  return LLT::vector(Mul.divideCoefficientBy(GCDElts),
907  OrigTy.getElementType());
908  }
909  } else {
910  if (OrigElt.getSizeInBits() == TargetSize)
911  return OrigTy;
912  }
913 
914  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
915  return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
916  }
917 
918  if (TargetTy.isVector()) {
919  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
920  return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
921  }
922 
923  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
924 
925  // Preserve pointer types.
926  if (LCMSize == OrigSize)
927  return OrigTy;
928  if (LCMSize == TargetSize)
929  return TargetTy;
930 
931  return LLT::scalar(LCMSize);
932 }
933 
934 LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
935  if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
936  (OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
937  return getLCMType(OrigTy, TargetTy);
938 
939  unsigned OrigTyNumElts = OrigTy.getNumElements();
940  unsigned TargetTyNumElts = TargetTy.getNumElements();
941  if (OrigTyNumElts % TargetTyNumElts == 0)
942  return OrigTy;
943 
944  unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);
946  OrigTy.getElementType());
947 }
948 
949 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
950  const unsigned OrigSize = OrigTy.getSizeInBits();
951  const unsigned TargetSize = TargetTy.getSizeInBits();
952 
953  if (OrigSize == TargetSize)
954  return OrigTy;
955 
956  if (OrigTy.isVector()) {
957  LLT OrigElt = OrigTy.getElementType();
958  if (TargetTy.isVector()) {
959  LLT TargetElt = TargetTy.getElementType();
960  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
961  int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
962  TargetTy.getNumElements());
963  return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
964  }
965  } else {
966  // If the source is a vector of pointers, return a pointer element.
967  if (OrigElt.getSizeInBits() == TargetSize)
968  return OrigElt;
969  }
970 
971  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
972  if (GCD == OrigElt.getSizeInBits())
973  return OrigElt;
974 
975  // If we can't produce the original element type, we have to use a smaller
976  // scalar.
977  if (GCD < OrigElt.getSizeInBits())
978  return LLT::scalar(GCD);
979  return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
980  }
981 
982  if (TargetTy.isVector()) {
983  // Try to preserve the original element type.
984  LLT TargetElt = TargetTy.getElementType();
985  if (TargetElt.getSizeInBits() == OrigSize)
986  return OrigTy;
987  }
988 
989  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
990  return LLT::scalar(GCD);
991 }
992 
994  assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
995  "Only G_SHUFFLE_VECTOR can have a splat index!");
996  ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
997  auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
998 
999  // If all elements are undefined, this shuffle can be considered a splat.
1000  // Return 0 for better potential for callers to simplify.
1001  if (FirstDefinedIdx == Mask.end())
1002  return 0;
1003 
1004  // Make sure all remaining elements are either undef or the same
1005  // as the first non-undef value.
1006  int SplatValue = *FirstDefinedIdx;
1007  if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
1008  [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1009  return None;
1010 
1011  return SplatValue;
1012 }
1013 
1014 static bool isBuildVectorOp(unsigned Opcode) {
1015  return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1016  Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1017 }
1018 
1019 namespace {
1020 
1021 Optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
1022  const MachineRegisterInfo &MRI,
1023  bool AllowUndef) {
1025  if (!MI)
1026  return None;
1027 
1028  if (!isBuildVectorOp(MI->getOpcode()))
1029  return None;
1030 
1031  Optional<ValueAndVReg> SplatValAndReg = None;
1032  for (MachineOperand &Op : MI->uses()) {
1033  Register Element = Op.getReg();
1034  auto ElementValAndReg =
1035  getAnyConstantVRegValWithLookThrough(Element, MRI, true, true);
1036 
1037  // If AllowUndef, treat undef as value that will result in a constant splat.
1038  if (!ElementValAndReg) {
1039  if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1040  continue;
1041  return None;
1042  }
1043 
1044  // Record splat value
1045  if (!SplatValAndReg)
1046  SplatValAndReg = ElementValAndReg;
1047 
1048  // Different constant then the one already recorded, not a constant splat.
1049  if (SplatValAndReg->Value != ElementValAndReg->Value)
1050  return None;
1051  }
1052 
1053  return SplatValAndReg;
1054 }
1055 
1056 } // end anonymous namespace
1057 
1059  const MachineRegisterInfo &MRI,
1060  int64_t SplatValue, bool AllowUndef) {
1061  if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
1062  return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
1063  return false;
1064 }
1065 
1067  const MachineRegisterInfo &MRI,
1068  int64_t SplatValue, bool AllowUndef) {
1069  return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1070  AllowUndef);
1071 }
1072 
1074  const MachineRegisterInfo &MRI) {
1075  if (auto SplatValAndReg =
1076  getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false)) {
1077  Optional<ValueAndVReg> ValAndVReg =
1078  getIConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1079  return ValAndVReg->Value;
1080  }
1081 
1082  return None;
1083 }
1084 
1086  const MachineRegisterInfo &MRI) {
1087  return getIConstantSplatVal(MI.getOperand(0).getReg(), MRI);
1088 }
1089 
1092  const MachineRegisterInfo &MRI) {
1093  if (auto SplatValAndReg =
1094  getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false))
1095  return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1096  return None;
1097 }
1098 
1101  const MachineRegisterInfo &MRI) {
1102  return getIConstantSplatSExtVal(MI.getOperand(0).getReg(), MRI);
1103 }
1104 
1106  const MachineRegisterInfo &MRI,
1107  bool AllowUndef) {
1108  if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1109  return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1110  return None;
1111 }
1112 
1114  const MachineRegisterInfo &MRI,
1115  bool AllowUndef) {
1116  return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1117 }
1118 
1120  const MachineRegisterInfo &MRI,
1121  bool AllowUndef) {
1122  return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1123 }
1124 
1126  const MachineRegisterInfo &MRI) {
1127  unsigned Opc = MI.getOpcode();
1128  if (!isBuildVectorOp(Opc))
1129  return None;
1130  if (auto Splat = getIConstantSplatSExtVal(MI, MRI))
1131  return RegOrConstant(*Splat);
1132  auto Reg = MI.getOperand(1).getReg();
1133  if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
1134  [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1135  return None;
1136  return RegOrConstant(Reg);
1137 }
1138 
1139 static bool isConstantScalar(const MachineInstr &MI,
1140  const MachineRegisterInfo &MRI,
1141  bool AllowFP = true,
1142  bool AllowOpaqueConstants = true) {
1143  switch (MI.getOpcode()) {
1144  case TargetOpcode::G_CONSTANT:
1145  case TargetOpcode::G_IMPLICIT_DEF:
1146  return true;
1147  case TargetOpcode::G_FCONSTANT:
1148  return AllowFP;
1149  case TargetOpcode::G_GLOBAL_VALUE:
1150  case TargetOpcode::G_FRAME_INDEX:
1151  case TargetOpcode::G_BLOCK_ADDR:
1152  case TargetOpcode::G_JUMP_TABLE:
1153  return AllowOpaqueConstants;
1154  default:
1155  return false;
1156  }
1157 }
1158 
1160  const MachineRegisterInfo &MRI) {
1161  Register Def = MI.getOperand(0).getReg();
1163  return true;
1164  GBuildVector *BV = dyn_cast<GBuildVector>(&MI);
1165  if (!BV)
1166  return false;
1167  for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1169  getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI))
1170  continue;
1171  return false;
1172  }
1173  return true;
1174 }
1175 
1177  const MachineRegisterInfo &MRI,
1178  bool AllowFP, bool AllowOpaqueConstants) {
1179  if (isConstantScalar(MI, MRI, AllowFP, AllowOpaqueConstants))
1180  return true;
1181 
1182  if (!isBuildVectorOp(MI.getOpcode()))
1183  return false;
1184 
1185  const unsigned NumOps = MI.getNumOperands();
1186  for (unsigned I = 1; I != NumOps; ++I) {
1187  const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg());
1188  if (!isConstantScalar(*ElementDef, MRI, AllowFP, AllowOpaqueConstants))
1189  return false;
1190  }
1191 
1192  return true;
1193 }
1194 
1197  const MachineRegisterInfo &MRI) {
1198  Register Def = MI.getOperand(0).getReg();
1200  return C->Value;
1201  auto MaybeCst = getIConstantSplatSExtVal(MI, MRI);
1202  if (!MaybeCst)
1203  return None;
1204  const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1205  return APInt(ScalarSize, *MaybeCst, true);
1206 }
1207 
1209  const MachineRegisterInfo &MRI, bool AllowUndefs) {
1210  switch (MI.getOpcode()) {
1211  case TargetOpcode::G_IMPLICIT_DEF:
1212  return AllowUndefs;
1213  case TargetOpcode::G_CONSTANT:
1214  return MI.getOperand(1).getCImm()->isNullValue();
1215  case TargetOpcode::G_FCONSTANT: {
1216  const ConstantFP *FPImm = MI.getOperand(1).getFPImm();
1217  return FPImm->isZero() && !FPImm->isNegative();
1218  }
1219  default:
1220  if (!AllowUndefs) // TODO: isBuildVectorAllZeros assumes undef is OK already
1221  return false;
1222  return isBuildVectorAllZeros(MI, MRI);
1223  }
1224 }
1225 
1227  const MachineRegisterInfo &MRI,
1228  bool AllowUndefs) {
1229  switch (MI.getOpcode()) {
1230  case TargetOpcode::G_IMPLICIT_DEF:
1231  return AllowUndefs;
1232  case TargetOpcode::G_CONSTANT:
1233  return MI.getOperand(1).getCImm()->isAllOnesValue();
1234  default:
1235  if (!AllowUndefs) // TODO: isBuildVectorAllOnes assumes undef is OK already
1236  return false;
1237  return isBuildVectorAllOnes(MI, MRI);
1238  }
1239 }
1240 
1243  std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1244 
1246  if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1247  return Match(nullptr);
1248 
1249  // TODO: Also handle fconstant
1250  if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1251  return Match(Def->getOperand(1).getCImm());
1252 
1253  if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1254  return false;
1255 
1256  for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1257  Register SrcElt = Def->getOperand(I).getReg();
1258  const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1259  if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1260  if (!Match(nullptr))
1261  return false;
1262  continue;
1263  }
1264 
1265  if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1266  !Match(SrcDef->getOperand(1).getCImm()))
1267  return false;
1268  }
1269 
1270  return true;
1271 }
1272 
1273 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1274  bool IsFP) {
1275  switch (TLI.getBooleanContents(IsVector, IsFP)) {
1277  return Val & 0x1;
1279  return Val == 1;
1281  return Val == -1;
1282  }
1283  llvm_unreachable("Invalid boolean contents");
1284 }
1285 
1286 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1287  bool IsFP) {
1288  switch (TLI.getBooleanContents(IsVector, IsFP)) {
1291  return 1;
1293  return -1;
1294  }
1295  llvm_unreachable("Invalid boolean contents");
1296 }
1297 
1300  const auto &F = MBB.getParent()->getFunction();
1301  return F.hasOptSize() || F.hasMinSize() ||
1303 }
1304 
1306  LostDebugLocObserver *LocObserver,
1307  SmallInstListTy &DeadInstChain) {
1308  for (MachineOperand &Op : MI.uses()) {
1309  if (Op.isReg() && Op.getReg().isVirtual())
1310  DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1311  }
1312  LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1313  DeadInstChain.remove(&MI);
1314  MI.eraseFromParent();
1315  if (LocObserver)
1316  LocObserver->checkpoint(false);
1317 }
1318 
1321  LostDebugLocObserver *LocObserver) {
1322  SmallInstListTy DeadInstChain;
1323  for (MachineInstr *MI : DeadInstrs)
1324  saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1325 
1326  while (!DeadInstChain.empty()) {
1327  MachineInstr *Inst = DeadInstChain.pop_back_val();
1328  if (!isTriviallyDead(*Inst, MRI))
1329  continue;
1330  saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1331  }
1332 }
1333 
1335  LostDebugLocObserver *LocObserver) {
1336  return eraseInstrs({&MI}, MRI, LocObserver);
1337 }
MIPatternMatch.h
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:437
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:298
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1105
StackProtector.h
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1305
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:667
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:459
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::GBuildVector
Represents a G_BUILD_VECTOR.
Definition: GenericMachineInstrs.h:192
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:280
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:576
Optional.h
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:205
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:224
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1223
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::ElementCount
Definition: TypeSize.h:404
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:179
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:479
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1222
llvm::greatestCommonDivisor
T greatestCommonDivisor(T A, T B)
Return the greatest common divisor of the values using Euclid's algorithm.
Definition: MathExtras.h:648
llvm::ore::MNV
DiagnosticInfoMIROptimization::MachineArgument MNV
Definition: MachineOptimizationRemarkEmitter.h:142
llvm::APInt::isPowerOf2
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:425
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:473
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::MachineFunction::getObserver
GISelChangeObserver * getObserver() const
Definition: MachineFunction.h:605
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1478
SizeOpts.h
GISelKnownBits.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:466
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:151
llvm::APInt::zextOrTrunc
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:994
RegisterBankInfo.h
llvm::isAllOnesOrAllOnesSplat
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1226
MachineSizeOpts.h
reportGISelDiagnostic
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:242
llvm::minimum
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
Definition: APFloat.h:1318
llvm::isConstantOrConstantVector
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1176
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::ConstantFP::isZero
bool isZero() const
Return true if the value is positive or negative zero.
Definition: Constants.h:302
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1298
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1411
TargetInstrInfo.h
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1319
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:450
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:556
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:324
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:636
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:298
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
GenericMachineInstrs.h
llvm::Optional
Definition: APInt.h:33
llvm::LLT::vector
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:56
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:878
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:654
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:260
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
Definition: TargetLowering.h:853
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:352
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:180
getLCMSize
static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize)
Definition: Utils.cpp:882
llvm::APIntOps::umin
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition: APInt.h:2137
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:150
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1286
llvm::commonAlignment
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:213
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::getFltSemanticForLLT
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
Definition: LowLevelType.cpp:72
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:181
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:712
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:949
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:865
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::GISelKnownBits::getKnownBits
KnownBits getKnownBits(Register R)
Definition: GISelKnownBits.cpp:62
Constants.h
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:180
llvm::maximum
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
Definition: APFloat.h:1331
LostDebugLocObserver.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::DS_Warning
@ DS_Warning
Definition: DiagnosticInfo.h:51
llvm::APFloatBase::IEEEhalf
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:164
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
isConstantScalar
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Definition: Utils.cpp:1139
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::StackProtector
Definition: StackProtector.h:36
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LostDebugLocObserver::checkpoint
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Definition: LostDebugLocObserver.cpp:70
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:233
Utils.h
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:747
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:745
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::DiagnosticSeverity
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Definition: DiagnosticInfo.h:49
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1563
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
APFloat.h
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:762
llvm::isConstantOrConstantSplatVector
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1196
llvm::MIPatternMatch::m_SpecificICst
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
Definition: MIPatternMatch.h:191
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1130
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::None
const NoneType None
Definition: None.h:24
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::RegisterBankInfo::constrainGenericRegister
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Definition: RegisterBankInfo.cpp:129
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::maxnum
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1307
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1241
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:888
llvm::APFloat
Definition: APFloat.h:701
llvm::FPValueAndVReg
Definition: Utils.h:197
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1334
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:332
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:620
llvm::MachineOptimizationRemarkMissed
Diagnostic information for missed-optimization remarks.
Definition: MachineOptimizationRemarkEmitter.h:83
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1273
llvm::GMergeLikeOp::getSourceReg
Register getSourceReg(unsigned I) const
Returns the I'th source register.
Definition: GenericMachineInstrs.h:161
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:695
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
llvm::getCoverTy
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:934
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
TargetPassConfig.h
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:556
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:565
llvm::ConstantFP::isNegative
bool isNegative() const
Return true if the sign bit is set.
Definition: Constants.h:305
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
isBuildVectorOp
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:1014
llvm::KnownBits::countMaxPopulation
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:291
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:286
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:210
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:676
llvm::getIConstantSplatSExtVal
Optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1091
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:677
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:574
llvm::APIntOps::smin
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Definition: APInt.h:2127
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:413
llvm::GISelWorkList::pop_back_val
MachineInstr * pop_back_val()
Definition: GISelWorkList.h:102
llvm::ArrayRef< int >
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:41
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:407
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:288
llvm::GISelWorkList::remove
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:83
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3787
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::isNullOrNullSplat
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1208
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:377
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::APInt::zext
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:973
llvm::GISelWorkList::insert
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:74
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:776
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1119
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::APIntOps::umax
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition: APInt.h:2142
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::minnum
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1296
llvm::APInt::trunc
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:898
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::KnownBits::countMinPopulation
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:286
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::isTargetSpecificOpcode
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:220
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:196
llvm::getIConstantSplatVal
Optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1073
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:301
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1125
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:90
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:421
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:946
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:266
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::GMergeLikeOp::getNumSources
unsigned getNumSources() const
Returns the number of source registers.
Definition: GenericMachineInstrs.h:159
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:326
llvm::APFloatBase::rmNearestTiesToEven
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:190
llvm::APFloat::convert
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4843
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:349
llvm::GISelWorkList
Definition: GISelWorkList.h:27
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
MachineInstrBuilder.h
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1105
llvm::LLT::getElementCount
ElementCount getElementCount() const
Definition: LowLevelTypeImpl.h:143
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:51
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:195
llvm::ConstantFoldVectorBinop
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:611
llvm::LLT::scalarOrVector
static LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
Definition: LowLevelTypeImpl.h:97
llvm::isBuildVectorConstantSplat
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1058
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:432
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::APFloat::convertFromAPInt
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition: APFloat.h:1113
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:25
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:327
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:222
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
GISelChangeObserver.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:248
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:221
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:440
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::GISelWorkList::empty
bool empty() const
Definition: GISelWorkList.h:38
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:50
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
llvm::APIntOps::smax
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition: APInt.h:2132
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1113
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:927
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:231
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:492
llvm::LLT
Definition: LowLevelTypeImpl.h:39