LLVM  13.0.0git
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file This file implements the utility functions used by the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/Optional.h"
30 #include "llvm/IR/Constants.h"
32 
33 #define DEBUG_TYPE "globalisel-utils"
34 
35 using namespace llvm;
36 using namespace MIPatternMatch;
37 
39  const TargetInstrInfo &TII,
40  const RegisterBankInfo &RBI, Register Reg,
41  const TargetRegisterClass &RegClass) {
42  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
43  return MRI.createVirtualRegister(&RegClass);
44 
45  return Reg;
46 }
47 
49  const MachineFunction &MF, const TargetRegisterInfo &TRI,
51  const RegisterBankInfo &RBI, MachineInstr &InsertPt,
52  const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
53  Register Reg = RegMO.getReg();
54  // Assume physical registers are properly constrained.
55  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
56 
57  Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
58  // If we created a new virtual register because the class is not compatible
59  // then create a copy between the new and the old register.
60  if (ConstrainedReg != Reg) {
61  MachineBasicBlock::iterator InsertIt(&InsertPt);
62  MachineBasicBlock &MBB = *InsertPt.getParent();
63  if (RegMO.isUse()) {
64  BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
65  TII.get(TargetOpcode::COPY), ConstrainedReg)
66  .addReg(Reg);
67  } else {
68  assert(RegMO.isDef() && "Must be a definition");
69  BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
70  TII.get(TargetOpcode::COPY), Reg)
71  .addReg(ConstrainedReg);
72  }
73  if (GISelChangeObserver *Observer = MF.getObserver()) {
74  Observer->changingInstr(*RegMO.getParent());
75  }
76  RegMO.setReg(ConstrainedReg);
77  if (GISelChangeObserver *Observer = MF.getObserver()) {
78  Observer->changedInstr(*RegMO.getParent());
79  }
80  } else {
81  if (GISelChangeObserver *Observer = MF.getObserver()) {
82  if (!RegMO.isDef()) {
83  MachineInstr *RegDef = MRI.getVRegDef(Reg);
84  Observer->changedInstr(*RegDef);
85  }
86  Observer->changingAllUsesOfReg(MRI, Reg);
87  Observer->finishedChangingAllUsesOfReg();
88  }
89  }
90  return ConstrainedReg;
91 }
92 
94  const MachineFunction &MF, const TargetRegisterInfo &TRI,
96  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
97  MachineOperand &RegMO, unsigned OpIdx) {
98  Register Reg = RegMO.getReg();
99  // Assume physical registers are properly constrained.
100  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
101 
102  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
103  // Some of the target independent instructions, like COPY, may not impose any
104  // register class constraints on some of their operands: If it's a use, we can
105  // skip constraining as the instruction defining the register would constrain
106  // it.
107 
108  // We can't constrain unallocatable register classes, because we can't create
109  // virtual registers for these classes, so we need to let targets handled this
110  // case.
111  if (RegClass && !RegClass->isAllocatable())
112  RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
113 
114  if (!RegClass) {
115  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
116  "Register class constraint is required unless either the "
117  "instruction is target independent or the operand is a use");
118  // FIXME: Just bailing out like this here could be not enough, unless we
119  // expect the users of this function to do the right thing for PHIs and
120  // COPY:
121  // v1 = COPY v0
122  // v2 = COPY v1
123  // v1 here may end up not being constrained at all. Please notice that to
124  // reproduce the issue we likely need a destination pattern of a selection
125  // rule producing such extra copies, not just an input GMIR with them as
126  // every existing target using selectImpl handles copies before calling it
127  // and they never reach this function.
128  return Reg;
129  }
130  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
131  RegMO);
132 }
133 
135  const TargetInstrInfo &TII,
136  const TargetRegisterInfo &TRI,
137  const RegisterBankInfo &RBI) {
138  assert(!isPreISelGenericOpcode(I.getOpcode()) &&
139  "A selected instruction is expected");
140  MachineBasicBlock &MBB = *I.getParent();
141  MachineFunction &MF = *MBB.getParent();
143 
144  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
145  MachineOperand &MO = I.getOperand(OpI);
146 
147  // There's nothing to be done on non-register operands.
148  if (!MO.isReg())
149  continue;
150 
151  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
152  assert(MO.isReg() && "Unsupported non-reg operand");
153 
154  Register Reg = MO.getReg();
155  // Physical registers don't need to be constrained.
157  continue;
158 
159  // Register operands with a value of 0 (e.g. predicate operands) don't need
160  // to be constrained.
161  if (Reg == 0)
162  continue;
163 
164  // If the operand is a vreg, we should constrain its regclass, and only
165  // insert COPYs if that's impossible.
166  // constrainOperandRegClass does that for us.
167  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
168 
169  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
170  // done.
171  if (MO.isUse()) {
172  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
173  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
174  I.tieOperands(DefIdx, OpI);
175  }
176  }
177  return true;
178 }
179 
182  // Give up if either DstReg or SrcReg is a physical register.
183  if (DstReg.isPhysical() || SrcReg.isPhysical())
184  return false;
185  // Give up if the types don't match.
186  if (MRI.getType(DstReg) != MRI.getType(SrcReg))
187  return false;
188  // Replace if either DstReg has no constraints or the register
189  // constraints match.
190  return !MRI.getRegClassOrRegBank(DstReg) ||
192 }
193 
195  const MachineRegisterInfo &MRI) {
196  // FIXME: This logical is mostly duplicated with
197  // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
198  // MachineInstr::isLabel?
199 
200  // Don't delete frame allocation labels.
201  if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
202  return false;
203  // LIFETIME markers should be preserved even if they seem dead.
204  if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
205  MI.getOpcode() == TargetOpcode::LIFETIME_END)
206  return false;
207 
208  // If we can move an instruction, we can remove it. Otherwise, it has
209  // a side-effect of some sort.
210  bool SawStore = false;
211  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
212  return false;
213 
214  // Instructions without side-effects are dead iff they only define dead vregs.
215  for (auto &MO : MI.operands()) {
216  if (!MO.isReg() || !MO.isDef())
217  continue;
218 
219  Register Reg = MO.getReg();
221  return false;
222  }
223  return true;
224 }
225 
227  MachineFunction &MF,
228  const TargetPassConfig &TPC,
231  bool IsFatal = Severity == DS_Error &&
233  // Print the function name explicitly if we don't have a debug location (which
234  // makes the diagnostic less useful) or if we're going to emit a raw error.
235  if (!R.getLocation().isValid() || IsFatal)
236  R << (" (in function: " + MF.getName() + ")").str();
237 
238  if (IsFatal)
239  report_fatal_error(R.getMsg());
240  else
241  MORE.emit(R);
242 }
243 
247  reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R);
248 }
249 
254  reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
255 }
256 
259  const char *PassName, StringRef Msg,
260  const MachineInstr &MI) {
261  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
262  MI.getDebugLoc(), MI.getParent());
263  R << Msg;
264  // Printing MI is expensive; only do it if expensive remarks are enabled.
265  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
266  R << ": " << ore::MNV("Inst", MI);
267  reportGISelFailure(MF, TPC, MORE, R);
268 }
269 
271  const MachineRegisterInfo &MRI) {
272  Optional<ValueAndVReg> ValAndVReg =
273  getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
274  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
275  "Value found while looking through instrs");
276  if (!ValAndVReg)
277  return None;
278  return ValAndVReg->Value;
279 }
280 
282  const MachineRegisterInfo &MRI) {
284  if (Val && Val->getBitWidth() <= 64)
285  return Val->getSExtValue();
286  return None;
287 }
288 
290  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
291  bool HandleFConstant, bool LookThroughAnyExt) {
293  MachineInstr *MI;
294  auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) {
295  return Opcode == TargetOpcode::G_CONSTANT ||
296  (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT);
297  };
298  auto GetImmediateValue = [HandleFConstant,
299  &MRI](const MachineInstr &MI) -> Optional<APInt> {
300  const MachineOperand &CstVal = MI.getOperand(1);
301  if (!CstVal.isImm() && !CstVal.isCImm() &&
302  (!HandleFConstant || !CstVal.isFPImm()))
303  return None;
304  if (!CstVal.isFPImm()) {
305  unsigned BitWidth =
306  MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
307  APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm())
308  : CstVal.getCImm()->getValue();
309  assert(Val.getBitWidth() == BitWidth &&
310  "Value bitwidth doesn't match definition type");
311  return Val;
312  }
313  return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
314  };
315  while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) &&
316  LookThroughInstrs) {
317  switch (MI->getOpcode()) {
318  case TargetOpcode::G_ANYEXT:
319  if (!LookThroughAnyExt)
320  return None;
322  case TargetOpcode::G_TRUNC:
323  case TargetOpcode::G_SEXT:
324  case TargetOpcode::G_ZEXT:
325  SeenOpcodes.push_back(std::make_pair(
326  MI->getOpcode(),
327  MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
328  VReg = MI->getOperand(1).getReg();
329  break;
330  case TargetOpcode::COPY:
331  VReg = MI->getOperand(1).getReg();
333  return None;
334  break;
335  case TargetOpcode::G_INTTOPTR:
336  VReg = MI->getOperand(1).getReg();
337  break;
338  default:
339  return None;
340  }
341  }
342  if (!MI || !IsConstantOpcode(MI->getOpcode()))
343  return None;
344 
345  Optional<APInt> MaybeVal = GetImmediateValue(*MI);
346  if (!MaybeVal)
347  return None;
348  APInt &Val = *MaybeVal;
349  while (!SeenOpcodes.empty()) {
350  std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
351  switch (OpcodeAndSize.first) {
352  case TargetOpcode::G_TRUNC:
353  Val = Val.trunc(OpcodeAndSize.second);
354  break;
355  case TargetOpcode::G_ANYEXT:
356  case TargetOpcode::G_SEXT:
357  Val = Val.sext(OpcodeAndSize.second);
358  break;
359  case TargetOpcode::G_ZEXT:
360  Val = Val.zext(OpcodeAndSize.second);
361  break;
362  }
363  }
364 
365  return ValueAndVReg{Val, VReg};
366 }
367 
368 const ConstantFP *
370  MachineInstr *MI = MRI.getVRegDef(VReg);
371  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
372  return nullptr;
373  return MI->getOperand(1).getFPImm();
374 }
375 
378  Register DefSrcReg = Reg;
379  auto *DefMI = MRI.getVRegDef(Reg);
380  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
381  if (!DstTy.isValid())
382  return None;
383  unsigned Opc = DefMI->getOpcode();
384  while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
385  Register SrcReg = DefMI->getOperand(1).getReg();
386  auto SrcTy = MRI.getType(SrcReg);
387  if (!SrcTy.isValid())
388  break;
389  DefMI = MRI.getVRegDef(SrcReg);
390  DefSrcReg = SrcReg;
391  Opc = DefMI->getOpcode();
392  }
393  return DefinitionAndSourceRegister{DefMI, DefSrcReg};
394 }
395 
397  const MachineRegisterInfo &MRI) {
400  return DefSrcReg ? DefSrcReg->MI : nullptr;
401 }
402 
404  const MachineRegisterInfo &MRI) {
407  return DefSrcReg ? DefSrcReg->Reg : Register();
408 }
409 
411  const MachineRegisterInfo &MRI) {
413  return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
414 }
415 
416 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
417  if (Size == 32)
418  return APFloat(float(Val));
419  if (Size == 64)
420  return APFloat(Val);
421  if (Size != 16)
422  llvm_unreachable("Unsupported FPConstant size");
423  bool Ignored;
424  APFloat APF(Val);
426  return APF;
427 }
428 
430  const Register Op2,
431  const MachineRegisterInfo &MRI) {
432  auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI);
433  if (!MaybeOp2Cst)
434  return None;
435 
436  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
437  if (!MaybeOp1Cst)
438  return None;
439 
440  const APInt &C1 = *MaybeOp1Cst;
441  const APInt &C2 = *MaybeOp2Cst;
442  switch (Opcode) {
443  default:
444  break;
445  case TargetOpcode::G_ADD:
446  return C1 + C2;
447  case TargetOpcode::G_AND:
448  return C1 & C2;
449  case TargetOpcode::G_ASHR:
450  return C1.ashr(C2);
451  case TargetOpcode::G_LSHR:
452  return C1.lshr(C2);
453  case TargetOpcode::G_MUL:
454  return C1 * C2;
455  case TargetOpcode::G_OR:
456  return C1 | C2;
457  case TargetOpcode::G_SHL:
458  return C1 << C2;
459  case TargetOpcode::G_SUB:
460  return C1 - C2;
461  case TargetOpcode::G_XOR:
462  return C1 ^ C2;
463  case TargetOpcode::G_UDIV:
464  if (!C2.getBoolValue())
465  break;
466  return C1.udiv(C2);
467  case TargetOpcode::G_SDIV:
468  if (!C2.getBoolValue())
469  break;
470  return C1.sdiv(C2);
471  case TargetOpcode::G_UREM:
472  if (!C2.getBoolValue())
473  break;
474  return C1.urem(C2);
475  case TargetOpcode::G_SREM:
476  if (!C2.getBoolValue())
477  break;
478  return C1.srem(C2);
479  }
480 
481  return None;
482 }
483 
485  const Register Op2,
486  const MachineRegisterInfo &MRI) {
487  const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
488  if (!Op2Cst)
489  return None;
490 
491  const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
492  if (!Op1Cst)
493  return None;
494 
495  APFloat C1 = Op1Cst->getValueAPF();
496  const APFloat &C2 = Op2Cst->getValueAPF();
497  switch (Opcode) {
498  case TargetOpcode::G_FADD:
500  return C1;
501  case TargetOpcode::G_FSUB:
502  C1.subtract(C2, APFloat::rmNearestTiesToEven);
503  return C1;
504  case TargetOpcode::G_FMUL:
505  C1.multiply(C2, APFloat::rmNearestTiesToEven);
506  return C1;
507  case TargetOpcode::G_FDIV:
508  C1.divide(C2, APFloat::rmNearestTiesToEven);
509  return C1;
510  case TargetOpcode::G_FREM:
511  C1.mod(C2);
512  return C1;
513  case TargetOpcode::G_FCOPYSIGN:
514  C1.copySign(C2);
515  return C1;
516  case TargetOpcode::G_FMINNUM:
517  return minnum(C1, C2);
518  case TargetOpcode::G_FMAXNUM:
519  return maxnum(C1, C2);
520  case TargetOpcode::G_FMINIMUM:
521  return minimum(C1, C2);
522  case TargetOpcode::G_FMAXIMUM:
523  return maximum(C1, C2);
524  case TargetOpcode::G_FMINNUM_IEEE:
525  case TargetOpcode::G_FMAXNUM_IEEE:
526  // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
527  // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
528  // and currently there isn't a nice wrapper in APFloat for the version with
529  // correct snan handling.
530  break;
531  default:
532  break;
533  }
534 
535  return None;
536 }
537 
539  bool SNaN) {
540  const MachineInstr *DefMI = MRI.getVRegDef(Val);
541  if (!DefMI)
542  return false;
543 
544  const TargetMachine& TM = DefMI->getMF()->getTarget();
545  if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
546  return true;
547 
548  // If the value is a constant, we can obviously see if it is a NaN or not.
549  if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
550  return !FPVal->getValueAPF().isNaN() ||
551  (SNaN && !FPVal->getValueAPF().isSignaling());
552  }
553 
554  if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
555  for (const auto &Op : DefMI->uses())
556  if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
557  return false;
558  return true;
559  }
560 
561  switch (DefMI->getOpcode()) {
562  default:
563  break;
564  case TargetOpcode::G_FMINNUM_IEEE:
565  case TargetOpcode::G_FMAXNUM_IEEE: {
566  if (SNaN)
567  return true;
568  // This can return a NaN if either operand is an sNaN, or if both operands
569  // are NaN.
570  return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
574  }
575  case TargetOpcode::G_FMINNUM:
576  case TargetOpcode::G_FMAXNUM: {
577  // Only one needs to be known not-nan, since it will be returned if the
578  // other ends up being one.
579  return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
580  isKnownNeverNaN(DefMI->getOperand(2).getReg(), MRI, SNaN);
581  }
582  }
583 
584  if (SNaN) {
585  // FP operations quiet. For now, just handle the ones inserted during
586  // legalization.
587  switch (DefMI->getOpcode()) {
588  case TargetOpcode::G_FPEXT:
589  case TargetOpcode::G_FPTRUNC:
590  case TargetOpcode::G_FCANONICALIZE:
591  return true;
592  default:
593  return false;
594  }
595  }
596 
597  return false;
598 }
599 
601  const MachinePointerInfo &MPO) {
602  auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>();
603  if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
604  MachineFrameInfo &MFI = MF.getFrameInfo();
605  return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
606  MPO.Offset);
607  }
608 
609  if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
610  const Module *M = MF.getFunction().getParent();
611  return V->getPointerAlignment(M->getDataLayout());
612  }
613 
614  return Align(1);
615 }
616 
618  const TargetInstrInfo &TII,
619  MCRegister PhysReg,
620  const TargetRegisterClass &RC,
621  LLT RegTy) {
622  DebugLoc DL; // FIXME: Is no location the right choice?
623  MachineBasicBlock &EntryMBB = MF.front();
625  Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
626  if (LiveIn) {
627  MachineInstr *Def = MRI.getVRegDef(LiveIn);
628  if (Def) {
629  // FIXME: Should the verifier check this is in the entry block?
630  assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
631  return LiveIn;
632  }
633 
634  // It's possible the incoming argument register and copy was added during
635  // lowering, but later deleted due to being/becoming dead. If this happens,
636  // re-insert the copy.
637  } else {
638  // The live in register was not present, so add it.
639  LiveIn = MF.addLiveIn(PhysReg, &RC);
640  if (RegTy.isValid())
641  MRI.setType(LiveIn, RegTy);
642  }
643 
644  BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
645  .addReg(PhysReg);
646  if (!EntryMBB.isLiveIn(PhysReg))
647  EntryMBB.addLiveIn(PhysReg);
648  return LiveIn;
649 }
650 
652  uint64_t Imm,
653  const MachineRegisterInfo &MRI) {
654  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
655  if (MaybeOp1Cst) {
656  switch (Opcode) {
657  default:
658  break;
659  case TargetOpcode::G_SEXT_INREG: {
660  LLT Ty = MRI.getType(Op1);
661  return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
662  }
663  }
664  }
665  return None;
666 }
667 
669  GISelKnownBits *KB) {
672  if (!DefSrcReg)
673  return false;
674 
675  const MachineInstr &MI = *DefSrcReg->MI;
676  const LLT Ty = MRI.getType(Reg);
677 
678  switch (MI.getOpcode()) {
679  case TargetOpcode::G_CONSTANT: {
680  unsigned BitWidth = Ty.getScalarSizeInBits();
681  const ConstantInt *CI = MI.getOperand(1).getCImm();
682  return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
683  }
684  case TargetOpcode::G_SHL: {
685  // A left-shift of a constant one will have exactly one bit set because
686  // shifting the bit off the end is undefined.
687 
688  // TODO: Constant splat
689  if (auto ConstLHS = getConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
690  if (*ConstLHS == 1)
691  return true;
692  }
693 
694  break;
695  }
696  case TargetOpcode::G_LSHR: {
697  if (auto ConstLHS = getConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
698  if (ConstLHS->isSignMask())
699  return true;
700  }
701 
702  break;
703  }
704  case TargetOpcode::G_BUILD_VECTOR: {
705  // TODO: Probably should have a recursion depth guard since you could have
706  // bitcasted vector elements.
707  for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
708  if (!isKnownToBeAPowerOfTwo(MI.getOperand(I).getReg(), MRI, KB))
709  return false;
710  }
711 
712  return true;
713  }
714  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
715  // Only handle constants since we would need to know if number of leading
716  // zeros is greater than the truncation amount.
717  const unsigned BitWidth = Ty.getScalarSizeInBits();
718  for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
719  auto Const = getConstantVRegVal(MI.getOperand(I).getReg(), MRI);
720  if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
721  return false;
722  }
723 
724  return true;
725  }
726  default:
727  break;
728  }
729 
730  if (!KB)
731  return false;
732 
733  // More could be done here, though the above checks are enough
734  // to handle some common cases.
735 
736  // Fall back to computeKnownBits to catch other known cases.
737  KnownBits Known = KB->getKnownBits(Reg);
738  return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
739 }
740 
743 }
744 
745 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) {
746  unsigned Mul = OrigSize * TargetSize;
747  unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize);
748  return Mul / GCDSize;
749 }
750 
751 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
752  const unsigned OrigSize = OrigTy.getSizeInBits();
753  const unsigned TargetSize = TargetTy.getSizeInBits();
754 
755  if (OrigSize == TargetSize)
756  return OrigTy;
757 
758  if (OrigTy.isVector()) {
759  const LLT OrigElt = OrigTy.getElementType();
760 
761  if (TargetTy.isVector()) {
762  const LLT TargetElt = TargetTy.getElementType();
763 
764  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
765  int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(),
766  TargetTy.getNumElements());
767  // Prefer the original element type.
768  int Mul = OrigTy.getNumElements() * TargetTy.getNumElements();
769  return LLT::vector(Mul / GCDElts, OrigTy.getElementType());
770  }
771  } else {
772  if (OrigElt.getSizeInBits() == TargetSize)
773  return OrigTy;
774  }
775 
776  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
777  return LLT::vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
778  }
779 
780  if (TargetTy.isVector()) {
781  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
782  return LLT::vector(LCMSize / OrigSize, OrigTy);
783  }
784 
785  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
786 
787  // Preserve pointer types.
788  if (LCMSize == OrigSize)
789  return OrigTy;
790  if (LCMSize == TargetSize)
791  return TargetTy;
792 
793  return LLT::scalar(LCMSize);
794 }
795 
796 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
797  const unsigned OrigSize = OrigTy.getSizeInBits();
798  const unsigned TargetSize = TargetTy.getSizeInBits();
799 
800  if (OrigSize == TargetSize)
801  return OrigTy;
802 
803  if (OrigTy.isVector()) {
804  LLT OrigElt = OrigTy.getElementType();
805  if (TargetTy.isVector()) {
806  LLT TargetElt = TargetTy.getElementType();
807  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
808  int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
809  TargetTy.getNumElements());
810  return LLT::scalarOrVector(GCD, OrigElt);
811  }
812  } else {
813  // If the source is a vector of pointers, return a pointer element.
814  if (OrigElt.getSizeInBits() == TargetSize)
815  return OrigElt;
816  }
817 
818  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
819  if (GCD == OrigElt.getSizeInBits())
820  return OrigElt;
821 
822  // If we can't produce the original element type, we have to use a smaller
823  // scalar.
824  if (GCD < OrigElt.getSizeInBits())
825  return LLT::scalar(GCD);
826  return LLT::vector(GCD / OrigElt.getSizeInBits(), OrigElt);
827  }
828 
829  if (TargetTy.isVector()) {
830  // Try to preserve the original element type.
831  LLT TargetElt = TargetTy.getElementType();
832  if (TargetElt.getSizeInBits() == OrigSize)
833  return OrigTy;
834  }
835 
836  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
837  return LLT::scalar(GCD);
838 }
839 
841  assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
842  "Only G_SHUFFLE_VECTOR can have a splat index!");
843  ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
844  auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
845 
846  // If all elements are undefined, this shuffle can be considered a splat.
847  // Return 0 for better potential for callers to simplify.
848  if (FirstDefinedIdx == Mask.end())
849  return 0;
850 
851  // Make sure all remaining elements are either undef or the same
852  // as the first non-undef value.
853  int SplatValue = *FirstDefinedIdx;
854  if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
855  [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
856  return None;
857 
858  return SplatValue;
859 }
860 
861 static bool isBuildVectorOp(unsigned Opcode) {
862  return Opcode == TargetOpcode::G_BUILD_VECTOR ||
863  Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
864 }
865 
866 // TODO: Handle mixed undef elements.
868  const MachineRegisterInfo &MRI,
869  int64_t SplatValue) {
870  if (!isBuildVectorOp(MI.getOpcode()))
871  return false;
872 
873  const unsigned NumOps = MI.getNumOperands();
874  for (unsigned I = 1; I != NumOps; ++I) {
875  Register Element = MI.getOperand(I).getReg();
876  if (!mi_match(Element, MRI, m_SpecificICst(SplatValue)))
877  return false;
878  }
879 
880  return true;
881 }
882 
885  const MachineRegisterInfo &MRI) {
886  if (!isBuildVectorOp(MI.getOpcode()))
887  return None;
888 
889  const unsigned NumOps = MI.getNumOperands();
890  Optional<int64_t> Scalar;
891  for (unsigned I = 1; I != NumOps; ++I) {
892  Register Element = MI.getOperand(I).getReg();
893  int64_t ElementValue;
894  if (!mi_match(Element, MRI, m_ICst(ElementValue)))
895  return None;
896  if (!Scalar)
897  Scalar = ElementValue;
898  else if (*Scalar != ElementValue)
899  return None;
900  }
901 
902  return Scalar;
903 }
904 
906  const MachineRegisterInfo &MRI) {
907  return isBuildVectorConstantSplat(MI, MRI, 0);
908 }
909 
911  const MachineRegisterInfo &MRI) {
912  return isBuildVectorConstantSplat(MI, MRI, -1);
913 }
914 
916  const MachineRegisterInfo &MRI) {
917  unsigned Opc = MI.getOpcode();
918  if (!isBuildVectorOp(Opc))
919  return None;
920  if (auto Splat = getBuildVectorConstantSplat(MI, MRI))
921  return RegOrConstant(*Splat);
922  auto Reg = MI.getOperand(1).getReg();
923  if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
924  [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
925  return None;
926  return RegOrConstant(Reg);
927 }
928 
931  std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
932 
934  if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
935  return Match(nullptr);
936 
937  // TODO: Also handle fconstant
938  if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
939  return Match(Def->getOperand(1).getCImm());
940 
941  if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
942  return false;
943 
944  for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
945  Register SrcElt = Def->getOperand(I).getReg();
946  const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
947  if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
948  if (!Match(nullptr))
949  return false;
950  continue;
951  }
952 
953  if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
954  !Match(SrcDef->getOperand(1).getCImm()))
955  return false;
956  }
957 
958  return true;
959 }
960 
961 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
962  bool IsFP) {
963  switch (TLI.getBooleanContents(IsVector, IsFP)) {
965  return Val & 0x1;
967  return Val == 1;
969  return Val == -1;
970  }
971  llvm_unreachable("Invalid boolean contents");
972 }
973 
974 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
975  bool IsFP) {
976  switch (TLI.getBooleanContents(IsVector, IsFP)) {
979  return 1;
981  return -1;
982  }
983  llvm_unreachable("Invalid boolean contents");
984 }
985 
988  const auto &F = MBB.getParent()->getFunction();
989  return F.hasOptSize() || F.hasMinSize() ||
991 }
992 
994 #ifndef NDEBUG
995  unsigned Opc = MI.getOpcode();
996  assert(Opc == TargetOpcode::G_INTRINSIC ||
997  Opc == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
998 #endif
999  return MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID();
1000 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MIPatternMatch.h
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:487
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1070
StackProtector.h
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:222
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:655
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:396
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:574
Optional.h
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:910
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:163
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1164
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:174
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:115
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:416
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1163
llvm::greatestCommonDivisor
T greatestCommonDivisor(T A, T B)
Return the greatest common divisor of the values using Euclid's algorithm.
Definition: MathExtras.h:621
llvm::ore::MNV
DiagnosticInfoMIROptimization::MachineArgument MNV
Definition: MachineOptimizationRemarkEmitter.h:135
llvm::APInt::isPowerOf2
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:469
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:410
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:131
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::MachineFunction::getObserver
GISelChangeObserver * getObserver() const
Definition: MachineFunction.h:504
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1643
GISelKnownBits.h
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:403
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:144
llvm::APInt::zextOrTrunc
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:948
RegisterBankInfo.h
MachineSizeOpts.h
reportGISelDiagnostic
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:226
llvm::minimum
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
Definition: APFloat.h:1308
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:986
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1581
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:617
TargetInstrInfo.h
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
Definition: MachineRegisterInfo.cpp:454
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:484
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:663
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:295
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:90
llvm::Optional
Definition: APInt.h:33
llvm::LLT::scalarOrVector
static LLT scalarOrVector(uint16_t NumElements, LLT ScalarTy)
Definition: LowLevelTypeImpl.h:74
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:741
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:244
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
Definition: TargetLowering.h:814
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:304
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:175
getLCMSize
static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize)
Definition: Utils.cpp:745
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:134
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:974
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:176
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:796
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:749
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::GISelKnownBits::getKnownBits
KnownBits getKnownBits(Register R)
Definition: GISelKnownBits.cpp:56
Constants.h
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:182
llvm::maximum
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
Definition: APFloat.h:1321
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::DS_Warning
@ DS_Warning
Definition: DiagnosticInfo.h:46
llvm::APFloatBase::IEEEhalf
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:157
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:367
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3141
llvm::StackProtector
Definition: StackProtector.h:37
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:230
Utils.h
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:646
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:651
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:166
llvm::DiagnosticSeverity
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Definition: DiagnosticInfo.h:44
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1450
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::LLT::vector
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:58
llvm::MIPatternMatch::m_SpecificICst
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
Definition: MIPatternMatch.h:82
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1132
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::None
const NoneType None
Definition: None.h:23
llvm::RegisterBankInfo::constrainGenericRegister
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Definition: RegisterBankInfo.cpp:132
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::maxnum
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1297
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:929
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:751
isBuildVectorConstantSplat
static bool isBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, int64_t SplatValue)
Definition: Utils.cpp:867
llvm::APFloat
Definition: APFloat.h:701
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:539
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
llvm::MachineOptimizationRemarkMissed
Diagnostic information for missed-optimization remarks.
Definition: MachineOptimizationRemarkEmitter.h:82
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:961
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:194
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:600
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:905
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:471
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:96
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:100
TargetPassConfig.h
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:544
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::getConstantVRegSExtVal
Optional< int64_t > getConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:281
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:522
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
isBuildVectorOp
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:861
llvm::KnownBits::countMaxPopulation
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:274
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:194
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:668
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::getConstantVRegVal
Optional< APInt > getConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:270
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:634
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::ArrayRef< int >
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:38
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
llvm::RecurKind::Mul
@ Mul
Product of integers.
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:419
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3662
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1532
llvm::APInt::zext
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:930
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::minnum
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1286
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:221
llvm::APInt::trunc
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:858
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
llvm::KnownBits::countMinPopulation
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:269
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::getBuildVectorConstantSplat
Optional< int64_t > getBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
Definition: Utils.cpp:884
llvm::isTargetSpecificOpcode
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:203
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:180
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:259
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:915
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:229
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:906
llvm::MIPatternMatch::m_ICst
ConstantMatch m_ICst(int64_t &Cst)
Definition: MIPatternMatch.h:69
llvm::getIntrinsicID
unsigned getIntrinsicID(const MachineInstr &MI)
Definition: Utils.cpp:993
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:250
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:324
llvm::APFloatBase::rmNearestTiesToEven
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:190
llvm::APFloat::convert
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4818
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:328
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:101
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:369
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:24
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:295
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:205
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
GISelChangeObserver.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:188
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:204
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:377
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:45
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:666
llvm::getConstantVRegValWithLookThrough
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
Definition: Utils.cpp:289
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:228
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:429
llvm::LLT
Definition: LowLevelTypeImpl.h:40