LLVM  14.0.0git
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file This file implements the utility functions used by the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/Optional.h"
32 #include "llvm/IR/Constants.h"
34 
35 #define DEBUG_TYPE "globalisel-utils"
36 
37 using namespace llvm;
38 using namespace MIPatternMatch;
39 
41  const TargetInstrInfo &TII,
42  const RegisterBankInfo &RBI, Register Reg,
43  const TargetRegisterClass &RegClass) {
44  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
45  return MRI.createVirtualRegister(&RegClass);
46 
47  return Reg;
48 }
49 
51  const MachineFunction &MF, const TargetRegisterInfo &TRI,
53  const RegisterBankInfo &RBI, MachineInstr &InsertPt,
54  const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
55  Register Reg = RegMO.getReg();
56  // Assume physical registers are properly constrained.
57  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
58 
59  Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
60  // If we created a new virtual register because the class is not compatible
61  // then create a copy between the new and the old register.
62  if (ConstrainedReg != Reg) {
63  MachineBasicBlock::iterator InsertIt(&InsertPt);
64  MachineBasicBlock &MBB = *InsertPt.getParent();
65  if (RegMO.isUse()) {
66  BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
67  TII.get(TargetOpcode::COPY), ConstrainedReg)
68  .addReg(Reg);
69  } else {
70  assert(RegMO.isDef() && "Must be a definition");
71  BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
72  TII.get(TargetOpcode::COPY), Reg)
73  .addReg(ConstrainedReg);
74  }
75  if (GISelChangeObserver *Observer = MF.getObserver()) {
76  Observer->changingInstr(*RegMO.getParent());
77  }
78  RegMO.setReg(ConstrainedReg);
79  if (GISelChangeObserver *Observer = MF.getObserver()) {
80  Observer->changedInstr(*RegMO.getParent());
81  }
82  } else {
83  if (GISelChangeObserver *Observer = MF.getObserver()) {
84  if (!RegMO.isDef()) {
85  MachineInstr *RegDef = MRI.getVRegDef(Reg);
86  Observer->changedInstr(*RegDef);
87  }
88  Observer->changingAllUsesOfReg(MRI, Reg);
89  Observer->finishedChangingAllUsesOfReg();
90  }
91  }
92  return ConstrainedReg;
93 }
94 
96  const MachineFunction &MF, const TargetRegisterInfo &TRI,
98  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
99  MachineOperand &RegMO, unsigned OpIdx) {
100  Register Reg = RegMO.getReg();
101  // Assume physical registers are properly constrained.
102  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
103 
104  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
105  // Some of the target independent instructions, like COPY, may not impose any
106  // register class constraints on some of their operands: If it's a use, we can
107  // skip constraining as the instruction defining the register would constrain
108  // it.
109 
110  // We can't constrain unallocatable register classes, because we can't create
111  // virtual registers for these classes, so we need to let targets handled this
112  // case.
113  if (RegClass && !RegClass->isAllocatable())
114  RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
115 
116  if (!RegClass) {
117  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
118  "Register class constraint is required unless either the "
119  "instruction is target independent or the operand is a use");
120  // FIXME: Just bailing out like this here could be not enough, unless we
121  // expect the users of this function to do the right thing for PHIs and
122  // COPY:
123  // v1 = COPY v0
124  // v2 = COPY v1
125  // v1 here may end up not being constrained at all. Please notice that to
126  // reproduce the issue we likely need a destination pattern of a selection
127  // rule producing such extra copies, not just an input GMIR with them as
128  // every existing target using selectImpl handles copies before calling it
129  // and they never reach this function.
130  return Reg;
131  }
132  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
133  RegMO);
134 }
135 
137  const TargetInstrInfo &TII,
138  const TargetRegisterInfo &TRI,
139  const RegisterBankInfo &RBI) {
140  assert(!isPreISelGenericOpcode(I.getOpcode()) &&
141  "A selected instruction is expected");
142  MachineBasicBlock &MBB = *I.getParent();
143  MachineFunction &MF = *MBB.getParent();
145 
146  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
147  MachineOperand &MO = I.getOperand(OpI);
148 
149  // There's nothing to be done on non-register operands.
150  if (!MO.isReg())
151  continue;
152 
153  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
154  assert(MO.isReg() && "Unsupported non-reg operand");
155 
156  Register Reg = MO.getReg();
157  // Physical registers don't need to be constrained.
159  continue;
160 
161  // Register operands with a value of 0 (e.g. predicate operands) don't need
162  // to be constrained.
163  if (Reg == 0)
164  continue;
165 
166  // If the operand is a vreg, we should constrain its regclass, and only
167  // insert COPYs if that's impossible.
168  // constrainOperandRegClass does that for us.
169  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
170 
171  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
172  // done.
173  if (MO.isUse()) {
174  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
175  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
176  I.tieOperands(DefIdx, OpI);
177  }
178  }
179  return true;
180 }
181 
184  // Give up if either DstReg or SrcReg is a physical register.
185  if (DstReg.isPhysical() || SrcReg.isPhysical())
186  return false;
187  // Give up if the types don't match.
188  if (MRI.getType(DstReg) != MRI.getType(SrcReg))
189  return false;
190  // Replace if either DstReg has no constraints or the register
191  // constraints match.
192  return !MRI.getRegClassOrRegBank(DstReg) ||
194 }
195 
197  const MachineRegisterInfo &MRI) {
198  // FIXME: This logical is mostly duplicated with
199  // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
200  // MachineInstr::isLabel?
201 
202  // Don't delete frame allocation labels.
203  if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
204  return false;
205  // LIFETIME markers should be preserved even if they seem dead.
206  if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
207  MI.getOpcode() == TargetOpcode::LIFETIME_END)
208  return false;
209 
210  // If we can move an instruction, we can remove it. Otherwise, it has
211  // a side-effect of some sort.
212  bool SawStore = false;
213  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
214  return false;
215 
216  // Instructions without side-effects are dead iff they only define dead vregs.
217  for (auto &MO : MI.operands()) {
218  if (!MO.isReg() || !MO.isDef())
219  continue;
220 
221  Register Reg = MO.getReg();
223  return false;
224  }
225  return true;
226 }
227 
229  MachineFunction &MF,
230  const TargetPassConfig &TPC,
233  bool IsFatal = Severity == DS_Error &&
235  // Print the function name explicitly if we don't have a debug location (which
236  // makes the diagnostic less useful) or if we're going to emit a raw error.
237  if (!R.getLocation().isValid() || IsFatal)
238  R << (" (in function: " + MF.getName() + ")").str();
239 
240  if (IsFatal)
241  report_fatal_error(Twine(R.getMsg()));
242  else
243  MORE.emit(R);
244 }
245 
249  reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R);
250 }
251 
256  reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
257 }
258 
261  const char *PassName, StringRef Msg,
262  const MachineInstr &MI) {
263  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
264  MI.getDebugLoc(), MI.getParent());
265  R << Msg;
266  // Printing MI is expensive; only do it if expensive remarks are enabled.
267  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
268  R << ": " << ore::MNV("Inst", MI);
269  reportGISelFailure(MF, TPC, MORE, R);
270 }
271 
273  const MachineRegisterInfo &MRI) {
275  VReg, MRI, /*LookThroughInstrs*/ false);
276  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
277  "Value found while looking through instrs");
278  if (!ValAndVReg)
279  return None;
280  return ValAndVReg->Value;
281 }
282 
286  if (Val && Val->getBitWidth() <= 64)
287  return Val->getSExtValue();
288  return None;
289 }
290 
291 namespace {
292 
293 typedef std::function<bool(const MachineInstr *)> IsOpcodeFn;
294 typedef std::function<Optional<APInt>(const MachineInstr *MI)> GetAPCstFn;
295 
296 Optional<ValueAndVReg> getConstantVRegValWithLookThrough(
297  Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode,
298  GetAPCstFn getAPCstValue, bool LookThroughInstrs = true,
299  bool LookThroughAnyExt = false) {
301  MachineInstr *MI;
302 
303  while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
304  LookThroughInstrs) {
305  switch (MI->getOpcode()) {
306  case TargetOpcode::G_ANYEXT:
307  if (!LookThroughAnyExt)
308  return None;
310  case TargetOpcode::G_TRUNC:
311  case TargetOpcode::G_SEXT:
312  case TargetOpcode::G_ZEXT:
313  SeenOpcodes.push_back(std::make_pair(
314  MI->getOpcode(),
315  MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
316  VReg = MI->getOperand(1).getReg();
317  break;
318  case TargetOpcode::COPY:
319  VReg = MI->getOperand(1).getReg();
321  return None;
322  break;
323  case TargetOpcode::G_INTTOPTR:
324  VReg = MI->getOperand(1).getReg();
325  break;
326  default:
327  return None;
328  }
329  }
330  if (!MI || !IsConstantOpcode(MI))
331  return None;
332 
333  Optional<APInt> MaybeVal = getAPCstValue(MI);
334  if (!MaybeVal)
335  return None;
336  APInt &Val = *MaybeVal;
337  while (!SeenOpcodes.empty()) {
338  std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
339  switch (OpcodeAndSize.first) {
340  case TargetOpcode::G_TRUNC:
341  Val = Val.trunc(OpcodeAndSize.second);
342  break;
343  case TargetOpcode::G_ANYEXT:
344  case TargetOpcode::G_SEXT:
345  Val = Val.sext(OpcodeAndSize.second);
346  break;
347  case TargetOpcode::G_ZEXT:
348  Val = Val.zext(OpcodeAndSize.second);
349  break;
350  }
351  }
352 
353  return ValueAndVReg{Val, VReg};
354 }
355 
356 bool isIConstant(const MachineInstr *MI) {
357  if (!MI)
358  return false;
359  return MI->getOpcode() == TargetOpcode::G_CONSTANT;
360 }
361 
362 bool isFConstant(const MachineInstr *MI) {
363  if (!MI)
364  return false;
365  return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
366 }
367 
368 bool isAnyConstant(const MachineInstr *MI) {
369  if (!MI)
370  return false;
371  unsigned Opc = MI->getOpcode();
372  return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
373 }
374 
375 Optional<APInt> getCImmAsAPInt(const MachineInstr *MI) {
376  const MachineOperand &CstVal = MI->getOperand(1);
377  if (CstVal.isCImm())
378  return CstVal.getCImm()->getValue();
379  return None;
380 }
381 
382 Optional<APInt> getCImmOrFPImmAsAPInt(const MachineInstr *MI) {
383  const MachineOperand &CstVal = MI->getOperand(1);
384  if (CstVal.isCImm())
385  return CstVal.getCImm()->getValue();
386  if (CstVal.isFPImm())
387  return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
388  return None;
389 }
390 
391 } // end anonymous namespace
392 
394  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
395  return getConstantVRegValWithLookThrough(VReg, MRI, isIConstant,
396  getCImmAsAPInt, LookThroughInstrs);
397 }
398 
400  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
401  bool LookThroughAnyExt) {
402  return getConstantVRegValWithLookThrough(
403  VReg, MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
404  LookThroughAnyExt);
405 }
406 
408  Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
409  auto Reg = getConstantVRegValWithLookThrough(
410  VReg, MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
411  if (!Reg)
412  return None;
414  Reg->VReg};
415 }
416 
417 const ConstantFP *
419  MachineInstr *MI = MRI.getVRegDef(VReg);
420  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
421  return nullptr;
422  return MI->getOperand(1).getFPImm();
423 }
424 
427  Register DefSrcReg = Reg;
428  auto *DefMI = MRI.getVRegDef(Reg);
429  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
430  if (!DstTy.isValid())
431  return None;
432  unsigned Opc = DefMI->getOpcode();
433  while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
434  Register SrcReg = DefMI->getOperand(1).getReg();
435  auto SrcTy = MRI.getType(SrcReg);
436  if (!SrcTy.isValid())
437  break;
438  DefMI = MRI.getVRegDef(SrcReg);
439  DefSrcReg = SrcReg;
440  Opc = DefMI->getOpcode();
441  }
442  return DefinitionAndSourceRegister{DefMI, DefSrcReg};
443 }
444 
446  const MachineRegisterInfo &MRI) {
449  return DefSrcReg ? DefSrcReg->MI : nullptr;
450 }
451 
453  const MachineRegisterInfo &MRI) {
456  return DefSrcReg ? DefSrcReg->Reg : Register();
457 }
458 
460  const MachineRegisterInfo &MRI) {
462  return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
463 }
464 
465 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
466  if (Size == 32)
467  return APFloat(float(Val));
468  if (Size == 64)
469  return APFloat(Val);
470  if (Size != 16)
471  llvm_unreachable("Unsupported FPConstant size");
472  bool Ignored;
473  APFloat APF(Val);
475  return APF;
476 }
477 
479  const Register Op2,
480  const MachineRegisterInfo &MRI) {
481  auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
482  if (!MaybeOp2Cst)
483  return None;
484 
485  auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
486  if (!MaybeOp1Cst)
487  return None;
488 
489  const APInt &C1 = MaybeOp1Cst->Value;
490  const APInt &C2 = MaybeOp2Cst->Value;
491  switch (Opcode) {
492  default:
493  break;
494  case TargetOpcode::G_ADD:
495  return C1 + C2;
496  case TargetOpcode::G_AND:
497  return C1 & C2;
498  case TargetOpcode::G_ASHR:
499  return C1.ashr(C2);
500  case TargetOpcode::G_LSHR:
501  return C1.lshr(C2);
502  case TargetOpcode::G_MUL:
503  return C1 * C2;
504  case TargetOpcode::G_OR:
505  return C1 | C2;
506  case TargetOpcode::G_SHL:
507  return C1 << C2;
508  case TargetOpcode::G_SUB:
509  return C1 - C2;
510  case TargetOpcode::G_XOR:
511  return C1 ^ C2;
512  case TargetOpcode::G_UDIV:
513  if (!C2.getBoolValue())
514  break;
515  return C1.udiv(C2);
516  case TargetOpcode::G_SDIV:
517  if (!C2.getBoolValue())
518  break;
519  return C1.sdiv(C2);
520  case TargetOpcode::G_UREM:
521  if (!C2.getBoolValue())
522  break;
523  return C1.urem(C2);
524  case TargetOpcode::G_SREM:
525  if (!C2.getBoolValue())
526  break;
527  return C1.srem(C2);
528  }
529 
530  return None;
531 }
532 
534  const Register Op2,
535  const MachineRegisterInfo &MRI) {
536  const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
537  if (!Op2Cst)
538  return None;
539 
540  const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
541  if (!Op1Cst)
542  return None;
543 
544  APFloat C1 = Op1Cst->getValueAPF();
545  const APFloat &C2 = Op2Cst->getValueAPF();
546  switch (Opcode) {
547  case TargetOpcode::G_FADD:
549  return C1;
550  case TargetOpcode::G_FSUB:
551  C1.subtract(C2, APFloat::rmNearestTiesToEven);
552  return C1;
553  case TargetOpcode::G_FMUL:
554  C1.multiply(C2, APFloat::rmNearestTiesToEven);
555  return C1;
556  case TargetOpcode::G_FDIV:
557  C1.divide(C2, APFloat::rmNearestTiesToEven);
558  return C1;
559  case TargetOpcode::G_FREM:
560  C1.mod(C2);
561  return C1;
562  case TargetOpcode::G_FCOPYSIGN:
563  C1.copySign(C2);
564  return C1;
565  case TargetOpcode::G_FMINNUM:
566  return minnum(C1, C2);
567  case TargetOpcode::G_FMAXNUM:
568  return maxnum(C1, C2);
569  case TargetOpcode::G_FMINIMUM:
570  return minimum(C1, C2);
571  case TargetOpcode::G_FMAXIMUM:
572  return maximum(C1, C2);
573  case TargetOpcode::G_FMINNUM_IEEE:
574  case TargetOpcode::G_FMAXNUM_IEEE:
575  // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
576  // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
577  // and currently there isn't a nice wrapper in APFloat for the version with
578  // correct snan handling.
579  break;
580  default:
581  break;
582  }
583 
584  return None;
585 }
586 
588 llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
589  const Register Op2,
590  const MachineRegisterInfo &MRI,
591  MachineIRBuilder &MIB) {
592  auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
593  if (!SrcVec1)
594  return None;
595  auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
596  if (!SrcVec2)
597  return None;
598 
599  const LLT EltTy = MRI.getType(SrcVec1->getSourceReg(0));
600 
601  SmallVector<Register, 16> FoldedElements;
602  for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
603  auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
604  SrcVec2->getSourceReg(Idx), MRI);
605  if (!MaybeCst)
606  return None;
607  auto FoldedCstReg = MIB.buildConstant(EltTy, *MaybeCst).getReg(0);
608  FoldedElements.emplace_back(FoldedCstReg);
609  }
610  // Create the new vector constant.
611  auto CstVec =
612  MIB.buildBuildVector(MRI.getType(SrcVec1->getReg(0)), FoldedElements);
613  return &*CstVec;
614 }
615 
617  bool SNaN) {
618  const MachineInstr *DefMI = MRI.getVRegDef(Val);
619  if (!DefMI)
620  return false;
621 
622  const TargetMachine& TM = DefMI->getMF()->getTarget();
623  if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
624  return true;
625 
626  // If the value is a constant, we can obviously see if it is a NaN or not.
627  if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
628  return !FPVal->getValueAPF().isNaN() ||
629  (SNaN && !FPVal->getValueAPF().isSignaling());
630  }
631 
632  if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
633  for (const auto &Op : DefMI->uses())
634  if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
635  return false;
636  return true;
637  }
638 
639  switch (DefMI->getOpcode()) {
640  default:
641  break;
642  case TargetOpcode::G_FMINNUM_IEEE:
643  case TargetOpcode::G_FMAXNUM_IEEE: {
644  if (SNaN)
645  return true;
646  // This can return a NaN if either operand is an sNaN, or if both operands
647  // are NaN.
648  return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
652  }
653  case TargetOpcode::G_FMINNUM:
654  case TargetOpcode::G_FMAXNUM: {
655  // Only one needs to be known not-nan, since it will be returned if the
656  // other ends up being one.
657  return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
658  isKnownNeverNaN(DefMI->getOperand(2).getReg(), MRI, SNaN);
659  }
660  }
661 
662  if (SNaN) {
663  // FP operations quiet. For now, just handle the ones inserted during
664  // legalization.
665  switch (DefMI->getOpcode()) {
666  case TargetOpcode::G_FPEXT:
667  case TargetOpcode::G_FPTRUNC:
668  case TargetOpcode::G_FCANONICALIZE:
669  return true;
670  default:
671  return false;
672  }
673  }
674 
675  return false;
676 }
677 
679  const MachinePointerInfo &MPO) {
680  auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>();
681  if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
682  MachineFrameInfo &MFI = MF.getFrameInfo();
683  return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
684  MPO.Offset);
685  }
686 
687  if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
688  const Module *M = MF.getFunction().getParent();
689  return V->getPointerAlignment(M->getDataLayout());
690  }
691 
692  return Align(1);
693 }
694 
696  const TargetInstrInfo &TII,
697  MCRegister PhysReg,
698  const TargetRegisterClass &RC,
699  LLT RegTy) {
700  DebugLoc DL; // FIXME: Is no location the right choice?
701  MachineBasicBlock &EntryMBB = MF.front();
703  Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
704  if (LiveIn) {
705  MachineInstr *Def = MRI.getVRegDef(LiveIn);
706  if (Def) {
707  // FIXME: Should the verifier check this is in the entry block?
708  assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
709  return LiveIn;
710  }
711 
712  // It's possible the incoming argument register and copy was added during
713  // lowering, but later deleted due to being/becoming dead. If this happens,
714  // re-insert the copy.
715  } else {
716  // The live in register was not present, so add it.
717  LiveIn = MF.addLiveIn(PhysReg, &RC);
718  if (RegTy.isValid())
719  MRI.setType(LiveIn, RegTy);
720  }
721 
722  BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
723  .addReg(PhysReg);
724  if (!EntryMBB.isLiveIn(PhysReg))
725  EntryMBB.addLiveIn(PhysReg);
726  return LiveIn;
727 }
728 
730  uint64_t Imm,
731  const MachineRegisterInfo &MRI) {
732  auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
733  if (MaybeOp1Cst) {
734  switch (Opcode) {
735  default:
736  break;
737  case TargetOpcode::G_SEXT_INREG: {
738  LLT Ty = MRI.getType(Op1);
739  return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
740  }
741  }
742  }
743  return None;
744 }
745 
747  Register Src,
748  const MachineRegisterInfo &MRI) {
749  assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
750  if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
751  APFloat DstVal(getFltSemanticForLLT(DstTy));
752  DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
754  return DstVal;
755  }
756  return None;
757 }
758 
761  LLT Ty = MRI.getType(Src);
762  SmallVector<unsigned> FoldedCTLZs;
763  auto tryFoldScalar = [&](Register R) -> Optional<unsigned> {
764  auto MaybeCst = getIConstantVRegVal(R, MRI);
765  if (!MaybeCst)
766  return None;
767  return MaybeCst->countLeadingZeros();
768  };
769  if (Ty.isVector()) {
770  // Try to constant fold each element.
771  auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
772  if (!BV)
773  return None;
774  for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
775  if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
776  FoldedCTLZs.emplace_back(*MaybeFold);
777  continue;
778  }
779  return None;
780  }
781  return FoldedCTLZs;
782  }
783  if (auto MaybeCst = tryFoldScalar(Src)) {
784  FoldedCTLZs.emplace_back(*MaybeCst);
785  return FoldedCTLZs;
786  }
787  return None;
788 }
789 
791  GISelKnownBits *KB) {
794  if (!DefSrcReg)
795  return false;
796 
797  const MachineInstr &MI = *DefSrcReg->MI;
798  const LLT Ty = MRI.getType(Reg);
799 
800  switch (MI.getOpcode()) {
801  case TargetOpcode::G_CONSTANT: {
802  unsigned BitWidth = Ty.getScalarSizeInBits();
803  const ConstantInt *CI = MI.getOperand(1).getCImm();
804  return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
805  }
806  case TargetOpcode::G_SHL: {
807  // A left-shift of a constant one will have exactly one bit set because
808  // shifting the bit off the end is undefined.
809 
810  // TODO: Constant splat
811  if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
812  if (*ConstLHS == 1)
813  return true;
814  }
815 
816  break;
817  }
818  case TargetOpcode::G_LSHR: {
819  if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
820  if (ConstLHS->isSignMask())
821  return true;
822  }
823 
824  break;
825  }
826  case TargetOpcode::G_BUILD_VECTOR: {
827  // TODO: Probably should have a recursion depth guard since you could have
828  // bitcasted vector elements.
829  for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
830  if (!isKnownToBeAPowerOfTwo(MI.getOperand(I).getReg(), MRI, KB))
831  return false;
832  }
833 
834  return true;
835  }
836  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
837  // Only handle constants since we would need to know if number of leading
838  // zeros is greater than the truncation amount.
839  const unsigned BitWidth = Ty.getScalarSizeInBits();
840  for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
841  auto Const = getIConstantVRegVal(MI.getOperand(I).getReg(), MRI);
842  if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
843  return false;
844  }
845 
846  return true;
847  }
848  default:
849  break;
850  }
851 
852  if (!KB)
853  return false;
854 
855  // More could be done here, though the above checks are enough
856  // to handle some common cases.
857 
858  // Fall back to computeKnownBits to catch other known cases.
859  KnownBits Known = KB->getKnownBits(Reg);
860  return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
861 }
862 
865 }
866 
867 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) {
868  unsigned Mul = OrigSize * TargetSize;
869  unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize);
870  return Mul / GCDSize;
871 }
872 
873 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
874  const unsigned OrigSize = OrigTy.getSizeInBits();
875  const unsigned TargetSize = TargetTy.getSizeInBits();
876 
877  if (OrigSize == TargetSize)
878  return OrigTy;
879 
880  if (OrigTy.isVector()) {
881  const LLT OrigElt = OrigTy.getElementType();
882 
883  if (TargetTy.isVector()) {
884  const LLT TargetElt = TargetTy.getElementType();
885 
886  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
887  int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(),
888  TargetTy.getNumElements());
889  // Prefer the original element type.
890  ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
891  return LLT::vector(Mul.divideCoefficientBy(GCDElts),
892  OrigTy.getElementType());
893  }
894  } else {
895  if (OrigElt.getSizeInBits() == TargetSize)
896  return OrigTy;
897  }
898 
899  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
900  return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
901  }
902 
903  if (TargetTy.isVector()) {
904  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
905  return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
906  }
907 
908  unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
909 
910  // Preserve pointer types.
911  if (LCMSize == OrigSize)
912  return OrigTy;
913  if (LCMSize == TargetSize)
914  return TargetTy;
915 
916  return LLT::scalar(LCMSize);
917 }
918 
919 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
920  const unsigned OrigSize = OrigTy.getSizeInBits();
921  const unsigned TargetSize = TargetTy.getSizeInBits();
922 
923  if (OrigSize == TargetSize)
924  return OrigTy;
925 
926  if (OrigTy.isVector()) {
927  LLT OrigElt = OrigTy.getElementType();
928  if (TargetTy.isVector()) {
929  LLT TargetElt = TargetTy.getElementType();
930  if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
931  int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
932  TargetTy.getNumElements());
933  return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
934  }
935  } else {
936  // If the source is a vector of pointers, return a pointer element.
937  if (OrigElt.getSizeInBits() == TargetSize)
938  return OrigElt;
939  }
940 
941  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
942  if (GCD == OrigElt.getSizeInBits())
943  return OrigElt;
944 
945  // If we can't produce the original element type, we have to use a smaller
946  // scalar.
947  if (GCD < OrigElt.getSizeInBits())
948  return LLT::scalar(GCD);
949  return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
950  }
951 
952  if (TargetTy.isVector()) {
953  // Try to preserve the original element type.
954  LLT TargetElt = TargetTy.getElementType();
955  if (TargetElt.getSizeInBits() == OrigSize)
956  return OrigTy;
957  }
958 
959  unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
960  return LLT::scalar(GCD);
961 }
962 
964  assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
965  "Only G_SHUFFLE_VECTOR can have a splat index!");
966  ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
967  auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
968 
969  // If all elements are undefined, this shuffle can be considered a splat.
970  // Return 0 for better potential for callers to simplify.
971  if (FirstDefinedIdx == Mask.end())
972  return 0;
973 
974  // Make sure all remaining elements are either undef or the same
975  // as the first non-undef value.
976  int SplatValue = *FirstDefinedIdx;
977  if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
978  [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
979  return None;
980 
981  return SplatValue;
982 }
983 
984 static bool isBuildVectorOp(unsigned Opcode) {
985  return Opcode == TargetOpcode::G_BUILD_VECTOR ||
986  Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
987 }
988 
989 namespace {
990 
991 Optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
992  const MachineRegisterInfo &MRI,
993  bool AllowUndef) {
995  if (!MI)
996  return None;
997 
998  if (!isBuildVectorOp(MI->getOpcode()))
999  return None;
1000 
1001  Optional<ValueAndVReg> SplatValAndReg = None;
1002  for (MachineOperand &Op : MI->uses()) {
1003  Register Element = Op.getReg();
1004  auto ElementValAndReg =
1005  getAnyConstantVRegValWithLookThrough(Element, MRI, true, true);
1006 
1007  // If AllowUndef, treat undef as value that will result in a constant splat.
1008  if (!ElementValAndReg) {
1009  if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1010  continue;
1011  return None;
1012  }
1013 
1014  // Record splat value
1015  if (!SplatValAndReg)
1016  SplatValAndReg = ElementValAndReg;
1017 
1018  // Different constant then the one already recorded, not a constant splat.
1019  if (SplatValAndReg->Value != ElementValAndReg->Value)
1020  return None;
1021  }
1022 
1023  return SplatValAndReg;
1024 }
1025 
1026 bool isBuildVectorConstantSplat(const MachineInstr &MI,
1027  const MachineRegisterInfo &MRI,
1028  int64_t SplatValue, bool AllowUndef) {
1029  if (auto SplatValAndReg =
1030  getAnyConstantSplat(MI.getOperand(0).getReg(), MRI, AllowUndef))
1031  return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
1032  return false;
1033 }
1034 
1035 } // end anonymous namespace
1036 
1039  const MachineRegisterInfo &MRI) {
1040  if (auto SplatValAndReg =
1041  getAnyConstantSplat(MI.getOperand(0).getReg(), MRI, false))
1042  return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1043  return None;
1044 }
1045 
1047  const MachineRegisterInfo &MRI,
1048  bool AllowUndef) {
1049  if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1050  return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1051  return None;
1052 }
1053 
1055  const MachineRegisterInfo &MRI,
1056  bool AllowUndef) {
1057  return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1058 }
1059 
1061  const MachineRegisterInfo &MRI,
1062  bool AllowUndef) {
1063  return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1064 }
1065 
1067  const MachineRegisterInfo &MRI) {
1068  unsigned Opc = MI.getOpcode();
1069  if (!isBuildVectorOp(Opc))
1070  return None;
1071  if (auto Splat = getBuildVectorConstantSplat(MI, MRI))
1072  return RegOrConstant(*Splat);
1073  auto Reg = MI.getOperand(1).getReg();
1074  if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
1075  [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1076  return None;
1077  return RegOrConstant(Reg);
1078 }
1079 
1081  const MachineRegisterInfo &MRI) {
1082  Register Def = MI.getOperand(0).getReg();
1084  return true;
1085  GBuildVector *BV = dyn_cast<GBuildVector>(&MI);
1086  if (!BV)
1087  return false;
1088  for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1090  getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI))
1091  continue;
1092  return false;
1093  }
1094  return true;
1095 }
1096 
1099  const MachineRegisterInfo &MRI) {
1100  Register Def = MI.getOperand(0).getReg();
1102  return C->Value;
1103  auto MaybeCst = getBuildVectorConstantSplat(MI, MRI);
1104  if (!MaybeCst)
1105  return None;
1106  const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1107  return APInt(ScalarSize, *MaybeCst, true);
1108 }
1109 
1112  std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1113 
1115  if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1116  return Match(nullptr);
1117 
1118  // TODO: Also handle fconstant
1119  if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1120  return Match(Def->getOperand(1).getCImm());
1121 
1122  if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1123  return false;
1124 
1125  for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1126  Register SrcElt = Def->getOperand(I).getReg();
1127  const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1128  if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1129  if (!Match(nullptr))
1130  return false;
1131  continue;
1132  }
1133 
1134  if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1135  !Match(SrcDef->getOperand(1).getCImm()))
1136  return false;
1137  }
1138 
1139  return true;
1140 }
1141 
1142 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1143  bool IsFP) {
1144  switch (TLI.getBooleanContents(IsVector, IsFP)) {
1146  return Val & 0x1;
1148  return Val == 1;
1150  return Val == -1;
1151  }
1152  llvm_unreachable("Invalid boolean contents");
1153 }
1154 
1155 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1156  bool IsFP) {
1157  switch (TLI.getBooleanContents(IsVector, IsFP)) {
1160  return 1;
1162  return -1;
1163  }
1164  llvm_unreachable("Invalid boolean contents");
1165 }
1166 
1169  const auto &F = MBB.getParent()->getFunction();
1170  return F.hasOptSize() || F.hasMinSize() ||
1172 }
1173 
1174 /// These artifacts generally don't have any debug users because they don't
1175 /// directly originate from IR instructions, but instead usually from
1176 /// legalization. Avoiding checking for debug users improves compile time.
1177 /// Note that truncates or extends aren't included because they have IR
1178 /// counterparts which can have debug users after translation.
1180  switch (MI.getOpcode()) {
1181  case TargetOpcode::G_UNMERGE_VALUES:
1182  case TargetOpcode::G_MERGE_VALUES:
1183  case TargetOpcode::G_CONCAT_VECTORS:
1184  case TargetOpcode::G_BUILD_VECTOR:
1185  case TargetOpcode::G_EXTRACT:
1186  case TargetOpcode::G_INSERT:
1187  return true;
1188  default:
1189  return false;
1190  }
1191 }
1192 
1194  LostDebugLocObserver *LocObserver,
1195  SmallInstListTy &DeadInstChain) {
1196  for (MachineOperand &Op : MI.uses()) {
1197  if (Op.isReg() && Op.getReg().isVirtual())
1198  DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1199  }
1200  LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1201  DeadInstChain.remove(&MI);
1203  MI.eraseFromParent();
1204  else
1205  MI.eraseFromParentAndMarkDBGValuesForRemoval();
1206  if (LocObserver)
1207  LocObserver->checkpoint(false);
1208 }
1209 
1212  LostDebugLocObserver *LocObserver) {
1213  SmallInstListTy DeadInstChain;
1214  for (MachineInstr *MI : DeadInstrs)
1215  saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1216 
1217  while (!DeadInstChain.empty()) {
1218  MachineInstr *Inst = DeadInstChain.pop_back_val();
1219  if (!isTriviallyDead(*Inst, MRI))
1220  continue;
1221  saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1222  }
1223 }
1224 
1226  LostDebugLocObserver *LocObserver) {
1227  return eraseInstrs({&MI}, MRI, LocObserver);
1228 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MIPatternMatch.h
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:495
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:284
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1086
StackProtector.h
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1193
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:666
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:445
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::GBuildVector
Represents a G_BUILD_VECTOR.
Definition: GenericMachineInstrs.h:191
MachineInstr.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:580
Optional.h
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:213
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1178
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ElementCount
Definition: TypeSize.h:386
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:178
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:117
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:465
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1177
llvm::greatestCommonDivisor
T greatestCommonDivisor(T A, T B)
Return the greatest common divisor of the values using Euclid's algorithm.
Definition: MathExtras.h:621
llvm::ore::MNV
DiagnosticInfoMIROptimization::MachineArgument MNV
Definition: MachineOptimizationRemarkEmitter.h:141
llvm::APInt::isPowerOf2
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:425
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:459
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::MachineFunction::getObserver
GISelChangeObserver * getObserver() const
Definition: MachineFunction.h:579
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1474
GISelKnownBits.h
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:452
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:150
llvm::APInt::zextOrTrunc
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:970
RegisterBankInfo.h
MachineSizeOpts.h
reportGISelDiagnostic
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:228
llvm::minimum
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
Definition: APFloat.h:1318
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1167
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1410
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:695
TargetInstrInfo.h
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1210
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:454
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:533
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:325
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:666
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:297
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
GenericMachineInstrs.h
llvm::Optional
Definition: APInt.h:33
llvm::LLT::vector
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:57
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:632
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:863
MachineIRBuilder.h
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:246
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
Definition: TargetLowering.h:828
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:347
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:179
getLCMSize
static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize)
Definition: Utils.cpp:867
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:136
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1155
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::getFltSemanticForLLT
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
Definition: LowLevelType.cpp:73
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:45
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:180
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:75
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:919
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:824
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::GISelKnownBits::getKnownBits
KnownBits getKnownBits(Register R)
Definition: GISelKnownBits.cpp:57
Constants.h
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:182
llvm::maximum
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
Definition: APFloat.h:1331
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::DS_Warning
@ DS_Warning
Definition: DiagnosticInfo.h:47
llvm::APFloatBase::IEEEhalf
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:164
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3187
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::StackProtector
Definition: StackProtector.h:37
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LostDebugLocObserver::checkpoint
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Definition: LostDebugLocObserver.cpp:70
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:234
Utils.h
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:721
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:729
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:173
llvm::DiagnosticSeverity
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Definition: DiagnosticInfo.h:45
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1526
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:746
llvm::isConstantOrConstantSplatVector
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1098
llvm::MIPatternMatch::m_SpecificICst
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
Definition: MIPatternMatch.h:128
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1130
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::RegisterBankInfo::constrainGenericRegister
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Definition: RegisterBankInfo.cpp:132
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::maxnum
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1307
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1110
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:873
llvm::isConstantOrConstantVector
bool isConstantOrConstantVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a build vector of constant integers.
Definition: Utils.cpp:1080
llvm::APFloat
Definition: APFloat.h:701
llvm::FPValueAndVReg
Definition: Utils.h:196
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1225
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:542
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:578
llvm::MachineOptimizationRemarkMissed
Diagnostic information for missed-optimization remarks.
Definition: MachineOptimizationRemarkEmitter.h:82
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1142
llvm::GMergeLikeOp::getSourceReg
Register getSourceReg(unsigned I) const
Returns the I'th source register.
Definition: GenericMachineInstrs.h:160
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:165
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:678
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:123
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:127
TargetPassConfig.h
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:547
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:542
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:646
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
isBuildVectorOp
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:984
llvm::KnownBits::countMaxPopulation
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:281
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:272
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:196
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:668
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:654
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:399
llvm::GISelWorkList::pop_back_val
MachineInstr * pop_back_val()
Definition: GISelWorkList.h:99
llvm::ArrayRef< int >
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:42
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:40
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1558
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:393
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::RecurKind::Mul
@ Mul
Product of integers.
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::GISelWorkList::remove
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:82
llvm::ConstantFoldVectorBinop
Optional< MachineInstr * > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI, MachineIRBuilder &MIB)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:588
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3737
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1578
llvm::APInt::zext
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:952
llvm::GISelWorkList::insert
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:75
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:760
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1060
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::minnum
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1296
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::APInt::trunc
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:883
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:596
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:626
llvm::KnownBits::countMinPopulation
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:276
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::getBuildVectorConstantSplat
Optional< int64_t > getBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
Definition: Utils.cpp:1038
llvm::isTargetSpecificOpcode
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:219
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:182
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:302
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1066
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:233
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:407
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:928
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:252
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::GMergeLikeOp::getNumSources
unsigned getNumSources() const
Returns the number of source registers.
Definition: GenericMachineInstrs.h:158
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:327
llvm::APFloatBase::rmNearestTiesToEven
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:190
llvm::APFloat::convert
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4836
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:344
llvm::GISelWorkList
Definition: GISelWorkList.h:28
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1046
llvm::LLT::getElementCount
ElementCount getElementCount() const
Definition: LowLevelTypeImpl.h:144
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:50
llvm::LLT::scalarOrVector
static LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
Definition: LowLevelTypeImpl.h:98
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:418
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::APFloat::convertFromAPInt
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition: APFloat.h:1113
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:24
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:292
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:221
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
GISelChangeObserver.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:237
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:220
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:426
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
shouldSkipDbgValueFor
static bool shouldSkipDbgValueFor(MachineInstr &MI)
These artifacts generally don't have any debug users because they don't directly originate from IR in...
Definition: Utils.cpp:1179
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::GISelWorkList::empty
bool empty() const
Definition: GISelWorkList.h:39
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:46
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:669
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1054
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:232
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:478
llvm::LLT
Definition: LowLevelTypeImpl.h:40