LLVM 22.0.0git
Utils.cpp
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1//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file This file implements the utility functions used by the GlobalISel
9/// pipeline.
10//===----------------------------------------------------------------------===//
11
13#include "llvm/ADT/APFloat.h"
14#include "llvm/ADT/APInt.h"
35#include "llvm/IR/Constants.h"
38#include <numeric>
39#include <optional>
40
41#define DEBUG_TYPE "globalisel-utils"
42
43using namespace llvm;
44using namespace MIPatternMatch;
45
47 const TargetInstrInfo &TII,
48 const RegisterBankInfo &RBI, Register Reg,
49 const TargetRegisterClass &RegClass) {
50 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
51 return MRI.createVirtualRegister(&RegClass);
52
53 return Reg;
54}
55
57 const MachineFunction &MF, const TargetRegisterInfo &TRI,
59 const RegisterBankInfo &RBI, MachineInstr &InsertPt,
60 const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
61 Register Reg = RegMO.getReg();
62 // Assume physical registers are properly constrained.
63 assert(Reg.isVirtual() && "PhysReg not implemented");
64
65 // Save the old register class to check whether
66 // the change notifications will be required.
67 // TODO: A better approach would be to pass
68 // the observers to constrainRegToClass().
69 auto *OldRegClass = MRI.getRegClassOrNull(Reg);
70 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
71 // If we created a new virtual register because the class is not compatible
72 // then create a copy between the new and the old register.
73 if (ConstrainedReg != Reg) {
74 MachineBasicBlock::iterator InsertIt(&InsertPt);
75 MachineBasicBlock &MBB = *InsertPt.getParent();
76 // FIXME: The copy needs to have the classes constrained for its operands.
77 // Use operand's regbank to get the class for old register (Reg).
78 if (RegMO.isUse()) {
79 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
80 TII.get(TargetOpcode::COPY), ConstrainedReg)
81 .addReg(Reg);
82 } else {
83 assert(RegMO.isDef() && "Must be a definition");
84 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
85 TII.get(TargetOpcode::COPY), Reg)
86 .addReg(ConstrainedReg);
87 }
88 if (GISelChangeObserver *Observer = MF.getObserver()) {
89 Observer->changingInstr(*RegMO.getParent());
90 }
91 RegMO.setReg(ConstrainedReg);
92 if (GISelChangeObserver *Observer = MF.getObserver()) {
93 Observer->changedInstr(*RegMO.getParent());
94 }
95 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) {
96 if (GISelChangeObserver *Observer = MF.getObserver()) {
97 if (!RegMO.isDef()) {
98 MachineInstr *RegDef = MRI.getVRegDef(Reg);
99 Observer->changedInstr(*RegDef);
100 }
101 Observer->changingAllUsesOfReg(MRI, Reg);
102 Observer->finishedChangingAllUsesOfReg();
103 }
104 }
105 return ConstrainedReg;
106}
107
109 const MachineFunction &MF, const TargetRegisterInfo &TRI,
111 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
112 MachineOperand &RegMO, unsigned OpIdx) {
113 Register Reg = RegMO.getReg();
114 // Assume physical registers are properly constrained.
115 assert(Reg.isVirtual() && "PhysReg not implemented");
116
117 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI);
118 // Some of the target independent instructions, like COPY, may not impose any
119 // register class constraints on some of their operands: If it's a use, we can
120 // skip constraining as the instruction defining the register would constrain
121 // it.
122
123 if (OpRC) {
124 // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
125 // can have multiple regbanks for a superclass that combine different
126 // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
127 // resolved by targets during regbankselect should not be overridden.
128 if (const auto *SubRC = TRI.getCommonSubClass(
129 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))
130 OpRC = SubRC;
131
132 OpRC = TRI.getAllocatableClass(OpRC);
133 }
134
135 if (!OpRC) {
136 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
137 "Register class constraint is required unless either the "
138 "instruction is target independent or the operand is a use");
139 // FIXME: Just bailing out like this here could be not enough, unless we
140 // expect the users of this function to do the right thing for PHIs and
141 // COPY:
142 // v1 = COPY v0
143 // v2 = COPY v1
144 // v1 here may end up not being constrained at all. Please notice that to
145 // reproduce the issue we likely need a destination pattern of a selection
146 // rule producing such extra copies, not just an input GMIR with them as
147 // every existing target using selectImpl handles copies before calling it
148 // and they never reach this function.
149 return Reg;
150 }
151 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
152 RegMO);
153}
154
156 const TargetInstrInfo &TII,
157 const TargetRegisterInfo &TRI,
158 const RegisterBankInfo &RBI) {
159 assert(!isPreISelGenericOpcode(I.getOpcode()) &&
160 "A selected instruction is expected");
161 MachineBasicBlock &MBB = *I.getParent();
162 MachineFunction &MF = *MBB.getParent();
164
165 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
166 MachineOperand &MO = I.getOperand(OpI);
167
168 // There's nothing to be done on non-register operands.
169 if (!MO.isReg())
170 continue;
171
172 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
173 assert(MO.isReg() && "Unsupported non-reg operand");
174
175 Register Reg = MO.getReg();
176 // Physical registers don't need to be constrained.
177 if (Reg.isPhysical())
178 continue;
179
180 // Register operands with a value of 0 (e.g. predicate operands) don't need
181 // to be constrained.
182 if (Reg == 0)
183 continue;
184
185 // If the operand is a vreg, we should constrain its regclass, and only
186 // insert COPYs if that's impossible.
187 // constrainOperandRegClass does that for us.
188 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
189
190 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
191 // done.
192 if (MO.isUse()) {
193 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
194 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
195 I.tieOperands(DefIdx, OpI);
196 }
197 }
198 return true;
199}
200
203 // Give up if either DstReg or SrcReg is a physical register.
204 if (DstReg.isPhysical() || SrcReg.isPhysical())
205 return false;
206 // Give up if the types don't match.
207 if (MRI.getType(DstReg) != MRI.getType(SrcReg))
208 return false;
209 // Replace if either DstReg has no constraints or the register
210 // constraints match.
211 const auto &DstRBC = MRI.getRegClassOrRegBank(DstReg);
212 if (!DstRBC || DstRBC == MRI.getRegClassOrRegBank(SrcReg))
213 return true;
214
215 // Otherwise match if the Src is already a regclass that is covered by the Dst
216 // RegBank.
217 return isa<const RegisterBank *>(DstRBC) && MRI.getRegClassOrNull(SrcReg) &&
218 cast<const RegisterBank *>(DstRBC)->covers(
219 *MRI.getRegClassOrNull(SrcReg));
220}
221
223 const MachineRegisterInfo &MRI) {
224 // Instructions without side-effects are dead iff they only define dead regs.
225 // This function is hot and this loop returns early in the common case,
226 // so only perform additional checks before this if absolutely necessary.
227 for (const auto &MO : MI.all_defs()) {
228 Register Reg = MO.getReg();
229 if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
230 return false;
231 }
232 return MI.wouldBeTriviallyDead();
233}
234
236 MachineFunction &MF,
237 const TargetPassConfig &TPC,
240 bool IsFatal = Severity == DS_Error &&
242 // Print the function name explicitly if we don't have a debug location (which
243 // makes the diagnostic less useful) or if we're going to emit a raw error.
244 if (!R.getLocation().isValid() || IsFatal)
245 R << (" (in function: " + MF.getName() + ")").str();
246
247 if (IsFatal)
248 reportFatalUsageError(Twine(R.getMsg()));
249 else
250 MORE.emit(R);
251}
252
258
265
268 const char *PassName, StringRef Msg,
269 const MachineInstr &MI) {
270 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
271 MI.getDebugLoc(), MI.getParent());
272 R << Msg;
273 // Printing MI is expensive; only do it if expensive remarks are enabled.
274 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
275 R << ": " << ore::MNV("Inst", MI);
276 reportGISelFailure(MF, TPC, MORE, R);
277}
278
279unsigned llvm::getInverseGMinMaxOpcode(unsigned MinMaxOpc) {
280 switch (MinMaxOpc) {
281 case TargetOpcode::G_SMIN:
282 return TargetOpcode::G_SMAX;
283 case TargetOpcode::G_SMAX:
284 return TargetOpcode::G_SMIN;
285 case TargetOpcode::G_UMIN:
286 return TargetOpcode::G_UMAX;
287 case TargetOpcode::G_UMAX:
288 return TargetOpcode::G_UMIN;
289 default:
290 llvm_unreachable("unrecognized opcode");
291 }
292}
293
294std::optional<APInt> llvm::getIConstantVRegVal(Register VReg,
295 const MachineRegisterInfo &MRI) {
296 std::optional<ValueAndVReg> ValAndVReg = getIConstantVRegValWithLookThrough(
297 VReg, MRI, /*LookThroughInstrs*/ false);
298 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
299 "Value found while looking through instrs");
300 if (!ValAndVReg)
301 return std::nullopt;
302 return ValAndVReg->Value;
303}
304
306 const MachineRegisterInfo &MRI) {
307 MachineInstr *Const = MRI.getVRegDef(Reg);
308 assert((Const && Const->getOpcode() == TargetOpcode::G_CONSTANT) &&
309 "expected a G_CONSTANT on Reg");
310 return Const->getOperand(1).getCImm()->getValue();
311}
312
313std::optional<int64_t>
315 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI);
316 if (Val && Val->getBitWidth() <= 64)
317 return Val->getSExtValue();
318 return std::nullopt;
319}
320
321namespace {
322
323// This function is used in many places, and as such, it has some
324// micro-optimizations to try and make it as fast as it can be.
325//
326// - We use template arguments to avoid an indirect call caused by passing a
327// function_ref/std::function
328// - GetAPCstValue does not return std::optional<APInt> as that's expensive.
329// Instead it returns true/false and places the result in a pre-constructed
330// APInt.
331//
332// Please change this function carefully and benchmark your changes.
333template <bool (*IsConstantOpcode)(const MachineInstr *),
334 bool (*GetAPCstValue)(const MachineInstr *MI, APInt &)>
335std::optional<ValueAndVReg>
336getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
337 bool LookThroughInstrs = true,
338 bool LookThroughAnyExt = false) {
341
342 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
343 LookThroughInstrs) {
344 switch (MI->getOpcode()) {
345 case TargetOpcode::G_ANYEXT:
346 if (!LookThroughAnyExt)
347 return std::nullopt;
348 [[fallthrough]];
349 case TargetOpcode::G_TRUNC:
350 case TargetOpcode::G_SEXT:
351 case TargetOpcode::G_ZEXT:
352 SeenOpcodes.push_back(std::make_pair(
353 MI->getOpcode(),
354 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
355 VReg = MI->getOperand(1).getReg();
356 break;
357 case TargetOpcode::COPY:
358 VReg = MI->getOperand(1).getReg();
359 if (VReg.isPhysical())
360 return std::nullopt;
361 break;
362 case TargetOpcode::G_INTTOPTR:
363 VReg = MI->getOperand(1).getReg();
364 break;
365 default:
366 return std::nullopt;
367 }
368 }
369 if (!MI || !IsConstantOpcode(MI))
370 return std::nullopt;
371
372 APInt Val;
373 if (!GetAPCstValue(MI, Val))
374 return std::nullopt;
375 for (auto &Pair : reverse(SeenOpcodes)) {
376 switch (Pair.first) {
377 case TargetOpcode::G_TRUNC:
378 Val = Val.trunc(Pair.second);
379 break;
380 case TargetOpcode::G_ANYEXT:
381 case TargetOpcode::G_SEXT:
382 Val = Val.sext(Pair.second);
383 break;
384 case TargetOpcode::G_ZEXT:
385 Val = Val.zext(Pair.second);
386 break;
387 }
388 }
389
390 return ValueAndVReg{std::move(Val), VReg};
391}
392
393bool isIConstant(const MachineInstr *MI) {
394 if (!MI)
395 return false;
396 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
397}
398
399bool isFConstant(const MachineInstr *MI) {
400 if (!MI)
401 return false;
402 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
403}
404
405bool isAnyConstant(const MachineInstr *MI) {
406 if (!MI)
407 return false;
408 unsigned Opc = MI->getOpcode();
409 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
410}
411
412bool getCImmAsAPInt(const MachineInstr *MI, APInt &Result) {
413 const MachineOperand &CstVal = MI->getOperand(1);
414 if (!CstVal.isCImm())
415 return false;
416 Result = CstVal.getCImm()->getValue();
417 return true;
418}
419
420bool getCImmOrFPImmAsAPInt(const MachineInstr *MI, APInt &Result) {
421 const MachineOperand &CstVal = MI->getOperand(1);
422 if (CstVal.isCImm())
423 Result = CstVal.getCImm()->getValue();
424 else if (CstVal.isFPImm())
426 else
427 return false;
428 return true;
429}
430
431} // end anonymous namespace
432
434 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
435 return getConstantVRegValWithLookThrough<isIConstant, getCImmAsAPInt>(
436 VReg, MRI, LookThroughInstrs);
437}
438
440 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
441 bool LookThroughAnyExt) {
442 return getConstantVRegValWithLookThrough<isAnyConstant,
443 getCImmOrFPImmAsAPInt>(
444 VReg, MRI, LookThroughInstrs, LookThroughAnyExt);
445}
446
447std::optional<FPValueAndVReg> llvm::getFConstantVRegValWithLookThrough(
448 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
449 auto Reg =
450 getConstantVRegValWithLookThrough<isFConstant, getCImmOrFPImmAsAPInt>(
451 VReg, MRI, LookThroughInstrs);
452 if (!Reg)
453 return std::nullopt;
455 Reg->VReg};
456}
457
458const ConstantFP *
460 MachineInstr *MI = MRI.getVRegDef(VReg);
461 if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
462 return nullptr;
463 return MI->getOperand(1).getFPImm();
464}
465
466std::optional<DefinitionAndSourceRegister>
468 Register DefSrcReg = Reg;
469 // This assumes that the code is in SSA form, so there should only be one
470 // definition.
471 auto DefIt = MRI.def_begin(Reg);
472 if (DefIt == MRI.def_end())
473 return {};
474 MachineOperand &DefOpnd = *DefIt;
475 MachineInstr *DefMI = DefOpnd.getParent();
476 auto DstTy = MRI.getType(DefOpnd.getReg());
477 if (!DstTy.isValid())
478 return std::nullopt;
479 unsigned Opc = DefMI->getOpcode();
480 while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
481 Register SrcReg = DefMI->getOperand(1).getReg();
482 auto SrcTy = MRI.getType(SrcReg);
483 if (!SrcTy.isValid())
484 break;
485 DefMI = MRI.getVRegDef(SrcReg);
486 DefSrcReg = SrcReg;
487 Opc = DefMI->getOpcode();
488 }
489 return DefinitionAndSourceRegister{DefMI, DefSrcReg};
490}
491
493 const MachineRegisterInfo &MRI) {
494 std::optional<DefinitionAndSourceRegister> DefSrcReg =
496 return DefSrcReg ? DefSrcReg->MI : nullptr;
497}
498
500 const MachineRegisterInfo &MRI) {
501 std::optional<DefinitionAndSourceRegister> DefSrcReg =
503 return DefSrcReg ? DefSrcReg->Reg : Register();
504}
505
506void llvm::extractParts(Register Reg, LLT Ty, int NumParts,
508 MachineIRBuilder &MIRBuilder,
510 for (int i = 0; i < NumParts; ++i)
511 VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
512 MIRBuilder.buildUnmerge(VRegs, Reg);
513}
514
515bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
517 SmallVectorImpl<Register> &LeftoverRegs,
518 MachineIRBuilder &MIRBuilder,
520 assert(!LeftoverTy.isValid() && "this is an out argument");
521
522 unsigned RegSize = RegTy.getSizeInBits();
523 unsigned MainSize = MainTy.getSizeInBits();
524 unsigned NumParts = RegSize / MainSize;
525 unsigned LeftoverSize = RegSize - NumParts * MainSize;
526
527 // Use an unmerge when possible.
528 if (LeftoverSize == 0) {
529 for (unsigned I = 0; I < NumParts; ++I)
530 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
531 MIRBuilder.buildUnmerge(VRegs, Reg);
532 return true;
533 }
534
535 // Try to use unmerge for irregular vector split where possible
536 // For example when splitting a <6 x i32> into <4 x i32> with <2 x i32>
537 // leftover, it becomes:
538 // <2 x i32> %2, <2 x i32>%3, <2 x i32> %4 = G_UNMERGE_VALUE <6 x i32> %1
539 // <4 x i32> %5 = G_CONCAT_VECTOR <2 x i32> %2, <2 x i32> %3
540 if (RegTy.isVector() && MainTy.isVector()) {
541 unsigned RegNumElts = RegTy.getNumElements();
542 unsigned MainNumElts = MainTy.getNumElements();
543 unsigned LeftoverNumElts = RegNumElts % MainNumElts;
544 // If can unmerge to LeftoverTy, do it
545 if (MainNumElts % LeftoverNumElts == 0 &&
546 RegNumElts % LeftoverNumElts == 0 &&
547 RegTy.getScalarSizeInBits() == MainTy.getScalarSizeInBits() &&
548 LeftoverNumElts > 1) {
549 LeftoverTy = LLT::fixed_vector(LeftoverNumElts, RegTy.getElementType());
550
551 // Unmerge the SrcReg to LeftoverTy vectors
552 SmallVector<Register, 4> UnmergeValues;
553 extractParts(Reg, LeftoverTy, RegNumElts / LeftoverNumElts, UnmergeValues,
554 MIRBuilder, MRI);
555
556 // Find how many LeftoverTy makes one MainTy
557 unsigned LeftoverPerMain = MainNumElts / LeftoverNumElts;
558 unsigned NumOfLeftoverVal =
559 ((RegNumElts % MainNumElts) / LeftoverNumElts);
560
561 // Create as many MainTy as possible using unmerged value
562 SmallVector<Register, 4> MergeValues;
563 for (unsigned I = 0; I < UnmergeValues.size() - NumOfLeftoverVal; I++) {
564 MergeValues.push_back(UnmergeValues[I]);
565 if (MergeValues.size() == LeftoverPerMain) {
566 VRegs.push_back(
567 MIRBuilder.buildMergeLikeInstr(MainTy, MergeValues).getReg(0));
568 MergeValues.clear();
569 }
570 }
571 // Populate LeftoverRegs with the leftovers
572 for (unsigned I = UnmergeValues.size() - NumOfLeftoverVal;
573 I < UnmergeValues.size(); I++) {
574 LeftoverRegs.push_back(UnmergeValues[I]);
575 }
576 return true;
577 }
578 }
579 // Perform irregular split. Leftover is last element of RegPieces.
580 if (MainTy.isVector()) {
581 SmallVector<Register, 8> RegPieces;
582 extractVectorParts(Reg, MainTy.getNumElements(), RegPieces, MIRBuilder,
583 MRI);
584 for (unsigned i = 0; i < RegPieces.size() - 1; ++i)
585 VRegs.push_back(RegPieces[i]);
586 LeftoverRegs.push_back(RegPieces[RegPieces.size() - 1]);
587 LeftoverTy = MRI.getType(LeftoverRegs[0]);
588 return true;
589 }
590
591 LeftoverTy = LLT::scalar(LeftoverSize);
592 // For irregular sizes, extract the individual parts.
593 for (unsigned I = 0; I != NumParts; ++I) {
594 Register NewReg = MRI.createGenericVirtualRegister(MainTy);
595 VRegs.push_back(NewReg);
596 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
597 }
598
599 for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
600 Offset += LeftoverSize) {
601 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
602 LeftoverRegs.push_back(NewReg);
603 MIRBuilder.buildExtract(NewReg, Reg, Offset);
604 }
605
606 return true;
607}
608
609void llvm::extractVectorParts(Register Reg, unsigned NumElts,
611 MachineIRBuilder &MIRBuilder,
613 LLT RegTy = MRI.getType(Reg);
614 assert(RegTy.isVector() && "Expected a vector type");
615
616 LLT EltTy = RegTy.getElementType();
617 LLT NarrowTy = (NumElts == 1) ? EltTy : LLT::fixed_vector(NumElts, EltTy);
618 unsigned RegNumElts = RegTy.getNumElements();
619 unsigned LeftoverNumElts = RegNumElts % NumElts;
620 unsigned NumNarrowTyPieces = RegNumElts / NumElts;
621
622 // Perfect split without leftover
623 if (LeftoverNumElts == 0)
624 return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs, MIRBuilder,
625 MRI);
626
627 // Irregular split. Provide direct access to all elements for artifact
628 // combiner using unmerge to elements. Then build vectors with NumElts
629 // elements. Remaining element(s) will be (used to build vector) Leftover.
631 extractParts(Reg, EltTy, RegNumElts, Elts, MIRBuilder, MRI);
632
633 unsigned Offset = 0;
634 // Requested sub-vectors of NarrowTy.
635 for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) {
636 ArrayRef<Register> Pieces(&Elts[Offset], NumElts);
637 VRegs.push_back(MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0));
638 }
639
640 // Leftover element(s).
641 if (LeftoverNumElts == 1) {
642 VRegs.push_back(Elts[Offset]);
643 } else {
644 LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy);
645 ArrayRef<Register> Pieces(&Elts[Offset], LeftoverNumElts);
646 VRegs.push_back(
647 MIRBuilder.buildMergeLikeInstr(LeftoverTy, Pieces).getReg(0));
648 }
649}
650
652 const MachineRegisterInfo &MRI) {
654 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
655}
656
657APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
658 if (Size == 32)
659 return APFloat(float(Val));
660 if (Size == 64)
661 return APFloat(Val);
662 if (Size != 16)
663 llvm_unreachable("Unsupported FPConstant size");
664 bool Ignored;
665 APFloat APF(Val);
667 return APF;
668}
669
670std::optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode,
671 const Register Op1,
672 const Register Op2,
673 const MachineRegisterInfo &MRI) {
674 auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
675 if (!MaybeOp2Cst)
676 return std::nullopt;
677
678 auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
679 if (!MaybeOp1Cst)
680 return std::nullopt;
681
682 const APInt &C1 = MaybeOp1Cst->Value;
683 const APInt &C2 = MaybeOp2Cst->Value;
684 switch (Opcode) {
685 default:
686 break;
687 case TargetOpcode::G_ADD:
688 return C1 + C2;
689 case TargetOpcode::G_PTR_ADD:
690 // Types can be of different width here.
691 // Result needs to be the same width as C1, so trunc or sext C2.
692 return C1 + C2.sextOrTrunc(C1.getBitWidth());
693 case TargetOpcode::G_AND:
694 return C1 & C2;
695 case TargetOpcode::G_ASHR:
696 return C1.ashr(C2);
697 case TargetOpcode::G_LSHR:
698 return C1.lshr(C2);
699 case TargetOpcode::G_MUL:
700 return C1 * C2;
701 case TargetOpcode::G_OR:
702 return C1 | C2;
703 case TargetOpcode::G_SHL:
704 return C1 << C2;
705 case TargetOpcode::G_SUB:
706 return C1 - C2;
707 case TargetOpcode::G_XOR:
708 return C1 ^ C2;
709 case TargetOpcode::G_UDIV:
710 if (!C2.getBoolValue())
711 break;
712 return C1.udiv(C2);
713 case TargetOpcode::G_SDIV:
714 if (!C2.getBoolValue())
715 break;
716 return C1.sdiv(C2);
717 case TargetOpcode::G_UREM:
718 if (!C2.getBoolValue())
719 break;
720 return C1.urem(C2);
721 case TargetOpcode::G_SREM:
722 if (!C2.getBoolValue())
723 break;
724 return C1.srem(C2);
725 case TargetOpcode::G_SMIN:
726 return APIntOps::smin(C1, C2);
727 case TargetOpcode::G_SMAX:
728 return APIntOps::smax(C1, C2);
729 case TargetOpcode::G_UMIN:
730 return APIntOps::umin(C1, C2);
731 case TargetOpcode::G_UMAX:
732 return APIntOps::umax(C1, C2);
733 }
734
735 return std::nullopt;
736}
737
738std::optional<APFloat>
739llvm::ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
740 const Register Op2, const MachineRegisterInfo &MRI) {
741 const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
742 if (!Op2Cst)
743 return std::nullopt;
744
745 const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
746 if (!Op1Cst)
747 return std::nullopt;
748
749 APFloat C1 = Op1Cst->getValueAPF();
750 const APFloat &C2 = Op2Cst->getValueAPF();
751 switch (Opcode) {
752 case TargetOpcode::G_FADD:
754 return C1;
755 case TargetOpcode::G_FSUB:
757 return C1;
758 case TargetOpcode::G_FMUL:
760 return C1;
761 case TargetOpcode::G_FDIV:
763 return C1;
764 case TargetOpcode::G_FREM:
765 C1.mod(C2);
766 return C1;
767 case TargetOpcode::G_FCOPYSIGN:
768 C1.copySign(C2);
769 return C1;
770 case TargetOpcode::G_FMINNUM:
771 return minnum(C1, C2);
772 case TargetOpcode::G_FMAXNUM:
773 return maxnum(C1, C2);
774 case TargetOpcode::G_FMINIMUM:
775 return minimum(C1, C2);
776 case TargetOpcode::G_FMAXIMUM:
777 return maximum(C1, C2);
778 case TargetOpcode::G_FMINNUM_IEEE:
779 case TargetOpcode::G_FMAXNUM_IEEE:
780 // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
781 // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
782 // and currently there isn't a nice wrapper in APFloat for the version with
783 // correct snan handling.
784 break;
785 default:
786 break;
787 }
788
789 return std::nullopt;
790}
791
793llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
794 const Register Op2,
795 const MachineRegisterInfo &MRI) {
796 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
797 if (!SrcVec2)
798 return SmallVector<APInt>();
799
800 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
801 if (!SrcVec1)
802 return SmallVector<APInt>();
803
804 SmallVector<APInt> FoldedElements;
805 for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
806 auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
807 SrcVec2->getSourceReg(Idx), MRI);
808 if (!MaybeCst)
809 return SmallVector<APInt>();
810 FoldedElements.push_back(*MaybeCst);
811 }
812 return FoldedElements;
813}
814
816 bool SNaN) {
817 const MachineInstr *DefMI = MRI.getVRegDef(Val);
818 if (!DefMI)
819 return false;
820
821 if (DefMI->getFlag(MachineInstr::FmNoNans))
822 return true;
823
824 // If the value is a constant, we can obviously see if it is a NaN or not.
825 if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
826 return !FPVal->getValueAPF().isNaN() ||
827 (SNaN && !FPVal->getValueAPF().isSignaling());
828 }
829
830 if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
831 for (const auto &Op : DefMI->uses())
832 if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
833 return false;
834 return true;
835 }
836
837 switch (DefMI->getOpcode()) {
838 default:
839 break;
840 case TargetOpcode::G_FADD:
841 case TargetOpcode::G_FSUB:
842 case TargetOpcode::G_FMUL:
843 case TargetOpcode::G_FDIV:
844 case TargetOpcode::G_FREM:
845 case TargetOpcode::G_FSIN:
846 case TargetOpcode::G_FCOS:
847 case TargetOpcode::G_FTAN:
848 case TargetOpcode::G_FACOS:
849 case TargetOpcode::G_FASIN:
850 case TargetOpcode::G_FATAN:
851 case TargetOpcode::G_FATAN2:
852 case TargetOpcode::G_FCOSH:
853 case TargetOpcode::G_FSINH:
854 case TargetOpcode::G_FTANH:
855 case TargetOpcode::G_FMA:
856 case TargetOpcode::G_FMAD:
857 if (SNaN)
858 return true;
859
860 // TODO: Need isKnownNeverInfinity
861 return false;
862 case TargetOpcode::G_FMINNUM_IEEE:
863 case TargetOpcode::G_FMAXNUM_IEEE: {
864 if (SNaN)
865 return true;
866 // This can return a NaN if either operand is an sNaN, or if both operands
867 // are NaN.
868 return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
869 isKnownNeverSNaN(DefMI->getOperand(2).getReg(), MRI)) ||
870 (isKnownNeverSNaN(DefMI->getOperand(1).getReg(), MRI) &&
871 isKnownNeverNaN(DefMI->getOperand(2).getReg(), MRI));
872 }
873 case TargetOpcode::G_FMINNUM:
874 case TargetOpcode::G_FMAXNUM: {
875 // Only one needs to be known not-nan, since it will be returned if the
876 // other ends up being one.
877 return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
878 isKnownNeverNaN(DefMI->getOperand(2).getReg(), MRI, SNaN);
879 }
880 }
881
882 if (SNaN) {
883 // FP operations quiet. For now, just handle the ones inserted during
884 // legalization.
885 switch (DefMI->getOpcode()) {
886 case TargetOpcode::G_FPEXT:
887 case TargetOpcode::G_FPTRUNC:
888 case TargetOpcode::G_FCANONICALIZE:
889 return true;
890 default:
891 return false;
892 }
893 }
894
895 return false;
896}
897
899 const MachinePointerInfo &MPO) {
902 MachineFrameInfo &MFI = MF.getFrameInfo();
903 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
904 MPO.Offset);
905 }
906
907 if (const Value *V = dyn_cast_if_present<const Value *>(MPO.V)) {
908 const Module *M = MF.getFunction().getParent();
909 return V->getPointerAlignment(M->getDataLayout());
910 }
911
912 return Align(1);
913}
914
916 const TargetInstrInfo &TII,
917 MCRegister PhysReg,
918 const TargetRegisterClass &RC,
919 const DebugLoc &DL, LLT RegTy) {
920 MachineBasicBlock &EntryMBB = MF.front();
922 Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
923 if (LiveIn) {
924 MachineInstr *Def = MRI.getVRegDef(LiveIn);
925 if (Def) {
926 // FIXME: Should the verifier check this is in the entry block?
927 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
928 return LiveIn;
929 }
930
931 // It's possible the incoming argument register and copy was added during
932 // lowering, but later deleted due to being/becoming dead. If this happens,
933 // re-insert the copy.
934 } else {
935 // The live in register was not present, so add it.
936 LiveIn = MF.addLiveIn(PhysReg, &RC);
937 if (RegTy.isValid())
938 MRI.setType(LiveIn, RegTy);
939 }
940
941 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
942 .addReg(PhysReg);
943 if (!EntryMBB.isLiveIn(PhysReg))
944 EntryMBB.addLiveIn(PhysReg);
945 return LiveIn;
946}
947
948std::optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode,
949 const Register Op1, uint64_t Imm,
950 const MachineRegisterInfo &MRI) {
951 auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
952 if (MaybeOp1Cst) {
953 switch (Opcode) {
954 default:
955 break;
956 case TargetOpcode::G_SEXT_INREG: {
957 LLT Ty = MRI.getType(Op1);
958 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
959 }
960 }
961 }
962 return std::nullopt;
963}
964
965std::optional<APInt> llvm::ConstantFoldCastOp(unsigned Opcode, LLT DstTy,
966 const Register Op0,
967 const MachineRegisterInfo &MRI) {
968 std::optional<APInt> Val = getIConstantVRegVal(Op0, MRI);
969 if (!Val)
970 return Val;
971
972 const unsigned DstSize = DstTy.getScalarSizeInBits();
973
974 switch (Opcode) {
975 case TargetOpcode::G_SEXT:
976 return Val->sext(DstSize);
977 case TargetOpcode::G_ZEXT:
978 case TargetOpcode::G_ANYEXT:
979 // TODO: DAG considers target preference when constant folding any_extend.
980 return Val->zext(DstSize);
981 default:
982 break;
983 }
984
985 llvm_unreachable("unexpected cast opcode to constant fold");
986}
987
988std::optional<APFloat>
989llvm::ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
990 const MachineRegisterInfo &MRI) {
991 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
992 if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
993 APFloat DstVal(getFltSemanticForLLT(DstTy));
994 DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
996 return DstVal;
997 }
998 return std::nullopt;
999}
1000
1001std::optional<SmallVector<unsigned>>
1003 std::function<unsigned(APInt)> CB) {
1004 LLT Ty = MRI.getType(Src);
1005 SmallVector<unsigned> FoldedCTLZs;
1006 auto tryFoldScalar = [&](Register R) -> std::optional<unsigned> {
1007 auto MaybeCst = getIConstantVRegVal(R, MRI);
1008 if (!MaybeCst)
1009 return std::nullopt;
1010 return CB(*MaybeCst);
1011 };
1012 if (Ty.isVector()) {
1013 // Try to constant fold each element.
1014 auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
1015 if (!BV)
1016 return std::nullopt;
1017 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1018 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
1019 FoldedCTLZs.emplace_back(*MaybeFold);
1020 continue;
1021 }
1022 return std::nullopt;
1023 }
1024 return FoldedCTLZs;
1025 }
1026 if (auto MaybeCst = tryFoldScalar(Src)) {
1027 FoldedCTLZs.emplace_back(*MaybeCst);
1028 return FoldedCTLZs;
1029 }
1030 return std::nullopt;
1031}
1032
1033std::optional<SmallVector<APInt>>
1034llvm::ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2,
1035 unsigned DstScalarSizeInBits, unsigned ExtOp,
1036 const MachineRegisterInfo &MRI) {
1037 assert(ExtOp == TargetOpcode::G_SEXT || ExtOp == TargetOpcode::G_ZEXT ||
1038 ExtOp == TargetOpcode::G_ANYEXT);
1039
1040 const LLT Ty = MRI.getType(Op1);
1041
1042 auto GetICmpResultCst = [&](bool IsTrue) {
1043 if (IsTrue)
1044 return ExtOp == TargetOpcode::G_SEXT
1045 ? APInt::getAllOnes(DstScalarSizeInBits)
1046 : APInt::getOneBitSet(DstScalarSizeInBits, 0);
1047 return APInt::getZero(DstScalarSizeInBits);
1048 };
1049
1050 auto TryFoldScalar = [&](Register LHS, Register RHS) -> std::optional<APInt> {
1051 auto RHSCst = getIConstantVRegVal(RHS, MRI);
1052 if (!RHSCst)
1053 return std::nullopt;
1054 auto LHSCst = getIConstantVRegVal(LHS, MRI);
1055 if (!LHSCst)
1056 return std::nullopt;
1057
1058 switch (Pred) {
1060 return GetICmpResultCst(LHSCst->eq(*RHSCst));
1062 return GetICmpResultCst(LHSCst->ne(*RHSCst));
1064 return GetICmpResultCst(LHSCst->ugt(*RHSCst));
1066 return GetICmpResultCst(LHSCst->uge(*RHSCst));
1068 return GetICmpResultCst(LHSCst->ult(*RHSCst));
1070 return GetICmpResultCst(LHSCst->ule(*RHSCst));
1072 return GetICmpResultCst(LHSCst->sgt(*RHSCst));
1074 return GetICmpResultCst(LHSCst->sge(*RHSCst));
1076 return GetICmpResultCst(LHSCst->slt(*RHSCst));
1078 return GetICmpResultCst(LHSCst->sle(*RHSCst));
1079 default:
1080 return std::nullopt;
1081 }
1082 };
1083
1084 SmallVector<APInt> FoldedICmps;
1085
1086 if (Ty.isVector()) {
1087 // Try to constant fold each element.
1088 auto *BV1 = getOpcodeDef<GBuildVector>(Op1, MRI);
1089 auto *BV2 = getOpcodeDef<GBuildVector>(Op2, MRI);
1090 if (!BV1 || !BV2)
1091 return std::nullopt;
1092 assert(BV1->getNumSources() == BV2->getNumSources() && "Invalid vectors");
1093 for (unsigned I = 0; I < BV1->getNumSources(); ++I) {
1094 if (auto MaybeFold =
1095 TryFoldScalar(BV1->getSourceReg(I), BV2->getSourceReg(I))) {
1096 FoldedICmps.emplace_back(*MaybeFold);
1097 continue;
1098 }
1099 return std::nullopt;
1100 }
1101 return FoldedICmps;
1102 }
1103
1104 if (auto MaybeCst = TryFoldScalar(Op1, Op2)) {
1105 FoldedICmps.emplace_back(*MaybeCst);
1106 return FoldedICmps;
1107 }
1108
1109 return std::nullopt;
1110}
1111
1113 GISelValueTracking *VT) {
1114 std::optional<DefinitionAndSourceRegister> DefSrcReg =
1116 if (!DefSrcReg)
1117 return false;
1118
1119 const MachineInstr &MI = *DefSrcReg->MI;
1120 const LLT Ty = MRI.getType(Reg);
1121
1122 switch (MI.getOpcode()) {
1123 case TargetOpcode::G_CONSTANT: {
1124 unsigned BitWidth = Ty.getScalarSizeInBits();
1125 const ConstantInt *CI = MI.getOperand(1).getCImm();
1126 return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
1127 }
1128 case TargetOpcode::G_SHL: {
1129 // A left-shift of a constant one will have exactly one bit set because
1130 // shifting the bit off the end is undefined.
1131
1132 // TODO: Constant splat
1133 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
1134 if (*ConstLHS == 1)
1135 return true;
1136 }
1137
1138 break;
1139 }
1140 case TargetOpcode::G_LSHR: {
1141 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
1142 if (ConstLHS->isSignMask())
1143 return true;
1144 }
1145
1146 break;
1147 }
1148 case TargetOpcode::G_BUILD_VECTOR: {
1149 // TODO: Probably should have a recursion depth guard since you could have
1150 // bitcasted vector elements.
1151 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
1152 if (!isKnownToBeAPowerOfTwo(MO.getReg(), MRI, VT))
1153 return false;
1154
1155 return true;
1156 }
1157 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1158 // Only handle constants since we would need to know if number of leading
1159 // zeros is greater than the truncation amount.
1160 const unsigned BitWidth = Ty.getScalarSizeInBits();
1161 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
1162 auto Const = getIConstantVRegVal(MO.getReg(), MRI);
1163 if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
1164 return false;
1165 }
1166
1167 return true;
1168 }
1169 default:
1170 break;
1171 }
1172
1173 if (!VT)
1174 return false;
1175
1176 // More could be done here, though the above checks are enough
1177 // to handle some common cases.
1178
1179 // Fall back to computeKnownBits to catch other known cases.
1180 KnownBits Known = VT->getKnownBits(Reg);
1181 return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
1182}
1183
1187
1188LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
1189 if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits())
1190 return OrigTy;
1191
1192 if (OrigTy.isVector() && TargetTy.isVector()) {
1193 LLT OrigElt = OrigTy.getElementType();
1194 LLT TargetElt = TargetTy.getElementType();
1195
1196 // TODO: The docstring for this function says the intention is to use this
1197 // function to build MERGE/UNMERGE instructions. It won't be the case that
1198 // we generate a MERGE/UNMERGE between fixed and scalable vector types. We
1199 // could implement getLCMType between the two in the future if there was a
1200 // need, but it is not worth it now as this function should not be used in
1201 // that way.
1202 assert(((OrigTy.isScalableVector() && !TargetTy.isFixedVector()) ||
1203 (OrigTy.isFixedVector() && !TargetTy.isScalableVector())) &&
1204 "getLCMType not implemented between fixed and scalable vectors.");
1205
1206 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
1207 int GCDMinElts = std::gcd(OrigTy.getElementCount().getKnownMinValue(),
1208 TargetTy.getElementCount().getKnownMinValue());
1209 // Prefer the original element type.
1211 TargetTy.getElementCount().getKnownMinValue());
1212 return LLT::vector(Mul.divideCoefficientBy(GCDMinElts),
1213 OrigTy.getElementType());
1214 }
1215 unsigned LCM = std::lcm(OrigTy.getSizeInBits().getKnownMinValue(),
1216 TargetTy.getSizeInBits().getKnownMinValue());
1217 return LLT::vector(
1218 ElementCount::get(LCM / OrigElt.getSizeInBits(), OrigTy.isScalable()),
1219 OrigElt);
1220 }
1221
1222 // One type is scalar, one type is vector
1223 if (OrigTy.isVector() || TargetTy.isVector()) {
1224 LLT VecTy = OrigTy.isVector() ? OrigTy : TargetTy;
1225 LLT ScalarTy = OrigTy.isVector() ? TargetTy : OrigTy;
1226 LLT EltTy = VecTy.getElementType();
1227 LLT OrigEltTy = OrigTy.isVector() ? OrigTy.getElementType() : OrigTy;
1228
1229 // Prefer scalar type from OrigTy.
1230 if (EltTy.getSizeInBits() == ScalarTy.getSizeInBits())
1231 return LLT::vector(VecTy.getElementCount(), OrigEltTy);
1232
1233 // Different size scalars. Create vector with the same total size.
1234 // LCM will take fixed/scalable from VecTy.
1235 unsigned LCM = std::lcm(EltTy.getSizeInBits().getFixedValue() *
1237 ScalarTy.getSizeInBits().getFixedValue());
1238 // Prefer type from OrigTy
1239 return LLT::vector(ElementCount::get(LCM / OrigEltTy.getSizeInBits(),
1240 VecTy.getElementCount().isScalable()),
1241 OrigEltTy);
1242 }
1243
1244 // At this point, both types are scalars of different size
1245 unsigned LCM = std::lcm(OrigTy.getSizeInBits().getFixedValue(),
1246 TargetTy.getSizeInBits().getFixedValue());
1247 // Preserve pointer types.
1248 if (LCM == OrigTy.getSizeInBits())
1249 return OrigTy;
1250 if (LCM == TargetTy.getSizeInBits())
1251 return TargetTy;
1252 return LLT::scalar(LCM);
1253}
1254
1255LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
1256
1257 if ((OrigTy.isScalableVector() && TargetTy.isFixedVector()) ||
1258 (OrigTy.isFixedVector() && TargetTy.isScalableVector()))
1260 "getCoverTy not implemented between fixed and scalable vectors.");
1261
1262 if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
1263 (OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
1264 return getLCMType(OrigTy, TargetTy);
1265
1266 unsigned OrigTyNumElts = OrigTy.getElementCount().getKnownMinValue();
1267 unsigned TargetTyNumElts = TargetTy.getElementCount().getKnownMinValue();
1268 if (OrigTyNumElts % TargetTyNumElts == 0)
1269 return OrigTy;
1270
1271 unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);
1273 OrigTy.getElementType());
1274}
1275
1276LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
1277 if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits())
1278 return OrigTy;
1279
1280 if (OrigTy.isVector() && TargetTy.isVector()) {
1281 LLT OrigElt = OrigTy.getElementType();
1282
1283 // TODO: The docstring for this function says the intention is to use this
1284 // function to build MERGE/UNMERGE instructions. It won't be the case that
1285 // we generate a MERGE/UNMERGE between fixed and scalable vector types. We
1286 // could implement getGCDType between the two in the future if there was a
1287 // need, but it is not worth it now as this function should not be used in
1288 // that way.
1289 assert(((OrigTy.isScalableVector() && !TargetTy.isFixedVector()) ||
1290 (OrigTy.isFixedVector() && !TargetTy.isScalableVector())) &&
1291 "getGCDType not implemented between fixed and scalable vectors.");
1292
1293 unsigned GCD = std::gcd(OrigTy.getSizeInBits().getKnownMinValue(),
1294 TargetTy.getSizeInBits().getKnownMinValue());
1295 if (GCD == OrigElt.getSizeInBits())
1297 OrigElt);
1298
1299 // Cannot produce original element type, but both have vscale in common.
1300 if (GCD < OrigElt.getSizeInBits())
1302 GCD);
1303
1304 return LLT::vector(
1306 OrigTy.isScalable()),
1307 OrigElt);
1308 }
1309
1310 // If one type is vector and the element size matches the scalar size, then
1311 // the gcd is the scalar type.
1312 if (OrigTy.isVector() &&
1313 OrigTy.getElementType().getSizeInBits() == TargetTy.getSizeInBits())
1314 return OrigTy.getElementType();
1315 if (TargetTy.isVector() &&
1316 TargetTy.getElementType().getSizeInBits() == OrigTy.getSizeInBits())
1317 return OrigTy;
1318
1319 // At this point, both types are either scalars of different type or one is a
1320 // vector and one is a scalar. If both types are scalars, the GCD type is the
1321 // GCD between the two scalar sizes. If one is vector and one is scalar, then
1322 // the GCD type is the GCD between the scalar and the vector element size.
1323 LLT OrigScalar = OrigTy.getScalarType();
1324 LLT TargetScalar = TargetTy.getScalarType();
1325 unsigned GCD = std::gcd(OrigScalar.getSizeInBits().getFixedValue(),
1326 TargetScalar.getSizeInBits().getFixedValue());
1327 return LLT::scalar(GCD);
1328}
1329
1331 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1332 "Only G_SHUFFLE_VECTOR can have a splat index!");
1333 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
1334 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
1335
1336 // If all elements are undefined, this shuffle can be considered a splat.
1337 // Return 0 for better potential for callers to simplify.
1338 if (FirstDefinedIdx == Mask.end())
1339 return 0;
1340
1341 // Make sure all remaining elements are either undef or the same
1342 // as the first non-undef value.
1343 int SplatValue = *FirstDefinedIdx;
1344 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
1345 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1346 return std::nullopt;
1347
1348 return SplatValue;
1349}
1350
1351static bool isBuildVectorOp(unsigned Opcode) {
1352 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1353 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1354}
1355
1356namespace {
1357
1358std::optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
1359 const MachineRegisterInfo &MRI,
1360 bool AllowUndef) {
1362 if (!MI)
1363 return std::nullopt;
1364
1365 bool isConcatVectorsOp = MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1366 if (!isBuildVectorOp(MI->getOpcode()) && !isConcatVectorsOp)
1367 return std::nullopt;
1368
1369 std::optional<ValueAndVReg> SplatValAndReg;
1370 for (MachineOperand &Op : MI->uses()) {
1371 Register Element = Op.getReg();
1372 // If we have a G_CONCAT_VECTOR, we recursively look into the
1373 // vectors that we're concatenating to see if they're splats.
1374 auto ElementValAndReg =
1375 isConcatVectorsOp
1376 ? getAnyConstantSplat(Element, MRI, AllowUndef)
1378
1379 // If AllowUndef, treat undef as value that will result in a constant splat.
1380 if (!ElementValAndReg) {
1381 if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1382 continue;
1383 return std::nullopt;
1384 }
1385
1386 // Record splat value
1387 if (!SplatValAndReg)
1388 SplatValAndReg = ElementValAndReg;
1389
1390 // Different constant than the one already recorded, not a constant splat.
1391 if (SplatValAndReg->Value != ElementValAndReg->Value)
1392 return std::nullopt;
1393 }
1394
1395 return SplatValAndReg;
1396}
1397
1398} // end anonymous namespace
1399
1401 const MachineRegisterInfo &MRI,
1402 int64_t SplatValue, bool AllowUndef) {
1403 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
1404 return SplatValAndReg->Value.getSExtValue() == SplatValue;
1405
1406 return false;
1407}
1408
1410 const MachineRegisterInfo &MRI,
1411 const APInt &SplatValue,
1412 bool AllowUndef) {
1413 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef)) {
1414 if (SplatValAndReg->Value.getBitWidth() < SplatValue.getBitWidth())
1415 return APInt::isSameValue(
1416 SplatValAndReg->Value.sext(SplatValue.getBitWidth()), SplatValue);
1417 return APInt::isSameValue(
1418 SplatValAndReg->Value,
1419 SplatValue.sext(SplatValAndReg->Value.getBitWidth()));
1420 }
1421
1422 return false;
1423}
1424
1426 const MachineRegisterInfo &MRI,
1427 int64_t SplatValue, bool AllowUndef) {
1428 return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1429 AllowUndef);
1430}
1431
1433 const MachineRegisterInfo &MRI,
1434 const APInt &SplatValue,
1435 bool AllowUndef) {
1436 return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1437 AllowUndef);
1438}
1439
1440std::optional<APInt>
1442 if (auto SplatValAndReg =
1443 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false)) {
1444 if (std::optional<ValueAndVReg> ValAndVReg =
1445 getIConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI))
1446 return ValAndVReg->Value;
1447 }
1448
1449 return std::nullopt;
1450}
1451
1452std::optional<APInt>
1454 const MachineRegisterInfo &MRI) {
1455 return getIConstantSplatVal(MI.getOperand(0).getReg(), MRI);
1456}
1457
1458std::optional<int64_t>
1460 const MachineRegisterInfo &MRI) {
1461 if (auto SplatValAndReg =
1462 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false))
1463 return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1464 return std::nullopt;
1465}
1466
1467std::optional<int64_t>
1469 const MachineRegisterInfo &MRI) {
1470 return getIConstantSplatSExtVal(MI.getOperand(0).getReg(), MRI);
1471}
1472
1473std::optional<FPValueAndVReg>
1475 bool AllowUndef) {
1476 if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1477 return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1478 return std::nullopt;
1479}
1480
1482 const MachineRegisterInfo &MRI,
1483 bool AllowUndef) {
1484 return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1485}
1486
1488 const MachineRegisterInfo &MRI,
1489 bool AllowUndef) {
1490 return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1491}
1492
1493std::optional<RegOrConstant>
1495 unsigned Opc = MI.getOpcode();
1496 if (!isBuildVectorOp(Opc))
1497 return std::nullopt;
1498 if (auto Splat = getIConstantSplatSExtVal(MI, MRI))
1499 return RegOrConstant(*Splat);
1500 auto Reg = MI.getOperand(1).getReg();
1501 if (any_of(drop_begin(MI.operands(), 2),
1502 [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1503 return std::nullopt;
1504 return RegOrConstant(Reg);
1505}
1506
1508 const MachineRegisterInfo &MRI,
1509 bool AllowFP = true,
1510 bool AllowOpaqueConstants = true) {
1511 switch (MI.getOpcode()) {
1512 case TargetOpcode::G_CONSTANT:
1513 case TargetOpcode::G_IMPLICIT_DEF:
1514 return true;
1515 case TargetOpcode::G_FCONSTANT:
1516 return AllowFP;
1517 case TargetOpcode::G_GLOBAL_VALUE:
1518 case TargetOpcode::G_FRAME_INDEX:
1519 case TargetOpcode::G_BLOCK_ADDR:
1520 case TargetOpcode::G_JUMP_TABLE:
1521 return AllowOpaqueConstants;
1522 default:
1523 return false;
1524 }
1525}
1526
1528 const MachineRegisterInfo &MRI) {
1529 Register Def = MI.getOperand(0).getReg();
1530 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1531 return true;
1533 if (!BV)
1534 return false;
1535 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1538 continue;
1539 return false;
1540 }
1541 return true;
1542}
1543
1545 const MachineRegisterInfo &MRI,
1546 bool AllowFP, bool AllowOpaqueConstants) {
1547 if (isConstantScalar(MI, MRI, AllowFP, AllowOpaqueConstants))
1548 return true;
1549
1550 if (!isBuildVectorOp(MI.getOpcode()))
1551 return false;
1552
1553 const unsigned NumOps = MI.getNumOperands();
1554 for (unsigned I = 1; I != NumOps; ++I) {
1555 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg());
1556 if (!isConstantScalar(*ElementDef, MRI, AllowFP, AllowOpaqueConstants))
1557 return false;
1558 }
1559
1560 return true;
1561}
1562
1563std::optional<APInt>
1565 const MachineRegisterInfo &MRI) {
1566 Register Def = MI.getOperand(0).getReg();
1567 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1568 return C->Value;
1569 auto MaybeCst = getIConstantSplatSExtVal(MI, MRI);
1570 if (!MaybeCst)
1571 return std::nullopt;
1572 const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1573 return APInt(ScalarSize, *MaybeCst, true);
1574}
1575
1576std::optional<APFloat>
1578 const MachineRegisterInfo &MRI) {
1579 Register Def = MI.getOperand(0).getReg();
1580 if (auto FpConst = getFConstantVRegValWithLookThrough(Def, MRI))
1581 return FpConst->Value;
1582 auto MaybeCstFP = getFConstantSplat(Def, MRI, /*allowUndef=*/false);
1583 if (!MaybeCstFP)
1584 return std::nullopt;
1585 return MaybeCstFP->Value;
1586}
1587
1589 const MachineRegisterInfo &MRI, bool AllowUndefs) {
1590 switch (MI.getOpcode()) {
1591 case TargetOpcode::G_IMPLICIT_DEF:
1592 return AllowUndefs;
1593 case TargetOpcode::G_CONSTANT:
1594 return MI.getOperand(1).getCImm()->isNullValue();
1595 case TargetOpcode::G_FCONSTANT: {
1596 const ConstantFP *FPImm = MI.getOperand(1).getFPImm();
1597 return FPImm->isZero() && !FPImm->isNegative();
1598 }
1599 default:
1600 if (!AllowUndefs) // TODO: isBuildVectorAllZeros assumes undef is OK already
1601 return false;
1602 return isBuildVectorAllZeros(MI, MRI);
1603 }
1604}
1605
1607 const MachineRegisterInfo &MRI,
1608 bool AllowUndefs) {
1609 switch (MI.getOpcode()) {
1610 case TargetOpcode::G_IMPLICIT_DEF:
1611 return AllowUndefs;
1612 case TargetOpcode::G_CONSTANT:
1613 return MI.getOperand(1).getCImm()->isAllOnesValue();
1614 default:
1615 if (!AllowUndefs) // TODO: isBuildVectorAllOnes assumes undef is OK already
1616 return false;
1617 return isBuildVectorAllOnes(MI, MRI);
1618 }
1619}
1620
1622 const MachineRegisterInfo &MRI, Register Reg,
1623 std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1624
1625 const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
1626 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1627 return Match(nullptr);
1628
1629 // TODO: Also handle fconstant
1630 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1631 return Match(Def->getOperand(1).getCImm());
1632
1633 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1634 return false;
1635
1636 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1637 Register SrcElt = Def->getOperand(I).getReg();
1638 const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1639 if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1640 if (!Match(nullptr))
1641 return false;
1642 continue;
1643 }
1644
1645 if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1646 !Match(SrcDef->getOperand(1).getCImm()))
1647 return false;
1648 }
1649
1650 return true;
1651}
1652
1653bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1654 bool IsFP) {
1655 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1657 return Val & 0x1;
1659 return Val == 1;
1661 return Val == -1;
1662 }
1663 llvm_unreachable("Invalid boolean contents");
1664}
1665
1666bool llvm::isConstFalseVal(const TargetLowering &TLI, int64_t Val,
1667 bool IsVector, bool IsFP) {
1668 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1670 return ~Val & 0x1;
1673 return Val == 0;
1674 }
1675 llvm_unreachable("Invalid boolean contents");
1676}
1677
1678int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1679 bool IsFP) {
1680 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1683 return 1;
1685 return -1;
1686 }
1687 llvm_unreachable("Invalid boolean contents");
1688}
1689
1691 LostDebugLocObserver *LocObserver,
1692 SmallInstListTy &DeadInstChain) {
1693 for (MachineOperand &Op : MI.uses()) {
1694 if (Op.isReg() && Op.getReg().isVirtual())
1695 DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1696 }
1697 LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1698 DeadInstChain.remove(&MI);
1699 MI.eraseFromParent();
1700 if (LocObserver)
1701 LocObserver->checkpoint(false);
1702}
1703
1706 LostDebugLocObserver *LocObserver) {
1707 SmallInstListTy DeadInstChain;
1708 for (MachineInstr *MI : DeadInstrs)
1709 saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1710
1711 while (!DeadInstChain.empty()) {
1712 MachineInstr *Inst = DeadInstChain.pop_back_val();
1713 if (!isTriviallyDead(*Inst, MRI))
1714 continue;
1715 saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1716 }
1717}
1718
1720 LostDebugLocObserver *LocObserver) {
1721 return eraseInstrs({&MI}, MRI, LocObserver);
1722}
1723
1725 for (auto &Def : MI.defs()) {
1726 assert(Def.isReg() && "Must be a reg");
1727
1729 for (auto &MOUse : MRI.use_operands(Def.getReg())) {
1730 MachineInstr *DbgValue = MOUse.getParent();
1731 // Ignore partially formed DBG_VALUEs.
1732 if (DbgValue->isNonListDebugValue() && DbgValue->getNumOperands() == 4) {
1733 DbgUsers.push_back(&MOUse);
1734 }
1735 }
1736
1737 if (!DbgUsers.empty()) {
1739 }
1740 }
1741}
1742
1744 switch (Opc) {
1745 case TargetOpcode::G_FABS:
1746 case TargetOpcode::G_FADD:
1747 case TargetOpcode::G_FCANONICALIZE:
1748 case TargetOpcode::G_FCEIL:
1749 case TargetOpcode::G_FCONSTANT:
1750 case TargetOpcode::G_FCOPYSIGN:
1751 case TargetOpcode::G_FCOS:
1752 case TargetOpcode::G_FDIV:
1753 case TargetOpcode::G_FEXP2:
1754 case TargetOpcode::G_FEXP:
1755 case TargetOpcode::G_FFLOOR:
1756 case TargetOpcode::G_FLOG10:
1757 case TargetOpcode::G_FLOG2:
1758 case TargetOpcode::G_FLOG:
1759 case TargetOpcode::G_FMA:
1760 case TargetOpcode::G_FMAD:
1761 case TargetOpcode::G_FMAXIMUM:
1762 case TargetOpcode::G_FMAXIMUMNUM:
1763 case TargetOpcode::G_FMAXNUM:
1764 case TargetOpcode::G_FMAXNUM_IEEE:
1765 case TargetOpcode::G_FMINIMUM:
1766 case TargetOpcode::G_FMINIMUMNUM:
1767 case TargetOpcode::G_FMINNUM:
1768 case TargetOpcode::G_FMINNUM_IEEE:
1769 case TargetOpcode::G_FMUL:
1770 case TargetOpcode::G_FNEARBYINT:
1771 case TargetOpcode::G_FNEG:
1772 case TargetOpcode::G_FPEXT:
1773 case TargetOpcode::G_FPOW:
1774 case TargetOpcode::G_FPTRUNC:
1775 case TargetOpcode::G_FREM:
1776 case TargetOpcode::G_FRINT:
1777 case TargetOpcode::G_FSIN:
1778 case TargetOpcode::G_FTAN:
1779 case TargetOpcode::G_FACOS:
1780 case TargetOpcode::G_FASIN:
1781 case TargetOpcode::G_FATAN:
1782 case TargetOpcode::G_FATAN2:
1783 case TargetOpcode::G_FCOSH:
1784 case TargetOpcode::G_FSINH:
1785 case TargetOpcode::G_FTANH:
1786 case TargetOpcode::G_FSQRT:
1787 case TargetOpcode::G_FSUB:
1788 case TargetOpcode::G_INTRINSIC_ROUND:
1789 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
1790 case TargetOpcode::G_INTRINSIC_TRUNC:
1791 return true;
1792 default:
1793 return false;
1794 }
1795}
1796
1797/// Shifts return poison if shiftwidth is larger than the bitwidth.
1798static bool shiftAmountKnownInRange(Register ShiftAmount,
1799 const MachineRegisterInfo &MRI) {
1800 LLT Ty = MRI.getType(ShiftAmount);
1801
1802 if (Ty.isScalableVector())
1803 return false; // Can't tell, just return false to be safe
1804
1805 if (Ty.isScalar()) {
1806 std::optional<ValueAndVReg> Val =
1808 if (!Val)
1809 return false;
1810 return Val->Value.ult(Ty.getScalarSizeInBits());
1811 }
1812
1813 GBuildVector *BV = getOpcodeDef<GBuildVector>(ShiftAmount, MRI);
1814 if (!BV)
1815 return false;
1816
1817 unsigned Sources = BV->getNumSources();
1818 for (unsigned I = 0; I < Sources; ++I) {
1819 std::optional<ValueAndVReg> Val =
1821 if (!Val)
1822 return false;
1823 if (!Val->Value.ult(Ty.getScalarSizeInBits()))
1824 return false;
1825 }
1826
1827 return true;
1828}
1829
1830namespace {
1831enum class UndefPoisonKind {
1832 PoisonOnly = (1 << 0),
1833 UndefOnly = (1 << 1),
1835};
1836}
1837
1839 return (unsigned(Kind) & unsigned(UndefPoisonKind::PoisonOnly)) != 0;
1840}
1841
1843 return (unsigned(Kind) & unsigned(UndefPoisonKind::UndefOnly)) != 0;
1844}
1845
1847 bool ConsiderFlagsAndMetadata,
1848 UndefPoisonKind Kind) {
1849 MachineInstr *RegDef = MRI.getVRegDef(Reg);
1850
1851 if (ConsiderFlagsAndMetadata && includesPoison(Kind))
1852 if (auto *GMI = dyn_cast<GenericMachineInstr>(RegDef))
1853 if (GMI->hasPoisonGeneratingFlags())
1854 return true;
1855
1856 // Check whether opcode is a poison/undef-generating operation.
1857 switch (RegDef->getOpcode()) {
1858 case TargetOpcode::G_BUILD_VECTOR:
1859 case TargetOpcode::G_CONSTANT_FOLD_BARRIER:
1860 return false;
1861 case TargetOpcode::G_SHL:
1862 case TargetOpcode::G_ASHR:
1863 case TargetOpcode::G_LSHR:
1864 return includesPoison(Kind) &&
1866 case TargetOpcode::G_FPTOSI:
1867 case TargetOpcode::G_FPTOUI:
1868 // fptosi/ui yields poison if the resulting value does not fit in the
1869 // destination type.
1870 return true;
1871 case TargetOpcode::G_CTLZ:
1872 case TargetOpcode::G_CTTZ:
1873 case TargetOpcode::G_ABS:
1874 case TargetOpcode::G_CTPOP:
1875 case TargetOpcode::G_BSWAP:
1876 case TargetOpcode::G_BITREVERSE:
1877 case TargetOpcode::G_FSHL:
1878 case TargetOpcode::G_FSHR:
1879 case TargetOpcode::G_SMAX:
1880 case TargetOpcode::G_SMIN:
1881 case TargetOpcode::G_SCMP:
1882 case TargetOpcode::G_UMAX:
1883 case TargetOpcode::G_UMIN:
1884 case TargetOpcode::G_UCMP:
1885 case TargetOpcode::G_PTRMASK:
1886 case TargetOpcode::G_SADDO:
1887 case TargetOpcode::G_SSUBO:
1888 case TargetOpcode::G_UADDO:
1889 case TargetOpcode::G_USUBO:
1890 case TargetOpcode::G_SMULO:
1891 case TargetOpcode::G_UMULO:
1892 case TargetOpcode::G_SADDSAT:
1893 case TargetOpcode::G_UADDSAT:
1894 case TargetOpcode::G_SSUBSAT:
1895 case TargetOpcode::G_USUBSAT:
1896 return false;
1897 case TargetOpcode::G_SSHLSAT:
1898 case TargetOpcode::G_USHLSAT:
1899 return includesPoison(Kind) &&
1901 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1903 if (includesPoison(Kind)) {
1904 std::optional<ValueAndVReg> Index =
1905 getIConstantVRegValWithLookThrough(Insert->getIndexReg(), MRI);
1906 if (!Index)
1907 return true;
1908 LLT VecTy = MRI.getType(Insert->getVectorReg());
1909 return Index->Value.uge(VecTy.getElementCount().getKnownMinValue());
1910 }
1911 return false;
1912 }
1913 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1915 if (includesPoison(Kind)) {
1916 std::optional<ValueAndVReg> Index =
1918 if (!Index)
1919 return true;
1920 LLT VecTy = MRI.getType(Extract->getVectorReg());
1921 return Index->Value.uge(VecTy.getElementCount().getKnownMinValue());
1922 }
1923 return false;
1924 }
1925 case TargetOpcode::G_SHUFFLE_VECTOR: {
1926 GShuffleVector *Shuffle = cast<GShuffleVector>(RegDef);
1927 ArrayRef<int> Mask = Shuffle->getMask();
1928 return includesPoison(Kind) && is_contained(Mask, -1);
1929 }
1930 case TargetOpcode::G_FNEG:
1931 case TargetOpcode::G_PHI:
1932 case TargetOpcode::G_SELECT:
1933 case TargetOpcode::G_UREM:
1934 case TargetOpcode::G_SREM:
1935 case TargetOpcode::G_FREEZE:
1936 case TargetOpcode::G_ICMP:
1937 case TargetOpcode::G_FCMP:
1938 case TargetOpcode::G_FADD:
1939 case TargetOpcode::G_FSUB:
1940 case TargetOpcode::G_FMUL:
1941 case TargetOpcode::G_FDIV:
1942 case TargetOpcode::G_FREM:
1943 case TargetOpcode::G_PTR_ADD:
1944 return false;
1945 default:
1946 return !isa<GCastOp>(RegDef) && !isa<GBinOp>(RegDef);
1947 }
1948}
1949
1951 const MachineRegisterInfo &MRI,
1952 unsigned Depth,
1953 UndefPoisonKind Kind) {
1955 return false;
1956
1957 MachineInstr *RegDef = MRI.getVRegDef(Reg);
1958
1959 switch (RegDef->getOpcode()) {
1960 case TargetOpcode::G_FREEZE:
1961 return true;
1962 case TargetOpcode::G_IMPLICIT_DEF:
1963 return !includesUndef(Kind);
1964 case TargetOpcode::G_CONSTANT:
1965 case TargetOpcode::G_FCONSTANT:
1966 return true;
1967 case TargetOpcode::G_BUILD_VECTOR: {
1968 GBuildVector *BV = cast<GBuildVector>(RegDef);
1969 unsigned NumSources = BV->getNumSources();
1970 for (unsigned I = 0; I < NumSources; ++I)
1972 Depth + 1, Kind))
1973 return false;
1974 return true;
1975 }
1976 case TargetOpcode::G_PHI: {
1977 GPhi *Phi = cast<GPhi>(RegDef);
1978 unsigned NumIncoming = Phi->getNumIncomingValues();
1979 for (unsigned I = 0; I < NumIncoming; ++I)
1980 if (!::isGuaranteedNotToBeUndefOrPoison(Phi->getIncomingValue(I), MRI,
1981 Depth + 1, Kind))
1982 return false;
1983 return true;
1984 }
1985 default: {
1986 auto MOCheck = [&](const MachineOperand &MO) {
1987 if (!MO.isReg())
1988 return true;
1989 return ::isGuaranteedNotToBeUndefOrPoison(MO.getReg(), MRI, Depth + 1,
1990 Kind);
1991 };
1993 /*ConsiderFlagsAndMetadata=*/true, Kind) &&
1994 all_of(RegDef->uses(), MOCheck);
1995 }
1996 }
1997}
1998
2000 bool ConsiderFlagsAndMetadata) {
2001 return ::canCreateUndefOrPoison(Reg, MRI, ConsiderFlagsAndMetadata,
2003}
2004
2006 bool ConsiderFlagsAndMetadata = true) {
2007 return ::canCreateUndefOrPoison(Reg, MRI, ConsiderFlagsAndMetadata,
2009}
2010
2012 const MachineRegisterInfo &MRI,
2013 unsigned Depth) {
2014 return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth,
2016}
2017
2019 const MachineRegisterInfo &MRI,
2020 unsigned Depth) {
2021 return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth,
2023}
2024
2026 const MachineRegisterInfo &MRI,
2027 unsigned Depth) {
2028 return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth,
2030}
2031
2033 if (Ty.isVector())
2034 return VectorType::get(IntegerType::get(C, Ty.getScalarSizeInBits()),
2035 Ty.getElementCount());
2036 return IntegerType::get(C, Ty.getSizeInBits());
2037}
2038
2040 switch (MI.getOpcode()) {
2041 default:
2042 return false;
2043 case TargetOpcode::G_ASSERT_ALIGN:
2044 case TargetOpcode::G_ASSERT_SEXT:
2045 case TargetOpcode::G_ASSERT_ZEXT:
2046 return true;
2047 }
2048}
2049
2051 assert(Kind == GIConstantKind::Scalar && "Expected scalar constant");
2052
2053 return Value;
2054}
2055
2056std::optional<GIConstant>
2059
2061 std::optional<ValueAndVReg> MayBeConstant =
2063 if (!MayBeConstant)
2064 return std::nullopt;
2065 return GIConstant(MayBeConstant->Value, GIConstantKind::ScalableVector);
2066 }
2067
2069 SmallVector<APInt> Values;
2070 unsigned NumSources = Build->getNumSources();
2071 for (unsigned I = 0; I < NumSources; ++I) {
2072 Register SrcReg = Build->getSourceReg(I);
2073 std::optional<ValueAndVReg> MayBeConstant =
2075 if (!MayBeConstant)
2076 return std::nullopt;
2077 Values.push_back(MayBeConstant->Value);
2078 }
2079 return GIConstant(Values);
2080 }
2081
2082 std::optional<ValueAndVReg> MayBeConstant =
2084 if (!MayBeConstant)
2085 return std::nullopt;
2086
2087 return GIConstant(MayBeConstant->Value, GIConstantKind::Scalar);
2088}
2089
2091 assert(Kind == GFConstantKind::Scalar && "Expected scalar constant");
2092
2093 return Values[0];
2094}
2095
2096std::optional<GFConstant>
2099
2101 std::optional<FPValueAndVReg> MayBeConstant =
2103 if (!MayBeConstant)
2104 return std::nullopt;
2105 return GFConstant(MayBeConstant->Value, GFConstantKind::ScalableVector);
2106 }
2107
2109 SmallVector<APFloat> Values;
2110 unsigned NumSources = Build->getNumSources();
2111 for (unsigned I = 0; I < NumSources; ++I) {
2112 Register SrcReg = Build->getSourceReg(I);
2113 std::optional<FPValueAndVReg> MayBeConstant =
2115 if (!MayBeConstant)
2116 return std::nullopt;
2117 Values.push_back(MayBeConstant->Value);
2118 }
2119 return GFConstant(Values);
2120 }
2121
2122 std::optional<FPValueAndVReg> MayBeConstant =
2124 if (!MayBeConstant)
2125 return std::nullopt;
2126
2127 return GFConstant(MayBeConstant->Value, GFConstantKind::Scalar);
2128}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned RegSize
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool includesPoison(UndefPoisonKind Kind)
Definition Utils.cpp:1838
static bool includesUndef(UndefPoisonKind Kind)
Definition Utils.cpp:1842
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition Utils.cpp:235
static bool shiftAmountKnownInRange(Register ShiftAmount, const MachineRegisterInfo &MRI)
Shifts return poison if shiftwidth is larger than the bitwidth.
Definition Utils.cpp:1798
static bool isBuildVectorOp(unsigned Opcode)
Definition Utils.cpp:1351
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Definition Utils.cpp:1507
This file contains the declarations for the subclasses of Constant, which represent the different fla...
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
Tracks DebugLocs between checkpoints and verifies that they are transferred.
#define I(x, y, z)
Definition MD5.cpp:58
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
MachineInstr unsigned OpIdx
uint64_t IntrinsicInst * II
#define LLVM_DEBUG(...)
Definition Debug.h:114
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
UndefPoisonKind
static const char PassName[]
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
Definition APFloat.h:1208
void copySign(const APFloat &RHS)
Definition APFloat.h:1302
LLVM_ABI opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition APFloat.cpp:6057
opStatus subtract(const APFloat &RHS, roundingMode RM)
Definition APFloat.h:1190
opStatus add(const APFloat &RHS, roundingMode RM)
Definition APFloat.h:1181
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition APFloat.h:1347
opStatus multiply(const APFloat &RHS, roundingMode RM)
Definition APFloat.h:1199
APInt bitcastToAPInt() const
Definition APFloat.h:1353
opStatus mod(const APFloat &RHS)
Definition APFloat.h:1226
Class for arbitrary precision integers.
Definition APInt.h:78
LLVM_ABI APInt udiv(const APInt &RHS) const
Unsigned division operation.
Definition APInt.cpp:1573
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition APInt.h:234
LLVM_ABI APInt zext(unsigned width) const
Zero extend to a new width.
Definition APInt.cpp:1012
LLVM_ABI APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition APInt.cpp:1033
LLVM_ABI APInt trunc(unsigned width) const
Truncate to new width.
Definition APInt.cpp:936
LLVM_ABI APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition APInt.cpp:1666
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition APInt.h:1488
LLVM_ABI APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
Definition APInt.cpp:1644
LLVM_ABI APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition APInt.cpp:1041
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition APInt.h:827
LLVM_ABI APInt srem(const APInt &RHS) const
Function for signed remainder operation.
Definition APInt.cpp:1736
LLVM_ABI APInt sext(unsigned width) const
Sign extend to a new width.
Definition APInt.cpp:985
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition APInt.h:440
static bool isSameValue(const APInt &I1, const APInt &I2)
Determine if two APInts have the same value, after zero-extending one of them (if needed!...
Definition APInt.h:553
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
Definition APInt.h:200
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
Definition APInt.h:239
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition APInt.h:851
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
@ ICMP_SLT
signed less than
Definition InstrTypes.h:705
@ ICMP_SLE
signed less or equal
Definition InstrTypes.h:706
@ ICMP_UGE
unsigned greater or equal
Definition InstrTypes.h:700
@ ICMP_UGT
unsigned greater than
Definition InstrTypes.h:699
@ ICMP_SGT
signed greater than
Definition InstrTypes.h:703
@ ICMP_ULT
unsigned less than
Definition InstrTypes.h:701
@ ICMP_NE
not equal
Definition InstrTypes.h:698
@ ICMP_SGE
signed greater or equal
Definition InstrTypes.h:704
@ ICMP_ULE
unsigned less or equal
Definition InstrTypes.h:702
ConstantFP - Floating Point Values [float, double].
Definition Constants.h:277
const APFloat & getValueAPF() const
Definition Constants.h:320
bool isNegative() const
Return true if the sign bit is set.
Definition Constants.h:327
bool isZero() const
Return true if the value is positive or negative zero.
Definition Constants.h:324
This is the shared class of boolean and integer constants.
Definition Constants.h:87
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition Constants.h:154
This is an important base class in LLVM.
Definition Constant.h:43
A debug info location.
Definition DebugLoc.h:124
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition TypeSize.h:310
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Definition TypeSize.h:316
Represents a G_BUILD_VECTOR.
Represents an extract vector element.
static LLVM_ABI std::optional< GFConstant > getConstant(Register Const, const MachineRegisterInfo &MRI)
Definition Utils.cpp:2097
GFConstant(ArrayRef< APFloat > Values)
Definition Utils.h:703
LLVM_ABI APFloat getScalarValue() const
Returns the value, if this constant is a scalar.
Definition Utils.cpp:2090
LLVM_ABI APInt getScalarValue() const
Returns the value, if this constant is a scalar.
Definition Utils.cpp:2050
static LLVM_ABI std::optional< GIConstant > getConstant(Register Const, const MachineRegisterInfo &MRI)
Definition Utils.cpp:2057
GIConstant(ArrayRef< APInt > Values)
Definition Utils.h:662
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
MachineInstr * pop_back_val()
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Represents an insert vector element.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Represents a G_PHI.
Represents a G_SHUFFLE_VECTOR.
ArrayRef< int > getMask() const
Represents a splat vector.
Module * getParent()
Get the module that this global value is contained inside of...
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition Type.cpp:319
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr bool isScalable() const
Returns true if the LLT is a scalable vector.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
constexpr LLT getScalarType() const
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineInstrBundleIterator< MachineInstr > iterator
LLVM_ABI bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Helper class to build MachineInstr.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
mop_range uses()
Returns all operands which may be register uses.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Diagnostic information for missed-optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition Module.h:67
Represents a value which can be a Register or a constant.
Definition Utils.h:407
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Wrapper class representing virtual and physical registers.
Definition Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:78
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
LLVM Value Representation.
Definition Value.h:75
static LLVM_ABI VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
constexpr ScalarTy getFixedValue() const
Definition TypeSize.h:201
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition TypeSize.h:169
constexpr LeafTy multiplyCoefficientBy(ScalarTy RHS) const
Definition TypeSize.h:257
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:166
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Definition APInt.h:2248
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition APInt.h:2253
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition APInt.h:2258
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition APInt.h:2263
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition Utils.cpp:915
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition STLExtras.h:316
LLVM_ABI std::optional< SmallVector< APInt > > ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2, unsigned DstScalarSizeInBits, unsigned ExtOp, const MachineRegisterInfo &MRI)
Definition Utils.cpp:1034
@ Offset
Definition DWP.cpp:477
LLVM_ABI bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition Utils.cpp:1481
LLVM_ABI Type * getTypeForLLT(LLT Ty, LLVMContext &C)
Get the type back from LLT.
Definition Utils.cpp:2032
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1725
LLVM_ABI Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition Utils.cpp:56
LLVM_ABI MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition Utils.cpp:651
LLVM_ABI const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition Utils.cpp:459
LLVM_ABI bool canCreatePoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
LLVM_ABI std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition Utils.cpp:294
LLVM_ABI std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition Utils.cpp:989
LLVM_ABI std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition Utils.cpp:1441
LLVM_ABI bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition Utils.cpp:1606
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:644
LLVM_ABI const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
LLVM_ABI std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition Utils.cpp:739
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition Utils.cpp:1724
LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition Utils.cpp:155
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
auto dyn_cast_if_present(const Y &Val)
dyn_cast_if_present<X> - Functionally identical to dyn_cast, except that a null (or none in the case ...
Definition Casting.h:733
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
LLVM_ABI std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)
Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
Definition Utils.cpp:1002
LLVM_ABI std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition Utils.cpp:948
LLVM_ABI std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition Utils.cpp:1494
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
Definition APFloat.h:1643
GISelWorkList< 4 > SmallInstListTy
Definition Utils.h:582
LLVM_ABI std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition Utils.cpp:1564
LLVM_ABI bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition Utils.cpp:1588
LLVM_ABI MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition Utils.cpp:492
LLVM_ABI bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition Utils.cpp:1621
bool isPreISelGenericOptimizationHint(unsigned Opcode)
LLVM_ABI bool isGuaranteedNotToBeUndef(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Returns true if V cannot be undef, but may be poison.
LLVM_ABI bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition Utils.cpp:1653
LLVM_ABI LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition Utils.cpp:1188
LLVM_ABI std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition Utils.cpp:314
LLVM_ABI std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition Utils.cpp:670
auto dyn_cast_or_null(const Y &Val)
Definition Casting.h:754
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1732
LLVM_ABI const APInt & getIConstantFromReg(Register VReg, const MachineRegisterInfo &MRI)
VReg is defined by a G_CONSTANT, return the corresponding value.
Definition Utils.cpp:305
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2008 maxNum semantics.
Definition APFloat.h:1598
LLVM_ABI bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition Utils.cpp:1544
constexpr unsigned MaxAnalysisRecursionDepth
auto reverse(ContainerTy &&C)
Definition STLExtras.h:406
LLVM_ABI bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition Utils.cpp:201
LLVM_ABI void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition Utils.cpp:1690
LLVM_ABI void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition Utils.cpp:259
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
LLVM_ABI std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition Utils.cpp:439
LLVM_ABI bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition Utils.cpp:1487
LLVM_ABI bool canCreateUndefOrPoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)
canCreateUndefOrPoison returns true if Op can create undef or poison from non-undef & non-poison oper...
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
LLVM_ABI SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition Utils.cpp:793
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:548
LLVM_ABI std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition Utils.cpp:1474
LLVM_ABI std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
Definition Utils.cpp:965
LLVM_ABI void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...
Definition Utils.cpp:506
LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition Utils.cpp:1184
LLVM_ABI LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition Utils.cpp:1255
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2008 minNum semantics.
Definition APFloat.h:1579
LLVM_ABI unsigned getInverseGMinMaxOpcode(unsigned MinMaxOpc)
Returns the inverse opcode of MinMaxOpc, which is a generic min/max opcode like G_SMIN.
Definition Utils.cpp:279
@ Mul
Product of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition Alignment.h:144
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
DWARFExpression::Operation Op
LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Return true if this function can prove that V does not have undef bits and is never poison.
LLVM_ABI std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition Utils.cpp:447
LLVM_ABI bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Definition Utils.cpp:1666
LLVM_ABI std::optional< APFloat > isConstantOrConstantSplatVectorFP(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a float constant integer or a splat vector of float constant integers.
Definition Utils.cpp:1577
constexpr unsigned BitWidth
LLVM_ABI APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition Utils.cpp:657
LLVM_ABI bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition Utils.cpp:1400
LLVM_ABI void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition Utils.cpp:1719
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition Utils.cpp:46
LLVM_ABI int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition Utils.cpp:1678
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:560
LLVM_ABI bool isKnownNeverNaN(const Value *V, const SimplifyQuery &SQ, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
LLVM_ABI std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition Utils.cpp:433
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1758
LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Definition Utils.cpp:1743
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition Utils.h:352
LLVM_ABI std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition Utils.cpp:467
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition STLExtras.h:1897
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition Alignment.h:201
LLVM_ABI void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition Utils.cpp:1704
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
LLVM_ABI bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true, unsigned Depth=0)
Return true if the given value is known to have exactly one bit set when defined.
LLVM_ABI Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition Utils.cpp:499
LLVM_ABI LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition Utils.cpp:1276
LLVM_ABI bool isGuaranteedNotToBePoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Returns true if V cannot be poison, but may be undef.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
Definition APFloat.h:1616
LLVM_ABI std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition Utils.cpp:1459
LLVM_ABI bool isAssertMI(const MachineInstr &MI)
Returns true if the instruction MI is one of the assert instructions.
Definition Utils.cpp:2039
LLVM_ABI void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Version which handles irregular sub-vector splits.
Definition Utils.cpp:609
LLVM_ABI int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition Utils.cpp:222
LLVM_ABI Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition Utils.cpp:898
LLVM_ABI void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition Utils.cpp:253
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
Definition Error.cpp:180
#define MORE()
Definition regcomp.c:246
static constexpr roundingMode rmNearestTiesToEven
Definition APFloat.h:304
static LLVM_ABI const fltSemantics & IEEEhalf() LLVM_READNONE
Definition APFloat.cpp:264
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
Simple struct used to hold a Register value and the instruction which defines it.
Definition Utils.h:234
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition KnownBits.h:289
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition KnownBits.h:286
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.
Definition Utils.h:193