38#define DEBUG_TYPE "globalisel-utils"
41using namespace MIPatternMatch;
48 return MRI.createVirtualRegister(&RegClass);
60 assert(Reg.isVirtual() &&
"PhysReg not implemented");
66 auto *OldRegClass =
MRI.getRegClassOrNull(Reg);
70 if (ConstrainedReg != Reg) {
77 TII.get(TargetOpcode::COPY), ConstrainedReg)
82 TII.get(TargetOpcode::COPY), Reg)
86 Observer->changingInstr(*RegMO.
getParent());
88 RegMO.
setReg(ConstrainedReg);
90 Observer->changedInstr(*RegMO.
getParent());
92 }
else if (OldRegClass !=
MRI.getRegClassOrNull(Reg)) {
96 Observer->changedInstr(*RegDef);
98 Observer->changingAllUsesOfReg(
MRI, Reg);
99 Observer->finishedChangingAllUsesOfReg();
102 return ConstrainedReg;
112 assert(Reg.isVirtual() &&
"PhysReg not implemented");
125 if (
const auto *SubRC =
TRI.getCommonSubClass(
126 OpRC,
TRI.getConstrainedRegClassForOperand(RegMO,
MRI)))
129 OpRC =
TRI.getAllocatableClass(OpRC);
134 "Register class constraint is required unless either the "
135 "instruction is target independent or the operand is a use");
157 "A selected instruction is expected");
162 for (
unsigned OpI = 0, OpE =
I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
170 assert(MO.
isReg() &&
"Unsupported non-reg operand");
174 if (Reg.isPhysical())
190 int DefIdx =
I.getDesc().getOperandConstraint(OpI,
MCOI::TIED_TO);
191 if (DefIdx != -1 && !
I.isRegTiedToUseOperand(DefIdx))
192 I.tieOperands(DefIdx, OpI);
204 if (
MRI.getType(DstReg) !=
MRI.getType(SrcReg))
208 const auto &DstRBC =
MRI.getRegClassOrRegBank(DstReg);
209 if (!DstRBC || DstRBC ==
MRI.getRegClassOrRegBank(SrcReg))
214 return DstRBC.is<
const RegisterBank *>() &&
MRI.getRegClassOrNull(SrcReg) &&
216 *
MRI.getRegClassOrNull(SrcReg));
226 if (
MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
229 if (
MI.getOpcode() == TargetOpcode::LIFETIME_START ||
230 MI.getOpcode() == TargetOpcode::LIFETIME_END)
235 bool SawStore =
false;
236 if (!
MI.isSafeToMove(
nullptr, SawStore) && !
MI.isPHI())
240 for (
const auto &MO :
MI.all_defs()) {
242 if (Reg.isPhysical() || !
MRI.use_nodbg_empty(Reg))
253 bool IsFatal = Severity ==
DS_Error &&
257 if (!R.getLocation().isValid() || IsFatal)
258 R << (
" (in function: " + MF.
getName() +
")").str();
284 MI.getDebugLoc(),
MI.getParent());
296 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
297 "Value found while looking through instrs");
300 return ValAndVReg->Value;
303std::optional<int64_t>
306 if (Val && Val->getBitWidth() <= 64)
307 return Val->getSExtValue();
314typedef std::function<std::optional<APInt>(
const MachineInstr *
MI)> GetAPCstFn;
316std::optional<ValueAndVReg> getConstantVRegValWithLookThrough(
318 GetAPCstFn getAPCstValue,
bool LookThroughInstrs =
true,
319 bool LookThroughAnyExt =
false) {
323 while ((
MI =
MRI.getVRegDef(VReg)) && !IsConstantOpcode(
MI) &&
325 switch (
MI->getOpcode()) {
326 case TargetOpcode::G_ANYEXT:
327 if (!LookThroughAnyExt)
330 case TargetOpcode::G_TRUNC:
331 case TargetOpcode::G_SEXT:
332 case TargetOpcode::G_ZEXT:
335 MRI.getType(
MI->getOperand(0).getReg()).getSizeInBits()));
336 VReg =
MI->getOperand(1).getReg();
338 case TargetOpcode::COPY:
339 VReg =
MI->getOperand(1).getReg();
343 case TargetOpcode::G_INTTOPTR:
344 VReg =
MI->getOperand(1).getReg();
350 if (!
MI || !IsConstantOpcode(
MI))
353 std::optional<APInt> MaybeVal = getAPCstValue(
MI);
356 APInt &Val = *MaybeVal;
357 while (!SeenOpcodes.
empty()) {
358 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.
pop_back_val();
359 switch (OpcodeAndSize.first) {
360 case TargetOpcode::G_TRUNC:
361 Val = Val.
trunc(OpcodeAndSize.second);
363 case TargetOpcode::G_ANYEXT:
364 case TargetOpcode::G_SEXT:
365 Val = Val.
sext(OpcodeAndSize.second);
367 case TargetOpcode::G_ZEXT:
368 Val = Val.
zext(OpcodeAndSize.second);
379 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
385 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
391 unsigned Opc =
MI->getOpcode();
392 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
402std::optional<APInt> getCImmOrFPImmAsAPInt(
const MachineInstr *
MI) {
415 return getConstantVRegValWithLookThrough(VReg,
MRI, isIConstant,
416 getCImmAsAPInt, LookThroughInstrs);
421 bool LookThroughAnyExt) {
422 return getConstantVRegValWithLookThrough(
423 VReg,
MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
429 auto Reg = getConstantVRegValWithLookThrough(
430 VReg,
MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
440 if (TargetOpcode::G_FCONSTANT !=
MI->getOpcode())
442 return MI->getOperand(1).getFPImm();
445std::optional<DefinitionAndSourceRegister>
450 if (!DstTy.isValid())
455 auto SrcTy =
MRI.getType(SrcReg);
456 if (!SrcTy.isValid())
467 std::optional<DefinitionAndSourceRegister> DefSrcReg =
469 return DefSrcReg ? DefSrcReg->MI :
nullptr;
474 std::optional<DefinitionAndSourceRegister> DefSrcReg =
476 return DefSrcReg ? DefSrcReg->Reg :
Register();
494 APF.
convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
510 const APInt &C1 = MaybeOp1Cst->Value;
511 const APInt &C2 = MaybeOp2Cst->Value;
515 case TargetOpcode::G_ADD:
516 case TargetOpcode::G_PTR_ADD:
518 case TargetOpcode::G_AND:
520 case TargetOpcode::G_ASHR:
522 case TargetOpcode::G_LSHR:
524 case TargetOpcode::G_MUL:
526 case TargetOpcode::G_OR:
528 case TargetOpcode::G_SHL:
530 case TargetOpcode::G_SUB:
532 case TargetOpcode::G_XOR:
534 case TargetOpcode::G_UDIV:
535 if (!C2.getBoolValue())
538 case TargetOpcode::G_SDIV:
539 if (!C2.getBoolValue())
542 case TargetOpcode::G_UREM:
543 if (!C2.getBoolValue())
546 case TargetOpcode::G_SREM:
547 if (!C2.getBoolValue())
550 case TargetOpcode::G_SMIN:
552 case TargetOpcode::G_SMAX:
554 case TargetOpcode::G_UMIN:
556 case TargetOpcode::G_UMAX:
563std::optional<APFloat>
577 case TargetOpcode::G_FADD:
578 C1.
add(C2, APFloat::rmNearestTiesToEven);
580 case TargetOpcode::G_FSUB:
581 C1.
subtract(C2, APFloat::rmNearestTiesToEven);
583 case TargetOpcode::G_FMUL:
584 C1.
multiply(C2, APFloat::rmNearestTiesToEven);
586 case TargetOpcode::G_FDIV:
587 C1.
divide(C2, APFloat::rmNearestTiesToEven);
589 case TargetOpcode::G_FREM:
592 case TargetOpcode::G_FCOPYSIGN:
595 case TargetOpcode::G_FMINNUM:
597 case TargetOpcode::G_FMAXNUM:
599 case TargetOpcode::G_FMINIMUM:
601 case TargetOpcode::G_FMAXIMUM:
603 case TargetOpcode::G_FMINNUM_IEEE:
604 case TargetOpcode::G_FMAXNUM_IEEE:
621 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2,
MRI);
625 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1,
MRI);
630 for (
unsigned Idx = 0,
E = SrcVec1->getNumSources();
Idx <
E; ++
Idx) {
632 SrcVec2->getSourceReg(
Idx),
MRI);
637 return FoldedElements;
652 return !FPVal->getValueAPF().isNaN() ||
653 (SNaN && !FPVal->getValueAPF().isSignaling());
666 case TargetOpcode::G_FADD:
667 case TargetOpcode::G_FSUB:
668 case TargetOpcode::G_FMUL:
669 case TargetOpcode::G_FDIV:
670 case TargetOpcode::G_FREM:
671 case TargetOpcode::G_FSIN:
672 case TargetOpcode::G_FCOS:
673 case TargetOpcode::G_FMA:
674 case TargetOpcode::G_FMAD:
680 case TargetOpcode::G_FMINNUM_IEEE:
681 case TargetOpcode::G_FMAXNUM_IEEE: {
691 case TargetOpcode::G_FMINNUM:
692 case TargetOpcode::G_FMAXNUM: {
704 case TargetOpcode::G_FPEXT:
705 case TargetOpcode::G_FPTRUNC:
706 case TargetOpcode::G_FCANONICALIZE:
718 auto PSV = dyn_cast_if_present<const PseudoSourceValue *>(MPO.
V);
719 if (
auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
725 if (
const Value *V = dyn_cast_if_present<const Value *>(MPO.
V)) {
727 return V->getPointerAlignment(M->getDataLayout());
745 assert(Def->getParent() == &EntryMBB &&
"live-in copy not in entry block");
756 MRI.setType(LiveIn, RegTy);
774 case TargetOpcode::G_SEXT_INREG: {
775 LLT Ty =
MRI.getType(Op1);
793 case TargetOpcode::G_SEXT:
794 return Val->sext(DstSize);
795 case TargetOpcode::G_ZEXT:
796 case TargetOpcode::G_ANYEXT:
798 return Val->zext(DstSize);
806std::optional<APFloat>
809 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
813 APFloat::rmNearestTiesToEven);
819std::optional<SmallVector<unsigned>>
821 LLT Ty =
MRI.getType(Src);
823 auto tryFoldScalar = [&](
Register R) -> std::optional<unsigned> {
827 return MaybeCst->countl_zero();
831 auto *BV = getOpcodeDef<GBuildVector>(Src,
MRI);
834 for (
unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
835 if (
auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
843 if (
auto MaybeCst = tryFoldScalar(Src)) {
852 std::optional<DefinitionAndSourceRegister> DefSrcReg =
858 const LLT Ty =
MRI.getType(Reg);
860 switch (
MI.getOpcode()) {
861 case TargetOpcode::G_CONSTANT: {
866 case TargetOpcode::G_SHL: {
878 case TargetOpcode::G_LSHR: {
880 if (ConstLHS->isSignMask())
886 case TargetOpcode::G_BUILD_VECTOR: {
895 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
901 if (!Const || !Const->zextOrTrunc(
BitWidth).isPowerOf2())
930 if (OrigSize == TargetSize)
952 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
957 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
961 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
964 if (LCMSize == OrigSize)
966 if (LCMSize == TargetSize)
979 if (OrigTyNumElts % TargetTyNumElts == 0)
982 unsigned NumElts =
alignTo(OrigTyNumElts, TargetTyNumElts);
991 if (OrigSize == TargetSize)
1008 unsigned GCD = std::gcd(OrigSize, TargetSize);
1026 unsigned GCD = std::gcd(OrigSize, TargetSize);
1031 assert(
MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1032 "Only G_SHUFFLE_VECTOR can have a splat index!");
1034 auto FirstDefinedIdx =
find_if(Mask, [](
int Elt) {
return Elt >= 0; });
1038 if (FirstDefinedIdx == Mask.end())
1043 int SplatValue = *FirstDefinedIdx;
1045 [&SplatValue](
int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1046 return std::nullopt;
1052 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1053 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1058std::optional<ValueAndVReg> getAnyConstantSplat(
Register VReg,
1063 return std::nullopt;
1065 bool isConcatVectorsOp =
MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1067 return std::nullopt;
1069 std::optional<ValueAndVReg> SplatValAndReg;
1074 auto ElementValAndReg =
1076 ? getAnyConstantSplat(Element,
MRI, AllowUndef)
1080 if (!ElementValAndReg) {
1081 if (AllowUndef && isa<GImplicitDef>(
MRI.getVRegDef(Element)))
1083 return std::nullopt;
1087 if (!SplatValAndReg)
1088 SplatValAndReg = ElementValAndReg;
1091 if (SplatValAndReg->Value != ElementValAndReg->Value)
1092 return std::nullopt;
1095 return SplatValAndReg;
1102 int64_t SplatValue,
bool AllowUndef) {
1103 if (
auto SplatValAndReg = getAnyConstantSplat(Reg,
MRI, AllowUndef))
1110 int64_t SplatValue,
bool AllowUndef) {
1117 if (
auto SplatValAndReg =
1118 getAnyConstantSplat(Reg,
MRI,
false)) {
1119 std::optional<ValueAndVReg> ValAndVReg =
1121 return ValAndVReg->Value;
1124 return std::nullopt;
1133std::optional<int64_t>
1136 if (
auto SplatValAndReg =
1137 getAnyConstantSplat(Reg,
MRI,
false))
1139 return std::nullopt;
1142std::optional<int64_t>
1148std::optional<FPValueAndVReg>
1151 if (
auto SplatValAndReg = getAnyConstantSplat(VReg,
MRI, AllowUndef))
1153 return std::nullopt;
1168std::optional<RegOrConstant>
1170 unsigned Opc =
MI.getOpcode();
1172 return std::nullopt;
1175 auto Reg =
MI.getOperand(1).getReg();
1178 return std::nullopt;
1184 bool AllowFP =
true,
1185 bool AllowOpaqueConstants =
true) {
1186 switch (
MI.getOpcode()) {
1187 case TargetOpcode::G_CONSTANT:
1188 case TargetOpcode::G_IMPLICIT_DEF:
1190 case TargetOpcode::G_FCONSTANT:
1192 case TargetOpcode::G_GLOBAL_VALUE:
1193 case TargetOpcode::G_FRAME_INDEX:
1194 case TargetOpcode::G_BLOCK_ADDR:
1195 case TargetOpcode::G_JUMP_TABLE:
1196 return AllowOpaqueConstants;
1210 for (
unsigned SrcIdx = 0; SrcIdx < BV->
getNumSources(); ++SrcIdx) {
1221 bool AllowFP,
bool AllowOpaqueConstants) {
1228 const unsigned NumOps =
MI.getNumOperands();
1229 for (
unsigned I = 1;
I != NumOps; ++
I) {
1246 return std::nullopt;
1247 const unsigned ScalarSize =
MRI.getType(Def).getScalarSizeInBits();
1248 return APInt(ScalarSize, *MaybeCst,
true);
1253 switch (
MI.getOpcode()) {
1254 case TargetOpcode::G_IMPLICIT_DEF:
1256 case TargetOpcode::G_CONSTANT:
1257 return MI.getOperand(1).getCImm()->isNullValue();
1258 case TargetOpcode::G_FCONSTANT: {
1272 switch (
MI.getOpcode()) {
1273 case TargetOpcode::G_IMPLICIT_DEF:
1275 case TargetOpcode::G_CONSTANT:
1276 return MI.getOperand(1).getCImm()->isAllOnesValue();
1286 std::function<
bool(
const Constant *ConstVal)>
Match,
bool AllowUndefs) {
1289 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1290 return Match(
nullptr);
1293 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1294 return Match(Def->getOperand(1).getCImm());
1296 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1299 for (
unsigned I = 1,
E = Def->getNumOperands();
I !=
E; ++
I) {
1300 Register SrcElt = Def->getOperand(
I).getReg();
1302 if (AllowUndefs && SrcDef->
getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1303 if (!
Match(
nullptr))
1308 if (SrcDef->
getOpcode() != TargetOpcode::G_CONSTANT ||
1319 case TargetLowering::UndefinedBooleanContent:
1321 case TargetLowering::ZeroOrOneBooleanContent:
1323 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1330 bool IsVector,
bool IsFP) {
1332 case TargetLowering::UndefinedBooleanContent:
1334 case TargetLowering::ZeroOrOneBooleanContent:
1335 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1344 case TargetLowering::UndefinedBooleanContent:
1345 case TargetLowering::ZeroOrOneBooleanContent:
1347 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1356 return F.hasOptSize() ||
F.hasMinSize() ||
1364 if (
Op.isReg() &&
Op.getReg().isVirtual())
1365 DeadInstChain.
insert(
MRI.getVRegDef(
Op.getReg()));
1369 MI.eraseFromParent();
1381 while (!DeadInstChain.
empty()) {
1395 for (
auto &Def :
MI.defs()) {
1396 assert(Def.isReg() &&
"Must be a reg");
1399 for (
auto &MOUse :
MRI.use_operands(Def.getReg())) {
1407 if (!DbgUsers.
empty()) {
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
static bool isBuildVectorOp(unsigned Opcode)
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
Tracks DebugLocs between checkpoints and verifies that they are transferred.
Contains matchers for matching SSA Machine Instructions.
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
static const char PassName[]
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
APInt bitcastToAPInt() const
opStatus mod(const APFloat &RHS)
Class for arbitrary precision integers.
APInt udiv(const APInt &RHS) const
Unsigned division operation.
APInt zext(unsigned width) const
Zero extend to a new width.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
APInt trunc(unsigned width) const
Truncate to new width.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
APInt sext(unsigned width) const
Sign extend to a new width.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
bool isNegative() const
Return true if the sign bit is set.
bool isZero() const
Return true if the value is positive or negative zero.
This is the shared class of boolean and integer constants.
const APInt & getValue() const
Return the constant as an APInt value reference.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
static constexpr ElementCount getFixed(ScalarTy MinVal)
Represents a G_BUILD_VECTOR.
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
MachineInstr * pop_back_val()
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Module * getParent()
Get the module that this global value is contained inside of...
constexpr unsigned getScalarSizeInBits() const
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Wrapper class representing physical registers. Should be passed by value.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionProperties & set(Property P)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Analysis providing profile information.
Represents a value which can be a Register or a constant.
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
@ C
The default llvm calling convention, compatible with C.
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
bool isKnownNeverNaN(const Value *V, const DataLayout &DL, const TargetLibraryInfo *TLI, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
constexpr unsigned BitWidth
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
std::optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Simple struct used to hold a Register value and the instruction which defines it.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
unsigned countMinPopulation() const
Returns the number of bits known to be one.
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.