LLVM  13.0.0git
Classes | Namespaces | Macros | Functions
Utils.h File Reference
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/LowLevelTypeImpl.h"
#include <cstdint>
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Classes

struct  llvm::ValueAndVReg
 Simple struct used to hold a constant integer value and a virtual register. More...
 
struct  llvm::DefinitionAndSourceRegister
 Simple struct used to hold a Register value and the instruction which defines it. More...
 
class  llvm::RegOrConstant
 Represents a value which can be a Register or a constant. More...
 

Namespaces

 llvm
 

Macros

#define GISEL_VECREDUCE_CASES_ALL
 
#define GISEL_VECREDUCE_CASES_NONSEQ
 

Functions

Register llvm::constrainRegToClass (MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
 Try to constrain Reg to the specified register class. More...
 
Register llvm::constrainOperandRegClass (const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
 Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed as an argument (RegClass). More...
 
Register llvm::constrainOperandRegClass (const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, MachineOperand &RegMO, unsigned OpIdx)
 Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II. More...
 
bool llvm::constrainSelectedInstRegOperands (MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class. More...
 
bool llvm::canReplaceReg (Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
 Check if DstReg can be replaced with SrcReg depending on the register constraints. More...
 
bool llvm::isTriviallyDead (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have other side effects. More...
 
void llvm::reportGISelFailure (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
 Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream. More...
 
void llvm::reportGISelFailure (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, const char *PassName, StringRef Msg, const MachineInstr &MI)
 
void llvm::reportGISelWarning (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
 Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream. More...
 
Optional< APIntllvm::getConstantVRegVal (Register VReg, const MachineRegisterInfo &MRI)
 If VReg is defined by a G_CONSTANT, return the corresponding value. More...
 
Optional< int64_t > llvm::getConstantVRegSExtVal (Register VReg, const MachineRegisterInfo &MRI)
 If VReg is defined by a G_CONSTANT fits in int64_t returns it. More...
 
Optional< ValueAndVRegllvm::getConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true, bool LookThroughAnyExt=false)
 If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThroughInstrs == true) and that constant fits in int64_t, returns its value as well as the virtual register defined by this G_F/CONSTANT. More...
 
const ConstantIntllvm::getConstantIntVRegVal (Register VReg, const MachineRegisterInfo &MRI)
 
const ConstantFPllvm::getConstantFPVRegVal (Register VReg, const MachineRegisterInfo &MRI)
 
MachineInstrllvm::getOpcodeDef (unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
 See if Reg is defined by an single def instruction that is Opcode. More...
 
Optional< DefinitionAndSourceRegisterllvm::getDefSrcRegIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI)
 Find the def instruction for Reg, and underlying value Register folding away any copies. More...
 
MachineInstrllvm::getDefIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI)
 Find the def instruction for Reg, folding away any trivial copies. More...
 
Register llvm::getSrcRegIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI)
 Find the source register for Reg, folding away any trivial copies. More...
 
APFloat llvm::getAPFloatFromSize (double Val, unsigned Size)
 Returns an APFloat from Val converted to the appropriate size. More...
 
void llvm::getSelectionDAGFallbackAnalysisUsage (AnalysisUsage &AU)
 Modify analysis usage so it preserves passes required for the SelectionDAG fallback. More...
 
Optional< APIntllvm::ConstantFoldBinOp (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
 
Optional< APFloatllvm::ConstantFoldFPBinOp (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
 
Optional< APIntllvm::ConstantFoldExtOp (unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
 
bool llvm::isKnownToBeAPowerOfTwo (Register Val, const MachineRegisterInfo &MRI, GISelKnownBits *KnownBits=nullptr)
 Test if the given value is known to have exactly one bit set. More...
 
bool llvm::isKnownNeverNaN (Register Val, const MachineRegisterInfo &MRI, bool SNaN=false)
 Returns true if Val can be assumed to never be a NaN. More...
 
bool llvm::isKnownNeverSNaN (Register Val, const MachineRegisterInfo &MRI)
 Returns true if Val can be assumed to never be a signaling NaN. More...
 
Align llvm::inferAlignFromPtrInfo (MachineFunction &MF, const MachinePointerInfo &MPO)
 
Register llvm::getFunctionLiveInPhysReg (MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, LLT RegTy=LLT())
 Return a virtual register corresponding to the incoming argument register PhysReg. More...
 
LLVM_READNONE LLT llvm::getLCMType (LLT OrigTy, LLT TargetTy)
 Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elements or scalar bitwidth. More...
 
LLVM_READNONE LLT llvm::getGCDType (LLT OrigTy, LLT TargetTy)
 Return a type where the total size is the greatest common divisor of OrigTy and TargetTy. More...
 
Optional< intllvm::getSplatIndex (MachineInstr &MI)
 
Optional< int64_t > llvm::getBuildVectorConstantSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 Returns a scalar constant of a G_BUILD_VECTOR splat if it exists. More...
 
bool llvm::isBuildVectorAllZeros (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef. More...
 
bool llvm::isBuildVectorAllOnes (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef. More...
 
Optional< RegOrConstantllvm::getVectorSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 
bool llvm::matchUnaryPredicate (const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
 Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_BUILD_VECTOR. More...
 
bool llvm::isConstTrueVal (const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
 Returns true if given the TargetLowering's boolean contents information, the value Val contains a true value. More...
 
int64_t llvm::getICmpTrueVal (const TargetLowering &TLI, bool IsVector, bool IsFP)
 Returns an integer representing true, as defined by the TargetBooleanContents. More...
 
bool llvm::shouldOptForSize (const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
 Returns true if the given block should be optimized for size. More...
 
unsigned llvm::getIntrinsicID (const MachineInstr &MI)
 

Macro Definition Documentation

◆ GISEL_VECREDUCE_CASES_ALL

#define GISEL_VECREDUCE_CASES_ALL
Value:
case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
case TargetOpcode::G_VECREDUCE_FADD: \
case TargetOpcode::G_VECREDUCE_FMUL: \
case TargetOpcode::G_VECREDUCE_FMAX: \
case TargetOpcode::G_VECREDUCE_FMIN: \
case TargetOpcode::G_VECREDUCE_ADD: \
case TargetOpcode::G_VECREDUCE_MUL: \
case TargetOpcode::G_VECREDUCE_AND: \
case TargetOpcode::G_VECREDUCE_OR: \
case TargetOpcode::G_VECREDUCE_XOR: \
case TargetOpcode::G_VECREDUCE_SMAX: \
case TargetOpcode::G_VECREDUCE_SMIN: \
case TargetOpcode::G_VECREDUCE_UMAX: \
case TargetOpcode::G_VECREDUCE_UMIN:

Definition at line 49 of file Utils.h.

◆ GISEL_VECREDUCE_CASES_NONSEQ

#define GISEL_VECREDUCE_CASES_NONSEQ
Value:
case TargetOpcode::G_VECREDUCE_FADD: \
case TargetOpcode::G_VECREDUCE_FMUL: \
case TargetOpcode::G_VECREDUCE_FMAX: \
case TargetOpcode::G_VECREDUCE_FMIN: \
case TargetOpcode::G_VECREDUCE_ADD: \
case TargetOpcode::G_VECREDUCE_MUL: \
case TargetOpcode::G_VECREDUCE_AND: \
case TargetOpcode::G_VECREDUCE_OR: \
case TargetOpcode::G_VECREDUCE_XOR: \
case TargetOpcode::G_VECREDUCE_SMAX: \
case TargetOpcode::G_VECREDUCE_SMIN: \
case TargetOpcode::G_VECREDUCE_UMAX: \
case TargetOpcode::G_VECREDUCE_UMIN:

Definition at line 66 of file Utils.h.