LLVM 20.0.0git
Classes | Namespaces | Macros | Typedefs | Functions
Utils.h File Reference
#include "GISelWorkList.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGenTypes/LowLevelType.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Casting.h"
#include <cstdint>

Go to the source code of this file.

Classes

struct  llvm::ValueAndVReg
 Simple struct used to hold a constant integer value and a virtual register. More...
 
struct  llvm::FPValueAndVReg
 
struct  llvm::DefinitionAndSourceRegister
 Simple struct used to hold a Register value and the instruction which defines it. More...
 
class  llvm::RegOrConstant
 Represents a value which can be a Register or a constant. More...
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 

Macros

#define GISEL_VECREDUCE_CASES_ALL
 
#define GISEL_VECREDUCE_CASES_NONSEQ
 

Typedefs

using llvm::SmallInstListTy = GISelWorkList< 4 >
 

Functions

Register llvm::constrainRegToClass (MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
 Try to constrain Reg to the specified register class.
 
Register llvm::constrainOperandRegClass (const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
 Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed as an argument (RegClass).
 
Register llvm::constrainOperandRegClass (const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, MachineOperand &RegMO, unsigned OpIdx)
 Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II.
 
bool llvm::constrainSelectedInstRegOperands (MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class.
 
bool llvm::canReplaceReg (Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
 Check if DstReg can be replaced with SrcReg depending on the register constraints.
 
bool llvm::isTriviallyDead (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have other side effects.
 
void llvm::reportGISelFailure (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
 Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
 
void llvm::reportGISelFailure (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, const char *PassName, StringRef Msg, const MachineInstr &MI)
 
void llvm::reportGISelWarning (MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
 Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
 
std::optional< APIntllvm::getIConstantVRegVal (Register VReg, const MachineRegisterInfo &MRI)
 If VReg is defined by a G_CONSTANT, return the corresponding value.
 
std::optional< int64_t > llvm::getIConstantVRegSExtVal (Register VReg, const MachineRegisterInfo &MRI)
 If VReg is defined by a G_CONSTANT fits in int64_t returns it.
 
APInt llvm::getIConstantFromReg (Register VReg, const MachineRegisterInfo &MRI)
 VReg is defined by a G_CONSTANT, return the corresponding value.
 
std::optional< ValueAndVRegllvm::getIConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
 If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its APInt value and def register.
 
std::optional< ValueAndVRegllvm::getAnyConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
 If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
 
std::optional< FPValueAndVRegllvm::getFConstantVRegValWithLookThrough (Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
 If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns its APFloat value and def register.
 
const ConstantFPllvm::getConstantFPVRegVal (Register VReg, const MachineRegisterInfo &MRI)
 
MachineInstrllvm::getOpcodeDef (unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
 See if Reg is defined by an single def instruction that is Opcode.
 
std::optional< DefinitionAndSourceRegisterllvm::getDefSrcRegIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI)
 Find the def instruction for Reg, and underlying value Register folding away any copies.
 
MachineInstrllvm::getDefIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI)
 Find the def instruction for Reg, folding away any trivial copies.
 
Register llvm::getSrcRegIgnoringCopies (Register Reg, const MachineRegisterInfo &MRI)
 Find the source register for Reg, folding away any trivial copies.
 
void llvm::extractParts (Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
 Helper function to split a wide generic register into bitwise blocks with the given Type (which implies the number of blocks needed).
 
bool llvm::extractParts (Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, SmallVectorImpl< Register > &VRegs, SmallVectorImpl< Register > &LeftoverVRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
 Version which handles irregular splits.
 
void llvm::extractVectorParts (Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
 Version which handles irregular sub-vector splits.
 
template<class T >
Tllvm::getOpcodeDef (Register Reg, const MachineRegisterInfo &MRI)
 See if Reg is defined by an single def instruction of type T Also try to do trivial folding if it's a COPY with same types.
 
APFloat llvm::getAPFloatFromSize (double Val, unsigned Size)
 Returns an APFloat from Val converted to the appropriate size.
 
void llvm::getSelectionDAGFallbackAnalysisUsage (AnalysisUsage &AU)
 Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
 
std::optional< APIntllvm::ConstantFoldBinOp (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
 
std::optional< APFloatllvm::ConstantFoldFPBinOp (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
 
SmallVector< APIntllvm::ConstantFoldVectorBinop (unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
 Tries to constant fold a vector binop with sources Op1 and Op2.
 
std::optional< APIntllvm::ConstantFoldCastOp (unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
 
std::optional< APIntllvm::ConstantFoldExtOp (unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
 
std::optional< APFloatllvm::ConstantFoldIntToFloat (unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
 
std::optional< SmallVector< unsigned > > llvm::ConstantFoldCountZeros (Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)
 Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
 
std::optional< SmallVector< APInt > > llvm::ConstantFoldICmp (unsigned Pred, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
 
bool llvm::isKnownToBeAPowerOfTwo (Register Val, const MachineRegisterInfo &MRI, GISelKnownBits *KnownBits=nullptr)
 Test if the given value is known to have exactly one bit set.
 
bool llvm::isKnownNeverNaN (Register Val, const MachineRegisterInfo &MRI, bool SNaN=false)
 Returns true if Val can be assumed to never be a NaN.
 
bool llvm::isKnownNeverSNaN (Register Val, const MachineRegisterInfo &MRI)
 Returns true if Val can be assumed to never be a signaling NaN.
 
Align llvm::inferAlignFromPtrInfo (MachineFunction &MF, const MachinePointerInfo &MPO)
 
Register llvm::getFunctionLiveInPhysReg (MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
 Return a virtual register corresponding to the incoming argument register PhysReg.
 
LLVM_READNONE LLT llvm::getLCMType (LLT OrigTy, LLT TargetTy)
 Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elements or scalar bitwidth.
 
LLVM_READNONE LLT llvm::getCoverTy (LLT OrigTy, LLT TargetTy)
 Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
 
LLVM_READNONE LLT llvm::getGCDType (LLT OrigTy, LLT TargetTy)
 Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
 
std::optional< int > llvm::getSplatIndex (MachineInstr &MI)
 
std::optional< APIntllvm::getIConstantSplatVal (const Register Reg, const MachineRegisterInfo &MRI)
 
std::optional< APIntllvm::getIConstantSplatVal (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 
std::optional< int64_t > llvm::getIConstantSplatSExtVal (const Register Reg, const MachineRegisterInfo &MRI)
 
std::optional< int64_t > llvm::getIConstantSplatSExtVal (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 
std::optional< FPValueAndVRegllvm::getFConstantSplat (Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
 Returns a floating point scalar constant of a build vector splat if it exists.
 
bool llvm::isBuildVectorConstantSplat (const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
 Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.
 
bool llvm::isBuildVectorConstantSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
 Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.
 
bool llvm::isBuildVectorAllZeros (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
 Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
 
bool llvm::isBuildVectorAllOnes (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
 Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
 
bool llvm::isConstantOrConstantVector (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
 Return true if the specified instruction is known to be a constant, or a vector of constants.
 
bool llvm::isNullOrNullSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
 Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with no undefs if AllowUndefs is false).
 
bool llvm::isAllOnesOrAllOnesSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
 Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with no undefs if AllowUndefs is false).
 
std::optional< RegOrConstantllvm::getVectorSplat (const MachineInstr &MI, const MachineRegisterInfo &MRI)
 
bool llvm::isConstantOrConstantVector (MachineInstr &MI, const MachineRegisterInfo &MRI)
 Determines if MI defines a constant integer or a build vector of constant integers.
 
std::optional< APIntllvm::isConstantOrConstantSplatVector (MachineInstr &MI, const MachineRegisterInfo &MRI)
 Determines if MI defines a constant integer or a splat vector of constant integers.
 
bool llvm::matchUnaryPredicate (const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
 Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_BUILD_VECTOR.
 
bool llvm::isConstTrueVal (const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
 Returns true if given the TargetLowering's boolean contents information, the value Val contains a true value.
 
bool llvm::isConstFalseVal (const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
 
int64_t llvm::getICmpTrueVal (const TargetLowering &TLI, bool IsVector, bool IsFP)
 Returns an integer representing true, as defined by the TargetBooleanContents.
 
bool llvm::shouldOptForSize (const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
 Returns true if the given block should be optimized for size.
 
void llvm::saveUsesAndErase (MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
 
void llvm::eraseInstrs (ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
 
void llvm::eraseInstr (MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
 
void llvm::salvageDebugInfo (const MachineRegisterInfo &MRI, MachineInstr &MI)
 Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing the effect of MI in a DIExpression.
 
bool llvm::isPreISelGenericFloatingPointOpcode (unsigned Opc)
 Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point operands.
 
bool llvm::canCreateUndefOrPoison (Register Reg, const MachineRegisterInfo &MRI, bool ConsiderFlagsAndMetadata=true)
 Returns true if Reg can create undef or poison from non-undef & non-poison operands.
 
bool llvm::canCreatePoison (Register Reg, const MachineRegisterInfo &MRI, bool ConsiderFlagsAndMetadata=true)
 Returns true if Reg can create poison from non-poison operands.
 
bool llvm::isGuaranteedNotToBeUndefOrPoison (Register Reg, const MachineRegisterInfo &MRI, unsigned Depth=0)
 Returns true if Reg cannot be poison and undef.
 
bool llvm::isGuaranteedNotToBePoison (Register Reg, const MachineRegisterInfo &MRI, unsigned Depth=0)
 Returns true if Reg cannot be poison, but may be undef.
 
bool llvm::isGuaranteedNotToBeUndef (Register Reg, const MachineRegisterInfo &MRI, unsigned Depth=0)
 Returns true if Reg cannot be undef, but may be poison.
 
Typellvm::getTypeForLLT (LLT Ty, LLVMContext &C)
 Get the type back from LLT.
 

Macro Definition Documentation

◆ GISEL_VECREDUCE_CASES_ALL

#define GISEL_VECREDUCE_CASES_ALL
Value:
case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
case TargetOpcode::G_VECREDUCE_FADD: \
case TargetOpcode::G_VECREDUCE_FMUL: \
case TargetOpcode::G_VECREDUCE_FMAX: \
case TargetOpcode::G_VECREDUCE_FMIN: \
case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
case TargetOpcode::G_VECREDUCE_FMINIMUM: \
case TargetOpcode::G_VECREDUCE_ADD: \
case TargetOpcode::G_VECREDUCE_MUL: \
case TargetOpcode::G_VECREDUCE_AND: \
case TargetOpcode::G_VECREDUCE_OR: \
case TargetOpcode::G_VECREDUCE_XOR: \
case TargetOpcode::G_VECREDUCE_SMAX: \
case TargetOpcode::G_VECREDUCE_SMIN: \
case TargetOpcode::G_VECREDUCE_UMAX: \
case TargetOpcode::G_VECREDUCE_UMIN:

Definition at line 55 of file Utils.h.

◆ GISEL_VECREDUCE_CASES_NONSEQ

#define GISEL_VECREDUCE_CASES_NONSEQ
Value:
case TargetOpcode::G_VECREDUCE_FADD: \
case TargetOpcode::G_VECREDUCE_FMUL: \
case TargetOpcode::G_VECREDUCE_FMAX: \
case TargetOpcode::G_VECREDUCE_FMIN: \
case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
case TargetOpcode::G_VECREDUCE_FMINIMUM: \
case TargetOpcode::G_VECREDUCE_ADD: \
case TargetOpcode::G_VECREDUCE_MUL: \
case TargetOpcode::G_VECREDUCE_AND: \
case TargetOpcode::G_VECREDUCE_OR: \
case TargetOpcode::G_VECREDUCE_XOR: \
case TargetOpcode::G_VECREDUCE_SMAX: \
case TargetOpcode::G_VECREDUCE_SMIN: \
case TargetOpcode::G_VECREDUCE_UMAX: \
case TargetOpcode::G_VECREDUCE_UMIN:

Definition at line 74 of file Utils.h.