69#include "llvm/Config/llvm-config.h"
99#define DEBUG_TYPE "pipeliner"
101STATISTIC(NumTrytoPipeline,
"Number of loops that we attempt to pipeline");
102STATISTIC(NumPipelined,
"Number of loops software pipelined");
103STATISTIC(NumNodeOrderIssues,
"Number of node order issues found");
104STATISTIC(NumFailBranch,
"Pipeliner abort due to unknown branch");
105STATISTIC(NumFailLoop,
"Pipeliner abort due to unsupported loop");
106STATISTIC(NumFailPreheader,
"Pipeliner abort due to missing preheader");
107STATISTIC(NumFailLargeMaxMII,
"Pipeliner abort due to MaxMII too large");
108STATISTIC(NumFailZeroMII,
"Pipeliner abort due to zero MII");
109STATISTIC(NumFailNoSchedule,
"Pipeliner abort due to no schedule found");
110STATISTIC(NumFailZeroStage,
"Pipeliner abort due to zero stage");
111STATISTIC(NumFailLargeMaxStage,
"Pipeliner abort due to too many stages");
115 cl::desc(
"Enable Software Pipelining"));
124 cl::desc(
"Size limit for the MII."),
130 cl::desc(
"Force pipeliner to use specified II."),
136 cl::desc(
"Maximum stages allowed in the generated scheduled."),
143 cl::desc(
"Prune dependences between unrelated Phi nodes."),
150 cl::desc(
"Prune loop carried order dependences."),
168 cl::desc(
"Instead of emitting the pipelined code, annotate instructions "
169 "with the generated schedule for feeding into the "
170 "-modulo-schedule-test pass"));
175 "Use the experimental peeling code generator for software pipelining"));
182 cl::desc(
"Enable CopyToPhi DAG Mutation"));
187 "pipeliner-force-issue-width",
193unsigned SwingSchedulerDAG::Circuits::MaxPaths = 5;
201 "Modulo Software Pipelining",
false,
false)
211 if (skipFunction(mf.getFunction()))
217 if (mf.getFunction().getAttributes().hasFnAttr(Attribute::OptimizeForSize) &&
221 if (!mf.getSubtarget().enableMachinePipeliner())
226 if (mf.getSubtarget().useDFAforSMS() &&
227 (!mf.getSubtarget().getInstrItineraryData() ||
228 mf.getSubtarget().getInstrItineraryData()->isEmpty()))
232 MLI = &getAnalysis<MachineLoopInfo>();
233 MDT = &getAnalysis<MachineDominatorTree>();
234 ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
235 TII = MF->getSubtarget().getInstrInfo();
236 RegClassInfo.runOnMachineFunction(*MF);
238 for (
const auto &L : *MLI)
248bool MachinePipeliner::scheduleLoop(
MachineLoop &L) {
249 bool Changed =
false;
250 for (
const auto &InnerLoop : L)
251 Changed |= scheduleLoop(*InnerLoop);
263 setPragmaPipelineOptions(L);
264 if (!canPipelineLoop(L)) {
268 L.getStartLoc(), L.getHeader())
269 <<
"Failed to pipeline loop";
278 Changed = swingModuloScheduler(L);
284void MachinePipeliner::setPragmaPipelineOptions(
MachineLoop &L) {
303 if (LoopID ==
nullptr)
320 if (S->
getString() ==
"llvm.loop.pipeline.initiationinterval") {
322 "Pipeline initiation interval hint metadata should have two operands.");
324 mdconst::extract<ConstantInt>(MD->
getOperand(1))->getZExtValue();
326 }
else if (S->
getString() ==
"llvm.loop.pipeline.disable") {
335bool MachinePipeliner::canPipelineLoop(
MachineLoop &L) {
340 <<
"Not a single basic block: "
350 <<
"Disabled by Pragma.";
361 LLVM_DEBUG(
dbgs() <<
"Unable to analyzeBranch, can NOT pipeline Loop\n");
366 <<
"The branch can't be understood";
375 LLVM_DEBUG(
dbgs() <<
"Unable to analyzeLoop, can NOT pipeline Loop\n");
380 <<
"The loop structure is not supported";
386 LLVM_DEBUG(
dbgs() <<
"Preheader not found, can NOT pipeline Loop\n");
391 <<
"No loop preheader found";
403 SlotIndexes &Slots = *getAnalysis<LiveIntervals>().getSlotIndexes();
408 auto *RC =
MRI.getRegClass(DefOp.
getReg());
410 for (
unsigned i = 1, n = PI.getNumOperands(); i != n; i += 2) {
435bool MachinePipeliner::swingModuloScheduler(
MachineLoop &L) {
436 assert(L.
getBlocks().size() == 1 &&
"SMS works on single blocks only.");
459 return SMS.hasNewSchedule();
472void SwingSchedulerDAG::setMII(
unsigned ResMII,
unsigned RecMII) {
475 else if (II_setByPragma > 0)
476 MII = II_setByPragma;
478 MII = std::max(ResMII, RecMII);
481void SwingSchedulerDAG::setMAX_II() {
484 else if (II_setByPragma > 0)
485 MAX_II = II_setByPragma;
495 addLoopCarriedDependences(AA);
496 updatePhiDependences();
503 findCircuits(NodeSets);
507 unsigned ResMII = calculateResMII();
508 unsigned RecMII = calculateRecMII(NodeSets);
516 setMII(ResMII, RecMII);
520 <<
" (rec=" << RecMII <<
", res=" << ResMII <<
")\n");
526 Pass.ORE->emit([&]() {
529 <<
"Invalid Minimal Initiation Interval: 0";
537 <<
", we don't pipeline large loops\n");
538 NumFailLargeMaxMII++;
539 Pass.ORE->emit([&]() {
542 <<
"Minimal Initiation Interval too large: "
543 <<
ore::NV(
"MII", (
int)MII) <<
" > "
545 <<
"Refer to -pipeliner-max-mii.";
550 computeNodeFunctions(NodeSets);
552 registerPressureFilter(NodeSets);
554 colocateNodeSets(NodeSets);
556 checkNodeSets(NodeSets);
559 for (
auto &
I : NodeSets) {
560 dbgs() <<
" Rec NodeSet ";
567 groupRemainingNodes(NodeSets);
569 removeDuplicateNodes(NodeSets);
572 for (
auto &
I : NodeSets) {
573 dbgs() <<
" NodeSet ";
578 computeNodeOrder(NodeSets);
581 checkValidNodeOrder(Circuits);
584 Scheduled = schedulePipeline(Schedule);
589 Pass.ORE->emit([&]() {
592 <<
"Unable to find schedule";
599 if (numStages == 0) {
602 Pass.ORE->emit([&]() {
605 <<
"No need to pipeline - no overlapped iterations in schedule.";
612 <<
" : too many stages, abort\n");
613 NumFailLargeMaxStage++;
614 Pass.ORE->emit([&]() {
617 <<
"Too many stages in schedule: "
618 <<
ore::NV(
"numStages", (
int)numStages) <<
" > "
620 <<
". Refer to -pipeliner-max-stages.";
625 Pass.ORE->emit([&]() {
628 <<
"Pipelined succesfully!";
633 std::vector<MachineInstr *> OrderedInsts;
637 OrderedInsts.push_back(SU->getInstr());
638 Cycles[SU->getInstr()] =
Cycle;
643 for (
auto &KV : NewMIs) {
644 Cycles[KV.first] = Cycles[KV.second];
645 Stages[KV.first] = Stages[KV.second];
646 NewInstrChanges[KV.first] = InstrChanges[
getSUnit(KV.first)];
653 "Cannot serialize a schedule with InstrChanges!");
672 for (
auto &KV : NewMIs)
683 unsigned &InitVal,
unsigned &LoopVal) {
694 assert(InitVal != 0 && LoopVal != 0 &&
"Unexpected Phi structure.");
710 while (!Worklist.
empty()) {
712 for (
const auto &
SI : SU->
Succs) {
715 if (Visited.
count(SuccSU))
730 return MI.isCall() ||
MI.mayRaiseFPException() ||
731 MI.hasUnmodeledSideEffects() ||
732 (
MI.hasOrderedMemoryRef() &&
733 (!
MI.mayLoad() || !
MI.isDereferenceableInvariantLoad()));
741 if (!
MI->hasOneMemOperand())
747 for (
const Value *V : Objs) {
760void SwingSchedulerDAG::addLoopCarriedDependences(
AliasAnalysis *AA) {
767 PendingLoads.
clear();
768 else if (
MI.mayLoad()) {
773 for (
const auto *V : Objs) {
777 }
else if (
MI.mayStore()) {
782 for (
const auto *V : Objs) {
784 PendingLoads.
find(V);
785 if (
I == PendingLoads.
end())
787 for (
auto *Load :
I->second) {
795 int64_t Offset1, Offset2;
796 bool Offset1IsScalable, Offset2IsScalable;
798 Offset1IsScalable,
TRI) &&
800 Offset2IsScalable,
TRI)) {
802 Offset1IsScalable == Offset2IsScalable &&
803 (
int)Offset1 < (
int)Offset2) {
805 "What happened to the chain edge?");
856void SwingSchedulerDAG::updatePhiDependences() {
864 unsigned HasPhiUse = 0;
865 unsigned HasPhiDef = 0;
869 MOE =
MI->operands_end();
891 if (SU->
NodeNum <
I.NodeNum && !
I.isPred(SU))
896 }
else if (MOI->isUse()) {
899 if (
DefMI ==
nullptr)
906 ST.adjustSchedDependency(SU, 0, &
I,
MI->getOperandNo(MOI), Dep);
912 if (SU->
NodeNum <
I.NodeNum && !
I.isPred(SU))
921 for (
auto &PI :
I.Preds) {
924 if (
I.getInstr()->isPHI()) {
933 for (
int i = 0, e = RemoveDeps.
size(); i != e; ++i)
934 I.removePred(RemoveDeps[i]);
940void SwingSchedulerDAG::changeDependences() {
945 unsigned BasePos = 0, OffsetPos = 0, NewBase = 0;
946 int64_t NewOffset = 0;
947 if (!canUseLastOffsetValue(
I.getInstr(), BasePos, OffsetPos, NewBase,
952 Register OrigBase =
I.getInstr()->getOperand(BasePos).getReg();
972 for (
const SDep &
P :
I.Preds)
973 if (
P.getSUnit() == DefSU)
975 for (
int i = 0, e = Deps.
size(); i != e; i++) {
977 I.removePred(Deps[i]);
981 for (
auto &
P : LastSU->
Preds)
984 for (
int i = 0, e = Deps.
size(); i != e; i++) {
997 InstrChanges[&
I] = std::make_pair(NewBase, NewOffset);
1005struct FuncUnitSorter {
1011 : InstrItins(TSI.getInstrItineraryData()), STI(&TSI) {}
1019 unsigned min = UINT_MAX;
1020 if (InstrItins && !InstrItins->
isEmpty()) {
1023 InstrItins->
endStage(SchedClass))) {
1026 if (numAlternatives <
min) {
1027 min = numAlternatives;
1048 unsigned NumUnits = ProcResource->
NumUnits;
1049 if (NumUnits <
min) {
1051 F = PRE.ProcResourceIdx;
1056 llvm_unreachable(
"Should have non-empty InstrItins or hasInstrSchedModel!");
1065 unsigned SchedClass =
MI.getDesc().getSchedClass();
1066 if (InstrItins && !InstrItins->
isEmpty()) {
1069 InstrItins->
endStage(SchedClass))) {
1072 Resources[FuncUnits]++;
1089 Resources[PRE.ProcResourceIdx]++;
1093 llvm_unreachable(
"Should have non-empty InstrItins or hasInstrSchedModel!");
1099 unsigned MFUs1 = minFuncUnits(IS1, F1);
1100 unsigned MFUs2 = minFuncUnits(IS2, F2);
1103 return MFUs1 > MFUs2;
1115unsigned SwingSchedulerDAG::calculateResMII() {
1118 return RM.calculateResMII();
1127unsigned SwingSchedulerDAG::calculateRecMII(NodeSetType &NodeSets) {
1128 unsigned RecMII = 0;
1130 for (
NodeSet &Nodes : NodeSets) {
1134 unsigned Delay = Nodes.getLatency();
1135 unsigned Distance = 1;
1138 unsigned CurMII = (Delay + Distance - 1) / Distance;
1139 Nodes.setRecMII(CurMII);
1140 if (CurMII > RecMII)
1151 for (
SUnit &SU : SUnits) {
1154 DepsAdded.
push_back(std::make_pair(&SU, Pred));
1156 for (std::pair<SUnit *, SDep> &
P : DepsAdded) {
1160 SUnit *TargetSU =
D.getSUnit();
1161 unsigned Reg =
D.getReg();
1162 unsigned Lat =
D.getLatency();
1171void SwingSchedulerDAG::Circuits::createAdjacencyStructure(
1175 for (
int i = 0, e = SUnits.size(); i != e; ++i) {
1178 for (
auto &SI : SUnits[i].Succs) {
1182 int N =
SI.getSUnit()->NodeNum;
1184 auto Dep = OutputDeps.
find(BackEdge);
1185 if (Dep != OutputDeps.
end()) {
1186 BackEdge = Dep->second;
1187 OutputDeps.
erase(Dep);
1189 OutputDeps[
N] = BackEdge;
1193 if (
SI.getSUnit()->isBoundaryNode() ||
SI.isArtificial() ||
1194 (
SI.getKind() ==
SDep::Anti && !
SI.getSUnit()->getInstr()->isPHI()))
1196 int N =
SI.getSUnit()->NodeNum;
1198 AdjK[i].push_back(
N);
1204 for (
auto &PI : SUnits[i].Preds) {
1205 if (!SUnits[i].getInstr()->mayStore() ||
1208 if (PI.getKind() ==
SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) {
1209 int N = PI.getSUnit()->NodeNum;
1211 AdjK[i].push_back(
N);
1218 for (
auto &OD : OutputDeps)
1219 if (!
Added.test(OD.second)) {
1220 AdjK[OD.first].push_back(OD.second);
1221 Added.set(OD.second);
1227bool SwingSchedulerDAG::Circuits::circuit(
int V,
int S, NodeSetType &NodeSets,
1229 SUnit *SV = &SUnits[V];
1234 for (
auto W : AdjK[V]) {
1235 if (NumPaths > MaxPaths)
1245 }
else if (!Blocked.test(W)) {
1246 if (circuit(W, S, NodeSets,
1247 Node2Idx->at(W) < Node2Idx->at(V) ?
true : HasBackedge))
1255 for (
auto W : AdjK[V]) {
1266void SwingSchedulerDAG::Circuits::unblock(
int U) {
1269 while (!BU.
empty()) {
1271 assert(SI != BU.
end() &&
"Invalid B set.");
1274 if (Blocked.test(
W->NodeNum))
1275 unblock(
W->NodeNum);
1281void SwingSchedulerDAG::findCircuits(NodeSetType &NodeSets) {
1286 Circuits Cir(
SUnits, Topo);
1288 Cir.createAdjacencyStructure(
this);
1289 for (
int i = 0, e =
SUnits.size(); i != e; ++i) {
1291 Cir.circuit(i, i, NodeSets);
1327 for (
auto &Dep : SU.
Preds) {
1328 SUnit *TmpSU = Dep.getSUnit();
1340 if (PHISUs.
size() == 0 || SrcSUs.
size() == 0)
1348 for (
auto &Dep : PHISUs[
Index]->Succs) {
1352 SUnit *TmpSU = Dep.getSUnit();
1362 if (UseSUs.
size() == 0)
1367 for (
auto *
I : UseSUs) {
1368 for (
auto *Src : SrcSUs) {
1382 if (
D.isArtificial() ||
D.getSUnit()->isBoundaryNode())
1393void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
1394 ScheduleInfo.resize(
SUnits.size());
1397 for (
int I : Topo) {
1405 for (
int I : Topo) {
1407 int zeroLatencyDepth = 0;
1411 if (
P.getLatency() == 0)
1416 asap = std::max(asap, (
int)(
getASAP(
pred) +
P.getLatency() -
1419 maxASAP = std::max(maxASAP, asap);
1420 ScheduleInfo[
I].ASAP = asap;
1421 ScheduleInfo[
I].ZeroLatencyDepth = zeroLatencyDepth;
1427 int zeroLatencyHeight = 0;
1442 ScheduleInfo[
I].ALAP = alap;
1443 ScheduleInfo[
I].ZeroLatencyHeight = zeroLatencyHeight;
1448 I.computeNodeSetInfo(
this);
1451 for (
unsigned i = 0; i <
SUnits.size(); i++) {
1452 dbgs() <<
"\tNode " << i <<
":\n";
1473 if (S && S->count(Pred.
getSUnit()) == 0)
1484 if (S && S->count(Succ.
getSUnit()) == 0)
1490 return !Preds.
empty();
1502 if (S && S->count(Succ.
getSUnit()) == 0)
1512 if (S && S->count(Pred.
getSUnit()) == 0)
1518 return !Succs.
empty();
1533 if (!Visited.
insert(Cur).second)
1534 return Path.contains(Cur);
1535 bool FoundPath =
false;
1539 computePath(
SI.getSUnit(), Path, DestNodes, Exclude, Visited);
1540 for (
auto &PI : Cur->
Preds)
1543 computePath(PI.getSUnit(), Path, DestNodes, Exclude, Visited);
1558 for (
SUnit *SU : NS) {
1563 if (MO.isReg() && MO.isUse()) {
1565 if (Reg.isVirtual())
1567 else if (
MRI.isAllocatable(Reg))
1570 Uses.insert(*Units);
1573 for (
SUnit *SU : NS)
1575 if (MO.isReg() && MO.isDef() && !MO.isDead()) {
1577 if (Reg.isVirtual()) {
1578 if (!
Uses.count(Reg))
1581 }
else if (
MRI.isAllocatable(Reg)) {
1584 if (!
Uses.count(*Units))
1594void SwingSchedulerDAG::registerPressureFilter(NodeSetType &NodeSets) {
1595 for (
auto &NS : NodeSets) {
1601 RecRPTracker.init(&
MF, &RegClassInfo, &LIS,
BB,
BB->
end(),
false,
true);
1603 RecRPTracker.closeBottom();
1605 std::vector<SUnit *>
SUnits(NS.begin(), NS.end());
1607 return A->NodeNum >
B->NodeNum;
1610 for (
auto &SU :
SUnits) {
1616 RecRPTracker.setPos(std::next(CurInstI));
1620 RecRPTracker.getMaxUpwardPressureDelta(SU->
getInstr(),
nullptr, RPDelta,
1625 dbgs() <<
"Excess register pressure: SU(" << SU->
NodeNum <<
") "
1628 NS.setExceedPressure(SU);
1631 RecRPTracker.recede();
1638void SwingSchedulerDAG::colocateNodeSets(NodeSetType &NodeSets) {
1639 unsigned Colocate = 0;
1640 for (
int i = 0, e = NodeSets.size(); i < e; ++i) {
1645 for (
int j = i + 1; j <
e; ++j) {
1666void SwingSchedulerDAG::checkNodeSets(NodeSetType &NodeSets) {
1671 for (
auto &NS : NodeSets) {
1672 if (NS.getRecMII() > 2)
1674 if (NS.getMaxDepth() > MII)
1683void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
1711 NodesAdded.
insert(
I.begin(),
I.end());
1720 addConnectedNodes(
I, NewSet, NodesAdded);
1721 if (!NewSet.
empty())
1722 NodeSets.push_back(NewSet);
1729 addConnectedNodes(
I, NewSet, NodesAdded);
1730 if (!NewSet.
empty())
1731 NodeSets.push_back(NewSet);
1736 if (NodesAdded.
count(&SU) == 0) {
1738 addConnectedNodes(&SU, NewSet, NodesAdded);
1739 if (!NewSet.
empty())
1740 NodeSets.push_back(NewSet);
1746void SwingSchedulerDAG::addConnectedNodes(
SUnit *SU,
NodeSet &NewSet,
1750 for (
auto &SI : SU->
Succs) {
1752 if (!
SI.isArtificial() && !
Successor->isBoundaryNode() &&
1754 addConnectedNodes(
Successor, NewSet, NodesAdded);
1756 for (
auto &PI : SU->
Preds) {
1757 SUnit *Predecessor = PI.getSUnit();
1758 if (!PI.isArtificial() && NodesAdded.
count(Predecessor) == 0)
1759 addConnectedNodes(Predecessor, NewSet, NodesAdded);
1768 for (
SUnit *SU : Set1) {
1769 if (Set2.
count(SU) != 0)
1772 return !Result.empty();
1776void SwingSchedulerDAG::fuseRecs(NodeSetType &NodeSets) {
1785 for (
SUnit *SU : *J)
1797void SwingSchedulerDAG::removeDuplicateNodes(NodeSetType &NodeSets) {
1801 J->remove_if([&](
SUnit *SUJ) {
return I->count(SUJ); });
1816void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
1820 for (
auto &Nodes : NodeSets) {
1825 R.insert(
N.begin(),
N.end());
1829 R.insert(
N.begin(),
N.end());
1837 }
else if (NodeSets.size() == 1) {
1838 for (
const auto &
N : Nodes)
1839 if (
N->Succs.size() == 0)
1845 SUnit *maxASAP =
nullptr;
1846 for (
SUnit *SU : Nodes) {
1856 while (!
R.empty()) {
1857 if (Order == TopDown) {
1861 while (!
R.empty()) {
1862 SUnit *maxHeight =
nullptr;
1875 NodeOrder.insert(maxHeight);
1877 R.remove(maxHeight);
1878 for (
const auto &
I : maxHeight->
Succs) {
1879 if (Nodes.count(
I.getSUnit()) == 0)
1881 if (NodeOrder.contains(
I.getSUnit()))
1885 R.insert(
I.getSUnit());
1888 for (
const auto &
I : maxHeight->
Preds) {
1891 if (Nodes.count(
I.getSUnit()) == 0)
1893 if (NodeOrder.contains(
I.getSUnit()))
1895 R.insert(
I.getSUnit());
1901 if (
pred_L(NodeOrder,
N, &Nodes))
1902 R.insert(
N.begin(),
N.end());
1907 while (!
R.empty()) {
1908 SUnit *maxDepth =
nullptr;
1920 NodeOrder.insert(maxDepth);
1923 if (Nodes.isExceedSU(maxDepth)) {
1926 R.insert(Nodes.getNode(0));
1929 for (
const auto &
I : maxDepth->
Preds) {
1930 if (Nodes.count(
I.getSUnit()) == 0)
1932 if (NodeOrder.contains(
I.getSUnit()))
1934 R.insert(
I.getSUnit());
1937 for (
const auto &
I : maxDepth->
Succs) {
1940 if (Nodes.count(
I.getSUnit()) == 0)
1942 if (NodeOrder.contains(
I.getSUnit()))
1944 R.insert(
I.getSUnit());
1950 if (
succ_L(NodeOrder,
N, &Nodes))
1951 R.insert(
N.begin(),
N.end());
1958 dbgs() <<
"Node order: ";
1959 for (
SUnit *
I : NodeOrder)
1960 dbgs() <<
" " <<
I->NodeNum <<
" ";
1967bool SwingSchedulerDAG::schedulePipeline(
SMSchedule &Schedule) {
1969 if (NodeOrder.empty()){
1974 bool scheduleFound =
false;
1976 for (
unsigned II = MII; II <= MAX_II && !scheduleFound; ++II) {
1988 int EarlyStart = INT_MIN;
1989 int LateStart = INT_MAX;
1992 int SchedEnd = INT_MAX;
1993 int SchedStart = INT_MIN;
1994 Schedule.
computeStart(SU, &EarlyStart, &LateStart, &SchedEnd, &SchedStart,
2003 dbgs() <<
format(
"\tes: %8x ls: %8x me: %8x ms: %8x\n", EarlyStart,
2004 LateStart, SchedEnd, SchedStart);
2007 if (EarlyStart > LateStart || SchedEnd < EarlyStart ||
2008 SchedStart > LateStart)
2009 scheduleFound =
false;
2010 else if (EarlyStart != INT_MIN && LateStart == INT_MAX) {
2011 SchedEnd = std::min(SchedEnd, EarlyStart + (
int)II - 1);
2012 scheduleFound = Schedule.
insert(SU, EarlyStart, SchedEnd, II);
2013 }
else if (EarlyStart == INT_MIN && LateStart != INT_MAX) {
2014 SchedStart = std::max(SchedStart, LateStart - (
int)II + 1);
2015 scheduleFound = Schedule.
insert(SU, LateStart, SchedStart, II);
2016 }
else if (EarlyStart != INT_MIN && LateStart != INT_MAX) {
2018 std::min(SchedEnd, std::min(LateStart, EarlyStart + (
int)II - 1));
2023 scheduleFound = Schedule.
insert(SU, SchedEnd, EarlyStart, II);
2025 scheduleFound = Schedule.
insert(SU, EarlyStart, SchedEnd, II);
2028 scheduleFound = Schedule.
insert(SU, FirstCycle +
getASAP(SU),
2029 FirstCycle +
getASAP(SU) + II - 1, II);
2036 scheduleFound =
false;
2040 dbgs() <<
"\tCan't schedule\n";
2042 }
while (++NI != NE && scheduleFound);
2058 if (scheduleFound) {
2064 if (scheduleFound) {
2066 Pass.ORE->emit([&]() {
2069 <<
"Schedule found with Initiation Interval: "
2071 <<
", MaxStageCount: "
2082bool SwingSchedulerDAG::computeDelta(
MachineInstr &
MI,
unsigned &Delta) {
2086 bool OffsetIsScalable;
2091 if (OffsetIsScalable)
2094 if (!BaseOp->
isReg())
2102 if (BaseDef && BaseDef->
isPHI()) {
2126 unsigned &OffsetPos,
2132 unsigned BasePosLd, OffsetPosLd;
2135 Register BaseReg =
MI->getOperand(BasePosLd).getReg();
2140 if (!Phi || !Phi->
isPHI())
2149 if (!PrevDef || PrevDef ==
MI)
2155 unsigned BasePos1 = 0, OffsetPos1 = 0;
2161 int64_t LoadOffset =
MI->getOperand(OffsetPosLd).getImm();
2171 BasePos = BasePosLd;
2172 OffsetPos = OffsetPosLd;
2184 InstrChanges.find(SU);
2185 if (It != InstrChanges.end()) {
2186 std::pair<unsigned, int64_t> RegAndOffset = It->second;
2187 unsigned BasePos, OffsetPos;
2190 Register BaseReg =
MI->getOperand(BasePos).getReg();
2196 if (BaseStageNum < DefStageNum) {
2198 int OffsetDiff = DefStageNum - BaseStageNum;
2199 if (DefCycleNum < BaseCycleNum) {
2205 MI->getOperand(OffsetPos).getImm() + RegAndOffset.second * OffsetDiff;
2220 while (Def->isPHI()) {
2221 if (!Visited.
insert(Def).second)
2223 for (
unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2)
2224 if (Def->getOperand(i + 1).getMBB() ==
BB) {
2251 assert(
SI !=
nullptr && DI !=
nullptr &&
"Expecting SUnit with an MI.");
2263 unsigned DeltaS, DeltaD;
2264 if (!computeDelta(*
SI, DeltaS) || !computeDelta(*DI, DeltaD))
2268 int64_t OffsetS, OffsetD;
2269 bool OffsetSIsScalable, OffsetDIsScalable;
2277 assert(!OffsetSIsScalable && !OffsetDIsScalable &&
2278 "Expected offsets to be byte offsets");
2282 if (!DefS || !DefD || !DefS->
isPHI() || !DefD->
isPHI())
2285 unsigned InitValS = 0;
2286 unsigned LoopValS = 0;
2287 unsigned InitValD = 0;
2288 unsigned LoopValD = 0;
2313 if (DeltaS != DeltaD || DeltaS < AccessSizeS || DeltaD < AccessSizeD)
2316 return (OffsetS + (int64_t)AccessSizeS < OffsetD + (int64_t)AccessSizeD);
2319void SwingSchedulerDAG::postprocessDAG() {
2320 for (
auto &M : Mutations)
2330 bool forward =
true;
2332 dbgs() <<
"Trying to insert node between " << StartCycle <<
" and "
2333 << EndCycle <<
" II: " << II <<
"\n";
2335 if (StartCycle > EndCycle)
2339 int termCycle = forward ? EndCycle + 1 : EndCycle - 1;
2340 for (
int curCycle = StartCycle; curCycle != termCycle;
2341 forward ? ++curCycle : --curCycle) {
2346 dbgs() <<
"\tinsert at cycle " << curCycle <<
" ";
2351 ProcItinResources.reserveResources(*SU, curCycle);
2352 ScheduledInstrs[curCycle].push_back(SU);
2353 InstrToCycle.insert(std::make_pair(SU, curCycle));
2354 if (curCycle > LastCycle)
2355 LastCycle = curCycle;
2356 if (curCycle < FirstCycle)
2357 FirstCycle = curCycle;
2361 dbgs() <<
"\tfailed to insert at cycle " << curCycle <<
" ";
2373 int EarlyCycle = INT_MAX;
2374 while (!Worklist.
empty()) {
2377 if (Visited.
count(PrevSU))
2379 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(PrevSU);
2380 if (it == InstrToCycle.end())
2382 EarlyCycle = std::min(EarlyCycle, it->second);
2383 for (
const auto &PI : PrevSU->
Preds)
2396 int LateCycle = INT_MIN;
2397 while (!Worklist.
empty()) {
2402 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SuccSU);
2403 if (it == InstrToCycle.end())
2405 LateCycle = std::max(LateCycle, it->second);
2406 for (
const auto &
SI : SuccSU->
Succs)
2418 for (
auto &
P : SU->
Preds)
2419 if (DAG->
isBackedge(SU,
P) &&
P.getSUnit()->getInstr()->isPHI())
2420 for (
auto &S :
P.getSUnit()->Succs)
2422 return P.getSUnit();
2429 int *MinEnd,
int *MaxStart,
int II,
2434 for (
int cycle =
getFirstCycle(); cycle <= LastCycle; ++cycle) {
2440 for (
unsigned i = 0, e = (
unsigned)SU->
Preds.size(); i != e; ++i) {
2446 *MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart);
2449 *MinEnd = std::min(*MinEnd, End);
2454 *MinLateStart = std::min(*MinLateStart, LateStart);
2462 *MinLateStart = std::min(*MinLateStart, cycle);
2464 for (
unsigned i = 0, e = (
unsigned)SU->
Succs.size(); i != e; ++i) {
2465 if (SU->
Succs[i].getSUnit() ==
I) {
2470 *MinLateStart = std::min(*MinLateStart, LateStart);
2473 *MaxStart = std::max(*MaxStart, Start);
2478 *MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart);
2490 std::deque<SUnit *> &Insts) {
2492 bool OrderBeforeUse =
false;
2493 bool OrderAfterDef =
false;
2494 bool OrderBeforeDef =
false;
2495 unsigned MoveDef = 0;
2496 unsigned MoveUse = 0;
2500 for (std::deque<SUnit *>::iterator
I = Insts.begin(),
E = Insts.end();
I !=
E;
2503 if (!MO.isReg() || !MO.getReg().isVirtual())
2507 unsigned BasePos, OffsetPos;
2508 if (ST.getInstrInfo()->getBaseAndOffsetPosition(*
MI, BasePos, OffsetPos))
2509 if (
MI->getOperand(BasePos).getReg() == Reg)
2513 std::tie(Reads, Writes) =
2514 (*I)->getInstr()->readsWritesVirtualRegister(Reg);
2516 OrderBeforeUse =
true;
2521 OrderAfterDef =
true;
2523 }
else if (MO.isUse() && Writes &&
stageScheduled(*
I) == StageInst1) {
2525 OrderBeforeUse =
true;
2529 OrderAfterDef =
true;
2533 OrderBeforeUse =
true;
2537 OrderAfterDef =
true;
2542 OrderBeforeUse =
true;
2548 OrderBeforeDef =
true;
2555 for (
auto &S : SU->
Succs) {
2559 OrderBeforeUse =
true;
2567 OrderBeforeUse =
true;
2568 if ((MoveUse == 0) || (Pos < MoveUse))
2572 for (
auto &
P : SU->
Preds) {
2573 if (
P.getSUnit() != *
I)
2576 OrderAfterDef =
true;
2583 if (OrderAfterDef && OrderBeforeUse && MoveUse == MoveDef)
2584 OrderBeforeUse =
false;
2589 OrderBeforeUse = !OrderAfterDef || (MoveUse > MoveDef);
2593 if (OrderBeforeUse && OrderAfterDef) {
2594 SUnit *UseSU = Insts.at(MoveUse);
2595 SUnit *DefSU = Insts.at(MoveDef);
2596 if (MoveUse > MoveDef) {
2597 Insts.erase(Insts.begin() + MoveUse);
2598 Insts.erase(Insts.begin() + MoveDef);
2600 Insts.erase(Insts.begin() + MoveDef);
2601 Insts.erase(Insts.begin() + MoveUse);
2611 Insts.push_front(SU);
2613 Insts.push_back(SU);
2625 unsigned InitVal = 0;
2626 unsigned LoopVal = 0;
2635 return (LoopCycle > DefCycle) || (LoopStage <= DefStage);
2652 if (!Phi || !Phi->
isPHI() || Phi->
getParent() != Def->getParent())
2657 for (
unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
2661 if (DMO.
getReg() == LoopReg)
2673 for (
auto &SU : SSD->
SUnits)
2677 while (!Worklist.
empty()) {
2679 if (DoNotPipeline.
count(SU))
2682 DoNotPipeline.
insert(SU);
2683 for (
auto &Dep : SU->
Preds)
2686 for (
auto &Dep : SU->
Succs)
2690 return DoNotPipeline;
2699 int NewLastCycle = INT_MIN;
2704 NewLastCycle = std::max(NewLastCycle, InstrToCycle[&SU]);
2710 for (
auto &Dep : SU.
Preds)
2711 NewCycle = std::max(InstrToCycle[Dep.getSUnit()], NewCycle);
2713 int OldCycle = InstrToCycle[&SU];
2714 if (OldCycle != NewCycle) {
2715 InstrToCycle[&SU] = NewCycle;
2720 <<
") is not pipelined; moving from cycle " << OldCycle
2721 <<
" to " << NewCycle <<
" Instr:" << *SU.
getInstr());
2723 NewLastCycle = std::max(NewLastCycle, NewCycle);
2725 LastCycle = NewLastCycle;
2742 int CycleDef = InstrToCycle[&SU];
2743 assert(StageDef != -1 &&
"Instruction should have been scheduled.");
2745 if (
SI.isAssignedRegDep() && !
SI.getSUnit()->isBoundaryNode())
2749 if (InstrToCycle[
SI.getSUnit()] <= CycleDef)
2766void SwingSchedulerDAG::checkValidNodeOrder(
const NodeSetType &Circuits)
const {
2769 typedef std::pair<SUnit *, unsigned> UnitIndex;
2770 std::vector<UnitIndex> Indices(NodeOrder.size(), std::make_pair(
nullptr, 0));
2772 for (
unsigned i = 0, s = NodeOrder.size(); i < s; ++i)
2773 Indices.push_back(std::make_pair(NodeOrder[i], i));
2775 auto CompareKey = [](UnitIndex i1, UnitIndex i2) {
2776 return std::get<0>(i1) < std::get<0>(i2);
2789 for (
unsigned i = 0, s = NodeOrder.size(); i < s; ++i) {
2790 SUnit *SU = NodeOrder[i];
2793 bool PredBefore =
false;
2794 bool SuccBefore =
false;
2803 unsigned PredIndex = std::get<1>(
2819 unsigned SuccIndex = std::get<1>(
2832 Circuits, [SU](
const NodeSet &Circuit) {
return Circuit.
count(SU); });
2837 NumNodeOrderIssues++;
2841 <<
" are scheduled before node " << SU->
NodeNum
2848 dbgs() <<
"Invalid node order found!\n";
2859 unsigned OverlapReg = 0;
2860 unsigned NewBaseReg = 0;
2861 for (
SUnit *SU : Instrs) {
2863 for (
unsigned i = 0, e =
MI->getNumOperands(); i < e; ++i) {
2871 InstrChanges.find(SU);
2872 if (It != InstrChanges.end()) {
2873 unsigned BasePos, OffsetPos;
2879 MI->getOperand(OffsetPos).getImm() - It->second.second;
2892 unsigned TiedUseIdx = 0;
2893 if (
MI->isRegTiedToUseOperand(i, &TiedUseIdx)) {
2895 OverlapReg =
MI->getOperand(TiedUseIdx).getReg();
2897 NewBaseReg =
MI->getOperand(i).getReg();
2912 std::deque<SUnit *> &cycleInstrs =
2913 ScheduledInstrs[cycle + (stage * InitiationInterval)];
2915 ScheduledInstrs[cycle].push_front(SU);
2921 for (
int cycle =
getFinalCycle() + 1; cycle <= LastCycle; ++cycle)
2922 ScheduledInstrs.erase(cycle);
2932 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[
Cycle];
2933 std::deque<SUnit *> newOrderPhi;
2934 for (
SUnit *SU : cycleInstrs) {
2936 newOrderPhi.push_back(SU);
2938 std::deque<SUnit *> newOrderI;
2939 for (
SUnit *SU : cycleInstrs) {
2944 cycleInstrs.swap(newOrderPhi);
2953 os <<
"Num nodes " <<
size() <<
" rec " << RecMII <<
" mov " << MaxMOV
2954 <<
" depth " << MaxDepth <<
" col " << Colocate <<
"\n";
2955 for (
const auto &
I : Nodes)
2956 os <<
" SU(" <<
I->NodeNum <<
") " << *(
I->getInstr());
2960#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
2967 for (
SUnit *CI : cycleInstrs->second) {
2969 os <<
"(" << CI->
NodeNum <<
") ";
2980void ResourceManager::dumpMRT()
const {
2984 std::stringstream SS;
2986 SS << std::setw(4) <<
"Slot";
2988 SS << std::setw(3) <<
I;
2989 SS << std::setw(7) <<
"#Mops"
2991 for (
int Slot = 0; Slot < InitiationInterval; ++Slot) {
2992 SS << std::setw(4) << Slot;
2994 SS << std::setw(3) << MRT[Slot][
I];
2995 SS << std::setw(7) << NumScheduledMops[Slot] <<
"\n";
3004 unsigned ProcResourceID = 0;
3009 "Too many kinds of resources, unsupported");
3017 Masks[
I] = 1ULL << ProcResourceID;
3025 Masks[
I] = 1ULL << ProcResourceID;
3026 for (
unsigned U = 0; U < Desc.
NumUnits; ++U)
3032 dbgs() <<
"ProcResourceDesc:\n";
3035 dbgs() <<
format(
" %16s(%2d): Mask: 0x%08x, NumUnits:%2d\n",
3036 ProcResource->
Name,
I, Masks[
I],
3039 dbgs() <<
" -----------------\n";
3047 dbgs() <<
"canReserveResources:\n";
3050 return DFAResources[positiveModulo(
Cycle, InitiationInterval)]
3056 dbgs() <<
"No valid Schedule Class Desc for schedClass!\n";
3062 reserveResources(SCDesc,
Cycle);
3063 bool Result = !isOverbooked();
3064 unreserveResources(SCDesc,
Cycle);
3073 dbgs() <<
"reserveResources:\n";
3076 return DFAResources[positiveModulo(
Cycle, InitiationInterval)]
3082 dbgs() <<
"No valid Schedule Class Desc for schedClass!\n";
3088 reserveResources(SCDesc,
Cycle);
3093 dbgs() <<
"reserveResources: done!\n\n";
3104 ++MRT[positiveModulo(
C, InitiationInterval)][PRE.ProcResourceIdx];
3107 ++NumScheduledMops[positiveModulo(
C, InitiationInterval)];
3116 --MRT[positiveModulo(
C, InitiationInterval)][PRE.ProcResourceIdx];
3119 --NumScheduledMops[positiveModulo(
C, InitiationInterval)];
3122bool ResourceManager::isOverbooked()
const {
3124 for (
int Slot = 0;
Slot < InitiationInterval; ++
Slot) {
3130 if (NumScheduledMops[Slot] > IssueWidth)
3136int ResourceManager::calculateResMIIDFA()
const {
3141 FuncUnitSorter FUS = FuncUnitSorter(*ST);
3143 FUS.calcCriticalResources(*SU.
getInstr());
3154 while (!FuncUnitOrder.empty()) {
3156 FuncUnitOrder.pop();
3163 unsigned ReservedCycles = 0;
3164 auto *RI = Resources.
begin();
3165 auto *RE = Resources.
end();
3167 dbgs() <<
"Trying to reserve resource for " << NumCycles
3168 <<
" cycles for \n";
3171 for (
unsigned C = 0;
C < NumCycles; ++
C)
3173 if ((*RI)->canReserveResources(*
MI)) {
3174 (*RI)->reserveResources(*
MI);
3181 <<
", NumCycles:" << NumCycles <<
"\n");
3183 for (
unsigned C = ReservedCycles;
C < NumCycles; ++
C) {
3185 <<
"NewResource created to reserve resources"
3188 assert(NewResource->canReserveResources(*
MI) &&
"Reserve error.");
3189 NewResource->reserveResources(*
MI);
3190 Resources.
push_back(std::unique_ptr<DFAPacketizer>(NewResource));
3194 int Resmii = Resources.
size();
3201 return calculateResMIIDFA();
3220 <<
" WriteProcRes: ";
3231 dbgs() << Desc->
Name <<
": " << PRE.Cycles <<
", ";
3234 ResourceCount[PRE.ProcResourceIdx] += PRE.Cycles;
3239 int Result = (NumMops + IssueWidth - 1) / IssueWidth;
3242 dbgs() <<
"#Mops: " << NumMops <<
", "
3243 <<
"IssueWidth: " << IssueWidth <<
", "
3244 <<
"Cycles: " << Result <<
"\n";
3249 std::stringstream SS;
3250 SS << std::setw(2) <<
"ID" << std::setw(16) <<
"Name" << std::setw(10)
3251 <<
"Units" << std::setw(10) <<
"Consumed" << std::setw(10) <<
"Cycles"
3261 std::stringstream SS;
3262 SS << std::setw(2) <<
I << std::setw(16) << Desc->
Name << std::setw(10)
3263 << Desc->
NumUnits << std::setw(10) << ResourceCount[
I]
3264 << std::setw(10) << Cycles <<
"\n";
3268 if (Cycles > Result)
3275 InitiationInterval = II;
3276 DFAResources.clear();
3277 DFAResources.resize(II);
3278 for (
auto &
I : DFAResources)
3279 I.reset(ST->getInstrInfo()->CreateTargetScheduleState(*ST));
3282 NumScheduledMops.
clear();
3283 NumScheduledMops.
resize(II);
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SmallPtrSet< MachineInstr *, 2 > Uses
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file declares an analysis pass that computes CycleInfo for LLVM IR, specialized from GenericCycl...
This file defines the DenseMap class.
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
static cl::opt< int > SwpForceII("pipeliner-force-ii", cl::desc("Force pipeliner to use specified II."), cl::Hidden, cl::init(-1))
A command line argument to force pipeliner to use specified initial interval.
static cl::opt< bool > ExperimentalCodeGen("pipeliner-experimental-cg", cl::Hidden, cl::init(false), cl::desc("Use the experimental peeling code generator for software pipelining"))
static bool pred_L(SetVector< SUnit * > &NodeOrder, SmallSetVector< SUnit *, 8 > &Preds, const NodeSet *S=nullptr)
Compute the Pred_L(O) set, as defined in the paper.
static unsigned getLoopPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB)
Return the Phi register value that comes the loop block.
static cl::opt< bool > SwpDebugResource("pipeliner-dbg-res", cl::Hidden, cl::init(false))
static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker, NodeSet &NS)
Compute the live-out registers for the instructions in a node-set.
static cl::opt< bool > EmitTestAnnotations("pipeliner-annotate-for-testing", cl::Hidden, cl::init(false), cl::desc("Instead of emitting the pipelined code, annotate instructions " "with the generated schedule for feeding into the " "-modulo-schedule-test pass"))
static bool isIntersect(SmallSetVector< SUnit *, 8 > &Set1, const NodeSet &Set2, SmallSetVector< SUnit *, 8 > &Result)
Return true if Set1 contains elements in Set2.
static cl::opt< bool > SwpIgnoreRecMII("pipeliner-ignore-recmii", cl::ReallyHidden, cl::desc("Ignore RecMII"))
static cl::opt< int > SwpLoopLimit("pipeliner-max", cl::Hidden, cl::init(-1))
static bool succ_L(SetVector< SUnit * > &NodeOrder, SmallSetVector< SUnit *, 8 > &Succs, const NodeSet *S=nullptr)
Compute the Succ_L(O) set, as defined in the paper.
Modulo Software Pipelining
static cl::opt< bool > SwpPruneLoopCarried("pipeliner-prune-loop-carried", cl::desc("Prune loop carried order dependences."), cl::Hidden, cl::init(true))
A command line option to disable the pruning of loop carried order dependences.
static bool isDependenceBarrier(MachineInstr &MI)
Return true if the instruction causes a chain between memory references before and after it.
static cl::opt< int > SwpMaxMii("pipeliner-max-mii", cl::desc("Size limit for the MII."), cl::Hidden, cl::init(27))
A command line argument to limit minimum initial interval for pipelining.
static void swapAntiDependences(std::vector< SUnit > &SUnits)
Swap all the anti dependences in the DAG.
static bool isSuccOrder(SUnit *SUa, SUnit *SUb)
Return true if SUb can be reached from SUa following the chain edges.
static cl::opt< int > SwpMaxStages("pipeliner-max-stages", cl::desc("Maximum stages allowed in the generated scheduled."), cl::Hidden, cl::init(3))
A command line argument to limit the number of stages in the pipeline.
static cl::opt< bool > EnableSWPOptSize("enable-pipeliner-opt-size", cl::desc("Enable SWP at Os."), cl::Hidden, cl::init(false))
A command line option to enable SWP at -Os.
static cl::opt< bool > SwpShowResMask("pipeliner-show-mask", cl::Hidden, cl::init(false))
static void getPhiRegs(MachineInstr &Phi, MachineBasicBlock *Loop, unsigned &InitVal, unsigned &LoopVal)
Return the register values for the operands of a Phi instruction.
static cl::opt< bool > EnableSWP("enable-pipeliner", cl::Hidden, cl::init(true), cl::desc("Enable Software Pipelining"))
A command line option to turn software pipelining on or off.
static bool ignoreDependence(const SDep &D, bool isPred)
Return true for DAG nodes that we ignore when computing the cost functions.
static cl::opt< bool > SwpPruneDeps("pipeliner-prune-deps", cl::desc("Prune dependences between unrelated Phi nodes."), cl::Hidden, cl::init(true))
A command line option to disable the pruning of chain dependences due to an unrelated Phi.
static SUnit * multipleIterations(SUnit *SU, SwingSchedulerDAG *DAG)
If an instruction has a use that spans multiple iterations, then return true.
static bool computePath(SUnit *Cur, SetVector< SUnit * > &Path, SetVector< SUnit * > &DestNodes, SetVector< SUnit * > &Exclude, SmallPtrSet< SUnit *, 8 > &Visited)
Return true if there is a path from the specified node to any of the nodes in DestNodes.
unsigned const TargetRegisterInfo * TRI
This file implements a map that provides insertion order iteration.
This file provides utility analysis objects describing memory locations.
return ToRemove size() > 0
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file defines the PriorityQueue class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines generic set operations that may be used on set's of different types,...
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static unsigned getSize(unsigned Kind)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM Basic Block Representation.
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
iterator find(const_arg_type_t< KeyT > Val)
bool erase(const KeyT &Val)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
A possibly irreducible generalization of a Loop.
Itinerary data supplied by a subtarget to be used by a target.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
bool isEmpty() const
Returns true if there are no itineraries.
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
unsigned getNumBlocks() const
Get the number of blocks in this loop in constant time.
BlockT * getHeader() const
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Represents a single loop in the control flow graph.
DebugLoc getStartLoc() const
Return the debug location of the start of this loop.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Generic base class for all target subtargets.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
const MDOperand & getOperand(unsigned I) const
unsigned getNumOperands() const
Return number of MDNode operands.
StringRef getString() const
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
instr_iterator instr_end()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void deleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
unsigned getNumOperands() const
Retuns the total number of operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isRegSequence() const
iterator_range< mop_iterator > operands()
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
const MachineOperand & getOperand(unsigned i) const
DebugLoc getStartLoc() const
Return the debug location of the start of this loop.
MachineBasicBlock * getTopBlock()
Return the "top" block in the loop, which is the first block in the linear layout,...
A description of a memory reference used in the backend.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
The main class in the implementation of the target independent software pipeliner pass.
const TargetInstrInfo * TII
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineOptimizationRemarkEmitter * ORE
RegisterClassInfo RegClassInfo
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
use_instr_iterator use_instr_begin(Register RegNo) const
static use_instr_iterator use_instr_end()
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
This class implements a map that also provides access to all stored values in a deterministic order.
iterator find(const KeyT &Key)
static MemoryLocation getAfter(const Value *Ptr, const AAMDNodes &AATags=AAMDNodes())
Return a location that may access any location after Ptr, while remaining within the underlying objec...
The ModuloScheduleExpander takes a ModuloSchedule and expands it in-place, rewriting the old loop and...
void cleanup()
Performs final cleanup after expansion.
void expand()
Performs the actual expansion.
Expander that simply annotates each scheduled instruction with a post-instr symbol that can be consum...
void annotate()
Performs the annotation.
Represents a schedule for a single-block loop.
A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...
SUnit * getNode(unsigned i) const
void print(raw_ostream &os) const
void setRecMII(unsigned mii)
unsigned count(SUnit *SU) const
void setColocate(unsigned c)
int compareRecMII(NodeSet &RHS)
LLVM_DUMP_METHOD void dump() const
Pass interface - Implemented by all 'passes'.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
A reimplementation of ModuloScheduleExpander.
PriorityQueue - This class behaves like std::priority_queue and provides a few additional convenience...
Track the current register pressure at some position in the instruction stream, and remember the high...
void addLiveRegs(ArrayRef< RegisterMaskPair > Regs)
Force liveness of virtual registers or physical register units.
Wrapper class representing virtual and physical registers.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
int calculateResMII() const
void initProcResourceVectors(const MCSchedModel &SM, SmallVectorImpl< uint64_t > &Masks)
void init(int II)
Initialize resources with the initiation interval II.
bool canReserveResources(SUnit &SU, int Cycle)
Check if the resources occupied by a machine instruction are available in the current state.
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Kind
These are the different kinds of scheduling dependencies.
@ Output
A register output-dependence (aka WAW).
@ Order
Any other ordering dependency.
@ Anti
A register anti-dependence (aka WAR).
@ Data
Regular data dependence (aka true-dependence).
void setLatency(unsigned Lat)
Sets the latency for this edge.
@ Barrier
An unknown scheduling barrier.
@ Artificial
Arbitrary strong DAG edge (no real dependence).
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for c...
This class represents the scheduled code.
int earliestCycleInChain(const SDep &Dep)
Return the cycle of the earliest scheduled instruction in the dependence chain.
void setInitiationInterval(int ii)
Set the initiation interval for this schedule.
SmallSet< SUnit *, 8 > computeUnpipelineableNodes(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
Determine transitive dependences of unpipelineable instructions.
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO)
Return true if the instruction is a definition that is loop carried and defines the use on the next i...
void dump() const
Utility function used for debugging to print the schedule.
bool insert(SUnit *SU, int StartCycle, int EndCycle, int II)
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the E...
unsigned getMaxStageCount()
Return the maximum stage count needed for this schedule.
void print(raw_ostream &os) const
Print the schedule information to the given output.
int latestCycleInChain(const SDep &Dep)
Return the cycle of the latest scheduled instruction in the dependence chain.
int stageScheduled(SUnit *SU) const
Return the stage for a scheduled instruction.
void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG)
Compute the scheduling start slot for the instruction.
bool isValidSchedule(SwingSchedulerDAG *SSD)
int getInitiationInterval() const
Return the initiation interval for this schedule.
std::deque< SUnit * > & getInstructions(int cycle)
Return the instructions that are scheduled at the specified cycle.
int getFirstCycle() const
Return the first cycle in the completed schedule.
unsigned cycleScheduled(SUnit *SU) const
Return the cycle for a scheduled instruction.
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi)
Return true if the scheduled Phi has a loop carried operand.
bool normalizeNonPipelinedInstructions(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
int getFinalCycle() const
Return the last cycle in the finalized schedule.
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts)
Order the instructions within a cycle so that the definitions occur before the uses.
void finalizeSchedule(SwingSchedulerDAG *SSD)
After the schedule has been formed, call this function to combine the instructions from the different...
Scheduling unit. This is a node in the scheduling DAG.
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
unsigned NodeNum
Entry # of node in the node vector.
void setInstr(MachineInstr *MI)
Assigns the instruction for the SUnit.
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
bool isPred(const SUnit *N) const
Tests if node N is a predecessor of this node.
unsigned short Latency
Node latency.
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
bool hasPhysRegDefs
Has physreg defs that are being used.
SmallVector< SDep, 4 > Succs
All sunit successors.
SmallVector< SDep, 4 > Preds
All sunit predecessors.
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
A ScheduleDAG for scheduling lists of MachineInstr.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
virtual void finishBlock()
Cleans up after scheduling in the given block.
MachineBasicBlock * BB
The block in which to insert instructions.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
void dumpNode(const SUnit &SU) const override
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
void buildSchedGraph(AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
Builds SUnits for the current region.
SUnit * getSUnit(MachineInstr *MI) const
Returns an existing SUnit for this MI, or nullptr.
void dump() const override
void RemovePred(SUnit *M, SUnit *N)
Updates the topological ordering to accommodate an an edge to be removed from the specified node N fr...
void InitDAGTopologicalSorting()
Creates the initial topological ordering from the DAG to be scheduled.
void AddPred(SUnit *Y, SUnit *X)
Updates the topological ordering to accommodate an edge to be added from SUnit X to SUnit Y.
bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
Checks if SU is reachable from TargetSU.
MachineRegisterInfo & MRI
Virtual/real register map.
const TargetInstrInfo * TII
Target instruction information.
std::vector< SUnit > SUnits
The scheduling units.
const TargetRegisterInfo * TRI
Target processor register info.
MachineFunction & MF
Machine function.
A vector that has set insertion semantics.
size_type size() const
Determine the number of elements in the SetVector.
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
bool contains(const key_type &key) const
Check if the SetVector contains the given key.
bool insert(const value_type &X)
Insert a new element into the SetVector.
void clear()
Completely clear the SetVector.
bool empty() const
Determine if the SetVector is empty or not.
typename vector_type::const_iterator iterator
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
A SetVector that performs no allocations if smaller than a certain size.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
bool contains(const T &V) const
Check if the SmallSet contains the given element.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
unsigned getDepth(SUnit *Node)
The depth, in the dependence graph, for a node.
unsigned getInstrBaseReg(SUnit *SU)
Return the new base register that was stored away for the changed instruction.
int getASAP(SUnit *Node)
Return the earliest time an instruction may be scheduled.
void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule)
Apply changes to the instruction if needed.
void finishBlock() override
Clean up after the software pipeliner runs.
void fixupRegisterOverlaps(std::deque< SUnit * > &Instrs)
Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes ...
int getZeroLatencyDepth(SUnit *Node)
The maximum unweighted length of a path from an arbitrary node to the given node in which each edge h...
bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc=true)
Return true for an order or output dependence that is loop carried potentially.
unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep)
The distance function, which indicates that operation V of iteration I depends on operations U of ite...
void schedule() override
We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing ...
int getMOV(SUnit *Node)
The mobility function, which the number of slots in which an instruction may be scheduled.
int getZeroLatencyHeight(SUnit *Node)
The maximum unweighted length of a path from the given node to an arbitrary node in which each edge h...
bool isBackedge(SUnit *Source, const SDep &Dep)
Return true if the dependence is a back-edge in the data dependence graph.
unsigned getHeight(SUnit *Node)
The height, in the dependence graph, for a node.
int getALAP(SUnit *Node)
Return the latest time an instruction my be scheduled.
Object returned by analyzeLoopForPipelining.
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS)
Return true if the proposed schedule should used.
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static Type * getVoidTy(LLVMContext &C)
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
LLVM Value Representation.
unsigned getPosition() const
This class implements an extremely fast bulk output stream that can only output to a stream.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
DiagnosticInfoOptimizationBase::Argument NV
This is an optimization pass for GlobalISel generic memory operations.
void stable_sort(R &&Range)
int popcount(T Value) noexcept
Count the number of set bits in a value.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool set_is_subset(const S1Ty &S1, const S2Ty &S2)
set_is_subset(A, B) - Return true iff A in B
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
void getUnderlyingObjects(const Value *V, SmallVectorImpl< const Value * > &Objects, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to getUnderlyingObject except that it can look through phi and select instruct...
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
cl::opt< bool > SwpEnableCopyToPhi
bool isIdentifiedObject(const Value *V)
Return true if this pointer refers to a distinct and identifiable object.
cl::opt< int > SwpForceIssueWidth
A command line argument to force pipeliner to use specified issue width.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
These values represent a non-pipelined step in the execution of an instruction.
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
static constexpr LaneBitmask getNone()
Define a kind of processor resource that will be modeled by the scheduler.
const unsigned * SubUnitsIdxBegin
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Machine model for scheduling, bundling, and heuristics.
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
unsigned getNumProcResourceKinds() const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
MachineInstr * LoopInductionVar
SmallVector< MachineOperand, 4 > BrCond
MachineInstr * LoopCompare
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > LoopPipelinerInfo
Store the effects of a change in pressure on things that MI scheduler cares about.
std::vector< unsigned > MaxSetPressure
Map of max reg pressure indexed by pressure set ID, not class ID.