LLVM 17.0.0git
Namespaces | Functions | Variables
HexagonTargetMachine.cpp File Reference
#include "HexagonTargetMachine.h"
#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonLoopIdiomRecognition.h"
#include "HexagonMachineFunctionInfo.h"
#include "HexagonMachineScheduler.h"
#include "HexagonTargetObjectFile.h"
#include "HexagonTargetTransformInfo.h"
#include "HexagonVectorLoopCarriedReuse.h"
#include "TargetInfo/HexagonTargetInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/VLIWMachineScheduler.h"
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Transforms/Scalar.h"
#include <optional>
Include dependency graph for HexagonTargetMachine.cpp:

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 

Functions

static ScheduleDAGInstrscreateVLIWMachineSched (MachineSchedContext *C)
 
void llvm::initializeHexagonBitSimplifyPass (PassRegistry &Registry)
 
void llvm::initializeHexagonConstExtendersPass (PassRegistry &)
 
void llvm::initializeHexagonConstPropagationPass (PassRegistry &Registry)
 
void llvm::initializeHexagonCopyToCombinePass (PassRegistry &)
 
void llvm::initializeHexagonEarlyIfConversionPass (PassRegistry &Registry)
 
void llvm::initializeHexagonExpandCondsetsPass (PassRegistry &)
 
void llvm::initializeHexagonGenMuxPass (PassRegistry &Registry)
 
void llvm::initializeHexagonHardwareLoopsPass (PassRegistry &)
 
void llvm::initializeHexagonLoopIdiomRecognizeLegacyPassPass (PassRegistry &)
 
void llvm::initializeHexagonNewValueJumpPass (PassRegistry &)
 
void llvm::initializeHexagonOptAddrModePass (PassRegistry &)
 
void llvm::initializeHexagonPacketizerPass (PassRegistry &)
 
void llvm::initializeHexagonRDFOptPass (PassRegistry &)
 
void llvm::initializeHexagonSplitDoubleRegsPass (PassRegistry &)
 
void llvm::initializeHexagonVExtractPass (PassRegistry &)
 
void llvm::initializeHexagonVectorCombineLegacyPass (PassRegistry &)
 
void llvm::initializeHexagonVectorLoopCarriedReuseLegacyPassPass (PassRegistry &)
 
Passllvm::createHexagonLoopIdiomPass ()
 
Passllvm::createHexagonVectorLoopCarriedReuseLegacyPass ()
 
FunctionPassllvm::createHexagonBitSimplify ()
 
FunctionPassllvm::createHexagonBranchRelaxation ()
 
FunctionPassllvm::createHexagonCallFrameInformation ()
 
FunctionPassllvm::createHexagonCFGOptimizer ()
 
FunctionPassllvm::createHexagonCommonGEP ()
 
FunctionPassllvm::createHexagonConstExtenders ()
 
FunctionPassllvm::createHexagonConstPropagationPass ()
 
FunctionPassllvm::createHexagonCopyToCombine ()
 
FunctionPassllvm::createHexagonEarlyIfConversion ()
 
FunctionPassllvm::createHexagonFixupHwLoops ()
 
FunctionPassllvm::createHexagonGenExtract ()
 
FunctionPassllvm::createHexagonGenInsert ()
 
FunctionPassllvm::createHexagonGenMux ()
 
FunctionPassllvm::createHexagonGenPredicate ()
 
FunctionPassllvm::createHexagonHardwareLoops ()
 
FunctionPassllvm::createHexagonISelDag (HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
 createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG, ready for instruction scheduling.
 
FunctionPassllvm::createHexagonLoopRescheduling ()
 
FunctionPassllvm::createHexagonNewValueJump ()
 
FunctionPassllvm::createHexagonOptAddrMode ()
 
FunctionPassllvm::createHexagonOptimizeSZextends ()
 
FunctionPassllvm::createHexagonPacketizer (bool Minimal)
 
FunctionPassllvm::createHexagonPeephole ()
 
FunctionPassllvm::createHexagonRDFOpt ()
 
FunctionPassllvm::createHexagonSplitConst32AndConst64 ()
 
FunctionPassllvm::createHexagonSplitDoubleRegs ()
 
FunctionPassllvm::createHexagonStoreWidening ()
 
FunctionPassllvm::createHexagonVectorCombineLegacyPass ()
 
FunctionPassllvm::createHexagonVectorPrint ()
 
FunctionPassllvm::createHexagonVExtract ()
 
static Reloc::Model getEffectiveRelocModel (std::optional< Reloc::Model > RM)
 
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget ()
 

Variables

static cl::opt< boolEnableCExtOpt ("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
 
static cl::opt< boolEnableRDFOpt ("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations"))
 
static cl::opt< boolDisableHardwareLoops ("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
 
static cl::opt< boolDisableAModeOpt ("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization"))
 
static cl::opt< boolDisableHexagonCFGOpt ("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization"))
 
static cl::opt< boolDisableHCP ("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation"))
 
static cl::opt< boolDisableStoreWidening ("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
 
static cl::opt< boolEnableExpandCondsets ("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX"))
 
static cl::opt< boolEnableEarlyIf ("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion"))
 
static cl::opt< boolEnableGenInsert ("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
 
static cl::opt< boolEnableCommGEP ("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions"))
 
static cl::opt< boolEnableGenExtract ("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
 
static cl::opt< boolEnableGenMux ("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
 
static cl::opt< boolEnableGenPred ("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
 
static cl::opt< boolEnableLoopPrefetch ("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon"))
 
static cl::opt< boolDisableHSDR ("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
 
static cl::opt< boolEnableBitSimplify ("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
 
static cl::opt< boolEnableLoopResched ("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
 
static cl::opt< boolHexagonNoOpt ("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
 
static cl::opt< boolEnableVectorPrint ("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass"))
 
static cl::opt< boolEnableVExtractOpt ("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization"))
 
static cl::opt< boolEnableVectorCombine ("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining"))
 
static cl::opt< boolEnableInitialCFGCleanup ("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
 
static cl::opt< boolEnableInstSimplify ("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify"))
 
int HexagonTargetMachineModule = 0
 HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless there are references into the library.
 
static MachineSchedRegistry SchedCustomRegistry ("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
 

Function Documentation

◆ createVLIWMachineSched()

static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext C)
static

◆ getEffectiveRelocModel()

static Reloc::Model getEffectiveRelocModel ( std::optional< Reloc::Model RM)
static

Definition at line 197 of file HexagonTargetMachine.cpp.

References llvm::Reloc::Static.

◆ LLVMInitializeHexagonTarget()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget ( )

Variable Documentation

◆ DisableAModeOpt

cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization")) ( "disable-hexagon-amodeopt"  ,
cl::Hidden  ,
cl::desc("Disable Hexagon Addressing Mode Optimization")   
)
static

◆ DisableHardwareLoops

cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")) ( "disable-hexagon-hwloops"  ,
cl::Hidden  ,
cl::desc("Disable Hardware Loops for Hexagon target")   
)
static

◆ DisableHCP

cl::opt< bool > DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation")) ( "disable-hcp"  ,
cl::Hidden  ,
cl::desc("Disable Hexagon constant propagation")   
)
static

◆ DisableHexagonCFGOpt

cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization")) ( "disable-hexagon-cfgopt"  ,
cl::Hidden  ,
cl::desc("Disable Hexagon CFG Optimization")   
)
static

◆ DisableHSDR

cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers")) ( "disable-hsdr"  ,
cl::init(false)  ,
cl::Hidden  ,
cl::desc("Disable splitting double registers")   
)
static

◆ DisableStoreWidening

cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening")) ( "disable-store-widen"  ,
cl::Hidden  ,
cl::init(false)  ,
cl::desc("Disable store widening")   
)
static

◆ EnableBitSimplify

cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification")) ( "hexagon-bit"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Bit simplification")   
)
static

◆ EnableCExtOpt

cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization")) ( "hexagon-cext"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Enable Hexagon constant-extender optimization")   
)
static

◆ EnableCommGEP

cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions")) ( "hexagon-commgep"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Enable commoning of GEP instructions")   
)
static

◆ EnableEarlyIf

cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion")) ( "hexagon-eif"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Enable early if-conversion")   
)
static

◆ EnableExpandCondsets

cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX")) ( "hexagon-expand-condsets"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Early expansion of MUX")   
)
static

◆ EnableGenExtract

cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions")) ( "hexagon-extract"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Generate \"extract\" instructions")   
)
static

◆ EnableGenInsert

cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions")) ( "hexagon-insert"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Generate \"insert\" instructions")   
)
static

◆ EnableGenMux

cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions")) ( "hexagon-mux"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Enable converting conditional transfers into MUX instructions")   
)
static

◆ EnableGenPred

cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions")) ( "hexagon-gen-pred"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Enable conversion of arithmetic operations to " "predicate instructions")   
)
static

◆ EnableInitialCFGCleanup

cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass")) ( "hexagon-initial-cfg-cleanup"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Simplify the CFG after atomic expansion pass")   
)
static

◆ EnableInstSimplify

cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify")) ( "hexagon-instsimplify"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Enable instsimplify")   
)
static

◆ EnableLoopPrefetch

cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon")) ( "hexagon-loop-prefetch"  ,
cl::Hidden  ,
cl::desc("Enable loop data prefetch on Hexagon")   
)
static

◆ EnableLoopResched

cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling")) ( "hexagon-loop-resched"  ,
cl::init(true ,
cl::Hidden  ,
cl::desc("Loop rescheduling")   
)
static

◆ EnableRDFOpt

cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations")) ( "rdf-opt"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Enable RDF-based optimizations")   
)
static

◆ EnableVectorCombine

cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining")) ( "hexagon-vector-combine"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Enable HVX vector combining")   
)
static

◆ EnableVectorPrint

cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass")) ( "enable-hexagon-vector-print"  ,
cl::Hidden  ,
cl::desc("Enable Hexagon Vector print instr pass")   
)
static

◆ EnableVExtractOpt

cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization")) ( "hexagon-opt-vextract"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Enable vextract optimization")   
)
static

◆ HexagonNoOpt

cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations")) ( "hexagon-noopt"  ,
cl::init(false)  ,
cl::Hidden  ,
cl::desc("Disable backend optimizations")   
)
static

◆ HexagonTargetMachineModule

int HexagonTargetMachineModule = 0

HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless there are references into the library.

In particular, it seems that it is not possible to get things to work on Win32 without this. Though it is unused, do not remove it.

Definition at line 126 of file HexagonTargetMachine.cpp.

◆ SchedCustomRegistry

MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched) ( "hexagon"  ,
"Run Hexagon's custom scheduler"  ,
createVLIWMachineSched   
)
static