LLVM 19.0.0git
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1//==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7/// \file
8/// This file implements a TargetTransformInfo analysis pass specific to the
9/// Hexagon target machine. It uses the target's detailed information to provide
10/// more precise answers to certain TTI queries, while letting the target
11/// independent and default TTI implementations handle the rest.
18#include "Hexagon.h"
19#include "HexagonSubtarget.h"
21#include "llvm/ADT/ArrayRef.h"
24#include "llvm/IR/Function.h"
26namespace llvm {
28class Loop;
29class ScalarEvolution;
30class User;
31class Value;
33class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
37 friend BaseT;
39 const HexagonSubtarget &ST;
40 const HexagonTargetLowering &TLI;
42 const HexagonSubtarget *getST() const { return &ST; }
43 const HexagonTargetLowering *getTLI() const { return &TLI; }
45 bool useHVX() const;
46 bool isHVXVectorType(Type *Ty) const;
48 // Returns the number of vector elements of Ty, if Ty is a vector type,
49 // or 1 if Ty is a scalar type. It is incorrect to call this function
50 // with any other type.
51 unsigned getTypeNumElements(Type *Ty) const;
56 ST(*TM->getSubtargetImpl(F)), TLI(*ST.getTargetLowering()) {}
58 /// \name Scalar TTI Implementations
59 /// @{
61 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
63 // The Hexagon target can unroll loops with run-time trip counts.
71 /// Bias LSR towards creating post-increment opportunities.
75 // L1 cache prefetch.
76 unsigned getPrefetchDistance() const override;
77 unsigned getCacheLineSize() const override;
79 /// @}
81 /// \name Vector TTI Implementations
82 /// @{
84 unsigned getNumberOfRegisters(bool vector) const;
87 unsigned getMinVectorRegisterBitWidth() const;
88 ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const;
90 bool
92 return true;
93 }
95 bool hasBranchDivergence(const Function *F = nullptr) { return false; }
96 bool enableAggressiveInterleaving(bool LoopHasReductions) {
97 return false;
98 }
100 return false;
101 }
103 return true;
104 }
107 const APInt &DemandedElts,
108 bool Insert, bool Extract,
120 const SCEV *S);
122 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
125 const Instruction *I = nullptr);
126 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
127 Align Alignment, unsigned AddressSpace,
129 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp,
130 ArrayRef<int> Mask,
132 Type *SubTp,
133 ArrayRef<const Value *> Args = std::nullopt);
134 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
135 const Value *Ptr, bool VariableMask,
136 Align Alignment,
138 const Instruction *I);
139 InstructionCost getInterleavedMemoryOpCost(
140 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
141 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
142 bool UseMaskForCond = false, bool UseMaskForGaps = false);
143 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
144 CmpInst::Predicate VecPred,
146 const Instruction *I = nullptr);
147 InstructionCost getArithmeticInstrCost(
148 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
149 TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
150 TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
151 ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
152 const Instruction *CxtI = nullptr);
153 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
156 const Instruction *I = nullptr);
158 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
160 unsigned Index, Value *Op0, Value *Op1);
163 const Instruction *I = nullptr) {
164 return 1;
165 }
167 bool isLegalMaskedStore(Type *DataType, Align Alignment);
168 bool isLegalMaskedLoad(Type *DataType, Align Alignment);
170 /// @}
176 // Hexagon specific decision to generate a lookup table.
177 bool shouldBuildLookupTables() const;
180} // end namespace llvm
static const Function * getParent(const Value *V)
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
const char LLVMTargetMachineRef TM
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:80
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:965
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
bool enableAggressiveInterleaving(bool LoopHasReductions)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE, const SCEV *S)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
unsigned getNumberOfRegisters(bool vector) const
— Vector TTI begin —
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
bool isLegalMaskedStore(Type *DataType, Align Alignment)
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Bias LSR towards creating post-increment opportunities.
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, ArrayRef< const Value * > Args=std::nullopt)
unsigned getMinVectorRegisterBitWidth() const
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
unsigned getCacheLineSize() const override
bool hasBranchDivergence(const Function *F=nullptr)
unsigned getPrefetchDistance() const override
— Vector TTI end —
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
unsigned getMaxInterleaveFactor(ElementCount VF)
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
The optimization diagnostic interface.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
const DataLayout & getDataLayout() const
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
The kind of cost model.
Flags indicating the kind of support for population count.
The various kinds of shuffle patterns for vector queries.
Represents a hint about the context in which a cast is used.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
@ User
could "use" a pointer
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Definition: NVPTXBaseInfo.h:21
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Parameters that control the generic loop unrolling transformation.