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HexagonTargetTransformInfo.h
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1 //==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
17 
18 #include "Hexagon.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/IR/Function.h"
25 
26 namespace llvm {
27 
28 class Loop;
29 class ScalarEvolution;
30 class User;
31 class Value;
32 
33 class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
35  using TTI = TargetTransformInfo;
36 
37  friend BaseT;
38 
39  const HexagonSubtarget &ST;
40  const HexagonTargetLowering &TLI;
41 
42  const HexagonSubtarget *getST() const { return &ST; }
43  const HexagonTargetLowering *getTLI() const { return &TLI; }
44 
45  bool useHVX() const;
46 
47  // Returns the number of vector elements of Ty, if Ty is a vector type,
48  // or 1 if Ty is a scalar type. It is incorrect to call this function
49  // with any other type.
50  unsigned getTypeNumElements(Type *Ty) const;
51 
52 public:
53  explicit HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
54  : BaseT(TM, F.getParent()->getDataLayout()),
55  ST(*TM->getSubtargetImpl(F)), TLI(*ST.getTargetLowering()) {}
56 
57  /// \name Scalar TTI Implementations
58  /// @{
59 
60  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
61 
62  // The Hexagon target can unroll loops with run-time trip counts.
66 
69 
70  /// Bias LSR towards creating post-increment opportunities.
72  getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const;
73 
74  // L1 cache prefetch.
75  unsigned getPrefetchDistance() const override;
76  unsigned getCacheLineSize() const override;
77 
78  /// @}
79 
80  /// \name Vector TTI Implementations
81  /// @{
82 
83  unsigned getNumberOfRegisters(bool vector) const;
84  unsigned getMaxInterleaveFactor(unsigned VF);
86  unsigned getMinVectorRegisterBitWidth() const;
87  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const;
88 
89  bool
91  return true;
92  }
93  bool supportsEfficientVectorElementLoadStore() { return false; }
95  return false;
96  }
97  bool enableAggressiveInterleaving(bool LoopHasReductions) {
98  return false;
99  }
101  return false;
102  }
104  return true;
105  }
106 
108  const APInt &DemandedElts,
109  bool Insert, bool Extract);
111  ArrayRef<Type *> Tys);
113  ArrayRef<Type *> Tys,
118  const SCEV *S);
119  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
120  MaybeAlign Alignment, unsigned AddressSpace,
122  const Instruction *I = nullptr);
123  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
124  Align Alignment, unsigned AddressSpace,
127  ArrayRef<int> Mask, int Index, Type *SubTp,
129  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
130  const Value *Ptr, bool VariableMask,
131  Align Alignment,
133  const Instruction *I);
135  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
136  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
137  bool UseMaskForCond = false, bool UseMaskForGaps = false);
138  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
139  CmpInst::Predicate VecPred,
141  const Instruction *I = nullptr);
143  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
149  const Instruction *CxtI = nullptr);
150  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
153  const Instruction *I = nullptr);
154  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
155  unsigned Index);
156 
158  const Instruction *I = nullptr) {
159  return 1;
160  }
161 
162  bool isLegalMaskedStore(Type *DataType, Align Alignment);
163  bool isLegalMaskedLoad(Type *DataType, Align Alignment);
164 
165  /// @}
166 
169 
170  // Hexagon specific decision to generate a lookup table.
171  bool shouldBuildLookupTables() const;
172 };
173 
174 } // end namespace llvm
175 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::HexagonTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: HexagonTargetTransformInfo.cpp:116
llvm::objcarc::ARCInstKind::User
@ User
could "use" a pointer
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:213
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::HexagonTTIImpl::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: HexagonTargetTransformInfo.h:90
llvm::ElementCount
Definition: TypeSize.h:404
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:546
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:601
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:170
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::HexagonTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:160
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:544
llvm::HexagonTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, int Index, Type *SubTp, ArrayRef< const Value * > Args=None)
Definition: HexagonTargetTransformInfo.cpp:224
llvm::HexagonTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: HexagonTargetTransformInfo.cpp:98
HexagonTargetMachine.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::HexagonTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: HexagonTargetTransformInfo.cpp:231
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::HexagonTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: HexagonTargetTransformInfo.cpp:308
llvm::HexagonTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: HexagonTargetTransformInfo.cpp:59
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:918
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:891
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1112
llvm::User
Definition: User.h:44
llvm::HexagonTTIImpl::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:345
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::Instruction
Definition: Instruction.h:42
llvm::HexagonTTIImpl::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: HexagonTargetTransformInfo.cpp:372
llvm::HexagonTTIImpl::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions)
Definition: HexagonTargetTransformInfo.h:97
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::None
const NoneType None
Definition: None.h:24
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
Hexagon.h
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::HexagonTTIImpl::prefersVectorizedAddressing
bool prefersVectorizedAddressing()
Definition: HexagonTargetTransformInfo.h:100
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::HexagonTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.h:157
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:433
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:918
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
ArrayRef.h
llvm::HexagonTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: HexagonTargetTransformInfo.cpp:238
llvm::HexagonTTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: HexagonTargetTransformInfo.h:103
llvm::HexagonTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:327
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:910
llvm::HexagonTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:285
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::HexagonTTIImpl::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:137
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::HexagonTTIImpl::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Definition: HexagonTargetTransformInfo.cpp:132
llvm::HexagonTargetLowering
Definition: HexagonISelLowering.h:105
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:845
llvm::HexagonTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: HexagonTargetTransformInfo.cpp:103
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:648
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:911
llvm::HexagonTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:217
llvm::HexagonTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: HexagonTargetTransformInfo.cpp:72
llvm::TypeSize
Definition: TypeSize.h:435
llvm::HexagonTTIImpl::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore()
Definition: HexagonTargetTransformInfo.h:93
llvm::HexagonTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: HexagonTargetTransformInfo.cpp:264
Function.h
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE, const SCEV *S)
Definition: HexagonTargetTransformInfo.cpp:154
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:939
llvm::HexagonTTIImpl::getPrefetchDistance
unsigned getPrefetchDistance() const override
— Vector TTI end —
Definition: HexagonTargetTransformInfo.cpp:337
llvm::HexagonTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:144
llvm::HexagonTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Bias LSR towards creating post-increment opportunities.
Definition: HexagonTargetTransformInfo.cpp:85
llvm::HexagonTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:251
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
TargetTransformInfo.h
llvm::HexagonTTIImpl::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: HexagonTargetTransformInfo.cpp:341
llvm::HexagonTTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: HexagonTargetTransformInfo.cpp:126
llvm::HexagonTTIImpl::hasBranchDivergence
bool hasBranchDivergence()
Definition: HexagonTargetTransformInfo.h:94
llvm::HexagonTTIImpl::HexagonTTIImpl
HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
Definition: HexagonTargetTransformInfo.h:53
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::HexagonTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:331
llvm::HexagonTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool vector) const
— Vector TTI begin —
Definition: HexagonTargetTransformInfo.cpp:92
llvm::HexagonTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: HexagonTargetTransformInfo.cpp:66
llvm::HexagonTTIImpl
Definition: HexagonTargetTransformInfo.h:33
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::HexagonTTIImpl::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: HexagonTargetTransformInfo.cpp:120