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14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
32 namespace HexagonISD {
124 class HexagonSubtarget;
127 int VarArgsFrameOffset;
146 unsigned Intrinsic)
const override;
168 unsigned DefinedValues)
const override;
170 unsigned Index)
const override;
283 EVT VT)
const override {
297 std::pair<unsigned, const TargetRegisterClass *>
310 Type *Ty,
unsigned AS,
317 bool ForCodeSize)
const override;
329 unsigned AddrSpace,
Align Alignment,
331 unsigned *Fast)
const override;
336 unsigned *Fast)
const override;
343 EVT NewVT)
const override;
364 void initializeHVXLowering();
365 unsigned getPreferredHvxVectorAction(
MVT VecTy)
const;
366 unsigned getCustomHvxOperationAction(
SDNode &
Op)
const;
372 std::pair<SDValue,int> getBaseAndOffset(
SDValue Addr)
const;
400 if (
Op.isMachineOpcode())
401 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
404 SDValue getInstr(
unsigned MachineOpc,
const SDLoc &dl, MVT Ty,
405 ArrayRef<SDValue> Ops, SelectionDAG &DAG)
const {
406 SDNode *
N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
407 return SDValue(
N, 0);
409 SDValue getZero(
const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
const;
411 using VectorPair = std::pair<SDValue, SDValue>;
412 using TypePair = std::pair<MVT, MVT>;
414 SDValue getInt(
unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
415 const SDLoc &dl, SelectionDAG &DAG)
const;
417 MVT ty(SDValue
Op)
const {
418 return Op.getValueType().getSimpleVT();
420 TypePair ty(
const VectorPair &Ops)
const {
421 return { Ops.first.getValueType().getSimpleVT(),
422 Ops.second.getValueType().getSimpleVT() };
424 MVT tyScalar(MVT Ty)
const {
429 MVT tyVector(MVT Ty, MVT ElemTy)
const {
430 if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
432 unsigned TyWidth = Ty.getSizeInBits();
433 unsigned ElemWidth = ElemTy.getSizeInBits();
434 assert((TyWidth % ElemWidth) == 0);
438 MVT typeJoin(
const TypePair &Tys)
const;
439 TypePair typeSplit(MVT Ty)
const;
440 MVT typeExtElem(MVT VecTy,
unsigned Factor)
const;
441 MVT typeTruncElem(MVT VecTy,
unsigned Factor)
const;
442 TypePair typeExtendToWider(MVT Ty0, MVT Ty1)
const;
443 TypePair typeWidenToWider(MVT Ty0, MVT Ty1)
const;
444 MVT typeLegalize(MVT Ty, SelectionDAG &DAG)
const;
445 MVT typeWidenToHvx(MVT Ty)
const;
447 SDValue opJoin(
const VectorPair &Ops,
const SDLoc &dl,
448 SelectionDAG &DAG)
const;
449 VectorPair opSplit(SDValue Vec,
const SDLoc &dl, SelectionDAG &DAG)
const;
450 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG)
const;
452 SDValue LoHalf(SDValue V, SelectionDAG &DAG)
const {
455 if (!Ty.isVector()) {
456 assert(Ty.getSizeInBits() == 64);
457 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl,
MVT::i32, V);
459 MVT HalfTy = typeSplit(Ty).first;
460 SDValue Idx = getZero(dl,
MVT::i32, DAG);
463 SDValue HiHalf(SDValue V, SelectionDAG &DAG)
const {
466 if (!Ty.isVector()) {
467 assert(Ty.getSizeInBits() == 64);
468 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl,
MVT::i32, V);
470 MVT HalfTy = typeSplit(Ty).first;
471 SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl,
MVT::i32);
476 unsigned *Fast)
const;
477 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
479 unsigned *Fast)
const;
480 void AdjustHvxInstrPostInstrSelection(MachineInstr &
MI, SDNode *
Node)
const;
482 bool isHvxSingleTy(MVT Ty)
const;
483 bool isHvxPairTy(MVT Ty)
const;
484 bool isHvxBoolTy(MVT Ty)
const;
485 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
486 SelectionDAG &DAG)
const;
487 SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG)
const;
488 SDValue getByteShuffle(
const SDLoc &dl, SDValue Op0, SDValue Op1,
489 ArrayRef<int>
Mask, SelectionDAG &DAG)
const;
491 SDValue buildHvxVectorReg(ArrayRef<SDValue> Values,
const SDLoc &dl,
492 MVT VecTy, SelectionDAG &DAG)
const;
493 SDValue buildHvxVectorPred(ArrayRef<SDValue> Values,
const SDLoc &dl,
494 MVT VecTy, SelectionDAG &DAG)
const;
495 SDValue createHvxPrefixPred(SDValue PredV,
const SDLoc &dl,
496 unsigned BitBytes,
bool ZeroFill,
497 SelectionDAG &DAG)
const;
498 SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV,
const SDLoc &dl,
499 MVT ResTy, SelectionDAG &DAG)
const;
500 SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV,
const SDLoc &dl,
501 MVT ResTy, SelectionDAG &DAG)
const;
502 SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
503 const SDLoc &dl, SelectionDAG &DAG)
const;
504 SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
505 const SDLoc &dl, SelectionDAG &DAG)
const;
506 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
507 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)
509 SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV,
const SDLoc &dl,
510 MVT ResTy, SelectionDAG &DAG)
const;
511 SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
512 const SDLoc &dl, SelectionDAG &DAG)
const;
513 SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
514 const SDLoc &dl, SelectionDAG &DAG)
const;
515 SDValue extendHvxVectorPred(SDValue VecV,
const SDLoc &dl, MVT ResTy,
516 bool ZeroExt, SelectionDAG &DAG)
const;
517 SDValue compressHvxPred(SDValue VecQ,
const SDLoc &dl, MVT ResTy,
518 SelectionDAG &DAG)
const;
519 SDValue resizeToWidth(SDValue VecV, MVT ResTy,
bool Signed,
const SDLoc &dl,
520 SelectionDAG &DAG)
const;
521 SDValue extractSubvector(SDValue Vec, MVT SubTy,
unsigned SubIdx,
522 SelectionDAG &DAG)
const;
523 VectorPair emitHvxAddWithOverflow(SDValue A, SDValue
B,
const SDLoc &dl,
524 bool Signed, SelectionDAG &DAG)
const;
525 VectorPair emitHvxShiftRightRnd(SDValue Val,
unsigned Amt,
bool Signed,
526 SelectionDAG &DAG)
const;
527 SDValue emitHvxMulHsV60(SDValue A, SDValue
B,
const SDLoc &dl,
528 SelectionDAG &DAG)
const;
529 SDValue emitHvxMulLoHiV60(SDValue A,
bool SignedA, SDValue
B,
bool SignedB,
530 const SDLoc &dl, SelectionDAG &DAG)
const;
531 SDValue emitHvxMulLoHiV62(SDValue A,
bool SignedA, SDValue
B,
bool SignedB,
532 const SDLoc &dl, SelectionDAG &DAG)
const;
534 SDValue LowerHvxBuildVector(SDValue
Op, SelectionDAG &DAG)
const;
535 SDValue LowerHvxSplatVector(SDValue
Op, SelectionDAG &DAG)
const;
536 SDValue LowerHvxConcatVectors(SDValue
Op, SelectionDAG &DAG)
const;
537 SDValue LowerHvxExtractElement(SDValue
Op, SelectionDAG &DAG)
const;
538 SDValue LowerHvxInsertElement(SDValue
Op, SelectionDAG &DAG)
const;
539 SDValue LowerHvxExtractSubvector(SDValue
Op, SelectionDAG &DAG)
const;
540 SDValue LowerHvxInsertSubvector(SDValue
Op, SelectionDAG &DAG)
const;
541 SDValue LowerHvxBitcast(SDValue
Op, SelectionDAG &DAG)
const;
542 SDValue LowerHvxAnyExt(SDValue
Op, SelectionDAG &DAG)
const;
543 SDValue LowerHvxSignExt(SDValue
Op, SelectionDAG &DAG)
const;
544 SDValue LowerHvxZeroExt(SDValue
Op, SelectionDAG &DAG)
const;
545 SDValue LowerHvxCttz(SDValue
Op, SelectionDAG &DAG)
const;
546 SDValue LowerHvxMulh(SDValue
Op, SelectionDAG &DAG)
const;
547 SDValue LowerHvxMulLoHi(SDValue
Op, SelectionDAG &DAG)
const;
548 SDValue LowerHvxSetCC(SDValue
Op, SelectionDAG &DAG)
const;
549 SDValue LowerHvxExtend(SDValue
Op, SelectionDAG &DAG)
const;
550 SDValue LowerHvxSelect(SDValue
Op, SelectionDAG &DAG)
const;
551 SDValue LowerHvxShift(SDValue
Op, SelectionDAG &DAG)
const;
552 SDValue LowerHvxFunnelShift(SDValue
Op, SelectionDAG &DAG)
const;
553 SDValue LowerHvxIntrinsic(SDValue
Op, SelectionDAG &DAG)
const;
554 SDValue LowerHvxMaskedOp(SDValue
Op, SelectionDAG &DAG)
const;
555 SDValue LowerHvxFpExtend(SDValue
Op, SelectionDAG &DAG)
const;
556 SDValue LowerHvxFpToInt(SDValue
Op, SelectionDAG &DAG)
const;
557 SDValue LowerHvxIntToFp(SDValue
Op, SelectionDAG &DAG)
const;
558 SDValue ExpandHvxFpToInt(SDValue
Op, SelectionDAG &DAG)
const;
559 SDValue ExpandHvxIntToFp(SDValue
Op, SelectionDAG &DAG)
const;
561 VectorPair SplitVectorOp(SDValue
Op, SelectionDAG &DAG)
const;
563 SDValue SplitHvxMemOp(SDValue
Op, SelectionDAG &DAG)
const;
564 SDValue WidenHvxLoad(SDValue
Op, SelectionDAG &DAG)
const;
565 SDValue WidenHvxStore(SDValue
Op, SelectionDAG &DAG)
const;
566 SDValue WidenHvxSetCC(SDValue
Op, SelectionDAG &DAG)
const;
567 SDValue LegalizeHvxResize(SDValue
Op, SelectionDAG &DAG)
const;
568 SDValue WidenHvxFpIntConv(SDValue
Op, SelectionDAG &DAG)
const;
569 SDValue ExpandHvxResizeIntoSteps(SDValue
Op, SelectionDAG &DAG)
const;
570 SDValue EqualizeFpIntConversion(SDValue
Op, SelectionDAG &DAG)
const;
572 SDValue CreateTLWrapper(SDValue
Op, SelectionDAG &DAG)
const;
573 SDValue RemoveTLWrapper(SDValue
Op, SelectionDAG &DAG)
const;
575 std::pair<const TargetRegisterClass*, uint8_t>
576 findRepresentativeClass(
const TargetRegisterInfo *
TRI, MVT VT)
579 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG)
const;
580 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG)
const;
581 bool isHvxOperation(SDNode *
N, SelectionDAG &DAG)
const;
582 SDValue LowerHvxOperation(SDValue
Op, SelectionDAG &DAG)
const;
583 void LowerHvxOperationWrapper(SDNode *
N, SmallVectorImpl<SDValue> &
Results,
584 SelectionDAG &DAG)
const;
585 void ReplaceHvxNodeResults(SDNode *
N, SmallVectorImpl<SDValue> &
Results,
586 SelectionDAG &DAG)
const;
588 SDValue combineTruncateBeforeLegal(SDValue
Op, DAGCombinerInfo &DCI)
const;
589 SDValue combineConcatVectorsBeforeLegal(SDValue
Op, DAGCombinerInfo & DCI)
591 SDValue combineVectorShuffleBeforeLegal(SDValue
Op, DAGCombinerInfo & DCI)
594 SDValue PerformHvxDAGCombine(SDNode *
N, DAGCombinerInfo & DCI)
const;
599 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
The instances of the Type class are immutable: once they are created, they are never changed.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Function Alias Analysis Results
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
unsigned const TargetRegisterInfo * TRI
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
(vector float) vec_cmpeq(*A, *B) C
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
LegalizeAction getCustomOperationAction(SDNode &Op) const override
How to legalize this custom operation?
Analysis containing CSE Info
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
This struct is a compact representation of a valid (non-zero power of two) alignment.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
AtomicOrdering
Atomic ordering for LLVM's memory model.
SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
An instruction for storing to memory.
This is an important base class in LLVM.
Representation of each machine instruction.
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
This is an important class for using LLVM in a threaded context.
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
Flags
Flags values. These may be or'd together.
This structure contains all information that is necessary for lowering calls.
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
static MVT getVectorVT(MVT VT, unsigned NumElements)
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
bool isVector() const
Return true if this is a vector value type.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
Common base class shared among various IRBuilders.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ UNDEF
UNDEF - An undefined node.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
An instruction for reading from memory.
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
an instruction that atomically reads a memory location, combines it with another value,...
Wrapper class representing virtual and physical registers.
amdgpu Simplify well known AMD library false FunctionCallee Callee
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
const char LLVMTargetMachineRef TM
This class represents a function call, abstracting a target machine's calling convention.
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Return true if the target supports a memory access of this type for the given address space and align...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
LLVM Value Representation.
An instruction that atomically checks whether a specified value is in a memory location,...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
static MVT getIntegerVT(unsigned BitWidth)
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const