LLVM  14.0.0git
HexagonTargetMachine.cpp
Go to the documentation of this file.
1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
22 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/IR/Module.h"
30 #include "llvm/Transforms/Scalar.h"
31 
32 using namespace llvm;
33 
35  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
36 
38  cl::init(true), cl::desc("Enable RDF-based optimizations"));
39 
40 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
41  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
42 
43 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
45  cl::desc("Disable Hexagon Addressing Mode Optimization"));
46 
47 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
49  cl::desc("Disable Hexagon CFG Optimization"));
50 
51 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
52  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
53 
54 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
55  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
56 
57 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
59  cl::desc("Early expansion of MUX"));
60 
61 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
62  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
63 
64 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
65  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
66 
67 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
68  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
69 
70 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
71  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
72 
73 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
74  cl::desc("Enable converting conditional transfers into MUX instructions"));
75 
76 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
77  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
78  "predicate instructions"));
79 
80 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
82  cl::desc("Enable loop data prefetch on Hexagon"));
83 
84 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
85  cl::desc("Disable splitting double registers"));
86 
87 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
88  cl::Hidden, cl::desc("Bit simplification"));
89 
90 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
91  cl::Hidden, cl::desc("Loop rescheduling"));
92 
93 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
94  cl::Hidden, cl::desc("Disable backend optimizations"));
95 
96 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
98  cl::desc("Enable Hexagon Vector print instr pass"));
99 
100 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
101  cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
102 
103 static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
104  cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
105 
106 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
108  cl::desc("Simplify the CFG after atomic expansion pass"));
109 
110 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
111  cl::ZeroOrMore, cl::init(true),
112  cl::desc("Enable instsimplify"));
113 
114 /// HexagonTargetMachineModule - Note that this is used on hosts that
115 /// cannot link in a library unless there are references into the
116 /// library. In particular, it seems that it is not possible to get
117 /// things to work on Win32 without this. Though it is unused, do not
118 /// remove it.
121 
123  ScheduleDAGMILive *DAG =
124  new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
125  DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
126  DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
127  DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
129  return DAG;
130 }
131 
133 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
135 
136 namespace llvm {
137  extern char &HexagonExpandCondsetsID;
156 
173  CodeGenOpt::Level OptLevel);
178  FunctionPass *createHexagonPacketizer(bool Minimal);
187 } // end namespace llvm;
188 
190  return RM.getValueOr(Reloc::Static);
191 }
192 
194  // Register the target.
196 
213 }
214 
216  StringRef CPU, StringRef FS,
217  const TargetOptions &Options,
220  CodeGenOpt::Level OL, bool JIT)
221  // Specify the vector alignment explicitly. For v512x1, the calculated
222  // alignment would be 512*alignment(i1), which is 512 bytes, instead of
223  // the required minimum of 64 bytes.
225  T,
226  "e-m:e-p:32:32:32-a:0-n16:32-"
227  "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
228  "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
229  TT, CPU, FS, Options, getEffectiveRelocModel(RM),
230  getEffectiveCodeModel(CM, CodeModel::Small),
231  (HexagonNoOpt ? CodeGenOpt::None : OL)),
232  TLOF(std::make_unique<HexagonTargetObjectFile>()) {
234  initAsmInfo();
235 }
236 
237 const HexagonSubtarget *
239  AttributeList FnAttrs = F.getAttributes();
240  Attribute CPUAttr =
241  FnAttrs.getFnAttr("target-cpu");
242  Attribute FSAttr =
243  FnAttrs.getFnAttr("target-features");
244 
245  std::string CPU =
246  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
247  std::string FS =
248  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
249  // Append the preexisting target features last, so that +mattr overrides
250  // the "unsafe-fp-math" function attribute.
251  // Creating a separate target feature is not strictly necessary, it only
252  // exists to make "unsafe-fp-math" force creating a new subtarget.
253 
254  if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
255  FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
256 
257  auto &I = SubtargetMap[CPU + FS];
258  if (!I) {
259  // This needs to be done before we create a new subtarget since any
260  // creation will depend on the TM and the code generation flags on the
261  // function that reside in TargetOptions.
263  I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
264  }
265  return I.get();
266 }
267 
269  PMB.addExtension(
271  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
273  });
274  PMB.addExtension(
276  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
278  });
279 }
280 
285  });
289  });
290 }
291 
294  return TargetTransformInfo(HexagonTTIImpl(this, F));
295 }
296 
297 
299 
300 namespace {
301 /// Hexagon Code Generator Pass Configuration Options.
302 class HexagonPassConfig : public TargetPassConfig {
303 public:
304  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
305  : TargetPassConfig(TM, PM) {}
306 
307  HexagonTargetMachine &getHexagonTargetMachine() const {
308  return getTM<HexagonTargetMachine>();
309  }
310 
312  createMachineScheduler(MachineSchedContext *C) const override {
313  return createVLIWMachineSched(C);
314  }
315 
316  void addIRPasses() override;
317  bool addInstSelector() override;
318  void addPreRegAlloc() override;
319  void addPostRegAlloc() override;
320  void addPreSched2() override;
321  void addPreEmitPass() override;
322 };
323 } // namespace
324 
326  return new HexagonPassConfig(*this, PM);
327 }
328 
329 void HexagonPassConfig::addIRPasses() {
331  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
332 
333  if (!NoOpt) {
334  if (EnableInstSimplify)
335  addPass(createInstSimplifyLegacyPass());
337  }
338 
339  addPass(createAtomicExpandPass());
340 
341  if (!NoOpt) {
344  .forwardSwitchCondToPhi(true)
345  .convertSwitchToLookupTable(true)
346  .needCanonicalLoops(false)
347  .hoistCommonInsts(true)
348  .sinkCommonInsts(true)));
349  if (EnableLoopPrefetch)
350  addPass(createLoopDataPrefetchPass());
353  if (EnableCommGEP)
354  addPass(createHexagonCommonGEP());
355  // Replace certain combinations of shifts and ands with extracts.
356  if (EnableGenExtract)
357  addPass(createHexagonGenExtract());
358  }
359 }
360 
361 bool HexagonPassConfig::addInstSelector() {
362  HexagonTargetMachine &TM = getHexagonTargetMachine();
363  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
364 
365  if (!NoOpt)
367 
368  addPass(createHexagonISelDag(TM, getOptLevel()));
369 
370  if (!NoOpt) {
371  if (EnableVExtractOpt)
372  addPass(createHexagonVExtract());
373  // Create logical operations on predicate registers.
374  if (EnableGenPred)
375  addPass(createHexagonGenPredicate());
376  // Rotate loops to expose bit-simplification opportunities.
377  if (EnableLoopResched)
379  // Split double registers.
380  if (!DisableHSDR)
381  addPass(createHexagonSplitDoubleRegs());
382  // Bit simplification.
383  if (EnableBitSimplify)
384  addPass(createHexagonBitSimplify());
385  addPass(createHexagonPeephole());
386  // Constant propagation.
387  if (!DisableHCP) {
390  }
391  if (EnableGenInsert)
392  addPass(createHexagonGenInsert());
393  if (EnableEarlyIf)
395  }
396 
397  return false;
398 }
399 
400 void HexagonPassConfig::addPreRegAlloc() {
401  if (getOptLevel() != CodeGenOpt::None) {
402  if (EnableCExtOpt)
403  addPass(createHexagonConstExtenders());
407  addPass(createHexagonStoreWidening());
409  addPass(createHexagonHardwareLoops());
410  }
411  if (TM->getOptLevel() >= CodeGenOpt::Default)
412  addPass(&MachinePipelinerID);
413 }
414 
415 void HexagonPassConfig::addPostRegAlloc() {
416  if (getOptLevel() != CodeGenOpt::None) {
417  if (EnableRDFOpt)
418  addPass(createHexagonRDFOpt());
420  addPass(createHexagonCFGOptimizer());
421  if (!DisableAModeOpt)
422  addPass(createHexagonOptAddrMode());
423  }
424 }
425 
426 void HexagonPassConfig::addPreSched2() {
427  addPass(createHexagonCopyToCombine());
428  if (getOptLevel() != CodeGenOpt::None)
429  addPass(&IfConverterID);
431 }
432 
433 void HexagonPassConfig::addPreEmitPass() {
434  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
435 
436  if (!NoOpt)
437  addPass(createHexagonNewValueJump());
438 
440 
441  if (!NoOpt) {
443  addPass(createHexagonFixupHwLoops());
444  // Generate MUX from pairs of conditional transfers.
445  if (EnableGenMux)
446  addPass(createHexagonGenMux());
447  }
448 
449  // Packetization is mandatory: it handles gather/scatter at all opt levels.
450  addPass(createHexagonPacketizer(NoOpt), false);
451 
452  if (EnableVectorPrint)
453  addPass(createHexagonVectorPrint(), false);
454 
455  // Add CFI instructions if necessary.
456  addPass(createHexagonCallFrameInformation(), false);
457 }
HexagonTargetInfo.h
EnableLoopResched
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
llvm::PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & >
Definition: LoopPassManager.h:70
DisableStoreWidening
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
EnableRDFOpt
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable RDF-based optimizations"))
llvm::createHexagonBranchRelaxation
FunctionPass * createHexagonBranchRelaxation()
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
PassBuilder.h
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:167
llvm::createHexagonLoopIdiomPass
Pass * createHexagonLoopIdiomPass()
Definition: HexagonLoopIdiomRecognition.cpp:2464
llvm::createHexagonNewValueJump
FunctionPass * createHexagonNewValueJump()
Definition: HexagonNewValueJump.cpp:725
llvm::createHexagonCallFrameInformation
FunctionPass * createHexagonCallFrameInformation()
DisableHCP
static cl::opt< bool > DisableHCP("disable-hcp", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"))
llvm::createHexagonVectorLoopCarriedReuseLegacyPass
Pass * createHexagonVectorLoopCarriedReuseLegacyPass()
Definition: HexagonVectorLoopCarriedReuse.cpp:669
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
EnableInstSimplify
static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable instsimplify"))
T
llvm::Function
Definition: Function.h:61
llvm::Attribute
Definition: Attributes.h:52
EnableGenPred
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:415
llvm::MachinePipelinerID
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
Definition: MachinePipeliner.cpp:184
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:136
llvm::createHexagonVectorCombineLegacyPass
FunctionPass * createHexagonVectorCombineLegacyPass()
Definition: HexagonVectorCombine.cpp:1527
llvm::initializeHexagonPacketizerPass
void initializeHexagonPacketizerPass(PassRegistry &)
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
llvm::createHexagonLoopRescheduling
FunctionPass * createHexagonLoopRescheduling()
Definition: HexagonBitSimplify.cpp:3375
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::initializeHexagonVectorCombineLegacyPass
void initializeHexagonVectorCombineLegacyPass(PassRegistry &)
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::HexagonTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: HexagonTargetMachine.cpp:325
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
HexagonTargetTransformInfo.h
llvm::initializeHexagonOptAddrModePass
void initializeHexagonOptAddrModePass(PassRegistry &)
Module.h
llvm::AttributeList
Definition: Attributes.h:398
llvm::Optional< Reloc::Model >
EnableCExtOpt
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
llvm::VLIWMachineScheduler
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
Definition: HexagonMachineScheduler.h:89
HexagonTargetMachineModule
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
Definition: HexagonTargetMachine.cpp:119
llvm::createHexagonCFGOptimizer
FunctionPass * createHexagonCFGOptimizer()
llvm::createHexagonGenExtract
FunctionPass * createHexagonGenExtract()
Definition: HexagonGenExtract.cpp:268
llvm::HexagonTargetObjectFile
Definition: HexagonTargetObjectFile.h:18
HexagonTargetMachine.h
EnableLoopPrefetch
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable loop data prefetch on Hexagon"))
llvm::createHexagonStoreWidening
FunctionPass * createHexagonStoreWidening()
Definition: HexagonStoreWidening.cpp:605
LegacyPassManager.h
PassManagerBuilder.h
llvm::initializeHexagonEarlyIfConversionPass
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::PassManagerBuilder::EP_LoopOptimizerEnd
@ EP_LoopOptimizerEnd
EP_LoopOptimizerEnd - This extension point allows adding loop passes to the end of the loop optimizer...
Definition: PassManagerBuilder.h:80
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::initializeHexagonVectorLoopCarriedReuseLegacyPassPass
void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)
CommandLine.h
llvm::createHexagonSplitDoubleRegs
FunctionPass * createHexagonSplitDoubleRegs()
Definition: HexagonSplitDouble.cpp:1233
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::createHexagonEarlyIfConversion
FunctionPass * createHexagonEarlyIfConversion()
Definition: HexagonEarlyIfConv.cpp:1077
llvm::createHexagonRDFOpt
FunctionPass * createHexagonRDFOpt()
Definition: HexagonRDFOpt.cpp:339
EnableVectorPrint
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector print instr pass"))
llvm::createHexagonGenMux
FunctionPass * createHexagonGenMux()
Definition: HexagonGenMux.cpp:394
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
createVLIWMachineSched
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
Definition: HexagonTargetMachine.cpp:122
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:84
llvm::createHexagonVExtract
FunctionPass * createHexagonVExtract()
Definition: HexagonVExtract.cpp:193
EnableCommGEP
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
llvm::createCopyConstrainDAGMutation
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1794
LLVMInitializeHexagonTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()
Definition: HexagonTargetMachine.cpp:193
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
EnableInitialCFGCleanup
static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::initializeHexagonExpandCondsetsPass
void initializeHexagonExpandCondsetsPass(PassRegistry &)
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:318
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
EnableGenMux
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
SchedCustomRegistry
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
DisableHardwareLoops
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
llvm::createHexagonISelDag
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...
Definition: HexagonISelDAGToDAG.cpp:60
EnableEarlyIf
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable early if-conversion"))
llvm::HexagonTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: HexagonTargetMachine.cpp:281
llvm::initializeHexagonBitSimplifyPass
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:100
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
llvm::None
const NoneType None
Definition: None.h:23
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Hexagon.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::HexagonLoopIdiomRecognitionPass
Definition: HexagonLoopIdiomRecognition.h:17
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:59
llvm::createHexagonGenInsert
FunctionPass * createHexagonGenInsert()
Definition: HexagonGenInsert.cpp:1620
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::initializeHexagonNewValueJumpPass
void initializeHexagonNewValueJumpPass(PassRegistry &)
llvm::createHexagonConstExtenders
FunctionPass * createHexagonConstExtenders()
Definition: HexagonConstExtenders.cpp:2021
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:98
llvm::createHexagonBitSimplify
FunctionPass * createHexagonBitSimplify()
Definition: HexagonBitSimplify.cpp:3379
EnableExpandCondsets
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
llvm::createHexagonOptimizeSZextends
FunctionPass * createHexagonOptimizeSZextends()
Definition: HexagonOptimizeSZextends.cpp:146
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
HexagonNoOpt
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
llvm::createHexagonVectorPrint
FunctionPass * createHexagonVectorPrint()
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::initializeHexagonLoopIdiomRecognizeLegacyPassPass
void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)
llvm::HexagonTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: HexagonTargetMachine.cpp:293
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:850
llvm::createHexagonConstPropagationPass
FunctionPass * createHexagonConstPropagationPass()
Definition: HexagonConstPropagation.cpp:3194
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
EnableBitSimplify
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
TargetPassConfig.h
llvm::createHexagonCopyToCombine
FunctionPass * createHexagonCopyToCombine()
Definition: HexagonCopyToCombine.cpp:888
HexagonVectorLoopCarriedReuse.h
HexagonMachineScheduler.h
llvm::HexagonExpandCondsetsID
char & HexagonExpandCondsetsID
Definition: HexagonExpandCondsets.cpp:249
llvm::PassBuilder::registerLoopOptimizerEndEPCallback
void registerLoopOptimizerEndEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:400
HexagonISelLowering.h
llvm::createHexagonSplitConst32AndConst64
FunctionPass * createHexagonSplitConst32AndConst64()
Definition: HexagonSplitConst32AndConst64.cpp:111
llvm::PassBuilder::registerLateLoopOptimizationsEPCallback
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:390
EnableVExtractOpt
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"))
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
DisableHexagonCFGOpt
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
llvm::UnreachableMachineBlockElimID
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
llvm::createHexagonCommonGEP
FunctionPass * createHexagonCommonGEP()
Definition: HexagonCommonGEP.cpp:1320
llvm::createHexagonFixupHwLoops
FunctionPass * createHexagonFixupHwLoops()
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::initializeHexagonConstPropagationPass
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
llvm::createHexagonOptAddrMode
FunctionPass * createHexagonOptAddrMode()
Definition: HexagonOptAddrMode.cpp:827
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::initializeHexagonConstExtendersPass
void initializeHexagonConstExtendersPass(PassRegistry &)
HexagonTargetObjectFile.h
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:481
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::HexagonTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &PMB) override
Allow the target to modify the pass manager, e.g.
Definition: HexagonTargetMachine.cpp:268
DisableHSDR
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
DisableAModeOpt
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon Addressing Mode Optimization"))
HexagonLoopIdiomRecognition.h
std
Definition: BitVector.h:838
llvm::HexagonTargetMachine::~HexagonTargetMachine
~HexagonTargetMachine() override
Definition: HexagonTargetMachine.cpp:298
llvm::createHexagonPacketizer
FunctionPass * createHexagonPacketizer(bool Minimal)
Definition: HexagonVLIWPacketizer.cpp:1950
llvm::initializeHexagonSplitDoubleRegsPass
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::HexagonTargetMachine::HexagonTargetMachine
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: HexagonTargetMachine.cpp:215
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:393
llvm::createInstSimplifyLegacyPass
FunctionPass * createInstSimplifyLegacyPass()
Definition: InstSimplifyPass.cpp:129
llvm::PassManagerBuilder::EP_LateLoopOptimizations
@ EP_LateLoopOptimizations
EP_LateLoopOptimizations - This extension point allows adding late loop canonicalization and simplifi...
Definition: PassManagerBuilder.h:112
llvm::initializeHexagonGenMuxPass
void initializeHexagonGenMuxPass(PassRegistry &Registry)
EnableGenExtract
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
llvm::HexagonTargetMachine::getSubtargetImpl
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
Definition: HexagonTargetMachine.cpp:238
EnableVectorCombine
static cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"))
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
llvm::PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & >::addPass
std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
Definition: LoopPassManager.h:107
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::HexagonVectorLoopCarriedReusePass
Hexagon Vector Loop Carried Reuse Pass.
Definition: HexagonVectorLoopCarriedReuse.h:128
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createHexagonPeephole
FunctionPass * createHexagonPeephole()
Definition: HexagonPeephole.cpp:295
llvm::initializeHexagonRDFOptPass
void initializeHexagonRDFOptPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::createDeadCodeEliminationPass
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:178
llvm::PassManagerBuilder::addExtension
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
Definition: PassManagerBuilder.cpp:271
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::createHexagonHardwareLoops
FunctionPass * createHexagonHardwareLoops()
Definition: HexagonHardwareLoops.cpp:374
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:436
EnableGenInsert
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
llvm::AttributeList::getFnAttr
Attribute getFnAttr(Attribute::AttrKind Kind) const
Return the attribute object that exists for the function.
Definition: Attributes.h:780
TargetRegistry.h
llvm::HexagonTTIImpl
Definition: HexagonTargetTransformInfo.h:33
llvm::initializeHexagonHardwareLoopsPass
void initializeHexagonHardwareLoopsPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:99
llvm::createHexagonGenPredicate
FunctionPass * createHexagonGenPredicate()
Definition: HexagonGenPredicate.cpp:541
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:155
llvm::initializeHexagonVExtractPass
void initializeHexagonVExtractPass(PassRegistry &)