LLVM  14.0.0git
LanaiAsmBackend.cpp
Go to the documentation of this file.
1 //===-- LanaiAsmBackend.cpp - Lanai Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "LanaiFixupKinds.h"
11 #include "llvm/MC/MCAsmBackend.h"
12 #include "llvm/MC/MCAssembler.h"
13 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCObjectWriter.h"
20 
21 using namespace llvm;
22 
23 // Prepare value for the target space
24 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
25  switch (Kind) {
26  case FK_Data_1:
27  case FK_Data_2:
28  case FK_Data_4:
29  case FK_Data_8:
30  return Value;
37  return Value;
38  default:
39  llvm_unreachable("Unknown fixup kind!");
40  }
41 }
42 
43 namespace {
44 class LanaiAsmBackend : public MCAsmBackend {
45  Triple::OSType OSType;
46 
47 public:
48  LanaiAsmBackend(const Target &T, Triple::OSType OST)
49  : MCAsmBackend(support::big), OSType(OST) {}
50 
51  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
53  uint64_t Value, bool IsResolved,
54  const MCSubtargetInfo *STI) const override;
55 
56  std::unique_ptr<MCObjectTargetWriter>
57  createObjectTargetWriter() const override;
58 
59  // No instruction requires relaxation
60  bool fixupNeedsRelaxation(const MCFixup & /*Fixup*/, uint64_t /*Value*/,
61  const MCRelaxableFragment * /*DF*/,
62  const MCAsmLayout & /*Layout*/) const override {
63  return false;
64  }
65 
66  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
67 
68  unsigned getNumFixupKinds() const override {
70  }
71 
72  bool writeNopData(raw_ostream &OS, uint64_t Count,
73  const MCSubtargetInfo *STI) const override;
74 };
75 
76 bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
77  const MCSubtargetInfo *STI) const {
78  if ((Count % 4) != 0)
79  return false;
80 
81  for (uint64_t i = 0; i < Count; i += 4)
82  OS.write("\x15\0\0\0", 4);
83 
84  return true;
85 }
86 
87 void LanaiAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
88  const MCValue &Target,
90  bool /*IsResolved*/,
91  const MCSubtargetInfo * /*STI*/) const {
92  MCFixupKind Kind = Fixup.getKind();
93  Value = adjustFixupValue(static_cast<unsigned>(Kind), Value);
94 
95  if (!Value)
96  return; // This value doesn't change the encoding
97 
98  // Where in the object and where the number of bytes that need
99  // fixing up
100  unsigned Offset = Fixup.getOffset();
101  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
102  unsigned FullSize = 4;
103 
104  // Grab current value, if any, from bits.
105  uint64_t CurVal = 0;
106 
107  // Load instruction and apply value
108  for (unsigned i = 0; i != NumBytes; ++i) {
109  unsigned Idx = (FullSize - 1 - i);
110  CurVal |= static_cast<uint64_t>(static_cast<uint8_t>(Data[Offset + Idx]))
111  << (i * 8);
112  }
113 
114  uint64_t Mask =
115  (static_cast<uint64_t>(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
116  CurVal |= Value & Mask;
117 
118  // Write out the fixed up bytes back to the code/data bits.
119  for (unsigned i = 0; i != NumBytes; ++i) {
120  unsigned Idx = (FullSize - 1 - i);
121  Data[Offset + Idx] = static_cast<uint8_t>((CurVal >> (i * 8)) & 0xff);
122  }
123 }
124 
125 std::unique_ptr<MCObjectTargetWriter>
126 LanaiAsmBackend::createObjectTargetWriter() const {
128 }
129 
130 const MCFixupKindInfo &
131 LanaiAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
132  static const MCFixupKindInfo Infos[Lanai::NumTargetFixupKinds] = {
133  // This table *must* be in same the order of fixup_* kinds in
134  // LanaiFixupKinds.h.
135  // Note: The number of bits indicated here are assumed to be contiguous.
136  // This does not hold true for LANAI_21 and LANAI_21_F which are applied
137  // to bits 0x7cffff and 0x7cfffc, respectively. Since the 'bits' counts
138  // here are used only for cosmetic purposes, we set the size to 16 bits
139  // for these 21-bit relocation as llvm/lib/MC/MCAsmStreamer.cpp checks
140  // no bits are set in the fixup range.
141  //
142  // name offset bits flags
143  {"FIXUP_LANAI_NONE", 0, 32, 0},
144  {"FIXUP_LANAI_21", 16, 16 /*21*/, 0},
145  {"FIXUP_LANAI_21_F", 16, 16 /*21*/, 0},
146  {"FIXUP_LANAI_25", 7, 25, 0},
147  {"FIXUP_LANAI_32", 0, 32, 0},
148  {"FIXUP_LANAI_HI16", 16, 16, 0},
149  {"FIXUP_LANAI_LO16", 16, 16, 0}};
150 
153 
154  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
155  "Invalid kind!");
156  return Infos[Kind - FirstTargetFixupKind];
157 }
158 
159 } // namespace
160 
162  const MCSubtargetInfo &STI,
163  const MCRegisterInfo & /*MRI*/,
164  const MCTargetOptions & /*Options*/) {
165  const Triple &TT = STI.getTargetTriple();
166  if (!TT.isOSBinFormatELF())
167  llvm_unreachable("OS not supported");
168 
169  return new LanaiAsmBackend(T, TT.getOS());
170 }
i
i
Definition: README.txt:29
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
T
MCDirectives.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
ErrorHandling.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MCAssembler.h
MCFixupKindInfo.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::Lanai::FIXUP_LANAI_HI16
@ FIXUP_LANAI_HI16
Definition: LanaiFixupKinds.h:32
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::Lanai::FIXUP_LANAI_25
@ FIXUP_LANAI_25
Definition: LanaiFixupKinds.h:30
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCSubtargetInfo.h
llvm::raw_ostream::write
raw_ostream & write(unsigned char C)
Definition: raw_ostream.cpp:220
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::Lanai::FIXUP_LANAI_21
@ FIXUP_LANAI_21
Definition: LanaiFixupKinds.h:28
llvm::createLanaiAsmBackend
MCAsmBackend * createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: LanaiAsmBackend.cpp:161
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
LanaiFixupKinds.h
llvm::MCAssembler
Definition: MCAssembler.h:60
uint64_t
MCELFObjectWriter.h
adjustFixupValue
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value)
Definition: LanaiAsmBackend.cpp:24
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Lanai::FIXUP_LANAI_LO16
@ FIXUP_LANAI_LO16
Definition: LanaiFixupKinds.h:33
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MCObjectWriter.h
llvm::Triple::OSType
OSType
Definition: Triple.h:167
llvm::createLanaiELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createLanaiELFObjectWriter(uint8_t OSABI)
Definition: LanaiELFObjectWriter.cpp:90
LanaiMCTargetDesc.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::Lanai::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: LanaiFixupKinds.h:37
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::Lanai::FIXUP_LANAI_32
@ FIXUP_LANAI_32
Definition: LanaiFixupKinds.h:31
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::Lanai::FIXUP_LANAI_21_F
@ FIXUP_LANAI_21_F
Definition: LanaiFixupKinds.h:29
raw_ostream.h
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::support::big
@ big
Definition: Endian.h:27