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56 std::unique_ptr<MCObjectTargetWriter>
57 createObjectTargetWriter()
const override;
68 unsigned getNumFixupKinds()
const override {
82 OS.
write(
"\x15\0\0\0", 4);
101 unsigned NumBytes = (getFixupKindInfo(
Kind).TargetSize + 7) / 8;
102 unsigned FullSize = 4;
108 for (
unsigned i = 0;
i != NumBytes; ++
i) {
109 unsigned Idx = (FullSize - 1 -
i);
115 (
static_cast<uint64_t>(-1) >> (64 - getFixupKindInfo(
Kind).TargetSize));
119 for (
unsigned i = 0;
i != NumBytes; ++
i) {
120 unsigned Idx = (FullSize - 1 -
i);
121 Data[
Offset + Idx] =
static_cast<uint8_t
>((CurVal >> (
i * 8)) & 0xff);
125 std::unique_ptr<MCObjectTargetWriter>
126 LanaiAsmBackend::createObjectTargetWriter()
const {
143 {
"FIXUP_LANAI_NONE", 0, 32, 0},
144 {
"FIXUP_LANAI_21", 16, 16 , 0},
145 {
"FIXUP_LANAI_21_F", 16, 16 , 0},
146 {
"FIXUP_LANAI_25", 7, 25, 0},
147 {
"FIXUP_LANAI_32", 0, 32, 0},
148 {
"FIXUP_LANAI_HI16", 16, 16, 0},
149 {
"FIXUP_LANAI_LO16", 16, 16, 0}};
166 if (!TT.isOSBinFormatELF())
169 return new LanaiAsmBackend(
T, TT.getOS());
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Error applyFixup(LinkGraph &G, Block &B, const Edge &E)
Apply fixup expression for edge to block content.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ FK_Data_4
A four-byte fixup.
Generic interface to target specific assembler backends.
const Triple & getTargetTriple() const
raw_ostream & write(unsigned char C)
This class implements an extremely fast bulk output stream that can only output to a stream.
MCAsmBackend * createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent information on a fixup kind.
@ FK_Data_1
A one-byte fixup.
PowerPC TLS Dynamic Call Fixup
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
std::unique_ptr< MCObjectTargetWriter > createLanaiELFObjectWriter(uint8_t OSABI)
Encapsulates the layout of an assembly file at a particular point in time.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_Data_8
A eight-byte fixup.
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
This represents an "assembler immediate".
@ FK_Data_2
A two-byte fixup.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.