LLVM 20.0.0git
LoongArchMCTargetDesc.cpp
Go to the documentation of this file.
1//===-- LoongArchMCTargetDesc.cpp - LoongArch Target Descriptions ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides LoongArch specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
14#include "LoongArchBaseInfo.h"
17#include "LoongArchMCAsmInfo.h"
20#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCDwarf.h"
24#include "llvm/MC/MCInstrInfo.h"
30
31#define GET_INSTRINFO_MC_DESC
32#define ENABLE_INSTR_PREDICATE_VERIFIER
33#include "LoongArchGenInstrInfo.inc"
34
35#define GET_REGINFO_MC_DESC
36#include "LoongArchGenRegisterInfo.inc"
37
38#define GET_SUBTARGETINFO_MC_DESC
39#include "LoongArchGenSubtargetInfo.inc"
40
41using namespace llvm;
42
45 InitLoongArchMCRegisterInfo(X, LoongArch::R1);
46 return X;
47}
48
50 MCInstrInfo *X = new MCInstrInfo();
51 InitLoongArchMCInstrInfo(X);
52 return X;
53}
54
55static MCSubtargetInfo *
57 if (CPU.empty() || CPU == "generic")
58 CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
59 return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
60}
61
63 const Triple &TT,
64 const MCTargetOptions &Options) {
65 MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT);
66
67 // Initial state of the frame pointer is sp(r3).
68 MCRegister SP = MRI.getDwarfRegNum(LoongArch::R3, true);
69 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
70 MAI->addInitialFrameState(Inst);
71
72 return MAI;
73}
74
76 unsigned SyntaxVariant,
77 const MCAsmInfo &MAI,
78 const MCInstrInfo &MII,
79 const MCRegisterInfo &MRI) {
80 return new LoongArchInstPrinter(MAI, MII, MRI);
81}
82
83static MCTargetStreamer *
86 ? new LoongArchTargetELFStreamer(S, STI)
87 : nullptr;
88}
89
90namespace {
91
92class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
93public:
94 explicit LoongArchMCInstrAnalysis(const MCInstrInfo *Info)
96
98 uint64_t &Target) const override {
99 unsigned NumOps = Inst.getNumOperands();
100 if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||
101 Inst.getOpcode() == LoongArch::BL) {
102 Target = Addr + Inst.getOperand(NumOps - 1).getImm();
103 return true;
104 }
105
106 return false;
107 }
108
109 bool isTerminator(const MCInst &Inst) const override {
111 return true;
112
113 switch (Inst.getOpcode()) {
114 default:
115 return false;
116 case LoongArch::JIRL:
117 return Inst.getOperand(0).getReg() == LoongArch::R0;
118 }
119 }
120
121 bool isCall(const MCInst &Inst) const override {
122 if (MCInstrAnalysis::isCall(Inst))
123 return true;
124
125 switch (Inst.getOpcode()) {
126 default:
127 return false;
128 case LoongArch::JIRL:
129 return Inst.getOperand(0).getReg() != LoongArch::R0;
130 }
131 }
132
133 bool isReturn(const MCInst &Inst) const override {
135 return true;
136
137 switch (Inst.getOpcode()) {
138 default:
139 return false;
140 case LoongArch::JIRL:
141 return Inst.getOperand(0).getReg() == LoongArch::R0 &&
142 Inst.getOperand(1).getReg() == LoongArch::R1;
143 }
144 }
145
146 bool isBranch(const MCInst &Inst) const override {
148 return true;
149
150 switch (Inst.getOpcode()) {
151 default:
152 return false;
153 case LoongArch::JIRL:
154 return Inst.getOperand(0).getReg() == LoongArch::R0 &&
155 Inst.getOperand(1).getReg() != LoongArch::R1;
156 }
157 }
158
159 bool isUnconditionalBranch(const MCInst &Inst) const override {
161 return true;
162
163 switch (Inst.getOpcode()) {
164 default:
165 return false;
166 case LoongArch::JIRL:
167 return Inst.getOperand(0).getReg() == LoongArch::R0 &&
168 Inst.getOperand(1).getReg() != LoongArch::R1;
169 }
170 }
171
172 bool isIndirectBranch(const MCInst &Inst) const override {
174 return true;
175
176 switch (Inst.getOpcode()) {
177 default:
178 return false;
179 case LoongArch::JIRL:
180 return Inst.getOperand(0).getReg() == LoongArch::R0 &&
181 Inst.getOperand(1).getReg() != LoongArch::R1;
182 }
183 }
184};
185
186} // end namespace
187
189 return new LoongArchMCInstrAnalysis(Info);
190}
191
192namespace {
194 std::unique_ptr<MCAsmBackend> &&MAB,
195 std::unique_ptr<MCObjectWriter> &&MOW,
196 std::unique_ptr<MCCodeEmitter> &&MCE) {
197 return createLoongArchELFStreamer(Context, std::move(MAB), std::move(MOW),
198 std::move(MCE));
199}
200} // end namespace
201
215 }
216}
unsigned const MachineRegisterInfo * MRI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
static MCSubtargetInfo * createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCTargetStreamer * createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstPrinter * createLoongArchMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTargetMC()
static MCRegisterInfo * createLoongArchMCRegisterInfo(const Triple &TT)
static MCAsmInfo * createLoongArchMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
static MCInstrAnalysis * createLoongArchInstrAnalysis(const MCInstrInfo *Info)
static MCInstrInfo * createLoongArchMCInstrInfo()
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:75
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:558
Context object for machine code objects.
Definition: MCContext.h:83
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
virtual bool isCall(const MCInst &Inst) const
virtual bool isBranch(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isTerminator(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual bool isIndirectBranch(const MCInst &Inst) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
int64_t getImm() const
Definition: MCInst.h:80
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:213
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Target specific streamer interface.
Definition: MCStreamer.h:94
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheLoongArch64Target()
MCCodeEmitter * createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend * createLoongArchAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheLoongArch32Target()
MCELFStreamer * createLoongArchELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.