LLVM 17.0.0git
RDFGraph.cpp
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1//===- RDFGraph.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Target-independent, SSA-based data flow graph for register data flow (RDF).
10//
12#include "llvm/ADT/BitVector.h"
13#include "llvm/ADT/STLExtras.h"
14#include "llvm/ADT/SetVector.h"
27#include "llvm/IR/Function.h"
28#include "llvm/MC/LaneBitmask.h"
29#include "llvm/MC/MCInstrDesc.h"
32#include <algorithm>
33#include <cassert>
34#include <cstdint>
35#include <cstring>
36#include <iterator>
37#include <set>
38#include <utility>
39#include <vector>
40
41using namespace llvm;
42using namespace rdf;
43
44// Printing functions. Have them here first, so that the rest of the code
45// can use them.
46namespace llvm {
47namespace rdf {
48
50 if (!P.Mask.all())
51 OS << ':' << PrintLaneMask(P.Mask);
52 return OS;
53}
54
56 auto &TRI = P.G.getTRI();
57 if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs())
58 OS << TRI.getName(P.Obj.Reg);
59 else
60 OS << '#' << P.Obj.Reg;
61 OS << PrintLaneMaskOpt(P.Obj.Mask);
62 return OS;
63}
64
66 auto NA = P.G.addr<NodeBase*>(P.Obj);
67 uint16_t Attrs = NA.Addr->getAttrs();
68 uint16_t Kind = NodeAttrs::kind(Attrs);
69 uint16_t Flags = NodeAttrs::flags(Attrs);
70 switch (NodeAttrs::type(Attrs)) {
71 case NodeAttrs::Code:
72 switch (Kind) {
73 case NodeAttrs::Func: OS << 'f'; break;
74 case NodeAttrs::Block: OS << 'b'; break;
75 case NodeAttrs::Stmt: OS << 's'; break;
76 case NodeAttrs::Phi: OS << 'p'; break;
77 default: OS << "c?"; break;
78 }
79 break;
80 case NodeAttrs::Ref:
81 if (Flags & NodeAttrs::Undef)
82 OS << '/';
83 if (Flags & NodeAttrs::Dead)
84 OS << '\\';
85 if (Flags & NodeAttrs::Preserving)
86 OS << '+';
87 if (Flags & NodeAttrs::Clobbering)
88 OS << '~';
89 switch (Kind) {
90 case NodeAttrs::Use: OS << 'u'; break;
91 case NodeAttrs::Def: OS << 'd'; break;
92 case NodeAttrs::Block: OS << 'b'; break;
93 default: OS << "r?"; break;
94 }
95 break;
96 default:
97 OS << '?';
98 break;
99 }
100 OS << P.Obj;
101 if (Flags & NodeAttrs::Shadow)
102 OS << '"';
103 return OS;
104}
105
107 const DataFlowGraph &G) {
108 OS << Print(RA.Id, G) << '<'
109 << Print(RA.Addr->getRegRef(G), G) << '>';
110 if (RA.Addr->getFlags() & NodeAttrs::Fixed)
111 OS << '!';
112}
113
115 printRefHeader(OS, P.Obj, P.G);
116 OS << '(';
117 if (NodeId N = P.Obj.Addr->getReachingDef())
118 OS << Print(N, P.G);
119 OS << ',';
120 if (NodeId N = P.Obj.Addr->getReachedDef())
121 OS << Print(N, P.G);
122 OS << ',';
123 if (NodeId N = P.Obj.Addr->getReachedUse())
124 OS << Print(N, P.G);
125 OS << "):";
126 if (NodeId N = P.Obj.Addr->getSibling())
127 OS << Print(N, P.G);
128 return OS;
129}
130
132 printRefHeader(OS, P.Obj, P.G);
133 OS << '(';
134 if (NodeId N = P.Obj.Addr->getReachingDef())
135 OS << Print(N, P.G);
136 OS << "):";
137 if (NodeId N = P.Obj.Addr->getSibling())
138 OS << Print(N, P.G);
139 return OS;
140}
141
143 const Print<NodeAddr<PhiUseNode*>> &P) {
144 printRefHeader(OS, P.Obj, P.G);
145 OS << '(';
146 if (NodeId N = P.Obj.Addr->getReachingDef())
147 OS << Print(N, P.G);
148 OS << ',';
149 if (NodeId N = P.Obj.Addr->getPredecessor())
150 OS << Print(N, P.G);
151 OS << "):";
152 if (NodeId N = P.Obj.Addr->getSibling())
153 OS << Print(N, P.G);
154 return OS;
155}
156
158 switch (P.Obj.Addr->getKind()) {
159 case NodeAttrs::Def:
160 OS << PrintNode<DefNode*>(P.Obj, P.G);
161 break;
162 case NodeAttrs::Use:
163 if (P.Obj.Addr->getFlags() & NodeAttrs::PhiRef)
164 OS << PrintNode<PhiUseNode*>(P.Obj, P.G);
165 else
166 OS << PrintNode<UseNode*>(P.Obj, P.G);
167 break;
168 }
169 return OS;
170}
171
173 unsigned N = P.Obj.size();
174 for (auto I : P.Obj) {
175 OS << Print(I.Id, P.G);
176 if (--N)
177 OS << ' ';
178 }
179 return OS;
180}
181
183 unsigned N = P.Obj.size();
184 for (auto I : P.Obj) {
185 OS << Print(I, P.G);
186 if (--N)
187 OS << ' ';
188 }
189 return OS;
190}
191
192namespace {
193
194 template <typename T>
195 struct PrintListV {
196 PrintListV(const NodeList &L, const DataFlowGraph &G) : List(L), G(G) {}
197
198 using Type = T;
201 };
202
203 template <typename T>
204 raw_ostream &operator<< (raw_ostream &OS, const PrintListV<T> &P) {
205 unsigned N = P.List.size();
206 for (NodeAddr<T> A : P.List) {
207 OS << PrintNode<T>(A, P.G);
208 if (--N)
209 OS << ", ";
210 }
211 return OS;
212 }
213
214} // end anonymous namespace
215
217 OS << Print(P.Obj.Id, P.G) << ": phi ["
218 << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']';
219 return OS;
220}
221
223 const MachineInstr &MI = *P.Obj.Addr->getCode();
224 unsigned Opc = MI.getOpcode();
225 OS << Print(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc);
226 // Print the target for calls and branches (for readability).
227 if (MI.isCall() || MI.isBranch()) {
229 llvm::find_if(MI.operands(),
230 [] (const MachineOperand &Op) -> bool {
231 return Op.isMBB() || Op.isGlobal() || Op.isSymbol();
232 });
233 if (T != MI.operands_end()) {
234 OS << ' ';
235 if (T->isMBB())
236 OS << printMBBReference(*T->getMBB());
237 else if (T->isGlobal())
238 OS << T->getGlobal()->getName();
239 else if (T->isSymbol())
240 OS << T->getSymbolName();
241 }
242 }
243 OS << " [" << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']';
244 return OS;
245}
246
248 const Print<NodeAddr<InstrNode*>> &P) {
249 switch (P.Obj.Addr->getKind()) {
250 case NodeAttrs::Phi:
251 OS << PrintNode<PhiNode*>(P.Obj, P.G);
252 break;
253 case NodeAttrs::Stmt:
254 OS << PrintNode<StmtNode*>(P.Obj, P.G);
255 break;
256 default:
257 OS << "instr? " << Print(P.Obj.Id, P.G);
258 break;
259 }
260 return OS;
261}
262
264 const Print<NodeAddr<BlockNode*>> &P) {
265 MachineBasicBlock *BB = P.Obj.Addr->getCode();
266 unsigned NP = BB->pred_size();
267 std::vector<int> Ns;
268 auto PrintBBs = [&OS] (std::vector<int> Ns) -> void {
269 unsigned N = Ns.size();
270 for (int I : Ns) {
271 OS << "%bb." << I;
272 if (--N)
273 OS << ", ";
274 }
275 };
276
277 OS << Print(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB)
278 << " --- preds(" << NP << "): ";
279 for (MachineBasicBlock *B : BB->predecessors())
280 Ns.push_back(B->getNumber());
281 PrintBBs(Ns);
282
283 unsigned NS = BB->succ_size();
284 OS << " succs(" << NS << "): ";
285 Ns.clear();
286 for (MachineBasicBlock *B : BB->successors())
287 Ns.push_back(B->getNumber());
288 PrintBBs(Ns);
289 OS << '\n';
290
291 for (auto I : P.Obj.Addr->members(P.G))
292 OS << PrintNode<InstrNode*>(I, P.G) << '\n';
293 return OS;
294}
295
297 OS << "DFG dump:[\n" << Print(P.Obj.Id, P.G) << ": Function: "
298 << P.Obj.Addr->getCode()->getName() << '\n';
299 for (auto I : P.Obj.Addr->members(P.G))
300 OS << PrintNode<BlockNode*>(I, P.G) << '\n';
301 OS << "]\n";
302 return OS;
303}
304
306 OS << '{';
307 for (auto I : P.Obj)
308 OS << ' ' << Print(I, P.G);
309 OS << " }";
310 return OS;
311}
312
314 P.Obj.print(OS);
315 return OS;
316}
317
320 for (auto I = P.Obj.top(), E = P.Obj.bottom(); I != E; ) {
321 OS << Print(I->Id, P.G)
322 << '<' << Print(I->Addr->getRegRef(P.G), P.G) << '>';
323 I.down();
324 if (I != E)
325 OS << ' ';
326 }
327 return OS;
328}
329
330} // end namespace rdf
331} // end namespace llvm
332
333// Node allocation functions.
334//
335// Node allocator is like a slab memory allocator: it allocates blocks of
336// memory in sizes that are multiples of the size of a node. Each block has
337// the same size. Nodes are allocated from the currently active block, and
338// when it becomes full, a new one is created.
339// There is a mapping scheme between node id and its location in a block,
340// and within that block is described in the header file.
341//
342void NodeAllocator::startNewBlock() {
343 void *T = MemPool.Allocate(NodesPerBlock*NodeMemSize, NodeMemSize);
344 char *P = static_cast<char*>(T);
345 Blocks.push_back(P);
346 // Check if the block index is still within the allowed range, i.e. less
347 // than 2^N, where N is the number of bits in NodeId for the block index.
348 // BitsPerIndex is the number of bits per node index.
349 assert((Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex))) &&
350 "Out of bits for block index");
351 ActiveEnd = P;
352}
353
354bool NodeAllocator::needNewBlock() {
355 if (Blocks.empty())
356 return true;
357
358 char *ActiveBegin = Blocks.back();
359 uint32_t Index = (ActiveEnd-ActiveBegin)/NodeMemSize;
360 return Index >= NodesPerBlock;
361}
362
364 if (needNewBlock())
365 startNewBlock();
366
367 uint32_t ActiveB = Blocks.size()-1;
368 uint32_t Index = (ActiveEnd - Blocks[ActiveB])/NodeMemSize;
369 NodeAddr<NodeBase*> NA = { reinterpret_cast<NodeBase*>(ActiveEnd),
370 makeId(ActiveB, Index) };
371 ActiveEnd += NodeMemSize;
372 return NA;
373}
374
376 uintptr_t A = reinterpret_cast<uintptr_t>(P);
377 for (unsigned i = 0, n = Blocks.size(); i != n; ++i) {
378 uintptr_t B = reinterpret_cast<uintptr_t>(Blocks[i]);
379 if (A < B || A >= B + NodesPerBlock*NodeMemSize)
380 continue;
382 return makeId(i, Idx);
383 }
384 llvm_unreachable("Invalid node address");
385}
386
388 MemPool.Reset();
389 Blocks.clear();
390 ActiveEnd = nullptr;
391}
392
393// Insert node NA after "this" in the circular chain.
395 NodeId Nx = Next;
396 // If NA is already "next", do nothing.
397 if (Next != NA.Id) {
398 Next = NA.Id;
399 NA.Addr->Next = Nx;
400 }
401}
402
403// Fundamental node manipulator functions.
404
405// Obtain the register reference from a reference node.
409 return G.unpack(Ref.PR);
410 assert(Ref.Op != nullptr);
411 return G.makeRegRef(*Ref.Op);
412}
413
414// Set the register reference in the reference node directly (for references
415// in phi nodes).
419 Ref.PR = G.pack(RR);
420}
421
422// Set the register reference in the reference node based on a machine
423// operand (for references in statement nodes).
427 (void)G;
428 Ref.Op = Op;
429}
430
431// Get the owner of a given reference node.
433 NodeAddr<NodeBase*> NA = G.addr<NodeBase*>(getNext());
434
435 while (NA.Addr != this) {
436 if (NA.Addr->getType() == NodeAttrs::Code)
437 return NA;
438 NA = G.addr<NodeBase*>(NA.Addr->getNext());
439 }
440 llvm_unreachable("No owner in circular list");
441}
442
443// Connect the def node to the reaching def node.
445 Ref.RD = DA.Id;
446 Ref.Sib = DA.Addr->getReachedDef();
447 DA.Addr->setReachedDef(Self);
448}
449
450// Connect the use node to the reaching def node.
452 Ref.RD = DA.Id;
453 Ref.Sib = DA.Addr->getReachedUse();
454 DA.Addr->setReachedUse(Self);
455}
456
457// Get the first member of the code node.
459 if (Code.FirstM == 0)
460 return NodeAddr<NodeBase*>();
461 return G.addr<NodeBase*>(Code.FirstM);
462}
463
464// Get the last member of the code node.
466 if (Code.LastM == 0)
467 return NodeAddr<NodeBase*>();
468 return G.addr<NodeBase*>(Code.LastM);
469}
470
471// Add node NA at the end of the member list of the given code node.
474 if (ML.Id != 0) {
475 ML.Addr->append(NA);
476 } else {
477 Code.FirstM = NA.Id;
478 NodeId Self = G.id(this);
479 NA.Addr->setNext(Self);
480 }
481 Code.LastM = NA.Id;
482}
483
484// Add node NA after member node MA in the given code node.
486 const DataFlowGraph &G) {
487 MA.Addr->append(NA);
488 if (Code.LastM == MA.Id)
489 Code.LastM = NA.Id;
490}
491
492// Remove member node NA from the given code node.
495 assert(MA.Id != 0);
496
497 // Special handling if the member to remove is the first member.
498 if (MA.Id == NA.Id) {
499 if (Code.LastM == MA.Id) {
500 // If it is the only member, set both first and last to 0.
501 Code.FirstM = Code.LastM = 0;
502 } else {
503 // Otherwise, advance the first member.
504 Code.FirstM = MA.Addr->getNext();
505 }
506 return;
507 }
508
509 while (MA.Addr != this) {
510 NodeId MX = MA.Addr->getNext();
511 if (MX == NA.Id) {
512 MA.Addr->setNext(NA.Addr->getNext());
513 // If the member to remove happens to be the last one, update the
514 // LastM indicator.
515 if (Code.LastM == NA.Id)
516 Code.LastM = MA.Id;
517 return;
518 }
519 MA = G.addr<NodeBase*>(MX);
520 }
521 llvm_unreachable("No such member");
522}
523
524// Return the list of all members of the code node.
526 static auto True = [] (NodeAddr<NodeBase*>) -> bool { return true; };
527 return members_if(True, G);
528}
529
530// Return the owner of the given instr node.
532 NodeAddr<NodeBase*> NA = G.addr<NodeBase*>(getNext());
533
534 while (NA.Addr != this) {
535 assert(NA.Addr->getType() == NodeAttrs::Code);
536 if (NA.Addr->getKind() == NodeAttrs::Block)
537 return NA;
538 NA = G.addr<NodeBase*>(NA.Addr->getNext());
539 }
540 llvm_unreachable("No owner in circular list");
541}
542
543// Add the phi node PA to the given block node.
546 if (M.Id == 0) {
547 addMember(PA, G);
548 return;
549 }
550
551 assert(M.Addr->getType() == NodeAttrs::Code);
552 if (M.Addr->getKind() == NodeAttrs::Stmt) {
553 // If the first member of the block is a statement, insert the phi as
554 // the first member.
555 Code.FirstM = PA.Id;
556 PA.Addr->setNext(M.Id);
557 } else {
558 // If the first member is a phi, find the last phi, and append PA to it.
559 assert(M.Addr->getKind() == NodeAttrs::Phi);
560 NodeAddr<NodeBase*> MN = M;
561 do {
562 M = MN;
563 MN = G.addr<NodeBase*>(M.Addr->getNext());
564 assert(MN.Addr->getType() == NodeAttrs::Code);
565 } while (MN.Addr->getKind() == NodeAttrs::Phi);
566
567 // M is the last phi.
568 addMemberAfter(M, PA, G);
569 }
570}
571
572// Find the block node corresponding to the machine basic block BB in the
573// given func node.
575 const DataFlowGraph &G) const {
576 auto EqBB = [BB] (NodeAddr<NodeBase*> NA) -> bool {
577 return NodeAddr<BlockNode*>(NA).Addr->getCode() == BB;
578 };
579 NodeList Ms = members_if(EqBB, G);
580 if (!Ms.empty())
581 return Ms[0];
582 return NodeAddr<BlockNode*>();
583}
584
585// Get the block node for the entry block in the given function.
587 MachineBasicBlock *EntryB = &getCode()->front();
588 return findBlock(EntryB, G);
589}
590
591// Target operand information.
592//
593
594// For a given instruction, check if there are any bits of RR that can remain
595// unchanged across this def.
596bool TargetOperandInfo::isPreserving(const MachineInstr &In, unsigned OpNum)
597 const {
598 return TII.isPredicated(In);
599}
600
601// Check if the definition of RR produces an unspecified value.
602bool TargetOperandInfo::isClobbering(const MachineInstr &In, unsigned OpNum)
603 const {
604 const MachineOperand &Op = In.getOperand(OpNum);
605 if (Op.isRegMask())
606 return true;
607 assert(Op.isReg());
608 if (In.isCall())
609 if (Op.isDef() && Op.isDead())
610 return true;
611 return false;
612}
613
614// Check if the given instruction specifically requires
615bool TargetOperandInfo::isFixedReg(const MachineInstr &In, unsigned OpNum)
616 const {
617 if (In.isCall() || In.isReturn() || In.isInlineAsm())
618 return true;
619 // Check for a tail call.
620 if (In.isBranch())
621 for (const MachineOperand &O : In.operands())
622 if (O.isGlobal() || O.isSymbol())
623 return true;
624
625 const MCInstrDesc &D = In.getDesc();
626 if (D.implicit_defs().empty() && D.implicit_uses().empty())
627 return false;
628 const MachineOperand &Op = In.getOperand(OpNum);
629 // If there is a sub-register, treat the operand as non-fixed. Currently,
630 // fixed registers are those that are listed in the descriptor as implicit
631 // uses or defs, and those lists do not allow sub-registers.
632 if (Op.getSubReg() != 0)
633 return false;
634 Register Reg = Op.getReg();
635 ArrayRef<MCPhysReg> ImpOps =
636 Op.isDef() ? D.implicit_defs() : D.implicit_uses();
637 return is_contained(ImpOps, Reg);
638}
639
640//
641// The data flow graph construction.
642//
643
645 const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
646 const MachineDominanceFrontier &mdf)
647 : DefaultTOI(std::make_unique<TargetOperandInfo>(tii)), MF(mf), TII(tii),
648 TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(*DefaultTOI),
649 LiveIns(PRI) {
650}
651
653 const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
654 const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi)
655 : MF(mf), TII(tii), TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi),
656 LiveIns(PRI) {
657}
658
659// The implementation of the definition stack.
660// Each register reference has its own definition stack. In particular,
661// for a register references "Reg" and "Reg:subreg" will each have their
662// own definition stacks.
663
664// Construct a stack iterator.
665DataFlowGraph::DefStack::Iterator::Iterator(const DataFlowGraph::DefStack &S,
666 bool Top) : DS(S) {
667 if (!Top) {
668 // Initialize to bottom.
669 Pos = 0;
670 return;
671 }
672 // Initialize to the top, i.e. top-most non-delimiter (or 0, if empty).
673 Pos = DS.Stack.size();
674 while (Pos > 0 && DS.isDelimiter(DS.Stack[Pos-1]))
675 Pos--;
676}
677
678// Return the size of the stack, including block delimiters.
680 unsigned S = 0;
681 for (auto I = top(), E = bottom(); I != E; I.down())
682 S++;
683 return S;
684}
685
686// Remove the top entry from the stack. Remove all intervening delimiters
687// so that after this, the stack is either empty, or the top of the stack
688// is a non-delimiter.
690 assert(!empty());
691 unsigned P = nextDown(Stack.size());
692 Stack.resize(P);
693}
694
695// Push a delimiter for block node N on the stack.
697 assert(N != 0);
698 Stack.push_back(NodeAddr<DefNode*>(nullptr, N));
699}
700
701// Remove all nodes from the top of the stack, until the delimited for
702// block node N is encountered. Remove the delimiter as well. In effect,
703// this will remove from the stack all definitions from block N.
705 assert(N != 0);
706 unsigned P = Stack.size();
707 while (P > 0) {
708 bool Found = isDelimiter(Stack[P-1], N);
709 P--;
710 if (Found)
711 break;
712 }
713 // This will also remove the delimiter, if found.
714 Stack.resize(P);
715}
716
717// Move the stack iterator up by one.
718unsigned DataFlowGraph::DefStack::nextUp(unsigned P) const {
719 // Get the next valid position after P (skipping all delimiters).
720 // The input position P does not have to point to a non-delimiter.
721 unsigned SS = Stack.size();
722 bool IsDelim;
723 assert(P < SS);
724 do {
725 P++;
726 IsDelim = isDelimiter(Stack[P-1]);
727 } while (P < SS && IsDelim);
728 assert(!IsDelim);
729 return P;
730}
731
732// Move the stack iterator down by one.
733unsigned DataFlowGraph::DefStack::nextDown(unsigned P) const {
734 // Get the preceding valid position before P (skipping all delimiters).
735 // The input position P does not have to point to a non-delimiter.
736 assert(P > 0 && P <= Stack.size());
737 bool IsDelim = isDelimiter(Stack[P-1]);
738 do {
739 if (--P == 0)
740 break;
741 IsDelim = isDelimiter(Stack[P-1]);
742 } while (P > 0 && IsDelim);
743 assert(!IsDelim);
744 return P;
745}
746
747// Register information.
748
749RegisterSet DataFlowGraph::getLandingPadLiveIns() const {
750 RegisterSet LR;
751 const Function &F = MF.getFunction();
752 const Constant *PF = F.hasPersonalityFn() ? F.getPersonalityFn()
753 : nullptr;
754 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
756 LR.insert(RegisterRef(R));
759 LR.insert(RegisterRef(R));
760 }
761 return LR;
762}
763
764// Node management functions.
765
766// Get the pointer to the node with the id N.
768 if (N == 0)
769 return nullptr;
770 return Memory.ptr(N);
771}
772
773// Get the id of the node at the address P.
775 if (P == nullptr)
776 return 0;
777 return Memory.id(P);
778}
779
780// Allocate a new node and set the attributes to Attrs.
781NodeAddr<NodeBase*> DataFlowGraph::newNode(uint16_t Attrs) {
783 P.Addr->init();
784 P.Addr->setAttrs(Attrs);
785 return P;
786}
787
788// Make a copy of the given node B, except for the data-flow links, which
789// are set to 0.
790NodeAddr<NodeBase*> DataFlowGraph::cloneNode(const NodeAddr<NodeBase*> B) {
791 NodeAddr<NodeBase*> NA = newNode(0);
792 memcpy(NA.Addr, B.Addr, sizeof(NodeBase));
793 // Ref nodes need to have the data-flow links reset.
794 if (NA.Addr->getType() == NodeAttrs::Ref) {
796 RA.Addr->setReachingDef(0);
797 RA.Addr->setSibling(0);
798 if (NA.Addr->getKind() == NodeAttrs::Def) {
799 NodeAddr<DefNode*> DA = NA;
800 DA.Addr->setReachedDef(0);
801 DA.Addr->setReachedUse(0);
802 }
803 }
804 return NA;
805}
806
807// Allocation routines for specific node types/kinds.
808
809NodeAddr<UseNode*> DataFlowGraph::newUse(NodeAddr<InstrNode*> Owner,
810 MachineOperand &Op, uint16_t Flags) {
811 NodeAddr<UseNode*> UA = newNode(NodeAttrs::Ref | NodeAttrs::Use | Flags);
812 UA.Addr->setRegRef(&Op, *this);
813 return UA;
814}
815
816NodeAddr<PhiUseNode*> DataFlowGraph::newPhiUse(NodeAddr<PhiNode*> Owner,
817 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) {
818 NodeAddr<PhiUseNode*> PUA = newNode(NodeAttrs::Ref | NodeAttrs::Use | Flags);
819 assert(Flags & NodeAttrs::PhiRef);
820 PUA.Addr->setRegRef(RR, *this);
821 PUA.Addr->setPredecessor(PredB.Id);
822 return PUA;
823}
824
825NodeAddr<DefNode*> DataFlowGraph::newDef(NodeAddr<InstrNode*> Owner,
826 MachineOperand &Op, uint16_t Flags) {
828 DA.Addr->setRegRef(&Op, *this);
829 return DA;
830}
831
832NodeAddr<DefNode*> DataFlowGraph::newDef(NodeAddr<InstrNode*> Owner,
833 RegisterRef RR, uint16_t Flags) {
835 assert(Flags & NodeAttrs::PhiRef);
836 DA.Addr->setRegRef(RR, *this);
837 return DA;
838}
839
840NodeAddr<PhiNode*> DataFlowGraph::newPhi(NodeAddr<BlockNode*> Owner) {
842 Owner.Addr->addPhi(PA, *this);
843 return PA;
844}
845
846NodeAddr<StmtNode*> DataFlowGraph::newStmt(NodeAddr<BlockNode*> Owner,
847 MachineInstr *MI) {
849 SA.Addr->setCode(MI);
850 Owner.Addr->addMember(SA, *this);
851 return SA;
852}
853
854NodeAddr<BlockNode*> DataFlowGraph::newBlock(NodeAddr<FuncNode*> Owner,
855 MachineBasicBlock *BB) {
857 BA.Addr->setCode(BB);
858 Owner.Addr->addMember(BA, *this);
859 return BA;
860}
861
862NodeAddr<FuncNode*> DataFlowGraph::newFunc(MachineFunction *MF) {
864 FA.Addr->setCode(MF);
865 return FA;
866}
867
868// Build the data flow graph.
870 reset();
871 Func = newFunc(&MF);
872
873 if (MF.empty())
874 return;
875
876 for (MachineBasicBlock &B : MF) {
877 NodeAddr<BlockNode*> BA = newBlock(Func, &B);
878 BlockNodes.insert(std::make_pair(&B, BA));
879 for (MachineInstr &I : B) {
880 if (I.isDebugInstr())
881 continue;
882 buildStmt(BA, I);
883 }
884 }
885
886 NodeAddr<BlockNode*> EA = Func.Addr->getEntryBlock(*this);
887 NodeList Blocks = Func.Addr->members(*this);
888
889 // Collect information about block references.
890 RegisterSet AllRefs;
891 for (NodeAddr<BlockNode*> BA : Blocks)
892 for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this))
893 for (NodeAddr<RefNode*> RA : IA.Addr->members(*this))
894 AllRefs.insert(RA.Addr->getRegRef(*this));
895
896 // Collect function live-ins and entry block live-ins.
897 MachineRegisterInfo &MRI = MF.getRegInfo();
898 MachineBasicBlock &EntryB = *EA.Addr->getCode();
899 assert(EntryB.pred_empty() && "Function entry block has predecessors");
900 for (std::pair<unsigned,unsigned> P : MRI.liveins())
901 LiveIns.insert(RegisterRef(P.first));
902 if (MRI.tracksLiveness()) {
903 for (auto I : EntryB.liveins())
904 LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask));
905 }
906
907 // Add function-entry phi nodes for the live-in registers.
908 //for (std::pair<RegisterId,LaneBitmask> P : LiveIns) {
909 for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) {
910 RegisterRef RR = *I;
911 NodeAddr<PhiNode*> PA = newPhi(EA);
913 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
914 PA.Addr->addMember(DA, *this);
915 }
916
917 // Add phis for landing pads.
918 // Landing pads, unlike usual backs blocks, are not entered through
919 // branches in the program, or fall-throughs from other blocks. They
920 // are entered from the exception handling runtime and target's ABI
921 // may define certain registers as defined on entry to such a block.
922 RegisterSet EHRegs = getLandingPadLiveIns();
923 if (!EHRegs.empty()) {
924 for (NodeAddr<BlockNode*> BA : Blocks) {
925 const MachineBasicBlock &B = *BA.Addr->getCode();
926 if (!B.isEHPad())
927 continue;
928
929 // Prepare a list of NodeIds of the block's predecessors.
930 NodeList Preds;
931 for (MachineBasicBlock *PB : B.predecessors())
932 Preds.push_back(findBlock(PB));
933
934 // Build phi nodes for each live-in.
935 for (RegisterRef RR : EHRegs) {
936 NodeAddr<PhiNode*> PA = newPhi(BA);
938 // Add def:
939 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
940 PA.Addr->addMember(DA, *this);
941 // Add uses (no reaching defs for phi uses):
942 for (NodeAddr<BlockNode*> PBA : Preds) {
943 NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA);
944 PA.Addr->addMember(PUA, *this);
945 }
946 }
947 }
948 }
949
950 // Build a map "PhiM" which will contain, for each block, the set
951 // of references that will require phi definitions in that block.
952 BlockRefsMap PhiM;
953 for (NodeAddr<BlockNode*> BA : Blocks)
954 recordDefsForDF(PhiM, BA);
955 for (NodeAddr<BlockNode*> BA : Blocks)
956 buildPhis(PhiM, AllRefs, BA);
957
958 // Link all the refs. This will recursively traverse the dominator tree.
960 linkBlockRefs(DM, EA);
961
962 // Finally, remove all unused phi nodes.
964 removeUnusedPhis();
965}
966
967RegisterRef DataFlowGraph::makeRegRef(unsigned Reg, unsigned Sub) const {
970 assert(Reg != 0);
971 if (Sub != 0)
972 Reg = TRI.getSubReg(Reg, Sub);
973 return RegisterRef(Reg);
974}
975
977 assert(Op.isReg() || Op.isRegMask());
978 if (Op.isReg())
979 return makeRegRef(Op.getReg(), Op.getSubReg());
980 return RegisterRef(PRI.getRegMaskId(Op.getRegMask()), LaneBitmask::getAll());
981}
982
983// For each stack in the map DefM, push the delimiter for block B on it.
985 // Push block delimiters.
986 for (auto &P : DefM)
987 P.second.start_block(B);
988}
989
990// Remove all definitions coming from block B from each stack in DefM.
992 // Pop all defs from this block from the definition stack. Defs that were
993 // added to the map during the traversal of instructions will not have a
994 // delimiter, but for those, the whole stack will be emptied.
995 for (auto &P : DefM)
996 P.second.clear_block(B);
997
998 // Finally, remove empty stacks from the map.
999 for (auto I = DefM.begin(), E = DefM.end(), NextI = I; I != E; I = NextI) {
1000 NextI = std::next(I);
1001 // This preserves the validity of iterators other than I.
1002 if (I->second.empty())
1003 DefM.erase(I);
1004 }
1005}
1006
1007// Push all definitions from the instruction node IA to an appropriate
1008// stack in DefM.
1010 pushClobbers(IA, DefM);
1011 pushDefs(IA, DefM);
1012}
1013
1014// Push all definitions from the instruction node IA to an appropriate
1015// stack in DefM.
1016void DataFlowGraph::pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
1017 NodeSet Visited;
1018 std::set<RegisterId> Defined;
1019
1020 // The important objectives of this function are:
1021 // - to be able to handle instructions both while the graph is being
1022 // constructed, and after the graph has been constructed, and
1023 // - maintain proper ordering of definitions on the stack for each
1024 // register reference:
1025 // - if there are two or more related defs in IA (i.e. coming from
1026 // the same machine operand), then only push one def on the stack,
1027 // - if there are multiple unrelated defs of non-overlapping
1028 // subregisters of S, then the stack for S will have both (in an
1029 // unspecified order), but the order does not matter from the data-
1030 // -flow perspective.
1031
1032 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) {
1033 if (Visited.count(DA.Id))
1034 continue;
1035 if (!(DA.Addr->getFlags() & NodeAttrs::Clobbering))
1036 continue;
1037
1038 NodeList Rel = getRelatedRefs(IA, DA);
1039 NodeAddr<DefNode*> PDA = Rel.front();
1040 RegisterRef RR = PDA.Addr->getRegRef(*this);
1041
1042 // Push the definition on the stack for the register and all aliases.
1043 // The def stack traversal in linkNodeUp will check the exact aliasing.
1044 DefM[RR.Reg].push(DA);
1045 Defined.insert(RR.Reg);
1046 for (RegisterId A : PRI.getAliasSet(RR.Reg)) {
1047 // Check that we don't push the same def twice.
1048 assert(A != RR.Reg);
1049 if (!Defined.count(A))
1050 DefM[A].push(DA);
1051 }
1052 // Mark all the related defs as visited.
1053 for (NodeAddr<NodeBase*> T : Rel)
1054 Visited.insert(T.Id);
1055 }
1056}
1057
1058// Push all definitions from the instruction node IA to an appropriate
1059// stack in DefM.
1060void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
1061 NodeSet Visited;
1062#ifndef NDEBUG
1063 std::set<RegisterId> Defined;
1064#endif
1065
1066 // The important objectives of this function are:
1067 // - to be able to handle instructions both while the graph is being
1068 // constructed, and after the graph has been constructed, and
1069 // - maintain proper ordering of definitions on the stack for each
1070 // register reference:
1071 // - if there are two or more related defs in IA (i.e. coming from
1072 // the same machine operand), then only push one def on the stack,
1073 // - if there are multiple unrelated defs of non-overlapping
1074 // subregisters of S, then the stack for S will have both (in an
1075 // unspecified order), but the order does not matter from the data-
1076 // -flow perspective.
1077
1078 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) {
1079 if (Visited.count(DA.Id))
1080 continue;
1081 if (DA.Addr->getFlags() & NodeAttrs::Clobbering)
1082 continue;
1083
1084 NodeList Rel = getRelatedRefs(IA, DA);
1085 NodeAddr<DefNode*> PDA = Rel.front();
1086 RegisterRef RR = PDA.Addr->getRegRef(*this);
1087#ifndef NDEBUG
1088 // Assert if the register is defined in two or more unrelated defs.
1089 // This could happen if there are two or more def operands defining it.
1090 if (!Defined.insert(RR.Reg).second) {
1091 MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
1092 dbgs() << "Multiple definitions of register: "
1093 << Print(RR, *this) << " in\n " << *MI << "in "
1094 << printMBBReference(*MI->getParent()) << '\n';
1095 llvm_unreachable(nullptr);
1096 }
1097#endif
1098 // Push the definition on the stack for the register and all aliases.
1099 // The def stack traversal in linkNodeUp will check the exact aliasing.
1100 DefM[RR.Reg].push(DA);
1101 for (RegisterId A : PRI.getAliasSet(RR.Reg)) {
1102 // Check that we don't push the same def twice.
1103 assert(A != RR.Reg);
1104 DefM[A].push(DA);
1105 }
1106 // Mark all the related defs as visited.
1107 for (NodeAddr<NodeBase*> T : Rel)
1108 Visited.insert(T.Id);
1109 }
1110}
1111
1112// Return the list of all reference nodes related to RA, including RA itself.
1113// See "getNextRelated" for the meaning of a "related reference".
1115 NodeAddr<RefNode*> RA) const {
1116 assert(IA.Id != 0 && RA.Id != 0);
1117
1118 NodeList Refs;
1119 NodeId Start = RA.Id;
1120 do {
1121 Refs.push_back(RA);
1122 RA = getNextRelated(IA, RA);
1123 } while (RA.Id != 0 && RA.Id != Start);
1124 return Refs;
1125}
1126
1127// Clear all information in the graph.
1128void DataFlowGraph::reset() {
1129 Memory.clear();
1130 BlockNodes.clear();
1131 Func = NodeAddr<FuncNode*>();
1132}
1133
1134// Return the next reference node in the instruction node IA that is related
1135// to RA. Conceptually, two reference nodes are related if they refer to the
1136// same instance of a register access, but differ in flags or other minor
1137// characteristics. Specific examples of related nodes are shadow reference
1138// nodes.
1139// Return the equivalent of nullptr if there are no more related references.
1141 NodeAddr<RefNode*> RA) const {
1142 assert(IA.Id != 0 && RA.Id != 0);
1143
1144 auto Related = [this,RA](NodeAddr<RefNode*> TA) -> bool {
1145 if (TA.Addr->getKind() != RA.Addr->getKind())
1146 return false;
1147 if (TA.Addr->getRegRef(*this) != RA.Addr->getRegRef(*this))
1148 return false;
1149 return true;
1150 };
1151 auto RelatedStmt = [&Related,RA](NodeAddr<RefNode*> TA) -> bool {
1152 return Related(TA) &&
1153 &RA.Addr->getOp() == &TA.Addr->getOp();
1154 };
1155 auto RelatedPhi = [&Related,RA](NodeAddr<RefNode*> TA) -> bool {
1156 if (!Related(TA))
1157 return false;
1158 if (TA.Addr->getKind() != NodeAttrs::Use)
1159 return true;
1160 // For phi uses, compare predecessor blocks.
1161 const NodeAddr<const PhiUseNode*> TUA = TA;
1162 const NodeAddr<const PhiUseNode*> RUA = RA;
1163 return TUA.Addr->getPredecessor() == RUA.Addr->getPredecessor();
1164 };
1165
1166 RegisterRef RR = RA.Addr->getRegRef(*this);
1167 if (IA.Addr->getKind() == NodeAttrs::Stmt)
1168 return RA.Addr->getNextRef(RR, RelatedStmt, true, *this);
1169 return RA.Addr->getNextRef(RR, RelatedPhi, true, *this);
1170}
1171
1172// Find the next node related to RA in IA that satisfies condition P.
1173// If such a node was found, return a pair where the second element is the
1174// located node. If such a node does not exist, return a pair where the
1175// first element is the element after which such a node should be inserted,
1176// and the second element is a null-address.
1177template <typename Predicate>
1178std::pair<NodeAddr<RefNode*>,NodeAddr<RefNode*>>
1179DataFlowGraph::locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA,
1180 Predicate P) const {
1181 assert(IA.Id != 0 && RA.Id != 0);
1182
1184 NodeId Start = RA.Id;
1185 while (true) {
1186 NA = getNextRelated(IA, RA);
1187 if (NA.Id == 0 || NA.Id == Start)
1188 break;
1189 if (P(NA))
1190 break;
1191 RA = NA;
1192 }
1193
1194 if (NA.Id != 0 && NA.Id != Start)
1195 return std::make_pair(RA, NA);
1196 return std::make_pair(RA, NodeAddr<RefNode*>());
1197}
1198
1199// Get the next shadow node in IA corresponding to RA, and optionally create
1200// such a node if it does not exist.
1202 NodeAddr<RefNode*> RA, bool Create) {
1203 assert(IA.Id != 0 && RA.Id != 0);
1204
1205 uint16_t Flags = RA.Addr->getFlags() | NodeAttrs::Shadow;
1206 auto IsShadow = [Flags] (NodeAddr<RefNode*> TA) -> bool {
1207 return TA.Addr->getFlags() == Flags;
1208 };
1209 auto Loc = locateNextRef(IA, RA, IsShadow);
1210 if (Loc.second.Id != 0 || !Create)
1211 return Loc.second;
1212
1213 // Create a copy of RA and mark is as shadow.
1214 NodeAddr<RefNode*> NA = cloneNode(RA);
1215 NA.Addr->setFlags(Flags | NodeAttrs::Shadow);
1216 IA.Addr->addMemberAfter(Loc.first, NA, *this);
1217 return NA;
1218}
1219
1220// Get the next shadow node in IA corresponding to RA. Return null-address
1221// if such a node does not exist.
1223 NodeAddr<RefNode*> RA) const {
1224 assert(IA.Id != 0 && RA.Id != 0);
1225 uint16_t Flags = RA.Addr->getFlags() | NodeAttrs::Shadow;
1226 auto IsShadow = [Flags] (NodeAddr<RefNode*> TA) -> bool {
1227 return TA.Addr->getFlags() == Flags;
1228 };
1229 return locateNextRef(IA, RA, IsShadow).second;
1230}
1231
1232// Create a new statement node in the block node BA that corresponds to
1233// the machine instruction MI.
1234void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) {
1235 NodeAddr<StmtNode*> SA = newStmt(BA, &In);
1236
1237 auto isCall = [] (const MachineInstr &In) -> bool {
1238 if (In.isCall())
1239 return true;
1240 // Is tail call?
1241 if (In.isBranch()) {
1242 for (const MachineOperand &Op : In.operands())
1243 if (Op.isGlobal() || Op.isSymbol())
1244 return true;
1245 // Assume indirect branches are calls. This is for the purpose of
1246 // keeping implicit operands, and so it won't hurt on intra-function
1247 // indirect branches.
1248 if (In.isIndirectBranch())
1249 return true;
1250 }
1251 return false;
1252 };
1253
1254 auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool {
1255 // This instruction defines DR. Check if there is a use operand that
1256 // would make DR live on entry to the instruction.
1257 for (const MachineOperand &Op : In.operands()) {
1258 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1259 continue;
1260 RegisterRef UR = makeRegRef(Op);
1261 if (PRI.alias(DR, UR))
1262 return false;
1263 }
1264 return true;
1265 };
1266
1267 bool IsCall = isCall(In);
1268 unsigned NumOps = In.getNumOperands();
1269
1270 // Avoid duplicate implicit defs. This will not detect cases of implicit
1271 // defs that define registers that overlap, but it is not clear how to
1272 // interpret that in the absence of explicit defs. Overlapping explicit
1273 // defs are likely illegal already.
1274 BitVector DoneDefs(TRI.getNumRegs());
1275 // Process explicit defs first.
1276 for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
1277 MachineOperand &Op = In.getOperand(OpN);
1278 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1279 continue;
1280 Register R = Op.getReg();
1281 if (!R || !R.isPhysical())
1282 continue;
1284 if (TOI.isPreserving(In, OpN)) {
1286 // If the def is preserving, check if it is also undefined.
1287 if (isDefUndef(In, makeRegRef(Op)))
1289 }
1290 if (TOI.isClobbering(In, OpN))
1292 if (TOI.isFixedReg(In, OpN))
1294 if (IsCall && Op.isDead())
1296 NodeAddr<DefNode*> DA = newDef(SA, Op, Flags);
1297 SA.Addr->addMember(DA, *this);
1298 assert(!DoneDefs.test(R));
1299 DoneDefs.set(R);
1300 }
1301
1302 // Process reg-masks (as clobbers).
1303 BitVector DoneClobbers(TRI.getNumRegs());
1304 for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
1305 MachineOperand &Op = In.getOperand(OpN);
1306 if (!Op.isRegMask())
1307 continue;
1310 NodeAddr<DefNode*> DA = newDef(SA, Op, Flags);
1311 SA.Addr->addMember(DA, *this);
1312 // Record all clobbered registers in DoneDefs.
1313 const uint32_t *RM = Op.getRegMask();
1314 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i)
1315 if (!(RM[i/32] & (1u << (i%32))))
1316 DoneClobbers.set(i);
1317 }
1318
1319 // Process implicit defs, skipping those that have already been added
1320 // as explicit.
1321 for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
1322 MachineOperand &Op = In.getOperand(OpN);
1323 if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
1324 continue;
1325 Register R = Op.getReg();
1326 if (!R || !R.isPhysical() || DoneDefs.test(R))
1327 continue;
1328 RegisterRef RR = makeRegRef(Op);
1330 if (TOI.isPreserving(In, OpN)) {
1332 // If the def is preserving, check if it is also undefined.
1333 if (isDefUndef(In, RR))
1335 }
1336 if (TOI.isClobbering(In, OpN))
1338 if (TOI.isFixedReg(In, OpN))
1340 if (IsCall && Op.isDead()) {
1341 if (DoneClobbers.test(R))
1342 continue;
1344 }
1345 NodeAddr<DefNode*> DA = newDef(SA, Op, Flags);
1346 SA.Addr->addMember(DA, *this);
1347 DoneDefs.set(R);
1348 }
1349
1350 for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
1351 MachineOperand &Op = In.getOperand(OpN);
1352 if (!Op.isReg() || !Op.isUse())
1353 continue;
1354 Register R = Op.getReg();
1355 if (!R || !R.isPhysical())
1356 continue;
1358 if (Op.isUndef())
1360 if (TOI.isFixedReg(In, OpN))
1362 NodeAddr<UseNode*> UA = newUse(SA, Op, Flags);
1363 SA.Addr->addMember(UA, *this);
1364 }
1365}
1366
1367// Scan all defs in the block node BA and record in PhiM the locations of
1368// phi nodes corresponding to these defs.
1369void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM,
1371 // Check all defs from block BA and record them in each block in BA's
1372 // iterated dominance frontier. This information will later be used to
1373 // create phi nodes.
1374 MachineBasicBlock *BB = BA.Addr->getCode();
1375 assert(BB);
1376 auto DFLoc = MDF.find(BB);
1377 if (DFLoc == MDF.end() || DFLoc->second.empty())
1378 return;
1379
1380 // Traverse all instructions in the block and collect the set of all
1381 // defined references. For each reference there will be a phi created
1382 // in the block's iterated dominance frontier.
1383 // This is done to make sure that each defined reference gets only one
1384 // phi node, even if it is defined multiple times.
1385 RegisterSet Defs;
1386 for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this))
1387 for (NodeAddr<RefNode*> RA : IA.Addr->members_if(IsDef, *this))
1388 Defs.insert(RA.Addr->getRegRef(*this));
1389
1390 // Calculate the iterated dominance frontier of BB.
1391 const MachineDominanceFrontier::DomSetType &DF = DFLoc->second;
1392 SetVector<MachineBasicBlock*> IDF(DF.begin(), DF.end());
1393 for (unsigned i = 0; i < IDF.size(); ++i) {
1394 auto F = MDF.find(IDF[i]);
1395 if (F != MDF.end())
1396 IDF.insert(F->second.begin(), F->second.end());
1397 }
1398
1399 // Finally, add the set of defs to each block in the iterated dominance
1400 // frontier.
1401 for (auto *DB : IDF) {
1403 PhiM[DBA.Id].insert(Defs.begin(), Defs.end());
1404 }
1405}
1406
1407// Given the locations of phi nodes in the map PhiM, create the phi nodes
1408// that are located in the block node BA.
1409void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
1411 // Check if this blocks has any DF defs, i.e. if there are any defs
1412 // that this block is in the iterated dominance frontier of.
1413 auto HasDF = PhiM.find(BA.Id);
1414 if (HasDF == PhiM.end() || HasDF->second.empty())
1415 return;
1416
1417 // First, remove all R in Refs in such that there exists T in Refs
1418 // such that T covers R. In other words, only leave those refs that
1419 // are not covered by another ref (i.e. maximal with respect to covering).
1420
1421 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef {
1422 for (RegisterRef I : RRs)
1423 if (I != RR && RegisterAggr::isCoverOf(I, RR, PRI))
1424 RR = I;
1425 return RR;
1426 };
1427
1428 RegisterSet MaxDF;
1429 for (RegisterRef I : HasDF->second)
1430 MaxDF.insert(MaxCoverIn(I, HasDF->second));
1431
1432 std::vector<RegisterRef> MaxRefs;
1433 for (RegisterRef I : MaxDF)
1434 MaxRefs.push_back(MaxCoverIn(I, AllRefs));
1435
1436 // Now, for each R in MaxRefs, get the alias closure of R. If the closure
1437 // only has R in it, create a phi a def for R. Otherwise, create a phi,
1438 // and add a def for each S in the closure.
1439
1440 // Sort the refs so that the phis will be created in a deterministic order.
1441 llvm::sort(MaxRefs);
1442 // Remove duplicates.
1443 auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end());
1444 MaxRefs.erase(NewEnd, MaxRefs.end());
1445
1446 auto Aliased = [this,&MaxRefs](RegisterRef RR,
1447 std::vector<unsigned> &Closure) -> bool {
1448 for (unsigned I : Closure)
1449 if (PRI.alias(RR, MaxRefs[I]))
1450 return true;
1451 return false;
1452 };
1453
1454 // Prepare a list of NodeIds of the block's predecessors.
1455 NodeList Preds;
1456 const MachineBasicBlock *MBB = BA.Addr->getCode();
1458 Preds.push_back(findBlock(PB));
1459
1460 while (!MaxRefs.empty()) {
1461 // Put the first element in the closure, and then add all subsequent
1462 // elements from MaxRefs to it, if they alias at least one element
1463 // already in the closure.
1464 // ClosureIdx: vector of indices in MaxRefs of members of the closure.
1465 std::vector<unsigned> ClosureIdx = { 0 };
1466 for (unsigned i = 1; i != MaxRefs.size(); ++i)
1467 if (Aliased(MaxRefs[i], ClosureIdx))
1468 ClosureIdx.push_back(i);
1469
1470 // Build a phi for the closure.
1471 unsigned CS = ClosureIdx.size();
1472 NodeAddr<PhiNode*> PA = newPhi(BA);
1473
1474 // Add defs.
1475 for (unsigned X = 0; X != CS; ++X) {
1476 RegisterRef RR = MaxRefs[ClosureIdx[X]];
1478 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
1479 PA.Addr->addMember(DA, *this);
1480 }
1481 // Add phi uses.
1482 for (NodeAddr<BlockNode*> PBA : Preds) {
1483 for (unsigned X = 0; X != CS; ++X) {
1484 RegisterRef RR = MaxRefs[ClosureIdx[X]];
1485 NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA);
1486 PA.Addr->addMember(PUA, *this);
1487 }
1488 }
1489
1490 // Erase from MaxRefs all elements in the closure.
1491 auto Begin = MaxRefs.begin();
1492 for (unsigned Idx : llvm::reverse(ClosureIdx))
1493 MaxRefs.erase(Begin + Idx);
1494 }
1495}
1496
1497// Remove any unneeded phi nodes that were created during the build process.
1498void DataFlowGraph::removeUnusedPhis() {
1499 // This will remove unused phis, i.e. phis where each def does not reach
1500 // any uses or other defs. This will not detect or remove circular phi
1501 // chains that are otherwise dead. Unused/dead phis are created during
1502 // the build process and this function is intended to remove these cases
1503 // that are easily determinable to be unnecessary.
1504
1505 SetVector<NodeId> PhiQ;
1506 for (NodeAddr<BlockNode*> BA : Func.Addr->members(*this)) {
1507 for (auto P : BA.Addr->members_if(IsPhi, *this))
1508 PhiQ.insert(P.Id);
1509 }
1510
1511 static auto HasUsedDef = [](NodeList &Ms) -> bool {
1512 for (NodeAddr<NodeBase*> M : Ms) {
1513 if (M.Addr->getKind() != NodeAttrs::Def)
1514 continue;
1516 if (DA.Addr->getReachedDef() != 0 || DA.Addr->getReachedUse() != 0)
1517 return true;
1518 }
1519 return false;
1520 };
1521
1522 // Any phi, if it is removed, may affect other phis (make them dead).
1523 // For each removed phi, collect the potentially affected phis and add
1524 // them back to the queue.
1525 while (!PhiQ.empty()) {
1526 auto PA = addr<PhiNode*>(PhiQ[0]);
1527 PhiQ.remove(PA.Id);
1528 NodeList Refs = PA.Addr->members(*this);
1529 if (HasUsedDef(Refs))
1530 continue;
1531 for (NodeAddr<RefNode*> RA : Refs) {
1532 if (NodeId RD = RA.Addr->getReachingDef()) {
1533 auto RDA = addr<DefNode*>(RD);
1534 NodeAddr<InstrNode*> OA = RDA.Addr->getOwner(*this);
1535 if (IsPhi(OA))
1536 PhiQ.insert(OA.Id);
1537 }
1538 if (RA.Addr->isDef())
1539 unlinkDef(RA, true);
1540 else
1541 unlinkUse(RA, true);
1542 }
1543 NodeAddr<BlockNode*> BA = PA.Addr->getOwner(*this);
1544 BA.Addr->removeMember(PA, *this);
1545 }
1546}
1547
1548// For a given reference node TA in an instruction node IA, connect the
1549// reaching def of TA to the appropriate def node. Create any shadow nodes
1550// as appropriate.
1551template <typename T>
1552void DataFlowGraph::linkRefUp(NodeAddr<InstrNode*> IA, NodeAddr<T> TA,
1553 DefStack &DS) {
1554 if (DS.empty())
1555 return;
1556 RegisterRef RR = TA.Addr->getRegRef(*this);
1557 NodeAddr<T> TAP;
1558
1559 // References from the def stack that have been examined so far.
1560 RegisterAggr Defs(PRI);
1561
1562 for (auto I = DS.top(), E = DS.bottom(); I != E; I.down()) {
1563 RegisterRef QR = I->Addr->getRegRef(*this);
1564
1565 // Skip all defs that are aliased to any of the defs that we have already
1566 // seen. If this completes a cover of RR, stop the stack traversal.
1567 bool Alias = Defs.hasAliasOf(QR);
1568 bool Cover = Defs.insert(QR).hasCoverOf(RR);
1569 if (Alias) {
1570 if (Cover)
1571 break;
1572 continue;
1573 }
1574
1575 // The reaching def.
1577
1578 // Pick the reached node.
1579 if (TAP.Id == 0) {
1580 TAP = TA;
1581 } else {
1582 // Mark the existing ref as "shadow" and create a new shadow.
1583 TAP.Addr->setFlags(TAP.Addr->getFlags() | NodeAttrs::Shadow);
1584 TAP = getNextShadow(IA, TAP, true);
1585 }
1586
1587 // Create the link.
1588 TAP.Addr->linkToDef(TAP.Id, RDA);
1589
1590 if (Cover)
1591 break;
1592 }
1593}
1594
1595// Create data-flow links for all reference nodes in the statement node SA.
1596template <typename Predicate>
1597void DataFlowGraph::linkStmtRefs(DefStackMap &DefM, NodeAddr<StmtNode*> SA,
1598 Predicate P) {
1599#ifndef NDEBUG
1600 RegisterSet Defs;
1601#endif
1602
1603 // Link all nodes (upwards in the data-flow) with their reaching defs.
1604 for (NodeAddr<RefNode*> RA : SA.Addr->members_if(P, *this)) {
1605 uint16_t Kind = RA.Addr->getKind();
1606 assert(Kind == NodeAttrs::Def || Kind == NodeAttrs::Use);
1607 RegisterRef RR = RA.Addr->getRegRef(*this);
1608#ifndef NDEBUG
1609 // Do not expect multiple defs of the same reference.
1610 assert(Kind != NodeAttrs::Def || !Defs.count(RR));
1611 Defs.insert(RR);
1612#endif
1613
1614 auto F = DefM.find(RR.Reg);
1615 if (F == DefM.end())
1616 continue;
1617 DefStack &DS = F->second;
1618 if (Kind == NodeAttrs::Use)
1619 linkRefUp<UseNode*>(SA, RA, DS);
1620 else if (Kind == NodeAttrs::Def)
1621 linkRefUp<DefNode*>(SA, RA, DS);
1622 else
1623 llvm_unreachable("Unexpected node in instruction");
1624 }
1625}
1626
1627// Create data-flow links for all instructions in the block node BA. This
1628// will include updating any phi nodes in BA.
1629void DataFlowGraph::linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA) {
1630 // Push block delimiters.
1631 markBlock(BA.Id, DefM);
1632
1633 auto IsClobber = [] (NodeAddr<RefNode*> RA) -> bool {
1634 return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering);
1635 };
1636 auto IsNoClobber = [] (NodeAddr<RefNode*> RA) -> bool {
1637 return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering);
1638 };
1639
1640 assert(BA.Addr && "block node address is needed to create a data-flow link");
1641 // For each non-phi instruction in the block, link all the defs and uses
1642 // to their reaching defs. For any member of the block (including phis),
1643 // push the defs on the corresponding stacks.
1644 for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this)) {
1645 // Ignore phi nodes here. They will be linked part by part from the
1646 // predecessors.
1647 if (IA.Addr->getKind() == NodeAttrs::Stmt) {
1648 linkStmtRefs(DefM, IA, IsUse);
1649 linkStmtRefs(DefM, IA, IsClobber);
1650 }
1651
1652 // Push the definitions on the stack.
1653 pushClobbers(IA, DefM);
1654
1655 if (IA.Addr->getKind() == NodeAttrs::Stmt)
1656 linkStmtRefs(DefM, IA, IsNoClobber);
1657
1658 pushDefs(IA, DefM);
1659 }
1660
1661 // Recursively process all children in the dominator tree.
1662 MachineDomTreeNode *N = MDT.getNode(BA.Addr->getCode());
1663 for (auto *I : *N) {
1664 MachineBasicBlock *SB = I->getBlock();
1666 linkBlockRefs(DefM, SBA);
1667 }
1668
1669 // Link the phi uses from the successor blocks.
1670 auto IsUseForBA = [BA](NodeAddr<NodeBase*> NA) -> bool {
1671 if (NA.Addr->getKind() != NodeAttrs::Use)
1672 return false;
1673 assert(NA.Addr->getFlags() & NodeAttrs::PhiRef);
1674 NodeAddr<PhiUseNode*> PUA = NA;
1675 return PUA.Addr->getPredecessor() == BA.Id;
1676 };
1677
1678 RegisterSet EHLiveIns = getLandingPadLiveIns();
1679 MachineBasicBlock *MBB = BA.Addr->getCode();
1680
1681 for (MachineBasicBlock *SB : MBB->successors()) {
1682 bool IsEHPad = SB->isEHPad();
1684 for (NodeAddr<InstrNode*> IA : SBA.Addr->members_if(IsPhi, *this)) {
1685 // Do not link phi uses for landing pad live-ins.
1686 if (IsEHPad) {
1687 // Find what register this phi is for.
1688 NodeAddr<RefNode*> RA = IA.Addr->getFirstMember(*this);
1689 assert(RA.Id != 0);
1690 if (EHLiveIns.count(RA.Addr->getRegRef(*this)))
1691 continue;
1692 }
1693 // Go over each phi use associated with MBB, and link it.
1694 for (auto U : IA.Addr->members_if(IsUseForBA, *this)) {
1695 NodeAddr<PhiUseNode*> PUA = U;
1696 RegisterRef RR = PUA.Addr->getRegRef(*this);
1697 linkRefUp<UseNode*>(IA, PUA, DefM[RR.Reg]);
1698 }
1699 }
1700 }
1701
1702 // Pop all defs from this block from the definition stacks.
1703 releaseBlock(BA.Id, DefM);
1704}
1705
1706// Remove the use node UA from any data-flow and structural links.
1707void DataFlowGraph::unlinkUseDF(NodeAddr<UseNode*> UA) {
1708 NodeId RD = UA.Addr->getReachingDef();
1709 NodeId Sib = UA.Addr->getSibling();
1710
1711 if (RD == 0) {
1712 assert(Sib == 0);
1713 return;
1714 }
1715
1716 auto RDA = addr<DefNode*>(RD);
1717 auto TA = addr<UseNode*>(RDA.Addr->getReachedUse());
1718 if (TA.Id == UA.Id) {
1719 RDA.Addr->setReachedUse(Sib);
1720 return;
1721 }
1722
1723 while (TA.Id != 0) {
1724 NodeId S = TA.Addr->getSibling();
1725 if (S == UA.Id) {
1726 TA.Addr->setSibling(UA.Addr->getSibling());
1727 return;
1728 }
1729 TA = addr<UseNode*>(S);
1730 }
1731}
1732
1733// Remove the def node DA from any data-flow and structural links.
1734void DataFlowGraph::unlinkDefDF(NodeAddr<DefNode*> DA) {
1735 //
1736 // RD
1737 // | reached
1738 // | def
1739 // :
1740 // .
1741 // +----+
1742 // ... -- | DA | -- ... -- 0 : sibling chain of DA
1743 // +----+
1744 // | | reached
1745 // | : def
1746 // | .
1747 // | ... : Siblings (defs)
1748 // |
1749 // : reached
1750 // . use
1751 // ... : sibling chain of reached uses
1752
1753 NodeId RD = DA.Addr->getReachingDef();
1754
1755 // Visit all siblings of the reached def and reset their reaching defs.
1756 // Also, defs reached by DA are now "promoted" to being reached by RD,
1757 // so all of them will need to be spliced into the sibling chain where
1758 // DA belongs.
1759 auto getAllNodes = [this] (NodeId N) -> NodeList {
1760 NodeList Res;
1761 while (N) {
1762 auto RA = addr<RefNode*>(N);
1763 // Keep the nodes in the exact sibling order.
1764 Res.push_back(RA);
1765 N = RA.Addr->getSibling();
1766 }
1767 return Res;
1768 };
1769 NodeList ReachedDefs = getAllNodes(DA.Addr->getReachedDef());
1770 NodeList ReachedUses = getAllNodes(DA.Addr->getReachedUse());
1771
1772 if (RD == 0) {
1773 for (NodeAddr<RefNode*> I : ReachedDefs)
1774 I.Addr->setSibling(0);
1775 for (NodeAddr<RefNode*> I : ReachedUses)
1776 I.Addr->setSibling(0);
1777 }
1778 for (NodeAddr<DefNode*> I : ReachedDefs)
1779 I.Addr->setReachingDef(RD);
1780 for (NodeAddr<UseNode*> I : ReachedUses)
1781 I.Addr->setReachingDef(RD);
1782
1783 NodeId Sib = DA.Addr->getSibling();
1784 if (RD == 0) {
1785 assert(Sib == 0);
1786 return;
1787 }
1788
1789 // Update the reaching def node and remove DA from the sibling list.
1790 auto RDA = addr<DefNode*>(RD);
1791 auto TA = addr<DefNode*>(RDA.Addr->getReachedDef());
1792 if (TA.Id == DA.Id) {
1793 // If DA is the first reached def, just update the RD's reached def
1794 // to the DA's sibling.
1795 RDA.Addr->setReachedDef(Sib);
1796 } else {
1797 // Otherwise, traverse the sibling list of the reached defs and remove
1798 // DA from it.
1799 while (TA.Id != 0) {
1800 NodeId S = TA.Addr->getSibling();
1801 if (S == DA.Id) {
1802 TA.Addr->setSibling(Sib);
1803 break;
1804 }
1805 TA = addr<DefNode*>(S);
1806 }
1807 }
1808
1809 // Splice the DA's reached defs into the RDA's reached def chain.
1810 if (!ReachedDefs.empty()) {
1811 auto Last = NodeAddr<DefNode*>(ReachedDefs.back());
1812 Last.Addr->setSibling(RDA.Addr->getReachedDef());
1813 RDA.Addr->setReachedDef(ReachedDefs.front().Id);
1814 }
1815 // Splice the DA's reached uses into the RDA's reached use chain.
1816 if (!ReachedUses.empty()) {
1817 auto Last = NodeAddr<UseNode*>(ReachedUses.back());
1818 Last.Addr->setSibling(RDA.Addr->getReachedUse());
1819 RDA.Addr->setReachedUse(ReachedUses.front().Id);
1820 }
1821}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
ReachingDefAnalysis & RDA
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static LVOptions Options
Definition: LVOptions.cpp:25
A common definition of LaneBitmask for use in TableGen and CodeGen.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
#define P(N)
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
const NodeList & List
Definition: RDFGraph.cpp:199
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file contains some templates that are useful if you are working with the STL at all.
This file implements a set that has insertion order iteration characteristics.
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
Definition: Allocator.h:148
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
Definition: Allocator.h:123
This is an important base class in LLVM.
Definition: Constant.h:41
Base class for the actual dominator tree node.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
unsigned succ_size() const
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
iterator find(MachineBasicBlock *B)
DominanceFrontierBase< MachineBasicBlock, false >::DomSetType DomSetType
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineBasicBlock & front() const
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...
unsigned count(SUnit *SU) const
bool insert(SUnit *SU)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
A vector that has set insertion semantics.
Definition: SetVector.h:40
bool remove(const value_type &X)
Remove an item from the set vector.
Definition: SetVector.h:157
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
bool empty() const
Definition: SmallVector.h:94
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual const TargetLowering * getTargetLowering() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This class provides various memory handling functions that manipulate MemoryBlock instances.
Definition: Memory.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:413
uint32_t NodeId
Definition: RDFGraph.h:261
static void printRefHeader(raw_ostream &OS, const NodeAddr< RefNode * > RA, const DataFlowGraph &G)
Definition: RDFGraph.cpp:106
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
Definition: RDFGraph.cpp:55
std::set< NodeId > NodeSet
Definition: RDFGraph.h:514
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:92
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:484
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1683
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1762
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1869
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: BitVector.h:851
#define N
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82
void addPhi(NodeAddr< PhiNode * > PA, const DataFlowGraph &G)
Definition: RDFGraph.cpp:544
NodeList members_if(Predicate P, const DataFlowGraph &G) const
Definition: RDFGraph.h:915
void removeMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
Definition: RDFGraph.cpp:493
void addMemberAfter(NodeAddr< NodeBase * > MA, NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
Definition: RDFGraph.cpp:485
NodeAddr< NodeBase * > getLastMember(const DataFlowGraph &G) const
Definition: RDFGraph.cpp:465
NodeAddr< NodeBase * > getFirstMember(const DataFlowGraph &G) const
Definition: RDFGraph.cpp:458
NodeList members(const DataFlowGraph &G) const
Definition: RDFGraph.cpp:525
void addMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
Definition: RDFGraph.cpp:472
NodeAddr< BlockNode * > findBlock(MachineBasicBlock *BB) const
Definition: RDFGraph.h:767
void releaseBlock(NodeId B, DefStackMap &DefM)
Definition: RDFGraph.cpp:991
void markBlock(NodeId B, DefStackMap &DefM)
Definition: RDFGraph.cpp:984
NodeAddr< RefNode * > getNextShadow(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA, bool Create)
Definition: RDFGraph.cpp:1201
DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, const MachineDominanceFrontier &mdf)
Definition: RDFGraph.cpp:644
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
Definition: RDFGraph.h:771
static bool IsPhi(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:806
NodeId id(const NodeBase *P) const
Definition: RDFGraph.cpp:774
static bool IsUse(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:801
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
Definition: RDFGraph.cpp:967
static bool IsDef(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:796
void unlinkDef(NodeAddr< DefNode * > DA, bool RemoveFromOwner)
Definition: RDFGraph.h:777
void build(unsigned Options=BuildOptions::None)
Definition: RDFGraph.cpp:869
NodeBase * ptr(NodeId N) const
Definition: RDFGraph.cpp:767
void pushAllDefs(NodeAddr< InstrNode * > IA, DefStackMap &DM)
Definition: RDFGraph.cpp:1009
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
Definition: RDFGraph.cpp:1114
NodeAddr< RefNode * > getNextRelated(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
Definition: RDFGraph.cpp:1140
std::unordered_map< RegisterId, DefStack > DefStackMap
Definition: RDFGraph.h:737
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
Definition: RDFGraph.cpp:444
MachineFunction * getCode() const
Definition: RDFGraph.h:636
NodeAddr< BlockNode * > getEntryBlock(const DataFlowGraph &G)
Definition: RDFGraph.cpp:586
NodeAddr< BlockNode * > findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const
Definition: RDFGraph.cpp:574
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
Definition: RDFGraph.cpp:531
NodeId id(const NodeBase *P) const
Definition: RDFGraph.cpp:375
NodeAddr< NodeBase * > New()
Definition: RDFGraph.cpp:363
static uint16_t flags(uint16_t T)
Definition: RDFGraph.h:296
static uint16_t kind(uint16_t T)
Definition: RDFGraph.h:295
static uint16_t type(uint16_t T)
Definition: RDFGraph.h:294
NodeId getNext() const
Definition: RDFGraph.h:458
Code_struct Code
Definition: RDFGraph.h:504
void append(NodeAddr< NodeBase * > NA)
Definition: RDFGraph.cpp:394
Ref_struct Ref
Definition: RDFGraph.h:503
RegisterId getRegMaskId(const uint32_t *RM) const
Definition: RDFRegisters.h:110
static bool isRegMaskId(RegisterId R)
Definition: RDFRegisters.h:106
bool alias(RegisterRef RA, RegisterRef RB) const
Definition: RDFRegisters.h:118
std::set< RegisterId > getAliasSet(RegisterId Reg) const
void setRegRef(RegisterRef RR, DataFlowGraph &G)
Definition: RDFGraph.cpp:416
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
Definition: RDFGraph.cpp:432
RegisterRef getRegRef(const DataFlowGraph &G) const
Definition: RDFGraph.cpp:406
rr_iterator rr_end() const
Definition: RDFRegisters.h:240
RegisterAggr & insert(RegisterRef RR)
rr_iterator rr_begin() const
Definition: RDFRegisters.h:237
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
Definition: RDFRegisters.h:182
virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const
Definition: RDFGraph.cpp:596
const TargetInstrInfo & TII
Definition: RDFGraph.h:423
virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const
Definition: RDFGraph.cpp:615
virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const
Definition: RDFGraph.cpp:602
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
Definition: RDFGraph.cpp:451