56 auto &
TRI =
P.G.getTRI();
57 if (
P.Obj.Reg > 0 &&
P.Obj.Reg <
TRI.getNumRegs())
58 OS <<
TRI.getName(
P.Obj.Reg);
60 OS <<
'#' <<
P.Obj.Reg;
67 uint16_t Attrs = NA.Addr->getAttrs();
77 default:
OS <<
"c?";
break;
93 default:
OS <<
"r?";
break;
109 <<
Print(
RA.Addr->getRegRef(
G),
G) <<
'>';
117 if (
NodeId N =
P.Obj.Addr->getReachingDef())
120 if (
NodeId N =
P.Obj.Addr->getReachedDef())
123 if (
NodeId N =
P.Obj.Addr->getReachedUse())
126 if (
NodeId N =
P.Obj.Addr->getSibling())
134 if (
NodeId N =
P.Obj.Addr->getReachingDef())
137 if (
NodeId N =
P.Obj.Addr->getSibling())
146 if (
NodeId N =
P.Obj.Addr->getReachingDef())
149 if (
NodeId N =
P.Obj.Addr->getPredecessor())
152 if (
NodeId N =
P.Obj.Addr->getSibling())
158 switch (
P.Obj.Addr->getKind()) {
160 OS << PrintNode<DefNode*>(
P.Obj,
P.G);
164 OS << PrintNode<PhiUseNode*>(
P.Obj,
P.G);
166 OS << PrintNode<UseNode*>(
P.Obj,
P.G);
173 unsigned N =
P.Obj.size();
174 for (
auto I :
P.Obj) {
183 unsigned N =
P.Obj.size();
184 for (
auto I :
P.Obj) {
194 template <
typename T>
203 template <
typename T>
205 unsigned N =
P.List.size();
207 OS << PrintNode<T>(
A,
P.G);
218 << PrintListV<RefNode*>(
P.Obj.Addr->members(
P.G),
P.G) <<
']';
224 unsigned Opc =
MI.getOpcode();
225 OS <<
Print(
P.Obj.Id,
P.G) <<
": " <<
P.G.getTII().getName(Opc);
227 if (
MI.isCall() ||
MI.isBranch()) {
231 return Op.isMBB() || Op.isGlobal() || Op.isSymbol();
233 if (
T !=
MI.operands_end()) {
237 else if (
T->isGlobal())
238 OS <<
T->getGlobal()->getName();
239 else if (
T->isSymbol())
240 OS <<
T->getSymbolName();
243 OS <<
" [" << PrintListV<RefNode*>(
P.Obj.Addr->members(
P.G),
P.G) <<
']';
249 switch (
P.Obj.Addr->getKind()) {
251 OS << PrintNode<PhiNode*>(
P.Obj,
P.G);
254 OS << PrintNode<StmtNode*>(
P.Obj,
P.G);
268 auto PrintBBs = [&
OS] (std::vector<int> Ns) ->
void {
269 unsigned N = Ns.size();
278 <<
" --- preds(" << NP <<
"): ";
280 Ns.push_back(
B->getNumber());
284 OS <<
" succs(" << NS <<
"): ";
287 Ns.push_back(
B->getNumber());
291 for (
auto I :
P.Obj.Addr->members(
P.G))
292 OS << PrintNode<InstrNode*>(
I,
P.G) <<
'\n';
297 OS <<
"DFG dump:[\n" <<
Print(
P.Obj.Id,
P.G) <<
": Function: "
298 <<
P.Obj.Addr->getCode()->getName() <<
'\n';
299 for (
auto I :
P.Obj.Addr->members(
P.G))
300 OS << PrintNode<BlockNode*>(
I,
P.G) <<
'\n';
320 for (
auto I =
P.Obj.top(),
E =
P.Obj.bottom();
I !=
E; ) {
322 <<
'<' <<
Print(
I->Addr->getRegRef(
P.G),
P.G) <<
'>';
342void NodeAllocator::startNewBlock() {
344 char *
P =
static_cast<char*
>(
T);
349 assert((Blocks.size() < ((
size_t)1 << (8*
sizeof(
NodeId)-BitsPerIndex))) &&
350 "Out of bits for block index");
354bool NodeAllocator::needNewBlock() {
358 char *ActiveBegin = Blocks.back();
360 return Index >= NodesPerBlock;
370 makeId(ActiveB,
Index) };
376 uintptr_t
A =
reinterpret_cast<uintptr_t
>(
P);
377 for (
unsigned i = 0, n = Blocks.size(); i != n; ++i) {
378 uintptr_t
B =
reinterpret_cast<uintptr_t
>(Blocks[i]);
382 return makeId(i,
Idx);
411 return G.makeRegRef(*
Ref.
Op);
435 while (NA.
Addr !=
this) {
446 Ref.
Sib = DA.Addr->getReachedDef();
447 DA.Addr->setReachedDef(Self);
453 Ref.
Sib = DA.Addr->getReachedUse();
454 DA.Addr->setReachedUse(Self);
479 NA.
Addr->setNext(Self);
498 if (MA.
Id == NA.
Id) {
509 while (MA.
Addr !=
this) {
512 MA.
Addr->setNext(NA.
Addr->getNext());
534 while (NA.
Addr !=
this) {
556 PA.
Addr->setNext(M.Id);
563 MN =
G.addr<
NodeBase*>(M.Addr->getNext());
609 if (Op.isDef() && Op.isDead())
617 if (In.isCall() || In.isReturn() || In.isInlineAsm())
622 if (O.isGlobal() || O.isSymbol())
626 if (
D.implicit_defs().empty() &&
D.implicit_uses().empty())
632 if (Op.getSubReg() != 0)
636 Op.isDef() ?
D.implicit_defs() :
D.implicit_uses();
648 TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(*DefaultTOI),
655 : MF(mf),
TII(tii),
TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi),
673 Pos = DS.Stack.size();
674 while (Pos > 0 && DS.isDelimiter(DS.Stack[Pos-1]))
691 unsigned P = nextDown(Stack.size());
706 unsigned P = Stack.size();
708 bool Found = isDelimiter(Stack[
P-1],
N);
718unsigned DataFlowGraph::DefStack::nextUp(
unsigned P)
const {
721 unsigned SS = Stack.size();
726 IsDelim = isDelimiter(Stack[
P-1]);
727 }
while (
P < SS && IsDelim);
733unsigned DataFlowGraph::DefStack::nextDown(
unsigned P)
const {
737 bool IsDelim = isDelimiter(Stack[
P-1]);
741 IsDelim = isDelimiter(Stack[
P-1]);
742 }
while (
P > 0 && IsDelim);
749RegisterSet DataFlowGraph::getLandingPadLiveIns()
const {
752 const Constant *PF =
F.hasPersonalityFn() ?
F.getPersonalityFn()
784 P.Addr->setAttrs(Attrs);
796 RA.Addr->setReachingDef(0);
797 RA.Addr->setSibling(0);
800 DA.Addr->setReachedDef(0);
801 DA.Addr->setReachedUse(0);
812 UA.
Addr->setRegRef(&Op, *
this);
820 PUA.
Addr->setRegRef(RR, *
this);
821 PUA.
Addr->setPredecessor(PredB.
Id);
828 DA.Addr->setRegRef(&Op, *
this);
836 DA.Addr->setRegRef(RR, *
this);
842 Owner.
Addr->addPhi(PA, *
this);
850 Owner.
Addr->addMember(SA, *
this);
857 BA.
Addr->setCode(BB);
858 Owner.
Addr->addMember(BA, *
this);
864 FA.
Addr->setCode(MF);
878 BlockNodes.insert(std::make_pair(&
B, BA));
880 if (
I.isDebugInstr())
894 AllRefs.insert(
RA.Addr->getRegRef(*
this));
900 for (std::pair<unsigned,unsigned>
P :
MRI.liveins())
902 if (
MRI.tracksLiveness()) {
914 PA.
Addr->addMember(DA, *
this);
923 if (!EHRegs.empty()) {
940 PA.
Addr->addMember(DA, *
this);
944 PA.
Addr->addMember(PUA, *
this);
954 recordDefsForDF(PhiM, BA);
956 buildPhis(PhiM, AllRefs, BA);
960 linkBlockRefs(
DM, EA);
977 assert(Op.isReg() || Op.isRegMask());
979 return makeRegRef(Op.getReg(), Op.getSubReg());
987 P.second.start_block(
B);
996 P.second.clear_block(
B);
999 for (
auto I = DefM.begin(),
E = DefM.end(), NextI =
I;
I !=
E;
I = NextI) {
1000 NextI = std::next(
I);
1002 if (
I->second.empty())
1010 pushClobbers(IA, DefM);
1018 std::set<RegisterId> Defined;
1033 if (Visited.
count(DA.Id))
1044 DefM[RR.
Reg].push(DA);
1045 Defined.insert(RR.
Reg);
1049 if (!Defined.count(
A))
1063 std::set<RegisterId> Defined;
1090 if (!Defined.insert(RR.
Reg).second) {
1092 dbgs() <<
"Multiple definitions of register: "
1093 <<
Print(RR, *
this) <<
" in\n " << *
MI <<
"in "
1100 DefM[RR.
Reg].push(DA);
1123 }
while (
RA.Id != 0 &&
RA.Id != Start);
1128void DataFlowGraph::reset() {
1145 if (TA.Addr->getKind() !=
RA.Addr->getKind())
1147 if (TA.Addr->getRegRef(*
this) !=
RA.Addr->getRegRef(*
this))
1152 return Related(TA) &&
1153 &
RA.Addr->getOp() == &TA.Addr->getOp();
1163 return TUA.
Addr->getPredecessor() == RUA.
Addr->getPredecessor();
1168 return RA.Addr->getNextRef(RR, RelatedStmt,
true, *
this);
1169 return RA.Addr->getNextRef(RR, RelatedPhi,
true, *
this);
1177template <
typename Predicate>
1180 Predicate
P)
const {
1187 if (NA.
Id == 0 || NA.
Id == Start)
1194 if (NA.
Id != 0 && NA.
Id != Start)
1195 return std::make_pair(
RA, NA);
1207 return TA.Addr->getFlags() ==
Flags;
1209 auto Loc = locateNextRef(IA,
RA, IsShadow);
1210 if (Loc.second.Id != 0 || !Create)
1216 IA.Addr->addMemberAfter(Loc.first, NA, *
this);
1227 return TA.Addr->getFlags() ==
Flags;
1229 return locateNextRef(IA,
RA, IsShadow).second;
1241 if (In.isBranch()) {
1243 if (Op.isGlobal() || Op.isSymbol())
1248 if (In.isIndirectBranch())
1258 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1261 if (PRI.
alias(DR, UR))
1267 bool IsCall = isCall(In);
1268 unsigned NumOps =
In.getNumOperands();
1276 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1278 if (!
Op.isReg() || !
Op.isDef() ||
Op.isImplicit())
1281 if (!R || !
R.isPhysical())
1294 if (IsCall &&
Op.isDead())
1297 SA.
Addr->addMember(DA, *
this);
1298 assert(!DoneDefs.test(R));
1304 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1306 if (!
Op.isRegMask())
1311 SA.
Addr->addMember(DA, *
this);
1314 for (
unsigned i = 1, e = TRI.
getNumRegs(); i != e; ++i)
1315 if (!(RM[i/32] & (1u << (i%32))))
1316 DoneClobbers.set(i);
1321 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1323 if (!
Op.isReg() || !
Op.isDef() || !
Op.isImplicit())
1326 if (!R || !
R.isPhysical() || DoneDefs.test(R))
1333 if (isDefUndef(In, RR))
1340 if (IsCall &&
Op.isDead()) {
1341 if (DoneClobbers.test(R))
1346 SA.
Addr->addMember(DA, *
this);
1350 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1352 if (!
Op.isReg() || !
Op.isUse())
1355 if (!R || !
R.isPhysical())
1363 SA.
Addr->addMember(UA, *
this);
1369void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM,
1376 auto DFLoc = MDF.
find(BB);
1377 if (DFLoc == MDF.
end() || DFLoc->second.empty())
1388 Defs.insert(
RA.Addr->getRegRef(*
this));
1393 for (
unsigned i = 0; i < IDF.size(); ++i) {
1394 auto F = MDF.
find(IDF[i]);
1396 IDF.insert(
F->second.begin(),
F->second.end());
1401 for (
auto *DB : IDF) {
1403 PhiM[DBA.
Id].insert(Defs.begin(), Defs.end());
1409void DataFlowGraph::buildPhis(BlockRefsMap &PhiM,
RegisterSet &AllRefs,
1413 auto HasDF = PhiM.find(BA.
Id);
1414 if (HasDF == PhiM.end() || HasDF->second.empty())
1430 MaxDF.insert(MaxCoverIn(
I, HasDF->second));
1432 std::vector<RegisterRef> MaxRefs;
1434 MaxRefs.push_back(MaxCoverIn(
I, AllRefs));
1443 auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end());
1444 MaxRefs.erase(NewEnd, MaxRefs.end());
1447 std::vector<unsigned> &Closure) ->
bool {
1448 for (
unsigned I : Closure)
1449 if (PRI.
alias(RR, MaxRefs[
I]))
1460 while (!MaxRefs.empty()) {
1465 std::vector<unsigned> ClosureIdx = { 0 };
1466 for (
unsigned i = 1; i != MaxRefs.size(); ++i)
1467 if (Aliased(MaxRefs[i], ClosureIdx))
1468 ClosureIdx.push_back(i);
1471 unsigned CS = ClosureIdx.size();
1475 for (
unsigned X = 0;
X != CS; ++
X) {
1479 PA.
Addr->addMember(DA, *
this);
1483 for (
unsigned X = 0;
X != CS; ++
X) {
1486 PA.
Addr->addMember(PUA, *
this);
1491 auto Begin = MaxRefs.begin();
1493 MaxRefs.erase(Begin +
Idx);
1498void DataFlowGraph::removeUnusedPhis() {
1507 for (
auto P : BA.
Addr->members_if(
IsPhi, *
this))
1511 static auto HasUsedDef = [](
NodeList &Ms) ->
bool {
1516 if (
DA.Addr->getReachedDef() != 0 ||
DA.Addr->getReachedUse() != 0)
1525 while (!PhiQ.
empty()) {
1526 auto PA = addr<PhiNode*>(PhiQ[0]);
1529 if (HasUsedDef(Refs))
1532 if (
NodeId RD =
RA.Addr->getReachingDef()) {
1533 auto RDA = addr<DefNode*>(RD);
1538 if (
RA.Addr->isDef())
1544 BA.
Addr->removeMember(PA, *
this);
1551template <
typename T>
1562 for (
auto I =
DS.top(),
E =
DS.bottom();
I !=
E;
I.down()) {
1567 bool Alias = Defs.hasAliasOf(QR);
1568 bool Cover = Defs.insert(QR).hasCoverOf(RR);
1596template <
typename Predicate>
1614 auto F = DefM.find(RR.
Reg);
1615 if (
F == DefM.end())
1617 DefStack &
DS =
F->second;
1619 linkRefUp<UseNode*>(SA,
RA, DS);
1621 linkRefUp<DefNode*>(SA,
RA, DS);
1640 assert(BA.
Addr &&
"block node address is needed to create a data-flow link");
1648 linkStmtRefs(DefM, IA,
IsUse);
1649 linkStmtRefs(DefM, IA, IsClobber);
1653 pushClobbers(IA, DefM);
1656 linkStmtRefs(DefM, IA, IsNoClobber);
1663 for (
auto *
I : *
N) {
1666 linkBlockRefs(DefM, SBA);
1675 return PUA.
Addr->getPredecessor() == BA.
Id;
1690 if (EHLiveIns.count(
RA.Addr->getRegRef(*
this)))
1694 for (
auto U :
IA.Addr->members_if(IsUseForBA, *
this)) {
1697 linkRefUp<UseNode*>(IA, PUA, DefM[RR.
Reg]);
1716 auto RDA = addr<DefNode*>(RD);
1717 auto TA = addr<UseNode*>(
RDA.Addr->getReachedUse());
1718 if (
TA.Id == UA.
Id) {
1719 RDA.Addr->setReachedUse(Sib);
1723 while (
TA.Id != 0) {
1726 TA.Addr->setSibling(UA.
Addr->getSibling());
1729 TA = addr<UseNode*>(S);
1753 NodeId RD =
DA.Addr->getReachingDef();
1762 auto RA = addr<RefNode*>(
N);
1765 N =
RA.Addr->getSibling();
1769 NodeList ReachedDefs = getAllNodes(
DA.Addr->getReachedDef());
1770 NodeList ReachedUses = getAllNodes(
DA.Addr->getReachedUse());
1774 I.Addr->setSibling(0);
1776 I.Addr->setSibling(0);
1779 I.Addr->setReachingDef(RD);
1781 I.Addr->setReachingDef(RD);
1783 NodeId Sib =
DA.Addr->getSibling();
1790 auto RDA = addr<DefNode*>(RD);
1791 auto TA = addr<DefNode*>(
RDA.Addr->getReachedDef());
1792 if (
TA.Id ==
DA.Id) {
1795 RDA.Addr->setReachedDef(Sib);
1799 while (
TA.Id != 0) {
1802 TA.Addr->setSibling(Sib);
1805 TA = addr<DefNode*>(S);
1810 if (!ReachedDefs.empty()) {
1812 Last.Addr->setSibling(
RDA.Addr->getReachedDef());
1813 RDA.Addr->setReachedDef(ReachedDefs.front().
Id);
1816 if (!ReachedUses.empty()) {
1818 Last.Addr->setSibling(
RDA.Addr->getReachedUse());
1819 RDA.Addr->setReachedUse(ReachedUses.front().
Id);
unsigned const MachineRegisterInfo * MRI
ReachingDefAnalysis & RDA
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
DenseMap< Block *, BlockRelaxAux > Blocks
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file implements a set that has insertion order iteration characteristics.
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
This is an important base class in LLVM.
Base class for the actual dominator tree node.
Describe properties that are true of each instruction in the target description file.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
unsigned succ_size() const
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
iterator find(MachineBasicBlock *B)
DominanceFrontierBase< MachineBasicBlock, false >::DomSetType DomSetType
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineBasicBlock & front() const
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...
unsigned count(SUnit *SU) const
Wrapper class representing virtual and physical registers.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
A vector that has set insertion semantics.
bool remove(const value_type &X)
Remove an item from the set vector.
bool insert(const value_type &X)
Insert a new element into the SetVector.
bool empty() const
Determine if the SetVector is empty or not.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual const TargetLowering * getTargetLowering() const
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
This class provides various memory handling functions that manipulate MemoryBlock instances.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::set< RegisterRef > RegisterSet
static void printRefHeader(raw_ostream &OS, const NodeAddr< RefNode * > RA, const DataFlowGraph &G)
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
std::set< NodeId > NodeSet
This is an optimization pass for GlobalISel generic memory operations.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
auto reverse(ContainerTy &&C)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
static constexpr LaneBitmask getAll()
void addPhi(NodeAddr< PhiNode * > PA, const DataFlowGraph &G)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
void removeMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
void addMemberAfter(NodeAddr< NodeBase * > MA, NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
NodeAddr< NodeBase * > getLastMember(const DataFlowGraph &G) const
NodeAddr< NodeBase * > getFirstMember(const DataFlowGraph &G) const
NodeList members(const DataFlowGraph &G) const
void addMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
void clear_block(NodeId N)
void start_block(NodeId N)
NodeAddr< BlockNode * > findBlock(MachineBasicBlock *BB) const
void releaseBlock(NodeId B, DefStackMap &DefM)
void markBlock(NodeId B, DefStackMap &DefM)
NodeAddr< RefNode * > getNextShadow(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA, bool Create)
DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, const MachineDominanceFrontier &mdf)
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
static bool IsPhi(const NodeAddr< NodeBase * > BA)
NodeId id(const NodeBase *P) const
static bool IsUse(const NodeAddr< NodeBase * > BA)
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
static bool IsDef(const NodeAddr< NodeBase * > BA)
void unlinkDef(NodeAddr< DefNode * > DA, bool RemoveFromOwner)
void build(unsigned Options=BuildOptions::None)
NodeBase * ptr(NodeId N) const
void pushAllDefs(NodeAddr< InstrNode * > IA, DefStackMap &DM)
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
NodeAddr< RefNode * > getNextRelated(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
std::unordered_map< RegisterId, DefStack > DefStackMap
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
MachineFunction * getCode() const
NodeAddr< BlockNode * > getEntryBlock(const DataFlowGraph &G)
NodeAddr< BlockNode * > findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
NodeId id(const NodeBase *P) const
NodeAddr< NodeBase * > New()
static uint16_t flags(uint16_t T)
static uint16_t kind(uint16_t T)
static uint16_t type(uint16_t T)
void append(NodeAddr< NodeBase * > NA)
RegisterId getRegMaskId(const uint32_t *RM) const
static bool isRegMaskId(RegisterId R)
bool alias(RegisterRef RA, RegisterRef RB) const
std::set< RegisterId > getAliasSet(RegisterId Reg) const
void setRegRef(RegisterRef RR, DataFlowGraph &G)
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
RegisterRef getRegRef(const DataFlowGraph &G) const
rr_iterator rr_end() const
RegisterAggr & insert(RegisterRef RR)
rr_iterator rr_begin() const
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const
const TargetInstrInfo & TII
virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const
virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)