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SPIRVDuplicatesTracker.cpp
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1 //===-- SPIRVDuplicatesTracker.cpp - SPIR-V Duplicates Tracker --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // General infrastructure for keeping track of the values that according to
10 // the SPIR-V binary layout should be global to the whole module.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SPIRVDuplicatesTracker.h"
15 
16 using namespace llvm;
17 
18 template <typename T>
19 void SPIRVGeneralDuplicatesTracker::prebuildReg2Entry(
20  SPIRVDuplicatesTracker<T> &DT, SPIRVReg2EntryTy &Reg2Entry) {
21  for (auto &TPair : DT.getAllUses()) {
22  for (auto &RegPair : TPair.second) {
23  const MachineFunction *MF = RegPair.first;
24  Register R = RegPair.second;
26  if (!MI)
27  continue;
28  Reg2Entry[&MI->getOperand(0)] = &TPair.second;
29  }
30  }
31 }
32 
34  std::vector<SPIRV::DTSortableEntry *> &Graph,
35  MachineModuleInfo *MMI = nullptr) {
36  SPIRVReg2EntryTy Reg2Entry;
37  prebuildReg2Entry(TT, Reg2Entry);
38  prebuildReg2Entry(CT, Reg2Entry);
39  prebuildReg2Entry(GT, Reg2Entry);
40  prebuildReg2Entry(FT, Reg2Entry);
41  prebuildReg2Entry(AT, Reg2Entry);
42  prebuildReg2Entry(ST, Reg2Entry);
43 
44  for (auto &Op2E : Reg2Entry) {
45  SPIRV::DTSortableEntry *E = Op2E.second;
46  Graph.push_back(E);
47  for (auto &U : *E) {
48  const MachineRegisterInfo &MRI = U.first->getRegInfo();
49  MachineInstr *MI = MRI.getUniqueVRegDef(U.second);
50  if (!MI)
51  continue;
52  assert(MI && MI->getParent() && "No MachineInstr created yet");
53  for (auto i = MI->getNumDefs(); i < MI->getNumOperands(); i++) {
54  MachineOperand &Op = MI->getOperand(i);
55  if (!Op.isReg())
56  continue;
57  MachineOperand *RegOp = &MRI.getVRegDef(Op.getReg())->getOperand(0);
58  assert((MI->getOpcode() == SPIRV::OpVariable && i == 3) ||
59  Reg2Entry.count(RegOp));
60  if (Reg2Entry.count(RegOp))
61  E->addDep(Reg2Entry[RegOp]);
62  }
63 
64  if (E->getIsFunc()) {
65  MachineInstr *Next = MI->getNextNode();
66  if (Next && (Next->getOpcode() == SPIRV::OpFunction ||
67  Next->getOpcode() == SPIRV::OpFunctionParameter)) {
68  E->addDep(Reg2Entry[&Next->getOperand(0)]);
69  }
70  }
71  }
72  }
73 
74 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
75  if (MMI) {
76  const Module *M = MMI->getModule();
77  for (auto F = M->begin(), E = M->end(); F != E; ++F) {
78  const MachineFunction *MF = MMI->getMachineFunction(*F);
79  if (!MF)
80  continue;
81  for (const MachineBasicBlock &MBB : *MF) {
82  for (const MachineInstr &CMI : MBB) {
83  MachineInstr &MI = const_cast<MachineInstr &>(CMI);
84  MI.dump();
85  if (MI.getNumExplicitDefs() > 0 &&
86  Reg2Entry.count(&MI.getOperand(0))) {
87  dbgs() << "\t[";
89  Reg2Entry.lookup(&MI.getOperand(0))->getDeps())
90  dbgs() << Register::virtReg2Index(D->lookup(MF)) << ", ";
91  dbgs() << "]\n";
92  }
93  }
94  }
95  }
96  }
97 #endif
98 }
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::SPIRVGeneralDuplicatesTracker::buildDepsGraph
void buildDepsGraph(std::vector< SPIRV::DTSortableEntry * > &Graph, MachineModuleInfo *MMI)
Definition: SPIRVDuplicatesTracker.cpp:33
llvm::MapVector
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:37
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
llvm::SPIRV::DTSortableEntry
Definition: SPIRVDuplicatesTracker.h:31
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SPIRVDuplicatesTrackerBase< const T * >::getAllUses
const StorageTy & getAllUses() const
Definition: SPIRVDuplicatesTracker.h:222
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SPIRVDuplicatesTracker.h
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:136
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::SPIRVDuplicatesTracker
Definition: SPIRVDuplicatesTracker.h:235