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13 #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
14 #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
19 #define GET_INSTRINFO_HEADER
20 #include "VEGenInstrInfo.inc"
46 #define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)
47 #define GET_VLINDEX(TSF) \
48 (HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)
53 virtual void anchor();
68 bool AllowModify =
false)
const override;
71 int *BytesRemoved =
nullptr)
const override;
76 int *BytesAdded =
nullptr)
const override;
84 bool KillSrc)
const override;
bool expandPostRAPseudo(MachineInstr &MI) const override
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder & UseMI
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
const VERegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
@ VE_VLInUse
VE_VLInUse - This instruction has a vector register in its operands.
VEInstrInfo(VESubtarget &ST)
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned const TargetRegisterInfo * TRI
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool expandGetStackTopPseudo(MachineInstr &MI) const
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
} Stack Spill & Reload
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
} Branch Analysis & Modification
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Representation of each machine instruction.
bool expandExtendStackPseudo(MachineInstr &MI) const
@ VE_Vector
VE_Vector - This instruction is Vector Instruction.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Branch Analysis & Modification {.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator MBBI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
@ VE_VLShift
VE_VLMask/Shift - This is a bitmask that selects the index number where an instruction holds vector l...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Stack Spill & Reload {.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Wrapper class representing physical registers. Should be passed by value.