LLVM  15.0.0git
VEInstrInfo.cpp
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1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the VE implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "VEInstrInfo.h"
14 #include "VE.h"
15 #include "VEMachineFunctionInfo.h"
16 #include "VESubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/Debug.h"
27 
28 #define DEBUG_TYPE "ve-instr-info"
29 
30 using namespace llvm;
31 
32 #define GET_INSTRINFO_CTOR_DTOR
33 #include "VEGenInstrInfo.inc"
34 
35 // Pin the vtable to this file.
36 void VEInstrInfo::anchor() {}
37 
39  : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
40 
41 static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); }
42 
44  switch (CC) {
45  case VECC::CC_IG:
46  return VECC::CC_ILE;
47  case VECC::CC_IL:
48  return VECC::CC_IGE;
49  case VECC::CC_INE:
50  return VECC::CC_IEQ;
51  case VECC::CC_IEQ:
52  return VECC::CC_INE;
53  case VECC::CC_IGE:
54  return VECC::CC_IL;
55  case VECC::CC_ILE:
56  return VECC::CC_IG;
57  case VECC::CC_AF:
58  return VECC::CC_AT;
59  case VECC::CC_G:
60  return VECC::CC_LENAN;
61  case VECC::CC_L:
62  return VECC::CC_GENAN;
63  case VECC::CC_NE:
64  return VECC::CC_EQNAN;
65  case VECC::CC_EQ:
66  return VECC::CC_NENAN;
67  case VECC::CC_GE:
68  return VECC::CC_LNAN;
69  case VECC::CC_LE:
70  return VECC::CC_GNAN;
71  case VECC::CC_NUM:
72  return VECC::CC_NAN;
73  case VECC::CC_NAN:
74  return VECC::CC_NUM;
75  case VECC::CC_GNAN:
76  return VECC::CC_LE;
77  case VECC::CC_LNAN:
78  return VECC::CC_GE;
79  case VECC::CC_NENAN:
80  return VECC::CC_EQ;
81  case VECC::CC_EQNAN:
82  return VECC::CC_NE;
83  case VECC::CC_GENAN:
84  return VECC::CC_L;
85  case VECC::CC_LENAN:
86  return VECC::CC_G;
87  case VECC::CC_AT:
88  return VECC::CC_AF;
89  case VECC::UNKNOWN:
90  return VECC::UNKNOWN;
91  }
92  llvm_unreachable("Invalid cond code");
93 }
94 
95 // Treat a branch relative long always instruction as unconditional branch.
96 // For example, br.l.t and br.l.
97 static bool isUncondBranchOpcode(int Opc) {
98  using namespace llvm::VE;
99 
100 #define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t)
101  // VE has other branch relative always instructions for word/double/float,
102  // but we use only long branches in our lower. So, check it here.
103  assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) &&
104  "Branch relative word/double/float always instructions should not be "
105  "used!");
106  return BRKIND(BRCFL);
107 #undef BRKIND
108 }
109 
110 // Treat branch relative conditional as conditional branch instructions.
111 // For example, brgt.l.t and brle.s.nt.
112 static bool isCondBranchOpcode(int Opc) {
113  using namespace llvm::VE;
114 
115 #define BRKIND(NAME) \
116  (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \
117  Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t)
118  return BRKIND(BRCFL) || BRKIND(BRCFW) || BRKIND(BRCFD) || BRKIND(BRCFS);
119 #undef BRKIND
120 }
121 
122 // Treat branch long always instructions as indirect branch.
123 // For example, b.l.t and b.l.
124 static bool isIndirectBranchOpcode(int Opc) {
125  using namespace llvm::VE;
126 
127 #define BRKIND(NAME) \
128  (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t)
129  // VE has other branch always instructions for word/double/float, but
130  // we use only long branches in our lower. So, check it here.
131  assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) &&
132  "Branch word/double/float always instructions should not be used!");
133  return BRKIND(BCFL);
134 #undef BRKIND
135 }
136 
139  Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm()));
140  Cond.push_back(LastInst->getOperand(1));
141  Cond.push_back(LastInst->getOperand(2));
142  Target = LastInst->getOperand(3).getMBB();
143 }
144 
146  MachineBasicBlock *&FBB,
148  bool AllowModify) const {
150  if (I == MBB.end())
151  return false;
152 
153  if (!isUnpredicatedTerminator(*I))
154  return false;
155 
156  // Get the last instruction in the block.
157  MachineInstr *LastInst = &*I;
158  unsigned LastOpc = LastInst->getOpcode();
159 
160  // If there is only one terminator instruction, process it.
161  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
162  if (isUncondBranchOpcode(LastOpc)) {
163  TBB = LastInst->getOperand(0).getMBB();
164  return false;
165  }
166  if (isCondBranchOpcode(LastOpc)) {
167  // Block ends with fall-through condbranch.
168  parseCondBranch(LastInst, TBB, Cond);
169  return false;
170  }
171  return true; // Can't handle indirect branch.
172  }
173 
174  // Get the instruction before it if it is a terminator.
175  MachineInstr *SecondLastInst = &*I;
176  unsigned SecondLastOpc = SecondLastInst->getOpcode();
177 
178  // If AllowModify is true and the block ends with two or more unconditional
179  // branches, delete all but the first unconditional branch.
180  if (AllowModify && isUncondBranchOpcode(LastOpc)) {
181  while (isUncondBranchOpcode(SecondLastOpc)) {
182  LastInst->eraseFromParent();
183  LastInst = SecondLastInst;
184  LastOpc = LastInst->getOpcode();
185  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
186  // Return now the only terminator is an unconditional branch.
187  TBB = LastInst->getOperand(0).getMBB();
188  return false;
189  }
190  SecondLastInst = &*I;
191  SecondLastOpc = SecondLastInst->getOpcode();
192  }
193  }
194 
195  // If there are three terminators, we don't know what sort of block this is.
196  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
197  return true;
198 
199  // If the block ends with a B and a Bcc, handle it.
200  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
201  parseCondBranch(SecondLastInst, TBB, Cond);
202  FBB = LastInst->getOperand(0).getMBB();
203  return false;
204  }
205 
206  // If the block ends with two unconditional branches, handle it. The second
207  // one is not executed.
208  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
209  TBB = SecondLastInst->getOperand(0).getMBB();
210  return false;
211  }
212 
213  // ...likewise if it ends with an indirect branch followed by an unconditional
214  // branch.
215  if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
216  I = LastInst;
217  if (AllowModify)
218  I->eraseFromParent();
219  return true;
220  }
221 
222  // Otherwise, can't handle this.
223  return true;
224 }
225 
227  MachineBasicBlock *TBB,
228  MachineBasicBlock *FBB,
230  const DebugLoc &DL, int *BytesAdded) const {
231  assert(TBB && "insertBranch must not be told to insert a fallthrough");
232  assert((Cond.size() == 3 || Cond.size() == 0) &&
233  "VE branch conditions should have three component!");
234  assert(!BytesAdded && "code size not handled");
235  if (Cond.empty()) {
236  // Uncondition branch
237  assert(!FBB && "Unconditional branch with multiple successors!");
238  BuildMI(&MBB, DL, get(VE::BRCFLa_t))
239  .addMBB(TBB);
240  return 1;
241  }
242 
243  // Conditional branch
244  // (BRCFir CC sy sz addr)
245  assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented");
246 
247  unsigned opc[2];
249  MachineFunction *MF = MBB.getParent();
250  const MachineRegisterInfo &MRI = MF->getRegInfo();
251  Register Reg = Cond[2].getReg();
252  if (IsIntegerCC(Cond[0].getImm())) {
253  if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
254  opc[0] = VE::BRCFWir;
255  opc[1] = VE::BRCFWrr;
256  } else {
257  opc[0] = VE::BRCFLir;
258  opc[1] = VE::BRCFLrr;
259  }
260  } else {
261  if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
262  opc[0] = VE::BRCFSir;
263  opc[1] = VE::BRCFSrr;
264  } else {
265  opc[0] = VE::BRCFDir;
266  opc[1] = VE::BRCFDrr;
267  }
268  }
269  if (Cond[1].isImm()) {
270  BuildMI(&MBB, DL, get(opc[0]))
271  .add(Cond[0]) // condition code
272  .add(Cond[1]) // lhs
273  .add(Cond[2]) // rhs
274  .addMBB(TBB);
275  } else {
276  BuildMI(&MBB, DL, get(opc[1]))
277  .add(Cond[0])
278  .add(Cond[1])
279  .add(Cond[2])
280  .addMBB(TBB);
281  }
282 
283  if (!FBB)
284  return 1;
285 
286  BuildMI(&MBB, DL, get(VE::BRCFLa_t))
287  .addMBB(FBB);
288  return 2;
289 }
290 
292  int *BytesRemoved) const {
293  assert(!BytesRemoved && "code size not handled");
294 
296  unsigned Count = 0;
297  while (I != MBB.begin()) {
298  --I;
299 
300  if (I->isDebugValue())
301  continue;
302 
303  if (!isUncondBranchOpcode(I->getOpcode()) &&
304  !isCondBranchOpcode(I->getOpcode()))
305  break; // Not a branch
306 
307  I->eraseFromParent();
308  I = MBB.end();
309  ++Count;
310  }
311  return Count;
312 }
313 
316  VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm());
317  Cond[0].setImm(GetOppositeBranchCondition(CC));
318  return false;
319 }
320 
321 static bool IsAliasOfSX(Register Reg) {
322  return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
323  VE::F32RegClass.contains(Reg);
324 }
325 
328  MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
329  const MCInstrDesc &MCID, unsigned int NumSubRegs,
330  const unsigned *SubRegIdx,
331  const TargetRegisterInfo *TRI) {
332  MachineInstr *MovMI = nullptr;
333 
334  for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) {
335  Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]);
336  Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]);
337  assert(SubDest && SubSrc && "Bad sub-register");
338 
339  if (MCID.getOpcode() == VE::ORri) {
340  // generate "ORri, dest, src, 0" instruction.
341  MachineInstrBuilder MIB =
342  BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0);
343  MovMI = MIB.getInstr();
344  } else if (MCID.getOpcode() == VE::ANDMmm) {
345  // generate "ANDM, dest, vm0, src" instruction.
346  MachineInstrBuilder MIB =
347  BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc);
348  MovMI = MIB.getInstr();
349  } else {
350  llvm_unreachable("Unexpected reg-to-reg copy instruction");
351  }
352  }
353  // Add implicit super-register defs and kills to the last MovMI.
354  MovMI->addRegisterDefined(DestReg, TRI);
355  if (KillSrc)
356  MovMI->addRegisterKilled(SrcReg, TRI, true);
357 }
358 
361  MCRegister DestReg, MCRegister SrcReg,
362  bool KillSrc) const {
363 
364  if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {
365  BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
366  .addReg(SrcReg, getKillRegState(KillSrc))
367  .addImm(0);
368  } else if (VE::V64RegClass.contains(DestReg, SrcReg)) {
369  // Generate following instructions
370  // %sw16 = LEA32zii 256
371  // VORmvl %dest, (0)1, %src, %sw16
372  // TODO: reuse a register if vl is already assigned to a register
373  // FIXME: it would be better to scavenge a register here instead of
374  // reserving SX16 all of the time.
376  Register TmpReg = VE::SX16;
377  Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32);
378  BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg)
379  .addImm(0)
380  .addImm(0)
381  .addImm(256);
382  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg)
383  .addImm(M1(0)) // Represent (0)1.
384  .addReg(SrcReg, getKillRegState(KillSrc))
385  .addReg(SubTmp, getKillRegState(true));
386  MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true);
387  } else if (VE::VMRegClass.contains(DestReg, SrcReg)) {
388  BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg)
389  .addReg(VE::VM0)
390  .addReg(SrcReg, getKillRegState(KillSrc));
391  } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) {
392  // Use two instructions.
393  const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};
394  unsigned int NumSubRegs = 2;
395  copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm),
396  NumSubRegs, SubRegIdx, &getRegisterInfo());
397  } else if (VE::F128RegClass.contains(DestReg, SrcReg)) {
398  // Use two instructions.
399  const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
400  unsigned int NumSubRegs = 2;
401  copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri),
402  NumSubRegs, SubRegIdx, &getRegisterInfo());
403  } else {
405  dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI)
406  << " to " << printReg(DestReg, TRI) << "\n";
407  llvm_unreachable("Impossible reg-to-reg copy");
408  }
409 }
410 
411 /// isLoadFromStackSlot - If the specified machine instruction is a direct
412 /// load from a stack slot, return the virtual or physical register number of
413 /// the destination along with the FrameIndex of the loaded stack slot. If
414 /// not, return 0. This predicate must return 0 if the instruction has
415 /// any side effects other than loading from the stack slot.
417  int &FrameIndex) const {
418  if (MI.getOpcode() == VE::LDrii || // I64
419  MI.getOpcode() == VE::LDLSXrii || // I32
420  MI.getOpcode() == VE::LDUrii || // F32
421  MI.getOpcode() == VE::LDQrii // F128 (pseudo)
422  ) {
423  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
424  MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() &&
425  MI.getOperand(3).getImm() == 0) {
426  FrameIndex = MI.getOperand(1).getIndex();
427  return MI.getOperand(0).getReg();
428  }
429  }
430  return 0;
431 }
432 
433 /// isStoreToStackSlot - If the specified machine instruction is a direct
434 /// store to a stack slot, return the virtual or physical register number of
435 /// the source reg along with the FrameIndex of the loaded stack slot. If
436 /// not, return 0. This predicate must return 0 if the instruction has
437 /// any side effects other than storing to the stack slot.
439  int &FrameIndex) const {
440  if (MI.getOpcode() == VE::STrii || // I64
441  MI.getOpcode() == VE::STLrii || // I32
442  MI.getOpcode() == VE::STUrii || // F32
443  MI.getOpcode() == VE::STQrii // F128 (pseudo)
444  ) {
445  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
446  MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() &&
447  MI.getOperand(2).getImm() == 0) {
448  FrameIndex = MI.getOperand(0).getIndex();
449  return MI.getOperand(3).getReg();
450  }
451  }
452  return 0;
453 }
454 
457  Register SrcReg, bool isKill, int FI,
458  const TargetRegisterClass *RC,
459  const TargetRegisterInfo *TRI) const {
460  DebugLoc DL;
461  if (I != MBB.end())
462  DL = I->getDebugLoc();
463 
464  MachineFunction *MF = MBB.getParent();
465  const MachineFrameInfo &MFI = MF->getFrameInfo();
468  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
469 
470  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
471  if (RC == &VE::I64RegClass) {
472  BuildMI(MBB, I, DL, get(VE::STrii))
473  .addFrameIndex(FI)
474  .addImm(0)
475  .addImm(0)
476  .addReg(SrcReg, getKillRegState(isKill))
477  .addMemOperand(MMO);
478  } else if (RC == &VE::I32RegClass) {
479  BuildMI(MBB, I, DL, get(VE::STLrii))
480  .addFrameIndex(FI)
481  .addImm(0)
482  .addImm(0)
483  .addReg(SrcReg, getKillRegState(isKill))
484  .addMemOperand(MMO);
485  } else if (RC == &VE::F32RegClass) {
486  BuildMI(MBB, I, DL, get(VE::STUrii))
487  .addFrameIndex(FI)
488  .addImm(0)
489  .addImm(0)
490  .addReg(SrcReg, getKillRegState(isKill))
491  .addMemOperand(MMO);
492  } else if (VE::F128RegClass.hasSubClassEq(RC)) {
493  BuildMI(MBB, I, DL, get(VE::STQrii))
494  .addFrameIndex(FI)
495  .addImm(0)
496  .addImm(0)
497  .addReg(SrcReg, getKillRegState(isKill))
498  .addMemOperand(MMO);
499  } else
500  report_fatal_error("Can't store this register to stack slot");
501 }
502 
505  Register DestReg, int FI,
506  const TargetRegisterClass *RC,
507  const TargetRegisterInfo *TRI) const {
508  DebugLoc DL;
509  if (I != MBB.end())
510  DL = I->getDebugLoc();
511 
512  MachineFunction *MF = MBB.getParent();
513  const MachineFrameInfo &MFI = MF->getFrameInfo();
516  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
517 
518  if (RC == &VE::I64RegClass) {
519  BuildMI(MBB, I, DL, get(VE::LDrii), DestReg)
520  .addFrameIndex(FI)
521  .addImm(0)
522  .addImm(0)
523  .addMemOperand(MMO);
524  } else if (RC == &VE::I32RegClass) {
525  BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg)
526  .addFrameIndex(FI)
527  .addImm(0)
528  .addImm(0)
529  .addMemOperand(MMO);
530  } else if (RC == &VE::F32RegClass) {
531  BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg)
532  .addFrameIndex(FI)
533  .addImm(0)
534  .addImm(0)
535  .addMemOperand(MMO);
536  } else if (VE::F128RegClass.hasSubClassEq(RC)) {
537  BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg)
538  .addFrameIndex(FI)
539  .addImm(0)
540  .addImm(0)
541  .addMemOperand(MMO);
542  } else
543  report_fatal_error("Can't load this register from stack slot");
544 }
545 
548  LLVM_DEBUG(dbgs() << "FoldImmediate\n");
549 
550  LLVM_DEBUG(dbgs() << "checking DefMI\n");
551  int64_t ImmVal;
552  switch (DefMI.getOpcode()) {
553  default:
554  return false;
555  case VE::ORim:
556  // General move small immediate instruction on VE.
557  LLVM_DEBUG(dbgs() << "checking ORim\n");
558  LLVM_DEBUG(DefMI.dump());
559  // FIXME: We may need to support FPImm too.
560  assert(DefMI.getOperand(1).isImm());
561  assert(DefMI.getOperand(2).isImm());
562  ImmVal =
563  DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm());
564  LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");
565  break;
566  case VE::LEAzii:
567  // General move immediate instruction on VE.
568  LLVM_DEBUG(dbgs() << "checking LEAzii\n");
569  LLVM_DEBUG(DefMI.dump());
570  // FIXME: We may need to support FPImm too.
571  assert(DefMI.getOperand(2).isImm());
572  if (!DefMI.getOperand(3).isImm())
573  // LEAzii may refer label
574  return false;
575  ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm();
576  LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");
577  break;
578  }
579 
580  // Try to fold like below:
581  // %1:i64 = ORim 0, 0(1)
582  // %2:i64 = CMPSLrr %0, %1
583  // To
584  // %2:i64 = CMPSLrm %0, 0(1)
585  //
586  // Another example:
587  // %1:i64 = ORim 6, 0(1)
588  // %2:i64 = CMPSLrr %1, %0
589  // To
590  // %2:i64 = CMPSLir 6, %0
591  //
592  // Support commutable instructions like below:
593  // %1:i64 = ORim 6, 0(1)
594  // %2:i64 = ADDSLrr %1, %0
595  // To
596  // %2:i64 = ADDSLri %0, 6
597  //
598  // FIXME: Need to support i32. Current implementtation requires
599  // EXTRACT_SUBREG, so input has following COPY and it avoids folding:
600  // %1:i64 = ORim 6, 0(1)
601  // %2:i32 = COPY %1.sub_i32
602  // %3:i32 = ADDSWSXrr %0, %2
603  // FIXME: Need to support shift, cmov, and more instructions.
604  // FIXME: Need to support lvl too, but LVLGen runs after peephole-opt.
605 
606  LLVM_DEBUG(dbgs() << "checking UseMI\n");
607  LLVM_DEBUG(UseMI.dump());
608  unsigned NewUseOpcSImm7;
609  unsigned NewUseOpcMImm;
610  enum InstType {
611  rr2ri_rm, // rr -> ri or rm, commutable
612  rr2ir_rm, // rr -> ir or rm
613  } InstType;
614 
615  using namespace llvm::VE;
616 #define INSTRKIND(NAME) \
617  case NAME##rr: \
618  NewUseOpcSImm7 = NAME##ri; \
619  NewUseOpcMImm = NAME##rm; \
620  InstType = rr2ri_rm; \
621  break
622 #define NCINSTRKIND(NAME) \
623  case NAME##rr: \
624  NewUseOpcSImm7 = NAME##ir; \
625  NewUseOpcMImm = NAME##rm; \
626  InstType = rr2ir_rm; \
627  break
628 
629  switch (UseMI.getOpcode()) {
630  default:
631  return false;
632 
633  INSTRKIND(ADDUL);
634  INSTRKIND(ADDSWSX);
635  INSTRKIND(ADDSWZX);
636  INSTRKIND(ADDSL);
637  NCINSTRKIND(SUBUL);
638  NCINSTRKIND(SUBSWSX);
639  NCINSTRKIND(SUBSWZX);
640  NCINSTRKIND(SUBSL);
641  INSTRKIND(MULUL);
642  INSTRKIND(MULSWSX);
643  INSTRKIND(MULSWZX);
644  INSTRKIND(MULSL);
645  NCINSTRKIND(DIVUL);
646  NCINSTRKIND(DIVSWSX);
647  NCINSTRKIND(DIVSWZX);
648  NCINSTRKIND(DIVSL);
649  NCINSTRKIND(CMPUL);
650  NCINSTRKIND(CMPSWSX);
651  NCINSTRKIND(CMPSWZX);
652  NCINSTRKIND(CMPSL);
653  INSTRKIND(MAXSWSX);
654  INSTRKIND(MAXSWZX);
655  INSTRKIND(MAXSL);
656  INSTRKIND(MINSWSX);
657  INSTRKIND(MINSWZX);
658  INSTRKIND(MINSL);
659  INSTRKIND(AND);
660  INSTRKIND(OR);
661  INSTRKIND(XOR);
662  INSTRKIND(EQV);
663  NCINSTRKIND(NND);
664  NCINSTRKIND(MRG);
665  }
666 
667 #undef INSTRKIND
668 
669  unsigned NewUseOpc;
670  unsigned UseIdx;
671  bool Commute = false;
672  LLVM_DEBUG(dbgs() << "checking UseMI operands\n");
673  switch (InstType) {
674  case rr2ri_rm:
675  UseIdx = 2;
676  if (UseMI.getOperand(1).getReg() == Reg) {
677  Commute = true;
678  } else {
679  assert(UseMI.getOperand(2).getReg() == Reg);
680  }
681  if (isInt<7>(ImmVal)) {
682  // This ImmVal matches to SImm7 slot, so change UseOpc to an instruction
683  // holds a simm7 slot.
684  NewUseOpc = NewUseOpcSImm7;
685  } else if (isMImmVal(ImmVal)) {
686  // Similarly, change UseOpc to an instruction holds a mimm slot.
687  NewUseOpc = NewUseOpcMImm;
688  ImmVal = val2MImm(ImmVal);
689  } else
690  return false;
691  break;
692  case rr2ir_rm:
693  if (UseMI.getOperand(1).getReg() == Reg) {
694  // Check immediate value whether it matchs to the UseMI instruction.
695  if (!isInt<7>(ImmVal))
696  return false;
697  NewUseOpc = NewUseOpcSImm7;
698  UseIdx = 1;
699  } else {
700  assert(UseMI.getOperand(2).getReg() == Reg);
701  // Check immediate value whether it matchs to the UseMI instruction.
702  if (!isMImmVal(ImmVal))
703  return false;
704  NewUseOpc = NewUseOpcMImm;
705  ImmVal = val2MImm(ImmVal);
706  UseIdx = 2;
707  }
708  break;
709  }
710 
711  LLVM_DEBUG(dbgs() << "modifying UseMI\n");
712  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
713  UseMI.setDesc(get(NewUseOpc));
714  if (Commute) {
715  UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg());
716  }
717  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
718  if (DeleteDef)
719  DefMI.eraseFromParent();
720 
721  return true;
722 }
723 
727  if (GlobalBaseReg != 0)
728  return GlobalBaseReg;
729 
730  // We use %s15 (%got) as a global base register
731  GlobalBaseReg = VE::SX15;
732 
733  // Insert a pseudo instruction to set the GlobalBaseReg into the first
734  // MBB of the function
735  MachineBasicBlock &FirstMBB = MF->front();
737  DebugLoc dl;
738  BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg);
740  return GlobalBaseReg;
741 }
742 
744  return (reg - VE::VMP0) * 2 + VE::VM0;
745 }
746 
747 static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; }
748 
749 // Expand pseudo logical vector instructions for VM512 registers.
750 static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID) {
751  MachineBasicBlock *MBB = MI.getParent();
752  DebugLoc DL = MI.getDebugLoc();
753 
754  Register VMXu = getVM512Upper(MI.getOperand(0).getReg());
755  Register VMXl = getVM512Lower(MI.getOperand(0).getReg());
756  Register VMYu = getVM512Upper(MI.getOperand(1).getReg());
757  Register VMYl = getVM512Lower(MI.getOperand(1).getReg());
758 
759  switch (MI.getOpcode()) {
760  default: {
761  Register VMZu = getVM512Upper(MI.getOperand(2).getReg());
762  Register VMZl = getVM512Lower(MI.getOperand(2).getReg());
763  BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu);
764  BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl);
765  break;
766  }
767  case VE::NEGMy:
768  BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu);
769  BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl);
770  break;
771  }
772  MI.eraseFromParent();
773 }
774 
776  bool Upper) {
777  // VM512
778  MIB.addReg(Upper ? getVM512Upper(MI.getOperand(0).getReg())
779  : getVM512Lower(MI.getOperand(0).getReg()));
780 
781  switch (MI.getNumExplicitOperands()) {
782  default:
783  report_fatal_error("unexpected number of operands for pvfmk");
784  case 2: // _Ml: VM512, VL
785  // VL
786  MIB.addReg(MI.getOperand(1).getReg());
787  break;
788  case 4: // _Mvl: VM512, CC, VR, VL
789  // CC
790  MIB.addImm(MI.getOperand(1).getImm());
791  // VR
792  MIB.addReg(MI.getOperand(2).getReg());
793  // VL
794  MIB.addReg(MI.getOperand(3).getReg());
795  break;
796  case 5: // _MvMl: VM512, CC, VR, VM512, VL
797  // CC
798  MIB.addImm(MI.getOperand(1).getImm());
799  // VR
800  MIB.addReg(MI.getOperand(2).getReg());
801  // VM512
802  MIB.addReg(Upper ? getVM512Upper(MI.getOperand(3).getReg())
803  : getVM512Lower(MI.getOperand(3).getReg()));
804  // VL
805  MIB.addReg(MI.getOperand(4).getReg());
806  break;
807  }
808 }
809 
811  // replace to pvfmk.w.up and pvfmk.w.lo
812  // replace to pvfmk.s.up and pvfmk.s.lo
813 
814  static const std::pair<unsigned, std::pair<unsigned, unsigned>> VFMKMap[] = {
815  {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}},
816  {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}},
817  {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}},
818  {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}},
819  {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}},
820  {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}},
821  };
822 
823  unsigned Opcode = MI.getOpcode();
824 
825  const auto *Found =
826  llvm::find_if(VFMKMap, [&](auto P) { return P.first == Opcode; });
827  if (Found == std::end(VFMKMap))
828  report_fatal_error("unexpected opcode for pseudo vfmk");
829 
830  unsigned OpcodeUpper = (*Found).second.first;
831  unsigned OpcodeLower = (*Found).second.second;
832 
833  MachineBasicBlock *MBB = MI.getParent();
834  DebugLoc DL = MI.getDebugLoc();
835 
836  MachineInstrBuilder Bu = BuildMI(*MBB, MI, DL, TI.get(OpcodeUpper));
837  addOperandsForVFMK(Bu, MI, /* Upper */ true);
838  MachineInstrBuilder Bl = BuildMI(*MBB, MI, DL, TI.get(OpcodeLower));
839  addOperandsForVFMK(Bl, MI, /* Upper */ false);
840 
841  MI.eraseFromParent();
842 }
843 
845  switch (MI.getOpcode()) {
846  case VE::EXTEND_STACK: {
847  return expandExtendStackPseudo(MI);
848  }
849  case VE::EXTEND_STACK_GUARD: {
850  MI.eraseFromParent(); // The pseudo instruction is gone now.
851  return true;
852  }
853  case VE::GETSTACKTOP: {
854  return expandGetStackTopPseudo(MI);
855  }
856 
857  case VE::ANDMyy:
858  expandPseudoLogM(MI, get(VE::ANDMmm));
859  return true;
860  case VE::ORMyy:
861  expandPseudoLogM(MI, get(VE::ORMmm));
862  return true;
863  case VE::XORMyy:
864  expandPseudoLogM(MI, get(VE::XORMmm));
865  return true;
866  case VE::EQVMyy:
867  expandPseudoLogM(MI, get(VE::EQVMmm));
868  return true;
869  case VE::NNDMyy:
870  expandPseudoLogM(MI, get(VE::NNDMmm));
871  return true;
872  case VE::NEGMy:
873  expandPseudoLogM(MI, get(VE::NEGMm));
874  return true;
875 
876  case VE::LVMyir:
877  case VE::LVMyim:
878  case VE::LVMyir_y:
879  case VE::LVMyim_y: {
880  Register VMXu = getVM512Upper(MI.getOperand(0).getReg());
881  Register VMXl = getVM512Lower(MI.getOperand(0).getReg());
882  int64_t Imm = MI.getOperand(1).getImm();
883  bool IsSrcReg =
884  MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y;
885  Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister;
886  int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm();
887  bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false;
888  Register VMX = VMXl;
889  if (Imm >= 4) {
890  VMX = VMXu;
891  Imm -= 4;
892  }
893  MachineBasicBlock *MBB = MI.getParent();
894  DebugLoc DL = MI.getDebugLoc();
895  switch (MI.getOpcode()) {
896  case VE::LVMyir:
897  BuildMI(*MBB, MI, DL, get(VE::LVMir))
898  .addDef(VMX)
899  .addImm(Imm)
900  .addReg(Src, getKillRegState(KillSrc));
901  break;
902  case VE::LVMyim:
903  BuildMI(*MBB, MI, DL, get(VE::LVMim))
904  .addDef(VMX)
905  .addImm(Imm)
906  .addImm(MImm);
907  break;
908  case VE::LVMyir_y:
909  assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&
910  "LVMyir_y has different register in 3rd operand");
911  BuildMI(*MBB, MI, DL, get(VE::LVMir_m))
912  .addDef(VMX)
913  .addImm(Imm)
914  .addReg(Src, getKillRegState(KillSrc))
915  .addReg(VMX);
916  break;
917  case VE::LVMyim_y:
918  assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&
919  "LVMyim_y has different register in 3rd operand");
920  BuildMI(*MBB, MI, DL, get(VE::LVMim_m))
921  .addDef(VMX)
922  .addImm(Imm)
923  .addImm(MImm)
924  .addReg(VMX);
925  break;
926  }
927  MI.eraseFromParent();
928  return true;
929  }
930  case VE::SVMyi: {
931  Register Dest = MI.getOperand(0).getReg();
932  Register VMZu = getVM512Upper(MI.getOperand(1).getReg());
933  Register VMZl = getVM512Lower(MI.getOperand(1).getReg());
934  bool KillSrc = MI.getOperand(1).isKill();
935  int64_t Imm = MI.getOperand(2).getImm();
936  Register VMZ = VMZl;
937  if (Imm >= 4) {
938  VMZ = VMZu;
939  Imm -= 4;
940  }
941  MachineBasicBlock *MBB = MI.getParent();
942  DebugLoc DL = MI.getDebugLoc();
943  MachineInstrBuilder MIB =
944  BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm);
945  MachineInstr *Inst = MIB.getInstr();
946  if (KillSrc) {
948  Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true);
949  }
950  MI.eraseFromParent();
951  return true;
952  }
953  case VE::VFMKyal:
954  case VE::VFMKynal:
955  case VE::VFMKWyvl:
956  case VE::VFMKWyvyl:
957  case VE::VFMKSyvl:
958  case VE::VFMKSyvyl:
959  expandPseudoVFMK(*this, MI);
960  return true;
961  }
962  return false;
963 }
964 
966  MachineBasicBlock &MBB = *MI.getParent();
967  MachineFunction &MF = *MBB.getParent();
968  const VESubtarget &STI = MF.getSubtarget<VESubtarget>();
969  const VEInstrInfo &TII = *STI.getInstrInfo();
970  DebugLoc dl = MBB.findDebugLoc(MI);
971 
972  // Create following instructions and multiple basic blocks.
973  //
974  // thisBB:
975  // brge.l.t %sp, %sl, sinkBB
976  // syscallBB:
977  // ld %s61, 0x18(, %tp) // load param area
978  // or %s62, 0, %s0 // spill the value of %s0
979  // lea %s63, 0x13b // syscall # of grow
980  // shm.l %s63, 0x0(%s61) // store syscall # at addr:0
981  // shm.l %sl, 0x8(%s61) // store old limit at addr:8
982  // shm.l %sp, 0x10(%s61) // store new limit at addr:16
983  // monc // call monitor
984  // or %s0, 0, %s62 // restore the value of %s0
985  // sinkBB:
986 
987  // Create new MBB
989  const BasicBlock *LLVM_BB = BB->getBasicBlock();
990  MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB);
991  MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB);
992  MachineFunction::iterator It = ++(BB->getIterator());
993  MF.insert(It, syscallMBB);
994  MF.insert(It, sinkMBB);
995 
996  // Transfer the remainder of BB and its successor edges to sinkMBB.
997  sinkMBB->splice(sinkMBB->begin(), BB,
998  std::next(std::next(MachineBasicBlock::iterator(MI))),
999  BB->end());
1001 
1002  // Next, add the true and fallthrough blocks as its successors.
1003  BB->addSuccessor(syscallMBB);
1004  BB->addSuccessor(sinkMBB);
1005  BuildMI(BB, dl, TII.get(VE::BRCFLrr_t))
1007  .addReg(VE::SX11) // %sp
1008  .addReg(VE::SX8) // %sl
1009  .addMBB(sinkMBB);
1010 
1011  BB = syscallMBB;
1012 
1013  // Update machine-CFG edges
1014  BB->addSuccessor(sinkMBB);
1015 
1016  BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61)
1017  .addReg(VE::SX14)
1018  .addImm(0)
1019  .addImm(0x18);
1020  BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62)
1021  .addReg(VE::SX0)
1022  .addImm(0);
1023  BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63)
1024  .addImm(0)
1025  .addImm(0)
1026  .addImm(0x13b);
1027  BuildMI(BB, dl, TII.get(VE::SHMLri))
1028  .addReg(VE::SX61)
1029  .addImm(0)
1030  .addReg(VE::SX63);
1031  BuildMI(BB, dl, TII.get(VE::SHMLri))
1032  .addReg(VE::SX61)
1033  .addImm(8)
1034  .addReg(VE::SX8);
1035  BuildMI(BB, dl, TII.get(VE::SHMLri))
1036  .addReg(VE::SX61)
1037  .addImm(16)
1038  .addReg(VE::SX11);
1039  BuildMI(BB, dl, TII.get(VE::MONC));
1040 
1041  BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0)
1042  .addReg(VE::SX62)
1043  .addImm(0);
1044 
1045  MI.eraseFromParent(); // The pseudo instruction is gone now.
1046  return true;
1047 }
1048 
1050  MachineBasicBlock *MBB = MI.getParent();
1051  MachineFunction &MF = *MBB->getParent();
1052  const VESubtarget &STI = MF.getSubtarget<VESubtarget>();
1053  const VEInstrInfo &TII = *STI.getInstrInfo();
1055 
1056  // Create following instruction
1057  //
1058  // dst = %sp + target specific frame + the size of parameter area
1059 
1060  const MachineFrameInfo &MFI = MF.getFrameInfo();
1061  const VEFrameLowering &TFL = *STI.getFrameLowering();
1062 
1063  // The VE ABI requires a reserved area at the top of stack as described
1064  // in VEFrameLowering.cpp. So, we adjust it here.
1065  unsigned NumBytes = STI.getAdjustedFrameSize(0);
1066 
1067  // Also adds the size of parameter area.
1068  if (MFI.adjustsStack() && TFL.hasReservedCallFrame(MF))
1069  NumBytes += MFI.getMaxCallFrameSize();
1070 
1071  BuildMI(*MBB, MI, DL, TII.get(VE::LEArii))
1072  .addDef(MI.getOperand(0).getReg())
1073  .addReg(VE::SX11)
1074  .addImm(0)
1075  .addImm(NumBytes);
1076 
1077  MI.eraseFromParent(); // The pseudo instruction is gone now.
1078  return true;
1079 }
llvm::VECC::CC_IL
@ CC_IL
Definition: VE.h:44
llvm::VEInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: VEInstrInfo.cpp:844
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::VEInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: VEInstrInfo.cpp:291
llvm::VEInstrInfo::getRegisterInfo
const VERegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: VEInstrInfo.h:62
llvm::HexPrintStyle::Upper
@ Upper
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::VECC::CC_INE
@ CC_INE
Definition: VE.h:45
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::VEInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: VEInstrInfo.cpp:503
llvm::VECC::CondCode
CondCode
Definition: VE.h:41
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::VEInstrInfo::VEInstrInfo
VEInstrInfo(VESubtarget &ST)
Definition: VEInstrInfo.cpp:38
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
getVM512Upper
static Register getVM512Upper(Register reg)
Definition: VEInstrInfo.cpp:743
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:1977
llvm::val2MImm
static uint64_t val2MImm(uint64_t Val)
val2MImm - Convert an integer immediate value to target MImm immediate.
Definition: VE.h:353
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1369
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:452
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:841
parseCondBranch
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
Definition: VEInstrInfo.cpp:137
llvm::isMImmVal
static bool isMImmVal(uint64_t Val)
Definition: VE.h:326
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:450
STLExtras.h
VEInstrInfo.h
llvm::VEISD::GETSTACKTOP
@ GETSTACKTOP
Definition: VEISelLowering.h:33
llvm::VECC::CC_LE
@ CC_LE
Definition: VE.h:57
llvm::VECC::CC_G
@ CC_G
Definition: VE.h:52
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
llvm::VESubtarget::getAdjustedFrameSize
uint64_t getAdjustedFrameSize(uint64_t FrameSize) const
Given a actual stack size as determined by FrameInfo, this function returns adjusted framesize which ...
Definition: VESubtarget.cpp:50
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:982
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
IsAliasOfSX
static bool IsAliasOfSX(Register Reg)
Definition: VEInstrInfo.cpp:321
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::VEInstrInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
Definition: VEInstrInfo.cpp:724
llvm::VECC::CC_NE
@ CC_NE
Definition: VE.h:54
CommandLine.h
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:834
llvm::VECC::CC_IG
@ CC_IG
Definition: VE.h:43
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::VEInstrInfo::expandGetStackTopPseudo
bool expandGetStackTopPseudo(MachineInstr &MI) const
Definition: VEInstrInfo.cpp:1049
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::VEMachineFunctionInfo::setGlobalBaseReg
void setGlobalBaseReg(Register Reg)
Definition: VEMachineFunctionInfo.h:37
llvm::VEInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: VEInstrInfo.cpp:455
IsIntegerCC
static bool IsIntegerCC(unsigned CC)
Definition: VEInstrInfo.cpp:41
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::PPCISD::GlobalBaseReg
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
Definition: PPCISelLowering.h:156
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::VECC::CC_EQNAN
@ CC_EQNAN
Definition: VE.h:63
llvm::VECC::UNKNOWN
@ UNKNOWN
Definition: VE.h:67
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::VEInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
} Stack Spill & Reload
Definition: VEInstrInfo.cpp:546
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1829
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::VECC::CC_NENAN
@ CC_NENAN
Definition: VE.h:62
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::VEInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
} Branch Analysis & Modification
Definition: VEInstrInfo.cpp:359
llvm::mimm2Val
static uint64_t mimm2Val(uint64_t Val)
mimm2Val - Convert a target MImm immediate to an integer immediate value.
Definition: VE.h:362
llvm::VECC::CC_LNAN
@ CC_LNAN
Definition: VE.h:61
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::VECC::CC_GNAN
@ CC_GNAN
Definition: VE.h:60
llvm::VEInstrInfo
Definition: VEInstrInfo.h:51
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::VEFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: VEFrameLowering.h:48
llvm::VECC::CC_NAN
@ CC_NAN
Definition: VE.h:59
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:469
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::VEInstrInfo::expandExtendStackPseudo
bool expandExtendStackPseudo(MachineInstr &MI) const
Definition: VEInstrInfo.cpp:965
llvm::VECC::CC_EQ
@ CC_EQ
Definition: VE.h:55
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::VECC::CC_GENAN
@ CC_GENAN
Definition: VE.h:64
copyPhysSubRegs
static void copyPhysSubRegs(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const MCInstrDesc &MCID, unsigned int NumSubRegs, const unsigned *SubRegIdx, const TargetRegisterInfo *TRI)
Definition: VEInstrInfo.cpp:326
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
expandPseudoLogM
static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID)
Definition: VEInstrInfo.cpp:750
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:441
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:263
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::VEMachineFunctionInfo::getGlobalBaseReg
Register getGlobalBaseReg() const
Definition: VEMachineFunctionInfo.h:36
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::VEFrameLowering
Definition: VEFrameLowering.h:23
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::VEInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Branch Analysis & Modification {.
Definition: VEInstrInfo.cpp:145
expandPseudoVFMK
static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI)
Definition: VEInstrInfo.cpp:810
llvm::VESubtarget::getFrameLowering
const VEFrameLowering * getFrameLowering() const override
Definition: VESubtarget.h:52
BRKIND
#define BRKIND(NAME)
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::VEInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: VEInstrInfo.cpp:226
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
VEGenInstrInfo
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::VEMachineFunctionInfo
Definition: VEMachineFunctionInfo.h:19
INSTRKIND
#define INSTRKIND(NAME)
llvm::VECC::CC_IEQ
@ CC_IEQ
Definition: VE.h:46
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1632
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VEInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: VEInstrInfo.cpp:314
GetOppositeBranchCondition
static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC)
Definition: VEInstrInfo.cpp:43
addOperandsForVFMK
static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI, bool Upper)
Definition: VEInstrInfo.cpp:775
llvm::VESubtarget::getInstrInfo
const VEInstrInfo * getInstrInfo() const override
Definition: VESubtarget.h:51
VEMachineFunctionInfo.h
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:277
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::VECC::CC_AF
@ CC_AF
Definition: VE.h:51
getVM512Lower
static Register getVM512Lower(Register reg)
Definition: VEInstrInfo.cpp:747
llvm::VECC::CC_IGE
@ CC_IGE
Definition: VE.h:47
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::VECC::CC_LENAN
@ CC_LENAN
Definition: VE.h:65
VE.h
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::VESubtarget
Definition: VESubtarget.h:31
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::VEInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Stack Spill & Reload {.
Definition: VEInstrInfo.cpp:416
VESubtarget.h
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::VECC::CC_NUM
@ CC_NUM
Definition: VE.h:58
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:886
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
llvm::VE
Definition: VEFixupKinds.h:15
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::VEInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: VEInstrInfo.cpp:438
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:601
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:371
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:650
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegistry.h
llvm::VECC::CC_ILE
@ CC_ILE
Definition: VE.h:48
llvm::VECC::CC_GE
@ CC_GE
Definition: VE.h:56
llvm::VECC::CC_AT
@ CC_AT
Definition: VE.h:66
llvm::VECC::CC_L
@ CC_L
Definition: VE.h:53
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
NCINSTRKIND
#define NCINSTRKIND(NAME)
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24