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LLVM 18.0.0git
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#include "MCTargetDesc/X86BaseInfo.h"#include "MCTargetDesc/X86FixupKinds.h"#include "MCTargetDesc/X86EncodingOptimization.h"#include "llvm/ADT/StringSwitch.h"#include "llvm/BinaryFormat/ELF.h"#include "llvm/BinaryFormat/MachO.h"#include "llvm/MC/MCAsmBackend.h"#include "llvm/MC/MCAsmLayout.h"#include "llvm/MC/MCAssembler.h"#include "llvm/MC/MCCodeEmitter.h"#include "llvm/MC/MCContext.h"#include "llvm/MC/MCDwarf.h"#include "llvm/MC/MCELFObjectWriter.h"#include "llvm/MC/MCExpr.h"#include "llvm/MC/MCFixupKindInfo.h"#include "llvm/MC/MCInst.h"#include "llvm/MC/MCInstrInfo.h"#include "llvm/MC/MCMachObjectWriter.h"#include "llvm/MC/MCObjectStreamer.h"#include "llvm/MC/MCObjectWriter.h"#include "llvm/MC/MCRegisterInfo.h"#include "llvm/MC/MCSectionMachO.h"#include "llvm/MC/MCSubtargetInfo.h"#include "llvm/MC/MCValue.h"#include "llvm/MC/TargetRegistry.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"#include "llvm/BinaryFormat/ELFRelocs/i386.def"Go to the source code of this file.
Namespaces | |
| namespace | CU |
Macros | |
| #define | ELF_RELOC(X, Y) .Case(#X, Y) |
| #define | ELF_RELOC(X, Y) .Case(#X, Y) |
Functions | |
| static bool | isRelaxableBranch (unsigned Opcode) |
| static unsigned | getRelaxedOpcodeBranch (unsigned Opcode, bool Is16BitMode=false) |
| static unsigned | getRelaxedOpcode (const MCInst &MI, bool Is16BitMode) |
| static X86::CondCode | getCondFromBranch (const MCInst &MI, const MCInstrInfo &MCII) |
| static X86::SecondMacroFusionInstKind | classifySecondInstInMacroFusion (const MCInst &MI, const MCInstrInfo &MCII) |
| static bool | isRIPRelative (const MCInst &MI, const MCInstrInfo &MCII) |
| Check if the instruction uses RIP relative addressing. | |
| static bool | isPrefix (const MCInst &MI, const MCInstrInfo &MCII) |
| Check if the instruction is a prefix. | |
| static bool | isFirstMacroFusibleInst (const MCInst &Inst, const MCInstrInfo &MCII) |
| Check if the instruction is valid as the first instruction in macro fusion. | |
| static bool | hasVariantSymbol (const MCInst &MI) |
| Check if the instruction has a variant symbol operand. | |
| static bool | hasInterruptDelaySlot (const MCInst &Inst) |
| X86 has certain instructions which enable interrupts exactly one instruction after the instruction which stores to SS. | |
| static bool | isRightAfterData (MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition) |
| Check if the instruction to be emitted is right after any data. | |
| static size_t | getSizeForInstFragment (const MCFragment *F) |
| static unsigned | getFixupKindSize (unsigned Kind) |
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Definition at line 249 of file X86AsmBackend.cpp.
References CC, getCondFromBranch(), and MI.
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Definition at line 234 of file X86AsmBackend.cpp.
References llvm::X86::COND_INVALID, llvm::MCInstrInfo::get(), MI, and Opcode.
Referenced by classifySecondInstInMacroFusion().
Definition at line 653 of file X86AsmBackend.cpp.
References llvm::FK_Data_1, llvm::FK_Data_2, llvm::FK_Data_4, llvm::FK_Data_8, llvm::FK_NONE, llvm::FK_PCRel_1, llvm::FK_PCRel_2, llvm::FK_PCRel_4, llvm::FK_PCRel_8, llvm::FK_SecRel_1, llvm::FK_SecRel_2, llvm::FK_SecRel_4, llvm::FK_SecRel_8, llvm_unreachable, llvm::X86::reloc_branch_4byte_pcrel, llvm::X86::reloc_global_offset_table, llvm::X86::reloc_global_offset_table8, llvm::X86::reloc_riprel_4byte, llvm::X86::reloc_riprel_4byte_movq_load, llvm::X86::reloc_riprel_4byte_relax, llvm::X86::reloc_riprel_4byte_relax_rex, llvm::X86::reloc_signed_4byte, and llvm::X86::reloc_signed_4byte_relax.
Definition at line 228 of file X86AsmBackend.cpp.
References llvm::X86::getOpcodeForLongImmediateForm(), getRelaxedOpcodeBranch(), isRelaxableBranch(), MI, and Opcode.
Definition at line 216 of file X86AsmBackend.cpp.
References llvm_unreachable, and Opcode.
Referenced by getRelaxedOpcode().
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Definition at line 433 of file X86AsmBackend.cpp.
References F, llvm::MCFragment::FT_CompactEncodedInst, llvm::MCFragment::FT_Data, llvm::MCFragment::FT_Relaxable, and llvm_unreachable.
X86 has certain instructions which enable interrupts exactly one instruction after the instruction which stores to SS.
Return true if the given instruction has such an interrupt delay slot.
Definition at line 385 of file X86AsmBackend.cpp.
References llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), and llvm::MCOperand::getReg().
Check if the instruction has a variant symbol operand.
Definition at line 362 of file X86AsmBackend.cpp.
References llvm::MCExpr::getKind(), MI, llvm::MCExpr::SymbolRef, and llvm::MCSymbolRefExpr::VK_None.
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Check if the instruction is valid as the first instruction in macro fusion.
Definition at line 274 of file X86AsmBackend.cpp.
References llvm::X86::classifyFirstOpcodeInMacroFusion(), llvm::MCInst::getOpcode(), and isRIPRelative().
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Check if the instruction is a prefix.
Definition at line 269 of file X86AsmBackend.cpp.
References llvm::MCInstrInfo::get(), llvm::X86II::isPrefix(), MI, and llvm::MCInstrDesc::TSFlags.
Referenced by readPrefixes().
Definition at line 212 of file X86AsmBackend.cpp.
References Opcode.
Referenced by getRelaxedOpcode().
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Check if the instruction to be emitted is right after any data.
Definition at line 405 of file X86AsmBackend.cpp.
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Check if the instruction uses RIP relative addressing.
Definition at line 255 of file X86AsmBackend.cpp.
References llvm::X86::AddrBaseReg, llvm::MCInstrInfo::get(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), MI, and Opcode.
Referenced by isFirstMacroFusibleInst().
1.9.6