LLVM 18.0.0git
X86Disassembler.cpp
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1//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the X86 Disassembler.
10// It contains code to translate the data produced by the decoder into
11// MCInsts.
12//
13//
14// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
15// 64-bit X86 instruction sets. The main decode sequence for an assembly
16// instruction in this disassembler is:
17//
18// 1. Read the prefix bytes and determine the attributes of the instruction.
19// These attributes, recorded in enum attributeBits
20// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
21// provides a mapping from bitmasks to contexts, which are represented by
22// enum InstructionContext (ibid.).
23//
24// 2. Read the opcode, and determine what kind of opcode it is. The
25// disassembler distinguishes four kinds of opcodes, which are enumerated in
26// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
27// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
28// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
29//
30// 3. Depending on the opcode type, look in one of four ClassDecision structures
31// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
32// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
33// a ModRMDecision (ibid.).
34//
35// 4. Some instructions, such as escape opcodes or extended opcodes, or even
36// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
37// ModR/M byte to complete decode. The ModRMDecision's type is an entry from
38// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
39// ModR/M byte is required and how to interpret it.
40//
41// 5. After resolving the ModRMDecision, the disassembler has a unique ID
42// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
43// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
44// meanings of its operands.
45//
46// 6. For each operand, its encoding is an entry from OperandEncoding
47// (X86DisassemblerDecoderCommon.h) and its type is an entry from
48// OperandType (ibid.). The encoding indicates how to read it from the
49// instruction; the type indicates how to interpret the value once it has
50// been read. For example, a register operand could be stored in the R/M
51// field of the ModR/M byte, the REG field of the ModR/M byte, or added to
52// the main opcode. This is orthogonal from its meaning (an GPR or an XMM
53// register, for instance). Given this information, the operands can be
54// extracted and interpreted.
55//
56// 7. As the last step, the disassembler translates the instruction information
57// and operands into a format understandable by the client - in this case, an
58// MCInst for use by the MC infrastructure.
59//
60// The disassembler is broken broadly into two parts: the table emitter that
61// emits the instruction decode tables discussed above during compilation, and
62// the disassembler itself. The table emitter is documented in more detail in
63// utils/TableGen/X86DisassemblerEmitter.h.
64//
65// X86Disassembler.cpp contains the code responsible for step 7, and for
66// invoking the decoder to execute steps 1-6.
67// X86DisassemblerDecoderCommon.h contains the definitions needed by both the
68// table emitter and the disassembler.
69// X86DisassemblerDecoder.h contains the public interface of the decoder,
70// factored out into C for possible use by other projects.
71// X86DisassemblerDecoder.c contains the source code of the decoder, which is
72// responsible for steps 1-6.
73//
74//===----------------------------------------------------------------------===//
75
80#include "llvm/MC/MCContext.h"
82#include "llvm/MC/MCExpr.h"
83#include "llvm/MC/MCInst.h"
84#include "llvm/MC/MCInstrInfo.h"
87#include "llvm/Support/Debug.h"
88#include "llvm/Support/Format.h"
90
91using namespace llvm;
92using namespace llvm::X86Disassembler;
93
94#define DEBUG_TYPE "x86-disassembler"
95
96#define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s);
97
98// Specifies whether a ModR/M byte is needed and (if so) which
99// instruction each possible value of the ModR/M byte corresponds to. Once
100// this information is known, we have narrowed down to a single instruction.
102 uint8_t modrm_type;
104};
105
106// Specifies which set of ModR/M->instruction tables to look at
107// given a particular opcode.
110};
111
112// Specifies which opcode->instruction tables to look at given
113// a particular context (set of attributes). Since there are many possible
114// contexts, the decoder first uses CONTEXTS_SYM to determine which context
115// applies given a specific set of attributes. Hence there are only IC_max
116// entries in this table, rather than 2^(ATTR_max).
119};
120
121#include "X86GenDisassemblerTables.inc"
122
124 uint8_t opcode, uint8_t modRM) {
125 const struct ModRMDecision *dec;
126
127 switch (type) {
128 case ONEBYTE:
129 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
130 break;
131 case TWOBYTE:
132 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 break;
134 case THREEBYTE_38:
135 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
136 break;
137 case THREEBYTE_3A:
138 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
139 break;
140 case XOP8_MAP:
141 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
142 break;
143 case XOP9_MAP:
144 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
145 break;
146 case XOPA_MAP:
147 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
148 break;
149 case THREEDNOW_MAP:
150 dec =
151 &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
152 break;
153 case MAP4:
154 dec = &MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
155 break;
156 case MAP5:
157 dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
158 break;
159 case MAP6:
160 dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
161 break;
162 case MAP7:
163 dec = &MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
164 break;
165 }
166
167 switch (dec->modrm_type) {
168 default:
169 llvm_unreachable("Corrupt table! Unknown modrm_type");
170 return 0;
171 case MODRM_ONEENTRY:
172 return modRMTable[dec->instructionIDs];
173 case MODRM_SPLITRM:
174 if (modFromModRM(modRM) == 0x3)
175 return modRMTable[dec->instructionIDs + 1];
176 return modRMTable[dec->instructionIDs];
177 case MODRM_SPLITREG:
178 if (modFromModRM(modRM) == 0x3)
179 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8];
180 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
181 case MODRM_SPLITMISC:
182 if (modFromModRM(modRM) == 0x3)
183 return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8];
184 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
185 case MODRM_FULL:
186 return modRMTable[dec->instructionIDs + modRM];
187 }
188}
189
190static bool peek(struct InternalInstruction *insn, uint8_t &byte) {
191 uint64_t offset = insn->readerCursor - insn->startLocation;
192 if (offset >= insn->bytes.size())
193 return true;
194 byte = insn->bytes[offset];
195 return false;
196}
197
198template <typename T> static bool consume(InternalInstruction *insn, T &ptr) {
199 auto r = insn->bytes;
200 uint64_t offset = insn->readerCursor - insn->startLocation;
201 if (offset + sizeof(T) > r.size())
202 return true;
203 ptr = support::endian::read<T>(&r[offset], llvm::endianness::little);
204 insn->readerCursor += sizeof(T);
205 return false;
206}
207
208static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
209 return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f;
210}
211
212static bool isREX2(struct InternalInstruction *insn, uint8_t prefix) {
213 return insn->mode == MODE_64BIT && prefix == 0xd5;
214}
215
216// Consumes all of an instruction's prefix bytes, and marks the
217// instruction as having them. Also sets the instruction's default operand,
218// address, and other relevant data sizes to report operands correctly.
219//
220// insn must not be empty.
221static int readPrefixes(struct InternalInstruction *insn) {
222 bool isPrefix = true;
223 uint8_t byte = 0;
224 uint8_t nextByte;
225
226 LLVM_DEBUG(dbgs() << "readPrefixes()");
227
228 while (isPrefix) {
229 // If we fail reading prefixes, just stop here and let the opcode reader
230 // deal with it.
231 if (consume(insn, byte))
232 break;
233
234 // If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
235 // break and let it be disassembled as a normal "instruction".
236 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
237 break;
238
239 if ((byte == 0xf2 || byte == 0xf3) && !peek(insn, nextByte)) {
240 // If the byte is 0xf2 or 0xf3, and any of the following conditions are
241 // met:
242 // - it is followed by a LOCK (0xf0) prefix
243 // - it is followed by an xchg instruction
244 // then it should be disassembled as a xacquire/xrelease not repne/rep.
245 if (((nextByte == 0xf0) ||
246 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
247 insn->xAcquireRelease = true;
248 if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
249 break;
250 }
251 // Also if the byte is 0xf3, and the following condition is met:
252 // - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
253 // "mov mem, imm" (opcode 0xc6/0xc7) instructions.
254 // then it should be disassembled as an xrelease not rep.
255 if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
256 nextByte == 0xc6 || nextByte == 0xc7)) {
257 insn->xAcquireRelease = true;
258 break;
259 }
260 if (isREX(insn, nextByte)) {
261 uint8_t nnextByte;
262 // Go to REX prefix after the current one
263 if (consume(insn, nnextByte))
264 return -1;
265 // We should be able to read next byte after REX prefix
266 if (peek(insn, nnextByte))
267 return -1;
268 --insn->readerCursor;
269 }
270 }
271
272 switch (byte) {
273 case 0xf0: // LOCK
274 insn->hasLockPrefix = true;
275 break;
276 case 0xf2: // REPNE/REPNZ
277 case 0xf3: { // REP or REPE/REPZ
278 uint8_t nextByte;
279 if (peek(insn, nextByte))
280 break;
281 // TODO:
282 // 1. There could be several 0x66
283 // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then
284 // it's not mandatory prefix
285 // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
286 // 0x0f exactly after it to be mandatory prefix
287 if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
288 // The last of 0xf2 /0xf3 is mandatory prefix
289 insn->mandatoryPrefix = byte;
290 insn->repeatPrefix = byte;
291 break;
292 }
293 case 0x2e: // CS segment override -OR- Branch not taken
295 break;
296 case 0x36: // SS segment override -OR- Branch taken
298 break;
299 case 0x3e: // DS segment override
301 break;
302 case 0x26: // ES segment override
304 break;
305 case 0x64: // FS segment override
307 break;
308 case 0x65: // GS segment override
310 break;
311 case 0x66: { // Operand-size override {
312 uint8_t nextByte;
313 insn->hasOpSize = true;
314 if (peek(insn, nextByte))
315 break;
316 // 0x66 can't overwrite existing mandatory prefix and should be ignored
317 if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
318 insn->mandatoryPrefix = byte;
319 break;
320 }
321 case 0x67: // Address-size override
322 insn->hasAdSize = true;
323 break;
324 default: // Not a prefix byte
325 isPrefix = false;
326 break;
327 }
328
329 if (isPrefix)
330 LLVM_DEBUG(dbgs() << format("Found prefix 0x%hhx", byte));
331 }
332
334
335 if (byte == 0x62) {
336 uint8_t byte1, byte2;
337 if (consume(insn, byte1)) {
338 LLVM_DEBUG(dbgs() << "Couldn't read second byte of EVEX prefix");
339 return -1;
340 }
341
342 if (peek(insn, byte2)) {
343 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
344 return -1;
345 }
346
347 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)) {
349 } else {
350 --insn->readerCursor; // unconsume byte1
351 --insn->readerCursor; // unconsume byte
352 }
353
354 if (insn->vectorExtensionType == TYPE_EVEX) {
355 insn->vectorExtensionPrefix[0] = byte;
356 insn->vectorExtensionPrefix[1] = byte1;
357 if (consume(insn, insn->vectorExtensionPrefix[2])) {
358 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
359 return -1;
360 }
361 if (consume(insn, insn->vectorExtensionPrefix[3])) {
362 LLVM_DEBUG(dbgs() << "Couldn't read fourth byte of EVEX prefix");
363 return -1;
364 }
365
366 if (insn->mode == MODE_64BIT) {
367 // We simulate the REX prefix for simplicity's sake
368 insn->rexPrefix = 0x40 |
369 (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) |
370 (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) |
371 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) |
372 (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
373
374 // We simulate the REX2 prefix for simplicity's sake
375 insn->rex2ExtensionPrefix[1] =
376 (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) |
377 (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) |
378 (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4);
379 }
380
382 dbgs() << format(
383 "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
385 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]));
386 }
387 } else if (byte == 0xc4) {
388 uint8_t byte1;
389 if (peek(insn, byte1)) {
390 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
391 return -1;
392 }
393
394 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
396 else
397 --insn->readerCursor;
398
399 if (insn->vectorExtensionType == TYPE_VEX_3B) {
400 insn->vectorExtensionPrefix[0] = byte;
401 consume(insn, insn->vectorExtensionPrefix[1]);
402 consume(insn, insn->vectorExtensionPrefix[2]);
403
404 // We simulate the REX prefix for simplicity's sake
405
406 if (insn->mode == MODE_64BIT)
407 insn->rexPrefix = 0x40 |
408 (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) |
409 (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) |
410 (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) |
411 (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
412
413 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
414 insn->vectorExtensionPrefix[0],
415 insn->vectorExtensionPrefix[1],
416 insn->vectorExtensionPrefix[2]));
417 }
418 } else if (byte == 0xc5) {
419 uint8_t byte1;
420 if (peek(insn, byte1)) {
421 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
422 return -1;
423 }
424
425 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
427 else
428 --insn->readerCursor;
429
430 if (insn->vectorExtensionType == TYPE_VEX_2B) {
431 insn->vectorExtensionPrefix[0] = byte;
432 consume(insn, insn->vectorExtensionPrefix[1]);
433
434 if (insn->mode == MODE_64BIT)
435 insn->rexPrefix =
436 0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
437
438 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
439 default:
440 break;
441 case VEX_PREFIX_66:
442 insn->hasOpSize = true;
443 break;
444 }
445
446 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx",
447 insn->vectorExtensionPrefix[0],
448 insn->vectorExtensionPrefix[1]));
449 }
450 } else if (byte == 0x8f) {
451 uint8_t byte1;
452 if (peek(insn, byte1)) {
453 LLVM_DEBUG(dbgs() << "Couldn't read second byte of XOP");
454 return -1;
455 }
456
457 if ((byte1 & 0x38) != 0x0) // 0 in these 3 bits is a POP instruction.
459 else
460 --insn->readerCursor;
461
462 if (insn->vectorExtensionType == TYPE_XOP) {
463 insn->vectorExtensionPrefix[0] = byte;
464 consume(insn, insn->vectorExtensionPrefix[1]);
465 consume(insn, insn->vectorExtensionPrefix[2]);
466
467 // We simulate the REX prefix for simplicity's sake
468
469 if (insn->mode == MODE_64BIT)
470 insn->rexPrefix = 0x40 |
471 (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) |
472 (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) |
473 (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) |
474 (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
475
476 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
477 default:
478 break;
479 case VEX_PREFIX_66:
480 insn->hasOpSize = true;
481 break;
482 }
483
484 LLVM_DEBUG(dbgs() << format("Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
485 insn->vectorExtensionPrefix[0],
486 insn->vectorExtensionPrefix[1],
487 insn->vectorExtensionPrefix[2]));
488 }
489 } else if (isREX2(insn, byte)) {
490 uint8_t byte1;
491 if (peek(insn, byte1)) {
492 LLVM_DEBUG(dbgs() << "Couldn't read second byte of REX2");
493 return -1;
494 }
495 insn->rex2ExtensionPrefix[0] = byte;
496 consume(insn, insn->rex2ExtensionPrefix[1]);
497
498 // We simulate the REX prefix for simplicity's sake
499 insn->rexPrefix = 0x40 | (wFromREX2(insn->rex2ExtensionPrefix[1]) << 3) |
500 (rFromREX2(insn->rex2ExtensionPrefix[1]) << 2) |
501 (xFromREX2(insn->rex2ExtensionPrefix[1]) << 1) |
502 (bFromREX2(insn->rex2ExtensionPrefix[1]) << 0);
503 LLVM_DEBUG(dbgs() << format("Found REX2 prefix 0x%hhx 0x%hhx",
504 insn->rex2ExtensionPrefix[0],
505 insn->rex2ExtensionPrefix[1]));
506 } else if (isREX(insn, byte)) {
507 if (peek(insn, nextByte))
508 return -1;
509 insn->rexPrefix = byte;
510 LLVM_DEBUG(dbgs() << format("Found REX prefix 0x%hhx", byte));
511 } else
512 --insn->readerCursor;
513
514 if (insn->mode == MODE_16BIT) {
515 insn->registerSize = (insn->hasOpSize ? 4 : 2);
516 insn->addressSize = (insn->hasAdSize ? 4 : 2);
517 insn->displacementSize = (insn->hasAdSize ? 4 : 2);
518 insn->immediateSize = (insn->hasOpSize ? 4 : 2);
519 } else if (insn->mode == MODE_32BIT) {
520 insn->registerSize = (insn->hasOpSize ? 2 : 4);
521 insn->addressSize = (insn->hasAdSize ? 2 : 4);
522 insn->displacementSize = (insn->hasAdSize ? 2 : 4);
523 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
524 } else if (insn->mode == MODE_64BIT) {
525 insn->displacementSize = 4;
526 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
527 insn->registerSize = 8;
528 insn->addressSize = (insn->hasAdSize ? 4 : 8);
529 insn->immediateSize = 4;
530 insn->hasOpSize = false;
531 } else {
532 insn->registerSize = (insn->hasOpSize ? 2 : 4);
533 insn->addressSize = (insn->hasAdSize ? 4 : 8);
534 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
535 }
536 }
537
538 return 0;
539}
540
541// Consumes the SIB byte to determine addressing information.
542static int readSIB(struct InternalInstruction *insn) {
543 SIBBase sibBaseBase = SIB_BASE_NONE;
544 uint8_t index, base;
545
546 LLVM_DEBUG(dbgs() << "readSIB()");
547 switch (insn->addressSize) {
548 case 2:
549 default:
550 llvm_unreachable("SIB-based addressing doesn't work in 16-bit mode");
551 case 4:
552 insn->sibIndexBase = SIB_INDEX_EAX;
553 sibBaseBase = SIB_BASE_EAX;
554 break;
555 case 8:
556 insn->sibIndexBase = SIB_INDEX_RAX;
557 sibBaseBase = SIB_BASE_RAX;
558 break;
559 }
560
561 if (consume(insn, insn->sib))
562 return -1;
563
564 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3) |
565 (x2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
566
567 if (index == 0x4) {
568 insn->sibIndex = SIB_INDEX_NONE;
569 } else {
570 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
571 }
572
573 insn->sibScale = 1 << scaleFromSIB(insn->sib);
574
575 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3) |
576 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
577
578 switch (base) {
579 case 0x5:
580 case 0xd:
581 switch (modFromModRM(insn->modRM)) {
582 case 0x0:
584 insn->sibBase = SIB_BASE_NONE;
585 break;
586 case 0x1:
588 insn->sibBase = (SIBBase)(sibBaseBase + base);
589 break;
590 case 0x2:
592 insn->sibBase = (SIBBase)(sibBaseBase + base);
593 break;
594 default:
595 llvm_unreachable("Cannot have Mod = 0b11 and a SIB byte");
596 }
597 break;
598 default:
599 insn->sibBase = (SIBBase)(sibBaseBase + base);
600 break;
601 }
602
603 return 0;
604}
605
606static int readDisplacement(struct InternalInstruction *insn) {
607 int8_t d8;
608 int16_t d16;
609 int32_t d32;
610 LLVM_DEBUG(dbgs() << "readDisplacement()");
611
612 insn->displacementOffset = insn->readerCursor - insn->startLocation;
613 switch (insn->eaDisplacement) {
614 case EA_DISP_NONE:
615 break;
616 case EA_DISP_8:
617 if (consume(insn, d8))
618 return -1;
619 insn->displacement = d8;
620 break;
621 case EA_DISP_16:
622 if (consume(insn, d16))
623 return -1;
624 insn->displacement = d16;
625 break;
626 case EA_DISP_32:
627 if (consume(insn, d32))
628 return -1;
629 insn->displacement = d32;
630 break;
631 }
632
633 return 0;
634}
635
636// Consumes all addressing information (ModR/M byte, SIB byte, and displacement.
637static int readModRM(struct InternalInstruction *insn) {
638 uint8_t mod, rm, reg;
639 LLVM_DEBUG(dbgs() << "readModRM()");
640
641 if (insn->consumedModRM)
642 return 0;
643
644 if (consume(insn, insn->modRM))
645 return -1;
646 insn->consumedModRM = true;
647
648 mod = modFromModRM(insn->modRM);
649 rm = rmFromModRM(insn->modRM);
650 reg = regFromModRM(insn->modRM);
651
652 // This goes by insn->registerSize to pick the correct register, which messes
653 // up if we're using (say) XMM or 8-bit register operands. That gets fixed in
654 // fixupReg().
655 switch (insn->registerSize) {
656 case 2:
657 insn->regBase = MODRM_REG_AX;
658 insn->eaRegBase = EA_REG_AX;
659 break;
660 case 4:
661 insn->regBase = MODRM_REG_EAX;
662 insn->eaRegBase = EA_REG_EAX;
663 break;
664 case 8:
665 insn->regBase = MODRM_REG_RAX;
666 insn->eaRegBase = EA_REG_RAX;
667 break;
668 }
669
670 reg |= (rFromREX(insn->rexPrefix) << 3) |
671 (r2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
672 rm |= (bFromREX(insn->rexPrefix) << 3) |
673 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
674
675 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT)
676 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
677
678 insn->reg = (Reg)(insn->regBase + reg);
679
680 switch (insn->addressSize) {
681 case 2: {
682 EABase eaBaseBase = EA_BASE_BX_SI;
683
684 switch (mod) {
685 case 0x0:
686 if (rm == 0x6) {
687 insn->eaBase = EA_BASE_NONE;
689 if (readDisplacement(insn))
690 return -1;
691 } else {
692 insn->eaBase = (EABase)(eaBaseBase + rm);
694 }
695 break;
696 case 0x1:
697 insn->eaBase = (EABase)(eaBaseBase + rm);
699 insn->displacementSize = 1;
700 if (readDisplacement(insn))
701 return -1;
702 break;
703 case 0x2:
704 insn->eaBase = (EABase)(eaBaseBase + rm);
706 if (readDisplacement(insn))
707 return -1;
708 break;
709 case 0x3:
710 insn->eaBase = (EABase)(insn->eaRegBase + rm);
711 if (readDisplacement(insn))
712 return -1;
713 break;
714 }
715 break;
716 }
717 case 4:
718 case 8: {
719 EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
720
721 switch (mod) {
722 case 0x0:
723 insn->eaDisplacement = EA_DISP_NONE; // readSIB may override this
724 // In determining whether RIP-relative mode is used (rm=5),
725 // or whether a SIB byte is present (rm=4),
726 // the extension bits (REX.b and EVEX.x) are ignored.
727 switch (rm & 7) {
728 case 0x4: // SIB byte is present
729 insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64);
730 if (readSIB(insn) || readDisplacement(insn))
731 return -1;
732 break;
733 case 0x5: // RIP-relative
734 insn->eaBase = EA_BASE_NONE;
736 if (readDisplacement(insn))
737 return -1;
738 break;
739 default:
740 insn->eaBase = (EABase)(eaBaseBase + rm);
741 break;
742 }
743 break;
744 case 0x1:
745 insn->displacementSize = 1;
746 [[fallthrough]];
747 case 0x2:
748 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
749 switch (rm & 7) {
750 case 0x4: // SIB byte is present
751 insn->eaBase = EA_BASE_sib;
752 if (readSIB(insn) || readDisplacement(insn))
753 return -1;
754 break;
755 default:
756 insn->eaBase = (EABase)(eaBaseBase + rm);
757 if (readDisplacement(insn))
758 return -1;
759 break;
760 }
761 break;
762 case 0x3:
764 insn->eaBase = (EABase)(insn->eaRegBase + rm);
765 break;
766 }
767 break;
768 }
769 } // switch (insn->addressSize)
770
771 return 0;
772}
773
774#define GENERIC_FIXUP_FUNC(name, base, prefix) \
775 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
776 uint8_t index, uint8_t *valid) { \
777 *valid = 1; \
778 switch (type) { \
779 default: \
780 debug("Unhandled register type"); \
781 *valid = 0; \
782 return 0; \
783 case TYPE_Rv: \
784 return base + index; \
785 case TYPE_R8: \
786 if (insn->rexPrefix && index >= 4 && index <= 7) \
787 return prefix##_SPL + (index - 4); \
788 else \
789 return prefix##_AL + index; \
790 case TYPE_R16: \
791 return prefix##_AX + index; \
792 case TYPE_R32: \
793 return prefix##_EAX + index; \
794 case TYPE_R64: \
795 return prefix##_RAX + index; \
796 case TYPE_ZMM: \
797 return prefix##_ZMM0 + index; \
798 case TYPE_YMM: \
799 return prefix##_YMM0 + index; \
800 case TYPE_XMM: \
801 return prefix##_XMM0 + index; \
802 case TYPE_TMM: \
803 if (index > 7) \
804 *valid = 0; \
805 return prefix##_TMM0 + index; \
806 case TYPE_VK: \
807 index &= 0xf; \
808 if (index > 7) \
809 *valid = 0; \
810 return prefix##_K0 + index; \
811 case TYPE_VK_PAIR: \
812 if (index > 7) \
813 *valid = 0; \
814 return prefix##_K0_K1 + (index / 2); \
815 case TYPE_MM64: \
816 return prefix##_MM0 + (index & 0x7); \
817 case TYPE_SEGMENTREG: \
818 if ((index & 7) > 5) \
819 *valid = 0; \
820 return prefix##_ES + (index & 7); \
821 case TYPE_DEBUGREG: \
822 return prefix##_DR0 + index; \
823 case TYPE_CONTROLREG: \
824 return prefix##_CR0 + index; \
825 case TYPE_MVSIBX: \
826 return prefix##_XMM0 + index; \
827 case TYPE_MVSIBY: \
828 return prefix##_YMM0 + index; \
829 case TYPE_MVSIBZ: \
830 return prefix##_ZMM0 + index; \
831 } \
832 }
833
834// Consult an operand type to determine the meaning of the reg or R/M field. If
835// the operand is an XMM operand, for example, an operand would be XMM0 instead
836// of AX, which readModRM() would otherwise misinterpret it as.
837//
838// @param insn - The instruction containing the operand.
839// @param type - The operand type.
840// @param index - The existing value of the field as reported by readModRM().
841// @param valid - The address of a uint8_t. The target is set to 1 if the
842// field is valid for the register class; 0 if not.
843// @return - The proper value.
844GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
845GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
846
847// Consult an operand specifier to determine which of the fixup*Value functions
848// to use in correcting readModRM()'ss interpretation.
849//
850// @param insn - See fixup*Value().
851// @param op - The operand specifier.
852// @return - 0 if fixup was successful; -1 if the register returned was
853// invalid for its class.
854static int fixupReg(struct InternalInstruction *insn,
855 const struct OperandSpecifier *op) {
856 uint8_t valid;
857 LLVM_DEBUG(dbgs() << "fixupReg()");
858
859 switch ((OperandEncoding)op->encoding) {
860 default:
861 debug("Expected a REG or R/M encoding in fixupReg");
862 return -1;
863 case ENCODING_VVVV:
864 insn->vvvv =
865 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid);
866 if (!valid)
867 return -1;
868 break;
869 case ENCODING_REG:
870 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type,
871 insn->reg - insn->regBase, &valid);
872 if (!valid)
873 return -1;
874 break;
876 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
877 modFromModRM(insn->modRM) == 3) {
878 // EVEX_X can extend the register id to 32 for a non-GPR register that is
879 // encoded in RM.
880 // mode : MODE_64_BIT
881 // Only 8 vector registers are available in 32 bit mode
882 // mod : 3
883 // RM encodes a register
884 switch (op->type) {
885 case TYPE_Rv:
886 case TYPE_R8:
887 case TYPE_R16:
888 case TYPE_R32:
889 case TYPE_R64:
890 break;
891 default:
892 insn->eaBase =
893 (EABase)(insn->eaBase +
894 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4));
895 break;
896 }
897 }
898 [[fallthrough]];
899 case ENCODING_SIB:
900 if (insn->eaBase >= insn->eaRegBase) {
901 insn->eaBase = (EABase)fixupRMValue(
902 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid);
903 if (!valid)
904 return -1;
905 }
906 break;
907 }
908
909 return 0;
910}
911
912// Read the opcode (except the ModR/M byte in the case of extended or escape
913// opcodes).
914static bool readOpcode(struct InternalInstruction *insn) {
915 uint8_t current;
916 LLVM_DEBUG(dbgs() << "readOpcode()");
917
918 insn->opcodeType = ONEBYTE;
919 if (insn->vectorExtensionType == TYPE_EVEX) {
920 switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
921 default:
923 dbgs() << format("Unhandled mmm field for instruction (0x%hhx)",
925 return true;
926 case VEX_LOB_0F:
927 insn->opcodeType = TWOBYTE;
928 return consume(insn, insn->opcode);
929 case VEX_LOB_0F38:
930 insn->opcodeType = THREEBYTE_38;
931 return consume(insn, insn->opcode);
932 case VEX_LOB_0F3A:
933 insn->opcodeType = THREEBYTE_3A;
934 return consume(insn, insn->opcode);
935 case VEX_LOB_MAP4:
936 insn->opcodeType = MAP4;
937 return consume(insn, insn->opcode);
938 case VEX_LOB_MAP5:
939 insn->opcodeType = MAP5;
940 return consume(insn, insn->opcode);
941 case VEX_LOB_MAP6:
942 insn->opcodeType = MAP6;
943 return consume(insn, insn->opcode);
944 }
945 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
946 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
947 default:
949 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
951 return true;
952 case VEX_LOB_0F:
953 insn->opcodeType = TWOBYTE;
954 return consume(insn, insn->opcode);
955 case VEX_LOB_0F38:
956 insn->opcodeType = THREEBYTE_38;
957 return consume(insn, insn->opcode);
958 case VEX_LOB_0F3A:
959 insn->opcodeType = THREEBYTE_3A;
960 return consume(insn, insn->opcode);
961 case VEX_LOB_MAP5:
962 insn->opcodeType = MAP5;
963 return consume(insn, insn->opcode);
964 case VEX_LOB_MAP6:
965 insn->opcodeType = MAP6;
966 return consume(insn, insn->opcode);
967 case VEX_LOB_MAP7:
968 insn->opcodeType = MAP7;
969 return consume(insn, insn->opcode);
970 }
971 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
972 insn->opcodeType = TWOBYTE;
973 return consume(insn, insn->opcode);
974 } else if (insn->vectorExtensionType == TYPE_XOP) {
975 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
976 default:
978 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
980 return true;
981 case XOP_MAP_SELECT_8:
982 insn->opcodeType = XOP8_MAP;
983 return consume(insn, insn->opcode);
984 case XOP_MAP_SELECT_9:
985 insn->opcodeType = XOP9_MAP;
986 return consume(insn, insn->opcode);
987 case XOP_MAP_SELECT_A:
988 insn->opcodeType = XOPA_MAP;
989 return consume(insn, insn->opcode);
990 }
991 } else if (mFromREX2(insn->rex2ExtensionPrefix[1])) {
992 // m bit indicates opcode map 1
993 insn->opcodeType = TWOBYTE;
994 return consume(insn, insn->opcode);
995 }
996
997 if (consume(insn, current))
998 return true;
999
1000 if (current == 0x0f) {
1001 LLVM_DEBUG(
1002 dbgs() << format("Found a two-byte escape prefix (0x%hhx)", current));
1003 if (consume(insn, current))
1004 return true;
1005
1006 if (current == 0x38) {
1007 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
1008 current));
1009 if (consume(insn, current))
1010 return true;
1011
1012 insn->opcodeType = THREEBYTE_38;
1013 } else if (current == 0x3a) {
1014 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
1015 current));
1016 if (consume(insn, current))
1017 return true;
1018
1019 insn->opcodeType = THREEBYTE_3A;
1020 } else if (current == 0x0f) {
1021 LLVM_DEBUG(
1022 dbgs() << format("Found a 3dnow escape prefix (0x%hhx)", current));
1023
1024 // Consume operands before the opcode to comply with the 3DNow encoding
1025 if (readModRM(insn))
1026 return true;
1027
1028 if (consume(insn, current))
1029 return true;
1030
1031 insn->opcodeType = THREEDNOW_MAP;
1032 } else {
1033 LLVM_DEBUG(dbgs() << "Didn't find a three-byte escape prefix");
1034 insn->opcodeType = TWOBYTE;
1035 }
1036 } else if (insn->mandatoryPrefix)
1037 // The opcode with mandatory prefix must start with opcode escape.
1038 // If not it's legacy repeat prefix
1039 insn->mandatoryPrefix = 0;
1040
1041 // At this point we have consumed the full opcode.
1042 // Anything we consume from here on must be unconsumed.
1043 insn->opcode = current;
1044
1045 return false;
1046}
1047
1048// Determine whether equiv is the 16-bit equivalent of orig (32-bit or 64-bit).
1049static bool is16BitEquivalent(const char *orig, const char *equiv) {
1050 for (int i = 0;; i++) {
1051 if (orig[i] == '\0' && equiv[i] == '\0')
1052 return true;
1053 if (orig[i] == '\0' || equiv[i] == '\0')
1054 return false;
1055 if (orig[i] != equiv[i]) {
1056 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
1057 continue;
1058 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
1059 continue;
1060 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
1061 continue;
1062 return false;
1063 }
1064 }
1065}
1066
1067// Determine whether this instruction is a 64-bit instruction.
1068static bool is64Bit(const char *name) {
1069 for (int i = 0;; ++i) {
1070 if (name[i] == '\0')
1071 return false;
1072 if (name[i] == '6' && name[i + 1] == '4')
1073 return true;
1074 }
1075}
1076
1077// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
1078// for extended and escape opcodes, and using a supplied attribute mask.
1079static int getInstructionIDWithAttrMask(uint16_t *instructionID,
1080 struct InternalInstruction *insn,
1081 uint16_t attrMask) {
1082 auto insnCtx = InstructionContext(x86DisassemblerContexts[attrMask]);
1083 const ContextDecision *decision;
1084 switch (insn->opcodeType) {
1085 case ONEBYTE:
1086 decision = &ONEBYTE_SYM;
1087 break;
1088 case TWOBYTE:
1089 decision = &TWOBYTE_SYM;
1090 break;
1091 case THREEBYTE_38:
1092 decision = &THREEBYTE38_SYM;
1093 break;
1094 case THREEBYTE_3A:
1095 decision = &THREEBYTE3A_SYM;
1096 break;
1097 case XOP8_MAP:
1098 decision = &XOP8_MAP_SYM;
1099 break;
1100 case XOP9_MAP:
1101 decision = &XOP9_MAP_SYM;
1102 break;
1103 case XOPA_MAP:
1104 decision = &XOPA_MAP_SYM;
1105 break;
1106 case THREEDNOW_MAP:
1107 decision = &THREEDNOW_MAP_SYM;
1108 break;
1109 case MAP4:
1110 decision = &MAP4_SYM;
1111 break;
1112 case MAP5:
1113 decision = &MAP5_SYM;
1114 break;
1115 case MAP6:
1116 decision = &MAP6_SYM;
1117 break;
1118 case MAP7:
1119 decision = &MAP7_SYM;
1120 break;
1121 }
1122
1123 if (decision->opcodeDecisions[insnCtx]
1124 .modRMDecisions[insn->opcode]
1125 .modrm_type != MODRM_ONEENTRY) {
1126 if (readModRM(insn))
1127 return -1;
1128 *instructionID =
1129 decode(insn->opcodeType, insnCtx, insn->opcode, insn->modRM);
1130 } else {
1131 *instructionID = decode(insn->opcodeType, insnCtx, insn->opcode, 0);
1132 }
1133
1134 return 0;
1135}
1136
1137// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
1138// for extended and escape opcodes. Determines the attributes and context for
1139// the instruction before doing so.
1141 const MCInstrInfo *mii) {
1142 uint16_t attrMask;
1143 uint16_t instructionID;
1144
1145 LLVM_DEBUG(dbgs() << "getID()");
1146
1147 attrMask = ATTR_NONE;
1148
1149 if (insn->mode == MODE_64BIT)
1150 attrMask |= ATTR_64BIT;
1151
1152 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
1153 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
1154
1155 if (insn->vectorExtensionType == TYPE_EVEX) {
1156 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
1157 case VEX_PREFIX_66:
1158 attrMask |= ATTR_OPSIZE;
1159 break;
1160 case VEX_PREFIX_F3:
1161 attrMask |= ATTR_XS;
1162 break;
1163 case VEX_PREFIX_F2:
1164 attrMask |= ATTR_XD;
1165 break;
1166 }
1167
1169 attrMask |= ATTR_EVEXKZ;
1171 attrMask |= ATTR_EVEXB;
1173 attrMask |= ATTR_EVEXK;
1175 attrMask |= ATTR_VEXL;
1177 attrMask |= ATTR_EVEXL2;
1178 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
1179 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
1180 case VEX_PREFIX_66:
1181 attrMask |= ATTR_OPSIZE;
1182 break;
1183 case VEX_PREFIX_F3:
1184 attrMask |= ATTR_XS;
1185 break;
1186 case VEX_PREFIX_F2:
1187 attrMask |= ATTR_XD;
1188 break;
1189 }
1190
1191 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
1192 attrMask |= ATTR_VEXL;
1193 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
1194 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
1195 case VEX_PREFIX_66:
1196 attrMask |= ATTR_OPSIZE;
1197 if (insn->hasAdSize)
1198 attrMask |= ATTR_ADSIZE;
1199 break;
1200 case VEX_PREFIX_F3:
1201 attrMask |= ATTR_XS;
1202 break;
1203 case VEX_PREFIX_F2:
1204 attrMask |= ATTR_XD;
1205 break;
1206 }
1207
1208 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
1209 attrMask |= ATTR_VEXL;
1210 } else if (insn->vectorExtensionType == TYPE_XOP) {
1211 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
1212 case VEX_PREFIX_66:
1213 attrMask |= ATTR_OPSIZE;
1214 break;
1215 case VEX_PREFIX_F3:
1216 attrMask |= ATTR_XS;
1217 break;
1218 case VEX_PREFIX_F2:
1219 attrMask |= ATTR_XD;
1220 break;
1221 }
1222
1223 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
1224 attrMask |= ATTR_VEXL;
1225 } else {
1226 return -1;
1227 }
1228 } else if (!insn->mandatoryPrefix) {
1229 // If we don't have mandatory prefix we should use legacy prefixes here
1230 if (insn->hasOpSize && (insn->mode != MODE_16BIT))
1231 attrMask |= ATTR_OPSIZE;
1232 if (insn->hasAdSize)
1233 attrMask |= ATTR_ADSIZE;
1234 if (insn->opcodeType == ONEBYTE) {
1235 if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90))
1236 // Special support for PAUSE
1237 attrMask |= ATTR_XS;
1238 } else {
1239 if (insn->repeatPrefix == 0xf2)
1240 attrMask |= ATTR_XD;
1241 else if (insn->repeatPrefix == 0xf3)
1242 attrMask |= ATTR_XS;
1243 }
1244 } else {
1245 switch (insn->mandatoryPrefix) {
1246 case 0xf2:
1247 attrMask |= ATTR_XD;
1248 break;
1249 case 0xf3:
1250 attrMask |= ATTR_XS;
1251 break;
1252 case 0x66:
1253 if (insn->mode != MODE_16BIT)
1254 attrMask |= ATTR_OPSIZE;
1255 if (insn->hasAdSize)
1256 attrMask |= ATTR_ADSIZE;
1257 break;
1258 case 0x67:
1259 attrMask |= ATTR_ADSIZE;
1260 break;
1261 }
1262 }
1263
1264 if (insn->rexPrefix & 0x08) {
1265 attrMask |= ATTR_REXW;
1266 attrMask &= ~ATTR_ADSIZE;
1267 }
1268
1269 // Absolute jump and pushp/popp need special handling
1270 if (insn->rex2ExtensionPrefix[0] == 0xd5 && insn->opcodeType == ONEBYTE &&
1271 (insn->opcode == 0xA1 || (insn->opcode & 0xf0) == 0x50))
1272 attrMask |= ATTR_REX2;
1273
1274 if (insn->mode == MODE_16BIT) {
1275 // JCXZ/JECXZ need special handling for 16-bit mode because the meaning
1276 // of the AdSize prefix is inverted w.r.t. 32-bit mode.
1277 if (insn->opcodeType == ONEBYTE && insn->opcode == 0xE3)
1278 attrMask ^= ATTR_ADSIZE;
1279 // If we're in 16-bit mode and this is one of the relative jumps and opsize
1280 // prefix isn't present, we need to force the opsize attribute since the
1281 // prefix is inverted relative to 32-bit mode.
1282 if (!insn->hasOpSize && insn->opcodeType == ONEBYTE &&
1283 (insn->opcode == 0xE8 || insn->opcode == 0xE9))
1284 attrMask |= ATTR_OPSIZE;
1285
1286 if (!insn->hasOpSize && insn->opcodeType == TWOBYTE &&
1287 insn->opcode >= 0x80 && insn->opcode <= 0x8F)
1288 attrMask |= ATTR_OPSIZE;
1289 }
1290
1291
1292 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask))
1293 return -1;
1294
1295 // The following clauses compensate for limitations of the tables.
1296
1297 if (insn->mode != MODE_64BIT &&
1299 // The tables can't distinquish between cases where the W-bit is used to
1300 // select register size and cases where its a required part of the opcode.
1301 if ((insn->vectorExtensionType == TYPE_EVEX &&
1303 (insn->vectorExtensionType == TYPE_VEX_3B &&
1305 (insn->vectorExtensionType == TYPE_XOP &&
1307
1308 uint16_t instructionIDWithREXW;
1309 if (getInstructionIDWithAttrMask(&instructionIDWithREXW, insn,
1310 attrMask | ATTR_REXW)) {
1311 insn->instructionID = instructionID;
1312 insn->spec = &INSTRUCTIONS_SYM[instructionID];
1313 return 0;
1314 }
1315
1316 auto SpecName = mii->getName(instructionIDWithREXW);
1317 // If not a 64-bit instruction. Switch the opcode.
1318 if (!is64Bit(SpecName.data())) {
1319 insn->instructionID = instructionIDWithREXW;
1320 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithREXW];
1321 return 0;
1322 }
1323 }
1324 }
1325
1326 // Absolute moves, umonitor, and movdir64b need special handling.
1327 // -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1328 // inverted w.r.t.
1329 // -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1330 // any position.
1331 if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
1332 (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
1333 (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
1334 // Make sure we observed the prefixes in any position.
1335 if (insn->hasAdSize)
1336 attrMask |= ATTR_ADSIZE;
1337 if (insn->hasOpSize)
1338 attrMask |= ATTR_OPSIZE;
1339
1340 // In 16-bit, invert the attributes.
1341 if (insn->mode == MODE_16BIT) {
1342 attrMask ^= ATTR_ADSIZE;
1343
1344 // The OpSize attribute is only valid with the absolute moves.
1345 if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
1346 attrMask ^= ATTR_OPSIZE;
1347 }
1348
1349 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask))
1350 return -1;
1351
1352 insn->instructionID = instructionID;
1353 insn->spec = &INSTRUCTIONS_SYM[instructionID];
1354 return 0;
1355 }
1356
1357 if ((insn->mode == MODE_16BIT || insn->hasOpSize) &&
1358 !(attrMask & ATTR_OPSIZE)) {
1359 // The instruction tables make no distinction between instructions that
1360 // allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1361 // particular spot (i.e., many MMX operations). In general we're
1362 // conservative, but in the specific case where OpSize is present but not in
1363 // the right place we check if there's a 16-bit operation.
1364 const struct InstructionSpecifier *spec;
1365 uint16_t instructionIDWithOpsize;
1366 llvm::StringRef specName, specWithOpSizeName;
1367
1368 spec = &INSTRUCTIONS_SYM[instructionID];
1369
1370 if (getInstructionIDWithAttrMask(&instructionIDWithOpsize, insn,
1371 attrMask | ATTR_OPSIZE)) {
1372 // ModRM required with OpSize but not present. Give up and return the
1373 // version without OpSize set.
1374 insn->instructionID = instructionID;
1375 insn->spec = spec;
1376 return 0;
1377 }
1378
1379 specName = mii->getName(instructionID);
1380 specWithOpSizeName = mii->getName(instructionIDWithOpsize);
1381
1382 if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1383 (insn->mode == MODE_16BIT) ^ insn->hasOpSize) {
1384 insn->instructionID = instructionIDWithOpsize;
1385 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithOpsize];
1386 } else {
1387 insn->instructionID = instructionID;
1388 insn->spec = spec;
1389 }
1390 return 0;
1391 }
1392
1393 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1394 insn->rexPrefix & 0x01) {
1395 // NOOP shouldn't decode as NOOP if REX.b is set. Instead it should decode
1396 // as XCHG %r8, %eax.
1397 const struct InstructionSpecifier *spec;
1398 uint16_t instructionIDWithNewOpcode;
1399 const struct InstructionSpecifier *specWithNewOpcode;
1400
1401 spec = &INSTRUCTIONS_SYM[instructionID];
1402
1403 // Borrow opcode from one of the other XCHGar opcodes
1404 insn->opcode = 0x91;
1405
1406 if (getInstructionIDWithAttrMask(&instructionIDWithNewOpcode, insn,
1407 attrMask)) {
1408 insn->opcode = 0x90;
1409
1410 insn->instructionID = instructionID;
1411 insn->spec = spec;
1412 return 0;
1413 }
1414
1415 specWithNewOpcode = &INSTRUCTIONS_SYM[instructionIDWithNewOpcode];
1416
1417 // Change back
1418 insn->opcode = 0x90;
1419
1420 insn->instructionID = instructionIDWithNewOpcode;
1421 insn->spec = specWithNewOpcode;
1422
1423 return 0;
1424 }
1425
1426 insn->instructionID = instructionID;
1427 insn->spec = &INSTRUCTIONS_SYM[insn->instructionID];
1428
1429 return 0;
1430}
1431
1432// Read an operand from the opcode field of an instruction and interprets it
1433// appropriately given the operand width. Handles AddRegFrm instructions.
1434//
1435// @param insn - the instruction whose opcode field is to be read.
1436// @param size - The width (in bytes) of the register being specified.
1437// 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1438// RAX.
1439// @return - 0 on success; nonzero otherwise.
1440static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) {
1441 LLVM_DEBUG(dbgs() << "readOpcodeRegister()");
1442
1443 if (size == 0)
1444 size = insn->registerSize;
1445
1446 auto setOpcodeRegister = [&](unsigned base) {
1447 insn->opcodeRegister =
1448 (Reg)(base + ((bFromREX(insn->rexPrefix) << 3) |
1449 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4) |
1450 (insn->opcode & 7)));
1451 };
1452
1453 switch (size) {
1454 case 1:
1455 setOpcodeRegister(MODRM_REG_AL);
1456 if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1457 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1458 insn->opcodeRegister =
1459 (Reg)(MODRM_REG_SPL + (insn->opcodeRegister - MODRM_REG_AL - 4));
1460 }
1461
1462 break;
1463 case 2:
1464 setOpcodeRegister(MODRM_REG_AX);
1465 break;
1466 case 4:
1467 setOpcodeRegister(MODRM_REG_EAX);
1468 break;
1469 case 8:
1470 setOpcodeRegister(MODRM_REG_RAX);
1471 break;
1472 }
1473
1474 return 0;
1475}
1476
1477// Consume an immediate operand from an instruction, given the desired operand
1478// size.
1479//
1480// @param insn - The instruction whose operand is to be read.
1481// @param size - The width (in bytes) of the operand.
1482// @return - 0 if the immediate was successfully consumed; nonzero
1483// otherwise.
1484static int readImmediate(struct InternalInstruction *insn, uint8_t size) {
1485 uint8_t imm8;
1486 uint16_t imm16;
1487 uint32_t imm32;
1488 uint64_t imm64;
1489
1490 LLVM_DEBUG(dbgs() << "readImmediate()");
1491
1492 assert(insn->numImmediatesConsumed < 2 && "Already consumed two immediates");
1493
1494 insn->immediateSize = size;
1495 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1496
1497 switch (size) {
1498 case 1:
1499 if (consume(insn, imm8))
1500 return -1;
1501 insn->immediates[insn->numImmediatesConsumed] = imm8;
1502 break;
1503 case 2:
1504 if (consume(insn, imm16))
1505 return -1;
1506 insn->immediates[insn->numImmediatesConsumed] = imm16;
1507 break;
1508 case 4:
1509 if (consume(insn, imm32))
1510 return -1;
1511 insn->immediates[insn->numImmediatesConsumed] = imm32;
1512 break;
1513 case 8:
1514 if (consume(insn, imm64))
1515 return -1;
1516 insn->immediates[insn->numImmediatesConsumed] = imm64;
1517 break;
1518 default:
1519 llvm_unreachable("invalid size");
1520 }
1521
1522 insn->numImmediatesConsumed++;
1523
1524 return 0;
1525}
1526
1527// Consume vvvv from an instruction if it has a VEX prefix.
1528static int readVVVV(struct InternalInstruction *insn) {
1529 LLVM_DEBUG(dbgs() << "readVVVV()");
1530
1531 int vvvv;
1532 if (insn->vectorExtensionType == TYPE_EVEX)
1533 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1535 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1536 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1537 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1538 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1539 else if (insn->vectorExtensionType == TYPE_XOP)
1540 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1541 else
1542 return -1;
1543
1544 if (insn->mode != MODE_64BIT)
1545 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1546
1547 insn->vvvv = static_cast<Reg>(vvvv);
1548 return 0;
1549}
1550
1551// Read an mask register from the opcode field of an instruction.
1552//
1553// @param insn - The instruction whose opcode field is to be read.
1554// @return - 0 on success; nonzero otherwise.
1555static int readMaskRegister(struct InternalInstruction *insn) {
1556 LLVM_DEBUG(dbgs() << "readMaskRegister()");
1557
1558 if (insn->vectorExtensionType != TYPE_EVEX)
1559 return -1;
1560
1561 insn->writemask =
1562 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1563 return 0;
1564}
1565
1566// Consults the specifier for an instruction and consumes all
1567// operands for that instruction, interpreting them as it goes.
1568static int readOperands(struct InternalInstruction *insn) {
1569 int hasVVVV, needVVVV;
1570 int sawRegImm = 0;
1571
1572 LLVM_DEBUG(dbgs() << "readOperands()");
1573
1574 // If non-zero vvvv specified, make sure one of the operands uses it.
1575 hasVVVV = !readVVVV(insn);
1576 needVVVV = hasVVVV && (insn->vvvv != 0);
1577
1578 for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1579 switch (Op.encoding) {
1580 case ENCODING_NONE:
1581 case ENCODING_SI:
1582 case ENCODING_DI:
1583 break;
1585 // VSIB can use the V2 bit so check only the other bits.
1586 if (needVVVV)
1587 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1588 if (readModRM(insn))
1589 return -1;
1590
1591 // Reject if SIB wasn't used.
1592 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1593 return -1;
1594
1595 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4.
1596 if (insn->sibIndex == SIB_INDEX_NONE)
1597 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4);
1598
1599 // If EVEX.v2 is set this is one of the 16-31 registers.
1600 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
1602 insn->sibIndex = (SIBIndex)(insn->sibIndex + 16);
1603
1604 // Adjust the index register to the correct size.
1605 switch ((OperandType)Op.type) {
1606 default:
1607 debug("Unhandled VSIB index type");
1608 return -1;
1609 case TYPE_MVSIBX:
1610 insn->sibIndex =
1611 (SIBIndex)(SIB_INDEX_XMM0 + (insn->sibIndex - insn->sibIndexBase));
1612 break;
1613 case TYPE_MVSIBY:
1614 insn->sibIndex =
1615 (SIBIndex)(SIB_INDEX_YMM0 + (insn->sibIndex - insn->sibIndexBase));
1616 break;
1617 case TYPE_MVSIBZ:
1618 insn->sibIndex =
1619 (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase));
1620 break;
1621 }
1622
1623 // Apply the AVX512 compressed displacement scaling factor.
1624 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1625 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1626 break;
1627 case ENCODING_SIB:
1628 // Reject if SIB wasn't used.
1629 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1630 return -1;
1631 if (readModRM(insn))
1632 return -1;
1633 if (fixupReg(insn, &Op))
1634 return -1;
1635 break;
1636 case ENCODING_REG:
1638 if (readModRM(insn))
1639 return -1;
1640 if (fixupReg(insn, &Op))
1641 return -1;
1642 // Apply the AVX512 compressed displacement scaling factor.
1643 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1644 insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1645 break;
1646 case ENCODING_IB:
1647 if (sawRegImm) {
1648 // Saw a register immediate so don't read again and instead split the
1649 // previous immediate. FIXME: This is a hack.
1650 insn->immediates[insn->numImmediatesConsumed] =
1651 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1652 ++insn->numImmediatesConsumed;
1653 break;
1654 }
1655 if (readImmediate(insn, 1))
1656 return -1;
1657 if (Op.type == TYPE_XMM || Op.type == TYPE_YMM)
1658 sawRegImm = 1;
1659 break;
1660 case ENCODING_IW:
1661 if (readImmediate(insn, 2))
1662 return -1;
1663 break;
1664 case ENCODING_ID:
1665 if (readImmediate(insn, 4))
1666 return -1;
1667 break;
1668 case ENCODING_IO:
1669 if (readImmediate(insn, 8))
1670 return -1;
1671 break;
1672 case ENCODING_Iv:
1673 if (readImmediate(insn, insn->immediateSize))
1674 return -1;
1675 break;
1676 case ENCODING_Ia:
1677 if (readImmediate(insn, insn->addressSize))
1678 return -1;
1679 break;
1680 case ENCODING_IRC:
1681 insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
1683 break;
1684 case ENCODING_RB:
1685 if (readOpcodeRegister(insn, 1))
1686 return -1;
1687 break;
1688 case ENCODING_RW:
1689 if (readOpcodeRegister(insn, 2))
1690 return -1;
1691 break;
1692 case ENCODING_RD:
1693 if (readOpcodeRegister(insn, 4))
1694 return -1;
1695 break;
1696 case ENCODING_RO:
1697 if (readOpcodeRegister(insn, 8))
1698 return -1;
1699 break;
1700 case ENCODING_Rv:
1701 if (readOpcodeRegister(insn, 0))
1702 return -1;
1703 break;
1704 case ENCODING_CC:
1705 insn->immediates[1] = insn->opcode & 0xf;
1706 break;
1707 case ENCODING_FP:
1708 break;
1709 case ENCODING_VVVV:
1710 needVVVV = 0; // Mark that we have found a VVVV operand.
1711 if (!hasVVVV)
1712 return -1;
1713 if (insn->mode != MODE_64BIT)
1714 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1715 if (fixupReg(insn, &Op))
1716 return -1;
1717 break;
1718 case ENCODING_WRITEMASK:
1719 if (readMaskRegister(insn))
1720 return -1;
1721 break;
1722 case ENCODING_DUP:
1723 break;
1724 default:
1725 LLVM_DEBUG(dbgs() << "Encountered an operand with an unknown encoding.");
1726 return -1;
1727 }
1728 }
1729
1730 // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail
1731 if (needVVVV)
1732 return -1;
1733
1734 return 0;
1735}
1736
1737namespace llvm {
1738
1739// Fill-ins to make the compiler happy. These constants are never actually
1740// assigned; they are just filler to make an automatically-generated switch
1741// statement work.
1742namespace X86 {
1743 enum {
1744 BX_SI = 500,
1745 BX_DI = 501,
1746 BP_SI = 502,
1747 BP_DI = 503,
1748 sib = 504,
1749 sib64 = 505
1751} // namespace X86
1752
1753} // namespace llvm
1754
1755static bool translateInstruction(MCInst &target,
1756 InternalInstruction &source,
1757 const MCDisassembler *Dis);
1758
1759namespace {
1760
1761/// Generic disassembler for all X86 platforms. All each platform class should
1762/// have to do is subclass the constructor, and provide a different
1763/// disassemblerMode value.
1764class X86GenericDisassembler : public MCDisassembler {
1765 std::unique_ptr<const MCInstrInfo> MII;
1766public:
1767 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
1768 std::unique_ptr<const MCInstrInfo> MII);
1769public:
1771 ArrayRef<uint8_t> Bytes, uint64_t Address,
1772 raw_ostream &cStream) const override;
1773
1774private:
1775 DisassemblerMode fMode;
1776};
1777
1778} // namespace
1779
1780X86GenericDisassembler::X86GenericDisassembler(
1781 const MCSubtargetInfo &STI,
1782 MCContext &Ctx,
1783 std::unique_ptr<const MCInstrInfo> MII)
1784 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
1785 const FeatureBitset &FB = STI.getFeatureBits();
1786 if (FB[X86::Is16Bit]) {
1787 fMode = MODE_16BIT;
1788 return;
1789 } else if (FB[X86::Is32Bit]) {
1790 fMode = MODE_32BIT;
1791 return;
1792 } else if (FB[X86::Is64Bit]) {
1793 fMode = MODE_64BIT;
1794 return;
1795 }
1796
1797 llvm_unreachable("Invalid CPU mode");
1798}
1799
1800MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
1802 raw_ostream &CStream) const {
1803 CommentStream = &CStream;
1804
1806 memset(&Insn, 0, sizeof(InternalInstruction));
1807 Insn.bytes = Bytes;
1808 Insn.startLocation = Address;
1809 Insn.readerCursor = Address;
1810 Insn.mode = fMode;
1811
1812 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) ||
1813 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 ||
1814 readOperands(&Insn)) {
1815 Size = Insn.readerCursor - Address;
1816 return Fail;
1817 }
1818
1819 Insn.operands = x86OperandSets[Insn.spec->operands];
1820 Insn.length = Insn.readerCursor - Insn.startLocation;
1821 Size = Insn.length;
1822 if (Size > 15)
1823 LLVM_DEBUG(dbgs() << "Instruction exceeds 15-byte limit");
1824
1825 bool Ret = translateInstruction(Instr, Insn, this);
1826 if (!Ret) {
1827 unsigned Flags = X86::IP_NO_PREFIX;
1828 if (Insn.hasAdSize)
1830 if (!Insn.mandatoryPrefix) {
1831 if (Insn.hasOpSize)
1833 if (Insn.repeatPrefix == 0xf2)
1835 else if (Insn.repeatPrefix == 0xf3 &&
1836 // It should not be 'pause' f3 90
1837 Insn.opcode != 0x90)
1839 if (Insn.hasLockPrefix)
1841 }
1842 Instr.setFlags(Flags);
1843 }
1844 return (!Ret) ? Success : Fail;
1845}
1846
1847//
1848// Private code that translates from struct InternalInstructions to MCInsts.
1849//
1850
1851/// translateRegister - Translates an internal register to the appropriate LLVM
1852/// register, and appends it as an operand to an MCInst.
1853///
1854/// @param mcInst - The MCInst to append to.
1855/// @param reg - The Reg to append.
1856static void translateRegister(MCInst &mcInst, Reg reg) {
1857#define ENTRY(x) X86::x,
1858 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
1859#undef ENTRY
1860
1861 MCPhysReg llvmRegnum = llvmRegnums[reg];
1862 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
1863}
1864
1865static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
1866 0, // SEG_OVERRIDE_NONE
1867 X86::CS,
1868 X86::SS,
1869 X86::DS,
1870 X86::ES,
1871 X86::FS,
1872 X86::GS
1873};
1874
1875/// translateSrcIndex - Appends a source index operand to an MCInst.
1876///
1877/// @param mcInst - The MCInst to append to.
1878/// @param insn - The internal instruction.
1879static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
1880 unsigned baseRegNo;
1881
1882 if (insn.mode == MODE_64BIT)
1883 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI;
1884 else if (insn.mode == MODE_32BIT)
1885 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI;
1886 else {
1887 assert(insn.mode == MODE_16BIT);
1888 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI;
1889 }
1890 MCOperand baseReg = MCOperand::createReg(baseRegNo);
1891 mcInst.addOperand(baseReg);
1892
1893 MCOperand segmentReg;
1895 mcInst.addOperand(segmentReg);
1896 return false;
1897}
1898
1899/// translateDstIndex - Appends a destination index operand to an MCInst.
1900///
1901/// @param mcInst - The MCInst to append to.
1902/// @param insn - The internal instruction.
1903
1904static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
1905 unsigned baseRegNo;
1906
1907 if (insn.mode == MODE_64BIT)
1908 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI;
1909 else if (insn.mode == MODE_32BIT)
1910 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI;
1911 else {
1912 assert(insn.mode == MODE_16BIT);
1913 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI;
1914 }
1915 MCOperand baseReg = MCOperand::createReg(baseRegNo);
1916 mcInst.addOperand(baseReg);
1917 return false;
1918}
1919
1920/// translateImmediate - Appends an immediate operand to an MCInst.
1921///
1922/// @param mcInst - The MCInst to append to.
1923/// @param immediate - The immediate value to append.
1924/// @param operand - The operand, as stored in the descriptor table.
1925/// @param insn - The internal instruction.
1926static void translateImmediate(MCInst &mcInst, uint64_t immediate,
1927 const OperandSpecifier &operand,
1928 InternalInstruction &insn,
1929 const MCDisassembler *Dis) {
1930 // Sign-extend the immediate if necessary.
1931
1932 OperandType type = (OperandType)operand.type;
1933
1934 bool isBranch = false;
1935 uint64_t pcrel = 0;
1936 if (type == TYPE_REL) {
1937 isBranch = true;
1938 pcrel = insn.startLocation + insn.length;
1939 switch (operand.encoding) {
1940 default:
1941 break;
1942 case ENCODING_Iv:
1943 switch (insn.displacementSize) {
1944 default:
1945 break;
1946 case 1:
1947 if(immediate & 0x80)
1948 immediate |= ~(0xffull);
1949 break;
1950 case 2:
1951 if(immediate & 0x8000)
1952 immediate |= ~(0xffffull);
1953 break;
1954 case 4:
1955 if(immediate & 0x80000000)
1956 immediate |= ~(0xffffffffull);
1957 break;
1958 case 8:
1959 break;
1960 }
1961 break;
1962 case ENCODING_IB:
1963 if(immediate & 0x80)
1964 immediate |= ~(0xffull);
1965 break;
1966 case ENCODING_IW:
1967 if(immediate & 0x8000)
1968 immediate |= ~(0xffffull);
1969 break;
1970 case ENCODING_ID:
1971 if(immediate & 0x80000000)
1972 immediate |= ~(0xffffffffull);
1973 break;
1974 }
1975 }
1976 // By default sign-extend all X86 immediates based on their encoding.
1977 else if (type == TYPE_IMM) {
1978 switch (operand.encoding) {
1979 default:
1980 break;
1981 case ENCODING_IB:
1982 if(immediate & 0x80)
1983 immediate |= ~(0xffull);
1984 break;
1985 case ENCODING_IW:
1986 if(immediate & 0x8000)
1987 immediate |= ~(0xffffull);
1988 break;
1989 case ENCODING_ID:
1990 if(immediate & 0x80000000)
1991 immediate |= ~(0xffffffffull);
1992 break;
1993 case ENCODING_IO:
1994 break;
1995 }
1996 }
1997
1998 switch (type) {
1999 case TYPE_XMM:
2000 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
2001 return;
2002 case TYPE_YMM:
2003 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
2004 return;
2005 case TYPE_ZMM:
2006 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
2007 return;
2008 default:
2009 // operand is 64 bits wide. Do nothing.
2010 break;
2011 }
2012
2013 if (!Dis->tryAddingSymbolicOperand(
2014 mcInst, immediate + pcrel, insn.startLocation, isBranch,
2015 insn.immediateOffset, insn.immediateSize, insn.length))
2016 mcInst.addOperand(MCOperand::createImm(immediate));
2017
2018 if (type == TYPE_MOFFS) {
2019 MCOperand segmentReg;
2021 mcInst.addOperand(segmentReg);
2022 }
2023}
2024
2025/// translateRMRegister - Translates a register stored in the R/M field of the
2026/// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
2027/// @param mcInst - The MCInst to append to.
2028/// @param insn - The internal instruction to extract the R/M field
2029/// from.
2030/// @return - 0 on success; -1 otherwise
2031static bool translateRMRegister(MCInst &mcInst,
2032 InternalInstruction &insn) {
2033 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
2034 debug("A R/M register operand may not have a SIB byte");
2035 return true;
2036 }
2037
2038 switch (insn.eaBase) {
2039 default:
2040 debug("Unexpected EA base register");
2041 return true;
2042 case EA_BASE_NONE:
2043 debug("EA_BASE_NONE for ModR/M base");
2044 return true;
2045#define ENTRY(x) case EA_BASE_##x:
2047#undef ENTRY
2048 debug("A R/M register operand may not have a base; "
2049 "the operand must be a register.");
2050 return true;
2051#define ENTRY(x) \
2052 case EA_REG_##x: \
2053 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2054 ALL_REGS
2055#undef ENTRY
2056 }
2057
2058 return false;
2059}
2060
2061/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
2062/// fields of an internal instruction (and possibly its SIB byte) to a memory
2063/// operand in LLVM's format, and appends it to an MCInst.
2064///
2065/// @param mcInst - The MCInst to append to.
2066/// @param insn - The instruction to extract Mod, R/M, and SIB fields
2067/// from.
2068/// @param ForceSIB - The instruction must use SIB.
2069/// @return - 0 on success; nonzero otherwise
2071 const MCDisassembler *Dis,
2072 bool ForceSIB = false) {
2073 // Addresses in an MCInst are represented as five operands:
2074 // 1. basereg (register) The R/M base, or (if there is a SIB) the
2075 // SIB base
2076 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
2077 // scale amount
2078 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
2079 // the index (which is multiplied by the
2080 // scale amount)
2081 // 4. displacement (immediate) 0, or the displacement if there is one
2082 // 5. segmentreg (register) x86_registerNONE for now, but could be set
2083 // if we have segment overrides
2084
2085 MCOperand baseReg;
2086 MCOperand scaleAmount;
2087 MCOperand indexReg;
2088 MCOperand displacement;
2089 MCOperand segmentReg;
2090 uint64_t pcrel = 0;
2091
2092 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
2093 if (insn.sibBase != SIB_BASE_NONE) {
2094 switch (insn.sibBase) {
2095 default:
2096 debug("Unexpected sibBase");
2097 return true;
2098#define ENTRY(x) \
2099 case SIB_BASE_##x: \
2100 baseReg = MCOperand::createReg(X86::x); break;
2102#undef ENTRY
2103 }
2104 } else {
2105 baseReg = MCOperand::createReg(X86::NoRegister);
2106 }
2107
2108 if (insn.sibIndex != SIB_INDEX_NONE) {
2109 switch (insn.sibIndex) {
2110 default:
2111 debug("Unexpected sibIndex");
2112 return true;
2113#define ENTRY(x) \
2114 case SIB_INDEX_##x: \
2115 indexReg = MCOperand::createReg(X86::x); break;
2118 REGS_XMM
2119 REGS_YMM
2120 REGS_ZMM
2121#undef ENTRY
2122 }
2123 } else {
2124 // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present,
2125 // but no index is used and modrm alone should have been enough.
2126 // -No base register in 32-bit mode. In 64-bit mode this is used to
2127 // avoid rip-relative addressing.
2128 // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
2129 // base always requires a SIB byte.
2130 // -A scale other than 1 is used.
2131 if (!ForceSIB &&
2132 (insn.sibScale != 1 ||
2133 (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
2134 (insn.sibBase != SIB_BASE_NONE &&
2135 insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
2136 insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) {
2137 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
2138 X86::RIZ);
2139 } else
2140 indexReg = MCOperand::createReg(X86::NoRegister);
2141 }
2142
2143 scaleAmount = MCOperand::createImm(insn.sibScale);
2144 } else {
2145 switch (insn.eaBase) {
2146 case EA_BASE_NONE:
2147 if (insn.eaDisplacement == EA_DISP_NONE) {
2148 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
2149 return true;
2150 }
2151 if (insn.mode == MODE_64BIT){
2152 pcrel = insn.startLocation + insn.length;
2154 insn.startLocation +
2155 insn.displacementOffset);
2156 // Section 2.2.1.6
2157 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP :
2158 X86::RIP);
2159 }
2160 else
2161 baseReg = MCOperand::createReg(X86::NoRegister);
2162
2163 indexReg = MCOperand::createReg(X86::NoRegister);
2164 break;
2165 case EA_BASE_BX_SI:
2166 baseReg = MCOperand::createReg(X86::BX);
2167 indexReg = MCOperand::createReg(X86::SI);
2168 break;
2169 case EA_BASE_BX_DI:
2170 baseReg = MCOperand::createReg(X86::BX);
2171 indexReg = MCOperand::createReg(X86::DI);
2172 break;
2173 case EA_BASE_BP_SI:
2174 baseReg = MCOperand::createReg(X86::BP);
2175 indexReg = MCOperand::createReg(X86::SI);
2176 break;
2177 case EA_BASE_BP_DI:
2178 baseReg = MCOperand::createReg(X86::BP);
2179 indexReg = MCOperand::createReg(X86::DI);
2180 break;
2181 default:
2182 indexReg = MCOperand::createReg(X86::NoRegister);
2183 switch (insn.eaBase) {
2184 default:
2185 debug("Unexpected eaBase");
2186 return true;
2187 // Here, we will use the fill-ins defined above. However,
2188 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
2189 // sib and sib64 were handled in the top-level if, so they're only
2190 // placeholders to keep the compiler happy.
2191#define ENTRY(x) \
2192 case EA_BASE_##x: \
2193 baseReg = MCOperand::createReg(X86::x); break;
2195#undef ENTRY
2196#define ENTRY(x) case EA_REG_##x:
2197 ALL_REGS
2198#undef ENTRY
2199 debug("A R/M memory operand may not be a register; "
2200 "the base field must be a base.");
2201 return true;
2202 }
2203 }
2204
2205 scaleAmount = MCOperand::createImm(1);
2206 }
2207
2208 displacement = MCOperand::createImm(insn.displacement);
2209
2211
2212 mcInst.addOperand(baseReg);
2213 mcInst.addOperand(scaleAmount);
2214 mcInst.addOperand(indexReg);
2215
2216 const uint8_t dispSize =
2217 (insn.eaDisplacement == EA_DISP_NONE) ? 0 : insn.displacementSize;
2218
2220 mcInst, insn.displacement + pcrel, insn.startLocation, false,
2221 insn.displacementOffset, dispSize, insn.length))
2222 mcInst.addOperand(displacement);
2223 mcInst.addOperand(segmentReg);
2224 return false;
2225}
2226
2227/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
2228/// byte of an instruction to LLVM form, and appends it to an MCInst.
2229///
2230/// @param mcInst - The MCInst to append to.
2231/// @param operand - The operand, as stored in the descriptor table.
2232/// @param insn - The instruction to extract Mod, R/M, and SIB fields
2233/// from.
2234/// @return - 0 on success; nonzero otherwise
2235static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
2236 InternalInstruction &insn, const MCDisassembler *Dis) {
2237 switch (operand.type) {
2238 default:
2239 debug("Unexpected type for a R/M operand");
2240 return true;
2241 case TYPE_R8:
2242 case TYPE_R16:
2243 case TYPE_R32:
2244 case TYPE_R64:
2245 case TYPE_Rv:
2246 case TYPE_MM64:
2247 case TYPE_XMM:
2248 case TYPE_YMM:
2249 case TYPE_ZMM:
2250 case TYPE_TMM:
2251 case TYPE_VK_PAIR:
2252 case TYPE_VK:
2253 case TYPE_DEBUGREG:
2254 case TYPE_CONTROLREG:
2255 case TYPE_BNDR:
2256 return translateRMRegister(mcInst, insn);
2257 case TYPE_M:
2258 case TYPE_MVSIBX:
2259 case TYPE_MVSIBY:
2260 case TYPE_MVSIBZ:
2261 return translateRMMemory(mcInst, insn, Dis);
2262 case TYPE_MSIB:
2263 return translateRMMemory(mcInst, insn, Dis, true);
2264 }
2265}
2266
2267/// translateFPRegister - Translates a stack position on the FPU stack to its
2268/// LLVM form, and appends it to an MCInst.
2269///
2270/// @param mcInst - The MCInst to append to.
2271/// @param stackPos - The stack position to translate.
2272static void translateFPRegister(MCInst &mcInst,
2273 uint8_t stackPos) {
2274 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
2275}
2276
2277/// translateMaskRegister - Translates a 3-bit mask register number to
2278/// LLVM form, and appends it to an MCInst.
2279///
2280/// @param mcInst - The MCInst to append to.
2281/// @param maskRegNum - Number of mask register from 0 to 7.
2282/// @return - false on success; true otherwise.
2283static bool translateMaskRegister(MCInst &mcInst,
2284 uint8_t maskRegNum) {
2285 if (maskRegNum >= 8) {
2286 debug("Invalid mask register number");
2287 return true;
2288 }
2289
2290 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
2291 return false;
2292}
2293
2294/// translateOperand - Translates an operand stored in an internal instruction
2295/// to LLVM's format and appends it to an MCInst.
2296///
2297/// @param mcInst - The MCInst to append to.
2298/// @param operand - The operand, as stored in the descriptor table.
2299/// @param insn - The internal instruction.
2300/// @return - false on success; true otherwise.
2301static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
2302 InternalInstruction &insn,
2303 const MCDisassembler *Dis) {
2304 switch (operand.encoding) {
2305 default:
2306 debug("Unhandled operand encoding during translation");
2307 return true;
2308 case ENCODING_REG:
2309 translateRegister(mcInst, insn.reg);
2310 return false;
2311 case ENCODING_WRITEMASK:
2312 return translateMaskRegister(mcInst, insn.writemask);
2313 case ENCODING_SIB:
2316 return translateRM(mcInst, operand, insn, Dis);
2317 case ENCODING_IB:
2318 case ENCODING_IW:
2319 case ENCODING_ID:
2320 case ENCODING_IO:
2321 case ENCODING_Iv:
2322 case ENCODING_Ia:
2323 translateImmediate(mcInst,
2325 operand,
2326 insn,
2327 Dis);
2328 return false;
2329 case ENCODING_IRC:
2330 mcInst.addOperand(MCOperand::createImm(insn.RC));
2331 return false;
2332 case ENCODING_SI:
2333 return translateSrcIndex(mcInst, insn);
2334 case ENCODING_DI:
2335 return translateDstIndex(mcInst, insn);
2336 case ENCODING_RB:
2337 case ENCODING_RW:
2338 case ENCODING_RD:
2339 case ENCODING_RO:
2340 case ENCODING_Rv:
2341 translateRegister(mcInst, insn.opcodeRegister);
2342 return false;
2343 case ENCODING_CC:
2345 return false;
2346 case ENCODING_FP:
2347 translateFPRegister(mcInst, insn.modRM & 7);
2348 return false;
2349 case ENCODING_VVVV:
2350 translateRegister(mcInst, insn.vvvv);
2351 return false;
2352 case ENCODING_DUP:
2353 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
2354 insn, Dis);
2355 }
2356}
2357
2358/// translateInstruction - Translates an internal instruction and all its
2359/// operands to an MCInst.
2360///
2361/// @param mcInst - The MCInst to populate with the instruction's data.
2362/// @param insn - The internal instruction.
2363/// @return - false on success; true otherwise.
2364static bool translateInstruction(MCInst &mcInst,
2365 InternalInstruction &insn,
2366 const MCDisassembler *Dis) {
2367 if (!insn.spec) {
2368 debug("Instruction has no specification");
2369 return true;
2370 }
2371
2372 mcInst.clear();
2373 mcInst.setOpcode(insn.instructionID);
2374 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
2375 // prefix bytes should be disassembled as xrelease and xacquire then set the
2376 // opcode to those instead of the rep and repne opcodes.
2377 if (insn.xAcquireRelease) {
2378 if(mcInst.getOpcode() == X86::REP_PREFIX)
2379 mcInst.setOpcode(X86::XRELEASE_PREFIX);
2380 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
2381 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
2382 }
2383
2384 insn.numImmediatesTranslated = 0;
2385
2386 for (const auto &Op : insn.operands) {
2387 if (Op.encoding != ENCODING_NONE) {
2388 if (translateOperand(mcInst, Op, insn, Dis)) {
2389 return true;
2390 }
2391 }
2392 }
2393
2394 return false;
2395}
2396
2398 const MCSubtargetInfo &STI,
2399 MCContext &Ctx) {
2400 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
2401 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
2402}
2403
2405 // Register the disassembler.
2410}
#define Fail
#define Success
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
aarch64 promote const
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
#define op(i)
if(VerifyEach)
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const char * name
Definition: SMEABIPass.cpp:48
static uint8_t readOpcode(WasmObjectFile::ReadContext &Ctx)
static int nextByte(ArrayRef< uint8_t > Bytes, uint64_t &Size)
static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
#define TWOBYTE_SYM
#define MAP4_SYM
#define CASE_ENCODING_VSIB
#define XOP9_MAP_SYM
#define CASE_ENCODING_RM
#define THREEDNOW_MAP_SYM
#define INSTRUCTIONS_SYM
#define THREEBYTE3A_SYM
#define XOP8_MAP_SYM
#define THREEBYTE38_SYM
#define XOPA_MAP_SYM
#define MAP6_SYM
#define MAP7_SYM
#define ONEBYTE_SYM
#define MAP5_SYM
#define rFromEVEX2of4(evex)
#define lFromEVEX4of4(evex)
#define l2FromEVEX4of4(evex)
#define rFromVEX2of3(vex)
#define zFromEVEX4of4(evex)
#define wFromREX2(rex2)
#define rFromREX(rex)
#define bFromXOP2of3(xop)
#define xFromVEX2of3(vex)
#define mmmmmFromVEX2of3(vex)
#define rmFromModRM(modRM)
#define bFromREX2(rex2)
#define baseFromSIB(sib)
#define bFromEVEX4of4(evex)
#define rFromVEX2of2(vex)
#define ppFromEVEX3of4(evex)
#define v2FromEVEX4of4(evex)
#define modFromModRM(modRM)
#define rFromXOP2of3(xop)
#define wFromREX(rex)
#define lFromXOP3of3(xop)
#define EA_BASES_64BIT
#define lFromVEX2of2(vex)
#define REGS_YMM
#define x2FromREX2(rex2)
#define scaleFromSIB(sib)
#define REGS_XMM
#define rFromREX2(rex2)
#define regFromModRM(modRM)
#define b2FromEVEX2of4(evex)
#define b2FromREX2(rex2)
#define vvvvFromVEX2of2(vex)
#define ALL_REGS
#define ppFromXOP3of3(xop)
#define ALL_SIB_BASES
#define vvvvFromVEX3of3(vex)
#define r2FromEVEX2of4(evex)
#define xFromREX2(rex2)
#define EA_BASES_32BIT
#define x2FromEVEX3of4(evex)
#define xFromXOP2of3(xop)
#define wFromEVEX3of4(evex)
#define bFromVEX2of3(vex)
#define wFromVEX3of3(vex)
#define mmmmmFromXOP2of3(xop)
#define aaaFromEVEX4of4(evex)
#define lFromVEX3of3(vex)
#define mmmFromEVEX2of4(evex)
#define ppFromVEX3of3(vex)
#define bFromEVEX2of4(evex)
#define xFromEVEX2of4(evex)
#define REGS_ZMM
#define ppFromVEX2of2(vex)
#define indexFromSIB(sib)
#define ALL_EA_BASES
#define mFromREX2(rex2)
#define vvvvFromXOP3of3(xop)
#define wFromXOP3of3(xop)
#define r2FromREX2(rex2)
#define vvvvFromEVEX3of4(evex)
#define xFromREX(rex)
#define bFromREX(rex)
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register,...
static bool isREX2(struct InternalInstruction *insn, uint8_t prefix)
static int getInstructionID(struct InternalInstruction *insn, const MCInstrInfo *mii)
static bool readOpcode(struct InternalInstruction *insn)
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Disassembler()
static int readOperands(struct InternalInstruction *insn)
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form,...
static bool is64Bit(const char *name)
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
static int readImmediate(struct InternalInstruction *insn, uint8_t size)
static int getInstructionIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction *insn, uint16_t attrMask)
static int readSIB(struct InternalInstruction *insn)
static bool isREX(struct InternalInstruction *insn, uint8_t prefix)
static int readVVVV(struct InternalInstruction *insn)
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
#define GENERIC_FIXUP_FUNC(name, base, prefix)
static int readMaskRegister(struct InternalInstruction *insn)
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM)
static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size)
static int readDisplacement(struct InternalInstruction *insn)
static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op)
#define debug(s)
static int readModRM(struct InternalInstruction *insn)
static bool is16BitEquivalent(const char *orig, const char *equiv)
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis, bool ForceSIB=false)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
static int readPrefixes(struct InternalInstruction *insn)
static bool peek(struct InternalInstruction *insn, uint8_t &byte)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
This class represents an Operation in the Expression.
Container class for subtarget features.
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
void clear()
Definition: MCInst.h:215
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:70
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86
Windows x64, Windows Itanium (IA-64)
EABase
All possible values of the base field for effective-address computations, a.k.a.
Reg
All possible values of the reg field in the ModR/M byte.
DisassemblerMode
Decoding mode for the Intel disassembler.
SIBBase
All possible values of the SIB base field.
SIBIndex
All possible values of the SIB index field.
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
@ IP_HAS_OP_SIZE
Definition: X86BaseInfo.h:53
@ IP_NO_PREFIX
Definition: X86BaseInfo.h:52
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:55
NodeAddr< InstrNode * > Instr
Definition: RDFGraph.h:389
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1684
Target & getTheX86_32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1853
Target & getTheX86_64Target()
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
OpcodeDecision opcodeDecisions[IC_max]
uint16_t instructionIDs
ModRMDecision modRMDecisions[256]
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
The specification for how to extract and interpret a full instruction and its operands.
The x86 internal instruction, which is produced by the decoder.
The specification for how to extract and interpret one operand.