LLVM  14.0.0git
Public Member Functions | List of all members
llvm::AMDGPUPassConfig Class Reference

#include "Target/AMDGPU/AMDGPUTargetMachine.h"

Inheritance diagram for llvm::AMDGPUPassConfig:
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Collaboration diagram for llvm::AMDGPUPassConfig:
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Public Member Functions

 AMDGPUPassConfig (LLVMTargetMachine &TM, PassManagerBase &PM)
 
AMDGPUTargetMachinegetAMDGPUTargetMachine () const
 
ScheduleDAGInstrscreateMachineScheduler (MachineSchedContext *C) const override
 Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level. More...
 
void addEarlyCSEOrGVNPass ()
 
void addStraightLineScalarOptimizationPasses ()
 
void addIRPasses () override
 Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization. More...
 
void addCodeGenPrepare () override
 Add pass to prepare the LLVM IR for code generation. More...
 
bool addPreISel () override
 Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes. More...
 
bool addInstSelector () override
 addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions. More...
 
bool addGCPasses () override
 addGCPasses - Add late codegen passes that analyze code for garbage collection. More...
 
std::unique_ptr< CSEConfigBasegetCSEConfig () const override
 Returns the CSEConfig object to use for the current optimization level. More...
 
bool isPassEnabled (const cl::opt< bool > &Opt, CodeGenOpt::Level Level=CodeGenOpt::Default) const
 Check if a pass is enabled given Opt option. More...
 
- Public Member Functions inherited from llvm::TargetPassConfig
 TargetPassConfig (LLVMTargetMachine &TM, PassManagerBase &pm)
 
 TargetPassConfig ()
 
 ~TargetPassConfig () override
 
template<typename TMC >
TMC & getTM () const
 Get the right type of TargetMachine for this target. More...
 
void setInitialized ()
 
CodeGenOpt::Level getOptLevel () const
 
void setDisableVerify (bool Disable)
 
bool getEnableTailMerge () const
 
void setEnableTailMerge (bool Enable)
 
bool requiresCodeGenSCCOrder () const
 
void setRequiresCodeGenSCCOrder (bool Enable=true)
 
void substitutePass (AnalysisID StandardID, IdentifyingPassPtr TargetID)
 Allow the target to override a specific pass without overriding the pass pipeline. More...
 
void insertPass (AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
 Insert InsertedPassID pass after TargetPassID pass. More...
 
void enablePass (AnalysisID PassID)
 Allow the target to enable a specific standard pass by default. More...
 
void disablePass (AnalysisID PassID)
 Allow the target to disable a specific standard pass by default. More...
 
IdentifyingPassPtr getPassSubstitution (AnalysisID StandardID) const
 Return the pass substituted for StandardID by the target. More...
 
bool isPassSubstitutedOrOverridden (AnalysisID ID) const
 Return true if the pass has been substituted by the target or overridden on the command line. More...
 
bool getOptimizeRegAlloc () const
 Return true if the optimized regalloc pipeline is enabled. More...
 
bool usingDefaultRegAlloc () const
 Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'. More...
 
bool addISelPasses ()
 High level function that adds all passes necessary to go from llvm IR representation to the MI representation. More...
 
void addPassesToHandleExceptions ()
 Add passes to lower exception handling for the code generator. More...
 
virtual void addISelPrepare ()
 Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection. More...
 
virtual bool addIRTranslator ()
 This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes. More...
 
virtual void addPreLegalizeMachineIR ()
 This method may be implemented by targets that want to run passes immediately before legalization. More...
 
virtual bool addLegalizeMachineIR ()
 This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target. More...
 
virtual void addPreRegBankSelect ()
 This method may be implemented by targets that want to run passes immediately before the register bank selection. More...
 
virtual bool addRegBankSelect ()
 This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks. More...
 
virtual void addPreGlobalInstructionSelect ()
 This method may be implemented by targets that want to run passes immediately before the (global) instruction selection. More...
 
virtual bool addGlobalInstructionSelect ()
 This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes. More...
 
virtual void addMachinePasses ()
 Add the complete, standard set of LLVM CodeGen passes. More...
 
virtual ScheduleDAGInstrscreatePostMachineScheduler (MachineSchedContext *C) const
 Similar to createMachineScheduler but used when postRA machine scheduling is enabled. More...
 
void printAndVerify (const std::string &Banner)
 printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled. More...
 
void addPrintPass (const std::string &Banner)
 Add a pass to print the machine function if printing is enabled. More...
 
void addVerifyPass (const std::string &Banner)
 Add a pass to perform basic verification of the machine function if verification is enabled. More...
 
void addDebugifyPass ()
 Add a pass to add synthesized debug info to the MIR. More...
 
void addStripDebugPass ()
 Add a pass to remove debug info from the MIR. More...
 
void addCheckDebugPass ()
 Add a pass to check synthesized debug info for MIR. More...
 
void addMachinePrePasses (bool AllowDebugify=true)
 Add standard passes before a pass that's about to be added. More...
 
void addMachinePostPasses (const std::string &Banner)
 Add standard passes after a pass that has just been added. More...
 
bool isGlobalISelAbortEnabled () const
 Check whether or not GlobalISel should abort on error. More...
 
virtual bool reportDiagnosticWhenGlobalISelFallback () const
 Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path. More...
 
virtual bool isGISelCSEEnabled () const
 Check whether continuous CSE should be enabled in GISel passes. More...
 
- Public Member Functions inherited from llvm::ImmutablePass
 ImmutablePass (char &pid)
 
 ~ImmutablePass () override
 
virtual void initializePass ()
 initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require. More...
 
ImmutablePassgetAsImmutablePass () override
 
bool runOnModule (Module &) override
 ImmutablePasses are never run. More...
 
- Public Member Functions inherited from llvm::ModulePass
 ModulePass (char &pid)
 
 ~ModulePass () override
 
PasscreatePrinterPass (raw_ostream &OS, const std::string &Banner) const override
 createPrinterPass - Get a module printer pass. More...
 
void assignPassManager (PMStack &PMS, PassManagerType T) override
 Find appropriate Module Pass Manager in the PM Stack and add self into that manager. More...
 
PassManagerType getPotentialPassManagerType () const override
 Return what kind of Pass Manager can manage this pass. More...
 
- Public Member Functions inherited from llvm::Pass
 Pass (PassKind K, char &pid)
 
 Pass (const Pass &)=delete
 
Passoperator= (const Pass &)=delete
 
virtual ~Pass ()
 
PassKind getPassKind () const
 
virtual StringRef getPassName () const
 getPassName - Return a nice clean name for a pass. More...
 
AnalysisID getPassID () const
 getPassID - Return the PassID number that corresponds to this pass. More...
 
virtual bool doInitialization (Module &)
 doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run. More...
 
virtual bool doFinalization (Module &)
 doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run. More...
 
virtual void print (raw_ostream &OS, const Module *M) const
 print - Print out the internal state of the pass. More...
 
void dump () const
 
virtual void preparePassManager (PMStack &)
 Check if available pass managers are suitable for this pass or not. More...
 
void setResolver (AnalysisResolver *AR)
 
AnalysisResolvergetResolver () const
 
virtual void getAnalysisUsage (AnalysisUsage &) const
 getAnalysisUsage - This function should be overriden by passes that need analysis information to do their job. More...
 
virtual void releaseMemory ()
 releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed. More...
 
virtual void * getAdjustedAnalysisPointer (AnalysisID ID)
 getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance. More...
 
virtual PMDataManagergetAsPMDataManager ()
 
virtual void verifyAnalysis () const
 verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information. More...
 
virtual void dumpPassStructure (unsigned Offset=0)
 
template<typename AnalysisType >
AnalysisType * getAnalysisIfAvailable () const
 getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it. More...
 
bool mustPreserveAnalysisID (char &AID) const
 mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID. More...
 
template<typename AnalysisType >
AnalysisType & getAnalysis () const
 getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More...
 
template<typename AnalysisType >
AnalysisType & getAnalysis (Function &F, bool *Changed=nullptr)
 getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More...
 
template<typename AnalysisType >
AnalysisType & getAnalysisID (AnalysisID PI) const
 
template<typename AnalysisType >
AnalysisType & getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr)
 

Additional Inherited Members

- Static Public Member Functions inherited from llvm::TargetPassConfig
static bool hasLimitedCodeGenPipeline ()
 Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set. More...
 
static bool willCompleteCodeGenPipeline ()
 Returns true if none of the -stop-before and -stop-after options is set. More...
 
static std::string getLimitedCodeGenPipelineReason (const char *Separator="/")
 If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options, separated by Separator that caused this pipeline to be limited. More...
 
- Static Public Member Functions inherited from llvm::Pass
static const PassInfolookupPassInfo (const void *TI)
 
static const PassInfolookupPassInfo (StringRef Arg)
 
static PasscreatePass (AnalysisID ID)
 
- Static Public Attributes inherited from llvm::TargetPassConfig
static char ID
 
- Protected Member Functions inherited from llvm::TargetPassConfig
bool addCoreISelPasses ()
 Add the actual instruction selection passes. More...
 
void setOpt (bool &Opt, bool Val)
 
virtual void addMachineSSAOptimization ()
 addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form. More...
 
virtual bool addILPOpts ()
 Add passes that optimize instruction level parallelism for out-of-order targets. More...
 
virtual void addPreRegAlloc ()
 This method may be implemented by targets that want to run passes immediately before register allocation. More...
 
virtual FunctionPasscreateTargetRegisterAllocator (bool Optimized)
 createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level. More...
 
virtual void addFastRegAlloc ()
 addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation. More...
 
virtual void addOptimizedRegAlloc ()
 addOptimizedRegAlloc - Add passes related to register allocation. More...
 
virtual bool addPreRewrite ()
 addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers. More...
 
virtual bool addPostFastRegAllocRewrite ()
 addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast register allocation is complete. More...
 
virtual void addPostRewrite ()
 Add passes to be run immediately after virtual registers are rewritten to physical registers. More...
 
virtual void addPostRegAlloc ()
 This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion. More...
 
virtual void addMachineLateOptimization ()
 Add passes that optimize machine instructions after register allocation. More...
 
virtual void addPreSched2 ()
 This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass. More...
 
virtual void addBlockPlacement ()
 Add standard basic block placement passes. More...
 
virtual void addPreEmitPass ()
 This pass may be implemented by targets that want to run passes immediately before machine code is emitted. More...
 
virtual void addPreEmitPass2 ()
 Targets may add passes immediately before machine code is emitted in this callback. More...
 
AnalysisID addPass (AnalysisID PassID)
 Utilities for targets to add passes to the pass manager. More...
 
void addPass (Pass *P)
 Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options. More...
 
virtual FunctionPasscreateRegAllocPass (bool Optimized)
 addMachinePasses helper to create the target-selected or overriden regalloc pass. More...
 
virtual bool addRegAssignAndRewriteFast ()
 Add core register allocator passes which do the actual register assignment and rewriting. More...
 
virtual bool addRegAssignAndRewriteOptimized ()
 
- Protected Member Functions inherited from llvm::ModulePass
bool skipModule (Module &M) const
 Optional passes call this function to check whether the pass should be skipped. More...
 
- Protected Attributes inherited from llvm::TargetPassConfig
LLVMTargetMachineTM
 
PassConfigImplImpl = nullptr
 
bool Initialized = false
 
bool DisableVerify = false
 
bool EnableTailMerge = true
 Default setting for -enable-tail-merge on this target. More...
 
bool RequireCodeGenSCCOrder = false
 Require processing of functions such that callees are generated before callers. More...
 

Detailed Description

Definition at line 109 of file AMDGPUTargetMachine.h.

Constructor & Destructor Documentation

◆ AMDGPUPassConfig()

AMDGPUPassConfig::AMDGPUPassConfig ( LLVMTargetMachine TM,
PassManagerBase PM 
)

Member Function Documentation

◆ addCodeGenPrepare()

void AMDGPUPassConfig::addCodeGenPrepare ( )
overridevirtual

◆ addEarlyCSEOrGVNPass()

void AMDGPUPassConfig::addEarlyCSEOrGVNPass ( )

◆ addGCPasses()

bool AMDGPUPassConfig::addGCPasses ( )
overridevirtual

addGCPasses - Add late codegen passes that analyze code for garbage collection.

Add standard GC passes.

This should return true if GC info should be printed after these passes.

Reimplemented from llvm::TargetPassConfig.

Definition at line 1083 of file AMDGPUTargetMachine.cpp.

◆ addInstSelector()

bool AMDGPUPassConfig::addInstSelector ( )
overridevirtual

addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions.

Reimplemented from llvm::TargetPassConfig.

Reimplemented in R600PassConfig.

Definition at line 1078 of file AMDGPUTargetMachine.cpp.

References llvm::TargetPassConfig::addPass(), llvm::createAMDGPUISelDag(), getAMDGPUTargetMachine(), and llvm::TargetPassConfig::getOptLevel().

◆ addIRPasses()

void AMDGPUPassConfig::addIRPasses ( )
overridevirtual

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.

Reimplemented from llvm::TargetPassConfig.

Definition at line 953 of file AMDGPUTargetMachine.cpp.

References llvm::AAResults::addAAResult(), addEarlyCSEOrGVNPass(), llvm::TargetPassConfig::addIRPasses(), llvm::TargetPassConfig::addPass(), addStraightLineScalarOptimizationPasses(), llvm::Triple::amdgcn, llvm::createAlwaysInlinerLegacyPass(), llvm::createAMDGPUAAWrapperPass(), llvm::createAMDGPUAlwaysInlinePass(), llvm::createAMDGPUCodeGenPreparePass(), llvm::createAMDGPUCtorDtorLoweringPass(), llvm::createAMDGPUFixFunctionBitcastsPass(), llvm::createAMDGPULowerIntrinsicsPass(), llvm::createAMDGPULowerModuleLDSPass(), llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass(), llvm::createAMDGPUPrintfRuntimeBinding(), llvm::createAMDGPUPromoteAlloca(), llvm::createAMDGPUPropagateAttributesEarlyPass(), llvm::createAMDGPUReplaceLDSUseWithPointerPass(), llvm::createAtomicExpandPass(), llvm::createBarrierNoopPass(), llvm::createExternalAAWrapperPass(), llvm::createInferAddressSpacesPass(), llvm::createR600OpenCLImageTypeLoweringPass(), llvm::createSROAPass(), llvm::TargetPassConfig::disablePass(), EnableAMDGPUAliasAnalysis, EnableLDSReplaceWithPointer, EnableLowerModuleLDS, EnableScalarIRPasses, EnableSROA, llvm::FuncletLayoutID, getAMDGPUTargetMachine(), llvm::Triple::getArch(), llvm::TargetMachine::getOptLevel(), llvm::TargetMachine::getTargetTriple(), isPassEnabled(), llvm::CodeGenOpt::None, P, llvm::PatchableFunctionID, llvm::Triple::r600, llvm::StackMapLivenessID, and llvm::TargetPassConfig::TM.

◆ addPreISel()

bool AMDGPUPassConfig::addPreISel ( )
overridevirtual

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes.

Methods with out-of-line standard implementations are major CodeGen stages called by addMachinePasses. Some targets may override major stages when inserting passes is insufficient, but maintaining overriden stages is more work. addPreISelPasses - This method should add any "last minute" LLVM->LLVM passes (which are run just before instruction selector).

Reimplemented from llvm::TargetPassConfig.

Reimplemented in R600PassConfig.

Definition at line 1072 of file AMDGPUTargetMachine.cpp.

References llvm::TargetPassConfig::addPass(), llvm::createFlattenCFGPass(), llvm::TargetMachine::getOptLevel(), llvm::CodeGenOpt::None, and llvm::TargetPassConfig::TM.

Referenced by R600PassConfig::addPreISel().

◆ addStraightLineScalarOptimizationPasses()

void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses ( )

◆ createMachineScheduler()

llvm::ScheduleDAGInstrs * AMDGPUPassConfig::createMachineScheduler ( MachineSchedContext C) const
overridevirtual

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level.

This can also be used to plug a new MachineSchedStrategy into an instance of the standard ScheduleDAGMI: return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*‍/false)

Return NULL to select the default (generic) machine scheduler.

Reimplemented from llvm::TargetPassConfig.

Reimplemented in R600PassConfig.

Definition at line 1089 of file AMDGPUTargetMachine.cpp.

References llvm::ScheduleDAGMI::addMutation(), llvm::createGenericSchedLive(), llvm::createLoadClusterDAGMutation(), llvm::ScheduleDAG::TII, and llvm::ScheduleDAG::TRI.

◆ getAMDGPUTargetMachine()

AMDGPUTargetMachine& llvm::AMDGPUPassConfig::getAMDGPUTargetMachine ( ) const
inline

Definition at line 113 of file AMDGPUTargetMachine.h.

Referenced by addInstSelector(), and addIRPasses().

◆ getCSEConfig()

std::unique_ptr< CSEConfigBase > llvm::AMDGPUPassConfig::getCSEConfig ( ) const
overridevirtual

Returns the CSEConfig object to use for the current optimization level.

Reimplemented from llvm::TargetPassConfig.

Definition at line 855 of file AMDGPUTargetMachine.cpp.

References llvm::TargetMachine::getOptLevel(), llvm::getStandardCSEConfigForOpt(), and llvm::TargetPassConfig::TM.

◆ isPassEnabled()

bool llvm::AMDGPUPassConfig::isPassEnabled ( const cl::opt< bool > &  Opt,
CodeGenOpt::Level  Level = CodeGenOpt::Default 
) const
inline

Check if a pass is enabled given Opt option.

The option always overrides defaults if explicitly used. Otherwise its default will be used given that a pass shall work at an optimization Level minimum.

Definition at line 134 of file AMDGPUTargetMachine.h.

References llvm::cl::Option::getNumOccurrences(), llvm::TargetMachine::getOptLevel(), and llvm::TargetPassConfig::TM.

Referenced by addCodeGenPrepare(), and addIRPasses().


The documentation for this class was generated from the following files: