37#define GET_CC_REGISTER_LISTS
38#include "AArch64GenCallingConv.inc"
39#define GET_REGINFO_TARGET_DESC
40#include "AArch64GenRegisterInfo.inc"
53 unsigned &RegToUseForCFI)
const {
54 if (AArch64::PPRRegClass.
contains(Reg))
57 if (AArch64::ZPRRegClass.
contains(Reg)) {
58 RegToUseForCFI = getSubReg(Reg, AArch64::dsub);
59 for (
int I = 0; CSR_AArch64_AAPCS_SaveList[
I]; ++
I) {
60 if (CSR_AArch64_AAPCS_SaveList[
I] == RegToUseForCFI)
72 assert(MF &&
"Invalid MachineFunction pointer.");
77 return CSR_AArch64_NoRegs_SaveList;
79 return CSR_AArch64_AllRegs_SaveList;
87 return CSR_Win_AArch64_CFGuard_Check_SaveList;
89 return CSR_Win_AArch64_AAPCS_SaveList;
91 return CSR_AArch64_AAVPCS_SaveList;
93 return CSR_AArch64_SVE_AAPCS_SaveList;
97 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
98 "only supported to improve calls to SME ACLE save/restore/disable-za "
99 "functions, and is not intended to be used beyond that scope.");
103 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
104 "only supported to improve calls to SME ACLE __arm_sme_state "
105 "and is not intended to be used beyond that scope.");
109 Attribute::SwiftError))
110 return CSR_AArch64_AAPCS_SwiftError_SaveList;
112 return CSR_AArch64_AAPCS_SwiftTail_SaveList;
114 return CSR_AArch64_RT_MostRegs_SaveList;
116 return CSR_AArch64_RT_AllRegs_SaveList;
120 return CSR_AArch64_AAPCS_X18_SaveList;
122 return CSR_AArch64_SVE_AAPCS_SaveList;
123 return CSR_AArch64_AAPCS_SaveList;
128 assert(MF &&
"Invalid MachineFunction pointer.");
130 "Invalid subtarget for getDarwinCalleeSavedRegs");
134 "Calling convention CFGuard_Check is unsupported on Darwin.");
136 return CSR_Darwin_AArch64_AAVPCS_SaveList;
139 "Calling convention SVE_VectorCall is unsupported on Darwin.");
143 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
144 "only supported to improve calls to SME ACLE save/restore/disable-za "
145 "functions, and is not intended to be used beyond that scope.");
149 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
150 "only supported to improve calls to SME ACLE __arm_sme_state "
151 "and is not intended to be used beyond that scope.");
154 ? CSR_Darwin_AArch64_CXX_TLS_PE_SaveList
155 : CSR_Darwin_AArch64_CXX_TLS_SaveList;
159 Attribute::SwiftError))
160 return CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList;
162 return CSR_Darwin_AArch64_AAPCS_SwiftTail_SaveList;
164 return CSR_Darwin_AArch64_RT_MostRegs_SaveList;
166 return CSR_Darwin_AArch64_RT_AllRegs_SaveList;
168 return CSR_Darwin_AArch64_AAPCS_Win64_SaveList;
169 return CSR_Darwin_AArch64_AAPCS_SaveList;
174 assert(MF &&
"Invalid MachineFunction pointer.");
177 return CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList;
188 for (
size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
190 UpdatedCSRs.
push_back(AArch64::GPR64commonRegClass.getRegister(i));
200 unsigned Idx)
const {
202 if (RC == &AArch64::GPR32allRegClass &&
Idx == AArch64::hsub)
203 return &AArch64::FPR32RegClass;
204 else if (RC == &AArch64::GPR64allRegClass &&
Idx == AArch64::hsub)
205 return &AArch64::FPR64RegClass;
208 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC,
Idx);
215 "Invalid subtarget for getDarwinCallPreservedMask");
218 return CSR_Darwin_AArch64_CXX_TLS_RegMask;
220 return CSR_Darwin_AArch64_AAVPCS_RegMask;
223 "Calling convention SVE_VectorCall is unsupported on Darwin.");
226 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
227 "unsupported on Darwin.");
230 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
231 "unsupported on Darwin.");
234 "Calling convention CFGuard_Check is unsupported on Darwin.");
239 return CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask;
241 return CSR_Darwin_AArch64_AAPCS_SwiftTail_RegMask;
243 return CSR_Darwin_AArch64_RT_MostRegs_RegMask;
245 return CSR_Darwin_AArch64_RT_AllRegs_RegMask;
246 return CSR_Darwin_AArch64_AAPCS_RegMask;
255 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
257 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
267 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
269 return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
270 : CSR_AArch64_SVE_AAPCS_RegMask;
272 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
274 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2_RegMask;
276 return CSR_Win_AArch64_CFGuard_Check_RegMask;
280 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
281 : CSR_AArch64_AAPCS_SwiftError_RegMask;
285 return CSR_AArch64_AAPCS_SwiftTail_RegMask;
288 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
289 : CSR_AArch64_RT_MostRegs_RegMask;
291 return SCS ? CSR_AArch64_RT_AllRegs_SCS_RegMask
292 : CSR_AArch64_RT_AllRegs_RegMask;
295 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
301 return CSR_AArch64_AAPCS_RegMask;
308 return CSR_Darwin_AArch64_TLS_RegMask;
311 return CSR_AArch64_TLS_ELF_RegMask;
318 memcpy(UpdatedMask, *Mask,
sizeof(UpdatedMask[0]) * RegMaskSize);
320 for (
size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
323 subregs_inclusive(AArch64::GPR64commonRegClass.getRegister(i))) {
334 return CSR_AArch64_SMStartStop_RegMask;
339 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
343 return CSR_AArch64_NoRegs_RegMask;
358 return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
359 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
363 return CSR_AArch64_StackProbe_Windows_RegMask;
366std::optional<std::string>
370 return std::string(
"X19 is used as the frame base pointer register.");
381 for (
unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
387 " is clobbered by asynchronous signals when using Arm64EC.";
399 markSuperRegs(
Reserved, AArch64::WSP);
400 markSuperRegs(
Reserved, AArch64::WZR);
403 markSuperRegs(
Reserved, AArch64::W29);
408 markSuperRegs(
Reserved, AArch64::W13);
409 markSuperRegs(
Reserved, AArch64::W14);
410 markSuperRegs(
Reserved, AArch64::W23);
411 markSuperRegs(
Reserved, AArch64::W24);
412 markSuperRegs(
Reserved, AArch64::W28);
413 for (
unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
417 for (
size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
419 markSuperRegs(
Reserved, AArch64::GPR32commonRegClass.getRegister(i));
423 markSuperRegs(
Reserved, AArch64::W19);
427 markSuperRegs(
Reserved, AArch64::W16);
435 markSuperRegs(
Reserved, AArch64::FPCR);
445 for (
size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
447 markSuperRegs(
Reserved, AArch64::GPR32commonRegClass.getRegister(i));
474 " function calls if any of the argument registers is reserved.")});
491 unsigned Kind)
const {
492 return &AArch64::GPR64spRegClass;
497 if (RC == &AArch64::CCRRegClass)
498 return &AArch64::GPR64RegClass;
516 if (hasStackRealignment(MF))
554 return HasReg(CC_AArch64_WebKit_JS_ArgRegs, Reg);
556 return HasReg(CC_AArch64_GHC_ArgRegs, Reg);
566 return HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
570 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
573 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg) ||
574 HasReg(CC_AArch64_AAPCS_Swift_ArgRegs, Reg);
580 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg);
583 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg) ||
584 HasReg(CC_AArch64_DarwinPCS_Swift_ArgRegs, Reg);
588 return HasReg(CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs, Reg);
589 return HasReg(CC_AArch64_DarwinPCS_VarArg_ArgRegs, Reg);
592 HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
593 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
595 return HasReg(CC_AArch64_Win64_CFGuard_Check_ArgRegs, Reg);
600 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
607 return TFI->
hasFP(MF) ? AArch64::FP : AArch64::SP;
634 "Expected SVE area to be calculated by this point");
657 for (
unsigned i = 0; !
MI->getOperand(i).isFI(); ++i)
658 assert(i < MI->getNumOperands() &&
659 "Instr doesn't have FrameIndex operand!");
670 if (!
MI->mayLoad() && !
MI->mayStore())
685 int64_t FPOffset =
Offset - 16 * 20;
722 assert(
MI &&
"Unable to get the legal offset for nil instruction.");
736 DL = Ins->getDebugLoc();
742 Register BaseReg =
MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
743 MRI.constrainRegClass(BaseReg,
TII->getRegClass(MCID, 0,
this, MF));
760 while (!
MI.getOperand(i).isFI()) {
762 assert(i <
MI.getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
769 assert(
Done &&
"Unable to resolve frame index!");
783 if (
MI.getOpcode() == AArch64::STGloop ||
784 MI.getOpcode() == AArch64::STZGloop) {
785 assert(FIOperandNum == 3 &&
786 "Wrong frame index operand for STGloop/STZGloop");
787 unsigned Op =
MI.getOpcode() == AArch64::STGloop ? AArch64::STGloop_wback
788 : AArch64::STZGloop_wback;
789 ScratchReg =
MI.getOperand(1).getReg();
790 MI.getOperand(3).ChangeToRegister(ScratchReg,
false,
false,
true);
791 MI.setDesc(
TII->get(Op));
792 MI.tieOperands(1, 3);
795 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
796 MI.getOperand(FIOperandNum)
797 .ChangeToRegister(ScratchReg,
false,
false,
true);
807 assert(
Offset.getScalable() % 2 == 0 &&
"Invalid frame offset");
813 int64_t VGSized =
Offset.getScalable() / 2;
817 Ops.
append({dwarf::DW_OP_bregx, VG, 0ULL});
820 }
else if (VGSized < 0) {
823 Ops.
append({dwarf::DW_OP_bregx, VG, 0ULL});
830 int SPAdj,
unsigned FIOperandNum,
832 assert(SPAdj == 0 &&
"Unexpected");
841 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
847 if (
MI.getOpcode() == TargetOpcode::STACKMAP ||
848 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
849 MI.getOpcode() == TargetOpcode::STATEPOINT) {
855 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false );
856 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset.getFixed());
860 if (
MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
864 "Frame offsets with a scalable component are not supported");
870 if (
MI.getOpcode() == AArch64::TAGPstack) {
873 FrameReg =
MI.getOperand(3).getReg();
885 MF, FrameIndex, FrameReg,
false,
true);
894 MI.getOperand(FIOperandNum)
895 .ChangeToRegister(ScratchReg,
false,
false,
true);
898 FrameReg = AArch64::SP;
903 MF, FrameIndex, FrameReg,
false,
true);
911 "Emergency spill slot is out of reach");
926 switch (RC->
getID()) {
929 case AArch64::GPR32RegClassID:
930 case AArch64::GPR32spRegClassID:
931 case AArch64::GPR32allRegClassID:
932 case AArch64::GPR64spRegClassID:
933 case AArch64::GPR64allRegClassID:
934 case AArch64::GPR64RegClassID:
935 case AArch64::GPR32commonRegClassID:
936 case AArch64::GPR64commonRegClassID:
941 case AArch64::FPR8RegClassID:
942 case AArch64::FPR16RegClassID:
943 case AArch64::FPR32RegClassID:
944 case AArch64::FPR64RegClassID:
945 case AArch64::FPR128RegClassID:
948 case AArch64::MatrixIndexGPR32_8_11RegClassID:
949 case AArch64::MatrixIndexGPR32_12_15RegClassID:
952 case AArch64::DDRegClassID:
953 case AArch64::DDDRegClassID:
954 case AArch64::DDDDRegClassID:
955 case AArch64::QQRegClassID:
956 case AArch64::QQQRegClassID:
957 case AArch64::QQQQRegClassID:
960 case AArch64::FPR128_loRegClassID:
961 case AArch64::FPR64_loRegClassID:
962 case AArch64::FPR16_loRegClassID:
972 else if (hasStackRealignment(MF))
983 ((DstRC->
getID() == AArch64::GPR64RegClassID) ||
984 (DstRC->
getID() == AArch64::GPR64commonRegClassID)) &&
985 MI->getOperand(0).getSubReg() &&
MI->getOperand(1).getSubReg())
unsigned const MachineRegisterInfo * MRI
static Register createScratchRegisterForInstruction(MachineInstr &MI, unsigned FIOperandNum, const AArch64InstrInfo *TII)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
unsigned getTaggedBasePointerOffset() const
uint64_t getStackSizeSVE() const
bool hasCalculatedStackSizeSVE() const
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
AArch64RegisterInfo(const Triple &TT)
bool isAnyArgRegReserved(const MachineFunction &MF) const
void emitReservedArgRegCallError(const MachineFunction &MF) const
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getTLSCallPreservedMask() const
const uint32_t * getNoPreservedMask() const override
Register getFrameRegister(const MachineFunction &MF) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * SMEABISupportRoutinesCallPreservedMaskFromX0() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
unsigned getLocalAddressRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
const uint32_t * getSMStartStopCallPreservedMask() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned getBaseRegister() const
bool isTargetWindows() const
bool isTargetDarwin() const
bool isTargetILP32() const
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
const AArch64TargetLowering * getTargetLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool isXRegCustomCalleeSaved(size_t i) const
bool isWindowsArm64EC() const
bool isXRegisterReserved(size_t i) const
bool isTargetLinux() const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
AttributeList getAttributes() const
Return the attribute list for this Function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Describe properties that are true of each instruction in the target description file.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
Wrapper class representing physical registers. Should be passed by value.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
int64_t getLocalFrameSize() const
Get the size of the local object blob.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasEHFunclets() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned getID() const
Return the register class ID number.
Triple - Helper class for working with autoconf configuration names.
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
@ AArch64_VectorCall
Used between AArch64 Advanced SIMD functions.
@ Swift
Calling convention for Swift.
@ AArch64_SVE_VectorCall
Used between AArch64 SVE functions.
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
@ PreserveMost
Used for runtime calls that preserves most registers.
@ AnyReg
Used for dynamic register based calls (e.g.
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2
Preserve X2-X15, X19-X29, SP, Z0-Z31, P0-P15.
@ CXX_FAST_TLS
Used for access functions.
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0
Preserve X0-X13, X19-X29, SP, Z0-Z31, P0-P15.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ WebKit_JS
Used for stack based JavaScript calls.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.