LLVM  13.0.0git
AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64RegisterInfo.h"
15 #include "AArch64FrameLowering.h"
16 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DiagnosticInfo.h"
29 #include "llvm/IR/Function.h"
32 
33 using namespace llvm;
34 
35 #define GET_REGINFO_TARGET_DESC
36 #include "AArch64GenRegisterInfo.inc"
37 
39  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
41 }
42 
43 /// Return whether the register needs a CFI entry. Not all unwinders may know
44 /// about SVE registers, so we assume the lowest common denominator, i.e. the
45 /// callee-saves required by the base ABI. For the SVE registers z8-z15 only the
46 /// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is
47 /// returned in \p RegToUseForCFI.
49  unsigned &RegToUseForCFI) const {
50  if (AArch64::PPRRegClass.contains(Reg))
51  return false;
52 
53  if (AArch64::ZPRRegClass.contains(Reg)) {
54  RegToUseForCFI = getSubReg(Reg, AArch64::dsub);
55  for (int I = 0; CSR_AArch64_AAPCS_SaveList[I]; ++I) {
56  if (CSR_AArch64_AAPCS_SaveList[I] == RegToUseForCFI)
57  return true;
58  }
59  return false;
60  }
61 
62  RegToUseForCFI = Reg;
63  return true;
64 }
65 
67  const Function &F = MF->getFunction();
68  return isa<ScalableVectorType>(F.getReturnType()) ||
69  any_of(F.args(), [](const Argument &Arg) {
70  return isa<ScalableVectorType>(Arg.getType());
71  });
72 }
73 
74 const MCPhysReg *
76  assert(MF && "Invalid MachineFunction pointer.");
77 
79  // GHC set of callee saved regs is empty as all those regs are
80  // used for passing STG regs around
81  return CSR_AArch64_NoRegs_SaveList;
83  return CSR_AArch64_AllRegs_SaveList;
84 
85  // Darwin has its own CSR_AArch64_AAPCS_SaveList, which means most CSR save
86  // lists depending on that will need to have their Darwin variant as well.
88  return getDarwinCalleeSavedRegs(MF);
89 
91  return CSR_Win_AArch64_CFGuard_Check_SaveList;
93  return CSR_Win_AArch64_AAPCS_SaveList;
95  return CSR_AArch64_AAVPCS_SaveList;
97  return CSR_AArch64_SVE_AAPCS_SaveList;
99  ->supportSwiftError() &&
101  Attribute::SwiftError))
102  return CSR_AArch64_AAPCS_SwiftError_SaveList;
104  return CSR_AArch64_RT_MostRegs_SaveList;
106  // This is for OSes other than Windows; Windows is a separate case further
107  // above.
108  return CSR_AArch64_AAPCS_X18_SaveList;
109  if (hasSVEArgsOrReturn(MF))
110  return CSR_AArch64_SVE_AAPCS_SaveList;
111  return CSR_AArch64_AAPCS_SaveList;
112 }
113 
114 const MCPhysReg *
116  assert(MF && "Invalid MachineFunction pointer.");
118  "Invalid subtarget for getDarwinCalleeSavedRegs");
119 
122  "Calling convention CFGuard_Check is unsupported on Darwin.");
124  return CSR_Darwin_AArch64_AAVPCS_SaveList;
127  "Calling convention SVE_VectorCall is unsupported on Darwin.");
129  return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()
130  ? CSR_Darwin_AArch64_CXX_TLS_PE_SaveList
131  : CSR_Darwin_AArch64_CXX_TLS_SaveList;
133  ->supportSwiftError() &&
135  Attribute::SwiftError))
136  return CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList;
138  return CSR_Darwin_AArch64_RT_MostRegs_SaveList;
139  return CSR_Darwin_AArch64_AAPCS_SaveList;
140 }
141 
143  const MachineFunction *MF) const {
144  assert(MF && "Invalid MachineFunction pointer.");
147  return CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList;
148  return nullptr;
149 }
150 
152  MachineFunction &MF) const {
153  const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
154  SmallVector<MCPhysReg, 32> UpdatedCSRs;
155  for (const MCPhysReg *I = CSRs; *I; ++I)
156  UpdatedCSRs.push_back(*I);
157 
158  for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
160  UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
161  }
162  }
163  // Register lists are zero-terminated.
164  UpdatedCSRs.push_back(0);
165  MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
166 }
167 
168 const TargetRegisterClass *
170  unsigned Idx) const {
171  // edge case for GPR/FPR register classes
172  if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
173  return &AArch64::FPR32RegClass;
174  else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
175  return &AArch64::FPR64RegClass;
176 
177  // Forward to TableGen's default version.
178  return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
179 }
180 
181 const uint32_t *
183  CallingConv::ID CC) const {
185  "Invalid subtarget for getDarwinCallPreservedMask");
186 
187  if (CC == CallingConv::CXX_FAST_TLS)
188  return CSR_Darwin_AArch64_CXX_TLS_RegMask;
190  return CSR_Darwin_AArch64_AAVPCS_RegMask;
193  "Calling convention SVE_VectorCall is unsupported on Darwin.");
194  if (CC == CallingConv::CFGuard_Check)
196  "Calling convention CFGuard_Check is unsupported on Darwin.");
199  ->supportSwiftError() &&
200  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
201  return CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask;
202  if (CC == CallingConv::PreserveMost)
203  return CSR_Darwin_AArch64_RT_MostRegs_RegMask;
204  return CSR_Darwin_AArch64_AAPCS_RegMask;
205 }
206 
207 const uint32_t *
209  CallingConv::ID CC) const {
210  bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
211  if (CC == CallingConv::GHC)
212  // This is academic because all GHC calls are (supposed to be) tail calls
213  return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
214  if (CC == CallingConv::AnyReg)
215  return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
216 
217  // All the following calling conventions are handled differently on Darwin.
219  if (SCS)
220  report_fatal_error("ShadowCallStack attribute not supported on Darwin.");
221  return getDarwinCallPreservedMask(MF, CC);
222  }
223 
225  return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
227  return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
228  : CSR_AArch64_SVE_AAPCS_RegMask;
229  if (CC == CallingConv::CFGuard_Check)
230  return CSR_Win_AArch64_CFGuard_Check_RegMask;
232  ->supportSwiftError() &&
233  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
234  return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
235  : CSR_AArch64_AAPCS_SwiftError_RegMask;
236  if (CC == CallingConv::PreserveMost)
237  return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
238  : CSR_AArch64_RT_MostRegs_RegMask;
239  else
240  return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
241 }
242 
244  const MachineFunction &MF) const {
246  return CSR_AArch64_AAPCS_RegMask;
247 
248  return nullptr;
249 }
250 
252  if (TT.isOSDarwin())
253  return CSR_Darwin_AArch64_TLS_RegMask;
254 
255  assert(TT.isOSBinFormatELF() && "Invalid target");
256  return CSR_AArch64_TLS_ELF_RegMask;
257 }
258 
260  const uint32_t **Mask) const {
261  uint32_t *UpdatedMask = MF.allocateRegMask();
262  unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
263  memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
264 
265  for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
267  for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),
268  this, true);
269  SubReg.isValid(); ++SubReg) {
270  // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
271  // register mask.
272  UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
273  }
274  }
275  }
276  *Mask = UpdatedMask;
277 }
278 
280  return CSR_AArch64_NoRegs_RegMask;
281 }
282 
283 const uint32_t *
285  CallingConv::ID CC) const {
286  // This should return a register mask that is the same as that returned by
287  // getCallPreservedMask but that additionally preserves the register used for
288  // the first i64 argument (which must also be the register used to return a
289  // single i64 return value)
290  //
291  // In case that the calling convention does not use the same register for
292  // both, the function should return NULL (does not currently apply)
293  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
295  return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
296  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
297 }
298 
300  return CSR_AArch64_StackProbe_Windows_RegMask;
301 }
302 
303 BitVector
305  const AArch64FrameLowering *TFI = getFrameLowering(MF);
306 
307  // FIXME: avoid re-calculating this every time.
308  BitVector Reserved(getNumRegs());
309  markSuperRegs(Reserved, AArch64::WSP);
310  markSuperRegs(Reserved, AArch64::WZR);
311 
312  if (TFI->hasFP(MF) || TT.isOSDarwin())
313  markSuperRegs(Reserved, AArch64::W29);
314 
315  for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
317  markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
318  }
319 
320  if (hasBasePointer(MF))
321  markSuperRegs(Reserved, AArch64::W19);
322 
323  // SLH uses register W16/X16 as the taint register.
324  if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
325  markSuperRegs(Reserved, AArch64::W16);
326 
327  assert(checkAllSuperRegsMarked(Reserved));
328  return Reserved;
329 }
330 
332  MCRegister Reg) const {
333  return getReservedRegs(MF)[Reg];
334 }
335 
337  return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
338  return isReservedReg(MF, r);
339  });
340 }
341 
343  const MachineFunction &MF) const {
344  const Function &F = MF.getFunction();
345  F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
346  " function calls if any of the argument registers is reserved.")});
347 }
348 
350  MCRegister PhysReg) const {
351  return !isReservedReg(MF, PhysReg);
352 }
353 
355  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
356 }
357 
358 const TargetRegisterClass *
360  unsigned Kind) const {
361  return &AArch64::GPR64spRegClass;
362 }
363 
364 const TargetRegisterClass *
366  if (RC == &AArch64::CCRRegClass)
367  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
368  return RC;
369 }
370 
371 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
372 
374  const MachineFrameInfo &MFI = MF.getFrameInfo();
375 
376  // In the presence of variable sized objects or funclets, if the fixed stack
377  // size is large enough that referencing from the FP won't result in things
378  // being in range relatively often, we can use a base pointer to allow access
379  // from the other direction like the SP normally works.
380  //
381  // Furthermore, if both variable sized objects are present, and the
382  // stack needs to be dynamically re-aligned, the base pointer is the only
383  // reliable way to reference the locals.
384  if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
385  if (hasStackRealignment(MF))
386  return true;
387 
388  if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) {
390  // Frames that have variable sized objects and scalable SVE objects,
391  // should always use a basepointer.
392  if (!AFI->hasCalculatedStackSizeSVE() || AFI->getStackSizeSVE())
393  return true;
394  }
395 
396  // Conservatively estimate whether the negative offset from the frame
397  // pointer will be sufficient to reach. If a function has a smallish
398  // frame, it's less likely to have lots of spills and callee saved
399  // space, so it's all more likely to be within range of the frame pointer.
400  // If it's wrong, we'll materialize the constant and still get to the
401  // object; it's just suboptimal. Negative offsets use the unscaled
402  // load/store instructions, which have a 9-bit signed immediate.
403  return MFI.getLocalFrameSize() >= 256;
404  }
405 
406  return false;
407 }
408 
409 Register
411  const AArch64FrameLowering *TFI = getFrameLowering(MF);
412  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
413 }
414 
416  const MachineFunction &MF) const {
417  return true;
418 }
419 
421  const MachineFunction &MF) const {
422  return true;
423 }
424 
425 bool
427  // This function indicates whether the emergency spillslot should be placed
428  // close to the beginning of the stackframe (closer to FP) or the end
429  // (closer to SP).
430  //
431  // The beginning works most reliably if we have a frame pointer.
432  // In the presence of any non-constant space between FP and locals,
433  // (e.g. in case of stack realignment or a scalable SVE area), it is
434  // better to use SP or BP.
435  const AArch64FrameLowering &TFI = *getFrameLowering(MF);
438  AFI->hasCalculatedStackSizeSVE()) &&
439  "Expected SVE area to be calculated by this point");
440  return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE();
441 }
442 
444  const MachineFunction &MF) const {
445  return true;
446 }
447 
448 bool
450  const MachineFrameInfo &MFI = MF.getFrameInfo();
452  return true;
453  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
454 }
455 
456 /// needsFrameBaseReg - Returns true if the instruction's frame index
457 /// reference would be better served by a base register other than FP
458 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
459 /// references it should create new base registers for.
461  int64_t Offset) const {
462  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
463  assert(i < MI->getNumOperands() &&
464  "Instr doesn't have FrameIndex operand!");
465 
466  // It's the load/store FI references that cause issues, as it can be difficult
467  // to materialize the offset if it won't fit in the literal field. Estimate
468  // based on the size of the local frame and some conservative assumptions
469  // about the rest of the stack frame (note, this is pre-regalloc, so
470  // we don't know everything for certain yet) whether this offset is likely
471  // to be out of range of the immediate. Return true if so.
472 
473  // We only generate virtual base registers for loads and stores, so
474  // return false for everything else.
475  if (!MI->mayLoad() && !MI->mayStore())
476  return false;
477 
478  // Without a virtual base register, if the function has variable sized
479  // objects, all fixed-size local references will be via the frame pointer,
480  // Approximate the offset and see if it's legal for the instruction.
481  // Note that the incoming offset is based on the SP value at function entry,
482  // so it'll be negative.
483  MachineFunction &MF = *MI->getParent()->getParent();
484  const AArch64FrameLowering *TFI = getFrameLowering(MF);
485  MachineFrameInfo &MFI = MF.getFrameInfo();
486 
487  // Estimate an offset from the frame pointer.
488  // Conservatively assume all GPR callee-saved registers get pushed.
489  // FP, LR, X19-X28, D8-D15. 64-bits each.
490  int64_t FPOffset = Offset - 16 * 20;
491  // Estimate an offset from the stack pointer.
492  // The incoming offset is relating to the SP at the start of the function,
493  // but when we access the local it'll be relative to the SP after local
494  // allocation, so adjust our SP-relative offset by that allocation size.
495  Offset += MFI.getLocalFrameSize();
496  // Assume that we'll have at least some spill slots allocated.
497  // FIXME: This is a total SWAG number. We should run some statistics
498  // and pick a real one.
499  Offset += 128; // 128 bytes of spill slots
500 
501  // If there is a frame pointer, try using it.
502  // The FP is only available if there is no dynamic realignment. We
503  // don't know for sure yet whether we'll need that, so we guess based
504  // on whether there are any local variables that would trigger it.
505  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
506  return false;
507 
508  // If we can reference via the stack pointer or base pointer, try that.
509  // FIXME: This (and the code that resolves the references) can be improved
510  // to only disallow SP relative references in the live range of
511  // the VLA(s). In practice, it's unclear how much difference that
512  // would make, but it may be worth doing.
513  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
514  return false;
515 
516  // If even offset 0 is illegal, we don't want a virtual base register.
517  if (!isFrameOffsetLegal(MI, AArch64::SP, 0))
518  return false;
519 
520  // The offset likely isn't legal; we want to allocate a virtual base register.
521  return true;
522 }
523 
525  Register BaseReg,
526  int64_t Offset) const {
527  assert(MI && "Unable to get the legal offset for nil instruction.");
530 }
531 
532 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
533 /// at the beginning of the basic block.
534 Register
536  int FrameIdx,
537  int64_t Offset) const {
539  DebugLoc DL; // Defaults to "unknown"
540  if (Ins != MBB->end())
541  DL = Ins->getDebugLoc();
542  const MachineFunction &MF = *MBB->getParent();
543  const AArch64InstrInfo *TII =
544  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
545  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
547  Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
548  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
549  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
550 
551  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
552  .addFrameIndex(FrameIdx)
553  .addImm(Offset)
554  .addImm(Shifter);
555 
556  return BaseReg;
557 }
558 
560  int64_t Offset) const {
561  // ARM doesn't need the general 64-bit offsets
563 
564  unsigned i = 0;
565  while (!MI.getOperand(i).isFI()) {
566  ++i;
567  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
568  }
569 
570  const MachineFunction *MF = MI.getParent()->getParent();
571  const AArch64InstrInfo *TII =
572  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
573  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
574  assert(Done && "Unable to resolve frame index!");
575  (void)Done;
576 }
577 
578 // Create a scratch register for the frame index elimination in an instruction.
579 // This function has special handling of stack tagging loop pseudos, in which
580 // case it can also change the instruction opcode (but not the operands).
581 static Register
583  const AArch64InstrInfo *TII) {
584  // ST*Gloop have a reserved scratch register in operand 1. Use it, and also
585  // replace the instruction with the writeback variant because it will now
586  // satisfy the operand constraints for it.
587  if (MI.getOpcode() == AArch64::STGloop) {
588  MI.setDesc(TII->get(AArch64::STGloop_wback));
589  return MI.getOperand(1).getReg();
590  } else if (MI.getOpcode() == AArch64::STZGloop) {
591  MI.setDesc(TII->get(AArch64::STZGloop_wback));
592  return MI.getOperand(1).getReg();
593  } else {
594  return MI.getMF()->getRegInfo().createVirtualRegister(
595  &AArch64::GPR64RegClass);
596  }
597 }
598 
600  const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
601  // The smallest scalable element supported by scaled SVE addressing
602  // modes are predicates, which are 2 scalable bytes in size. So the scalable
603  // byte offset must always be a multiple of 2.
604  assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset");
605 
606  // Add fixed-sized offset using existing DIExpression interface.
607  DIExpression::appendOffset(Ops, Offset.getFixed());
608 
609  unsigned VG = getDwarfRegNum(AArch64::VG, true);
610  int64_t VGSized = Offset.getScalable() / 2;
611  if (VGSized > 0) {
612  Ops.push_back(dwarf::DW_OP_constu);
613  Ops.push_back(VGSized);
614  Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
615  Ops.push_back(dwarf::DW_OP_mul);
616  Ops.push_back(dwarf::DW_OP_plus);
617  } else if (VGSized < 0) {
618  Ops.push_back(dwarf::DW_OP_constu);
619  Ops.push_back(-VGSized);
620  Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
621  Ops.push_back(dwarf::DW_OP_mul);
622  Ops.push_back(dwarf::DW_OP_minus);
623  }
624 }
625 
627  int SPAdj, unsigned FIOperandNum,
628  RegScavenger *RS) const {
629  assert(SPAdj == 0 && "Unexpected");
630 
631  MachineInstr &MI = *II;
632  MachineBasicBlock &MBB = *MI.getParent();
633  MachineFunction &MF = *MBB.getParent();
634  const MachineFrameInfo &MFI = MF.getFrameInfo();
635  const AArch64InstrInfo *TII =
636  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
637  const AArch64FrameLowering *TFI = getFrameLowering(MF);
638  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
639  bool Tagged =
640  MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
641  Register FrameReg;
642 
643  // Special handling of dbg_value, stackmap patchpoint statepoint instructions.
644  if (MI.getOpcode() == TargetOpcode::STACKMAP ||
645  MI.getOpcode() == TargetOpcode::PATCHPOINT ||
646  MI.getOpcode() == TargetOpcode::STATEPOINT) {
648  TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
649  /*PreferFP=*/true,
650  /*ForSimm=*/false);
651  Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
652  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
653  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
654  return;
655  }
656 
657  if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
658  MachineOperand &FI = MI.getOperand(FIOperandNum);
660  assert(!Offset.getScalable() &&
661  "Frame offsets with a scalable component are not supported");
662  FI.ChangeToImmediate(Offset.getFixed());
663  return;
664  }
665 
667  if (MI.getOpcode() == AArch64::TAGPstack) {
668  // TAGPstack must use the virtual frame register in its 3rd operand.
670  FrameReg = MI.getOperand(3).getReg();
673  } else if (Tagged) {
675  MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize());
676  if (MFI.hasVarSizedObjects() ||
677  isAArch64FrameOffsetLegal(MI, SPOffset, nullptr, nullptr, nullptr) !=
679  // Can't update to SP + offset in place. Precalculate the tagged pointer
680  // in a scratch register.
682  MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
683  Register ScratchReg =
684  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
685  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
686  TII);
687  BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
688  .addReg(ScratchReg)
689  .addReg(ScratchReg)
690  .addImm(0);
691  MI.getOperand(FIOperandNum)
692  .ChangeToRegister(ScratchReg, false, false, true);
693  return;
694  }
695  FrameReg = AArch64::SP;
697  (int64_t)MFI.getStackSize());
698  } else {
700  MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
701  }
702 
703  // Modify MI as necessary to handle as much of 'Offset' as possible
704  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
705  return;
706 
707  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
708  "Emergency spill slot is out of reach");
709 
710  // If we get here, the immediate doesn't fit into the instruction. We folded
711  // as much as possible above. Handle the rest, providing a register that is
712  // SP+LargeImm.
714  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
715  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
716 }
717 
719  MachineFunction &MF) const {
720  const AArch64FrameLowering *TFI = getFrameLowering(MF);
721 
722  switch (RC->getID()) {
723  default:
724  return 0;
725  case AArch64::GPR32RegClassID:
726  case AArch64::GPR32spRegClassID:
727  case AArch64::GPR32allRegClassID:
728  case AArch64::GPR64spRegClassID:
729  case AArch64::GPR64allRegClassID:
730  case AArch64::GPR64RegClassID:
731  case AArch64::GPR32commonRegClassID:
732  case AArch64::GPR64commonRegClassID:
733  return 32 - 1 // XZR/SP
734  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
736  - hasBasePointer(MF); // X19
737  case AArch64::FPR8RegClassID:
738  case AArch64::FPR16RegClassID:
739  case AArch64::FPR32RegClassID:
740  case AArch64::FPR64RegClassID:
741  case AArch64::FPR128RegClassID:
742  return 32;
743 
744  case AArch64::DDRegClassID:
745  case AArch64::DDDRegClassID:
746  case AArch64::DDDDRegClassID:
747  case AArch64::QQRegClassID:
748  case AArch64::QQQRegClassID:
749  case AArch64::QQQQRegClassID:
750  return 32;
751 
752  case AArch64::FPR128_loRegClassID:
753  case AArch64::FPR64_loRegClassID:
754  case AArch64::FPR16_loRegClassID:
755  return 16;
756  }
757 }
758 
760  const MachineFunction &MF) const {
761  const auto &MFI = MF.getFrameInfo();
762  if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
763  return AArch64::SP;
764  else if (hasStackRealignment(MF))
765  return getBaseRegister();
766  return getFrameRegister(MF);
767 }
768 
769 /// SrcRC and DstRC will be morphed into NewRC if this returns true
771  MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
772  const TargetRegisterClass *DstRC, unsigned DstSubReg,
773  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
774  if (MI->isCopy() &&
775  ((DstRC->getID() == AArch64::GPR64RegClassID) ||
776  (DstRC->getID() == AArch64::GPR64commonRegClassID)) &&
777  MI->getOperand(0).getSubReg() && MI->getOperand(1).getSubReg())
778  // Do not coalesce in the case of a 32-bit subregister copy
779  // which implements a 32 to 64 bit zero extension
780  // which relies on the upper 32 bits being zeroed.
781  return false;
782  return true;
783 }
i
i
Definition: README.txt:29
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::AArch64RegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: AArch64RegisterInfo.cpp:208
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:351
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AArch64Subtarget::isTargetWindows
bool isTargetWindows() const
Definition: AArch64Subtarget.h:484
AArch64RegisterInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
Definition: AllocatorList.h:23
AArch64MachineFunctionInfo.h
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AArch64RegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: AArch64RegisterInfo.cpp:626
TargetFrameLowering.h
llvm::AArch64RegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition: AArch64RegisterInfo.cpp:770
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:34
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::AttributeList::hasAttrSomewhere
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
Definition: Attributes.cpp:1592
llvm::MachineFunction::allocateRegMask
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
Definition: MachineFunction.cpp:502
llvm::DiagnosticInfoUnsupported
Diagnostic information for unsupported feature in backend.
Definition: DiagnosticInfo.h:993
DebugInfoMetadata.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Function
Definition: Function.h:61
llvm::AArch64FrameOffsetCanUpdate
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
Definition: AArch64InstrInfo.h:380
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
AArch64GenRegisterInfo
llvm::AArch64Subtarget::hasSVE
bool hasSVE() const
Definition: AArch64Subtarget.h:447
llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
Definition: AArch64RegisterInfo.cpp:259
llvm::AArch64RegisterInfo::getBaseRegister
unsigned getBaseRegister() const
Definition: AArch64RegisterInfo.cpp:371
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
llvm::AArch64RegisterInfo::isAnyArgRegReserved
bool isAnyArgRegReserved(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:336
llvm::AArch64RegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: AArch64RegisterInfo.cpp:279
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:481
llvm::AArch64RegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: AArch64RegisterInfo.cpp:142
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
getDwarfRegNum
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:178
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::AArch64RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:410
llvm::rewriteAArch64FrameIndex
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: AArch64InstrInfo.cpp:4172
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:345
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::AArch64Subtarget::isXRegCustomCalleeSaved
bool isXRegCustomCalleeSaved(size_t i) const
Definition: AArch64Subtarget.h:355
llvm::AArch64FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: AArch64FrameLowering.cpp:353
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:302
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::AArch64RegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:718
llvm::RegScavenger::isScavengingFrameIndex
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
Definition: RegisterScavenging.h:128
llvm::AArch64RegisterInfo::cannotEliminateFrame
bool cannotEliminateFrame(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:449
llvm::AArch64RegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Definition: AArch64RegisterInfo.cpp:365
llvm::AArch64FrameLowering
Definition: AArch64FrameLowering.h:23
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:632
llvm::AArch64RegisterInfo::getSubClassWithSubReg
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
Definition: AArch64RegisterInfo.cpp:169
AArch64InstrInfo.h
llvm::AArch64RegisterInfo::hasSVEArgsOrReturn
static bool hasSVEArgsOrReturn(const MachineFunction *MF)
Definition: AArch64RegisterInfo.cpp:66
llvm::CallingConv::AArch64_VectorCall
@ AArch64_VectorCall
Definition: CallingConv.h:234
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:38
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:484
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:648
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:633
llvm::AArch64TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: AArch64ISelLowering.h:777
createScratchRegisterForInstruction
static Register createScratchRegisterForInstruction(MachineInstr &MI, const AArch64InstrInfo *TII)
Definition: AArch64RegisterInfo.cpp:582
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineRegisterInfo::setCalleeSavedRegs
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
Definition: MachineRegisterInfo.cpp:627
llvm::AArch64_AM::getShifterImm
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
Definition: AArch64AddressingModes.h:98
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:563
llvm::CallingConv::CFGuard_Check
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:87
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:504
llvm::BitVector
Definition: BitVector.h:74
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:164
llvm::AArch64RegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Definition: AArch64RegisterInfo.cpp:535
llvm::emitFrameOffset
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
Definition: AArch64InstrInfo.cpp:3855
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AArch64RegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: AArch64RegisterInfo.cpp:524
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:239
AArch64AddressingModes.h
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
llvm::AArch64FrameOffsetIsLegal
@ AArch64FrameOffsetIsLegal
Offset is legal.
Definition: AArch64InstrInfo.h:379
llvm::AArch64FrameLowering::resolveFrameIndexReference
StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const
Definition: AArch64FrameLowering.cpp:1941
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::AArch64RegisterInfo::AArch64RegisterInfo
AArch64RegisterInfo(const Triple &TT)
Definition: AArch64RegisterInfo.cpp:38
llvm::AArch64FunctionInfo::isSplitCSR
bool isSplitCSR() const
Definition: AArch64MachineFunctionInfo.h:196
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:153
llvm::isAArch64FrameOffsetLegal
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
Definition: AArch64InstrInfo.cpp:4075
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::MachineFrameInfo::getLocalFrameSize
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Definition: MachineFrameInfo.h:419
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
AArch64FrameLowering.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:228
llvm::AArch64FunctionInfo::getTaggedBasePointerOffset
unsigned getTaggedBasePointerOffset() const
Definition: AArch64MachineFunctionInfo.h:354
llvm::CallingConv::AArch64_SVE_VectorCall
@ AArch64_SVE_VectorCall
Calling convention between AArch64 SVE functions.
Definition: CallingConv.h:237
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
llvm::AArch64RegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Definition: AArch64RegisterInfo.cpp:460
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
memcpy
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
llvm::AArch64RegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: AArch64RegisterInfo.cpp:354
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::AArch64Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: AArch64Subtarget.h:483
llvm::AArch64RegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:426
llvm::AArch64FrameLowering::getNonLocalFrameIndexReference
StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
Definition: AArch64FrameLowering.cpp:1905
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::AArch64RegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: AArch64RegisterInfo.cpp:75
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::AArch64RegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:304
Triple.h
llvm::AArch64RegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:443
TargetOptions.h
llvm::AArch64RegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: AArch64RegisterInfo.cpp:349
llvm::AArch64Subtarget::isXRegisterReserved
bool isXRegisterReserved(size_t i) const
Definition: AArch64Subtarget.h:353
llvm::AArch64RegisterInfo::getLocalAddressRegister
unsigned getLocalAddressRegister(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:759
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
llvm::AArch64FunctionInfo::hasCalculatedStackSizeSVE
bool hasCalculatedStackSizeSVE() const
Definition: AArch64MachineFunctionInfo.h:175
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo::getCustomEHPadPreservedMask
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:243
llvm::AArch64RegisterInfo::getThisReturnPreservedMask
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
Definition: AArch64RegisterInfo.cpp:284
llvm::AArch64RegisterInfo::emitReservedArgRegCallError
void emitReservedArgRegCallError(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:342
llvm::AArch64RegisterInfo::getDarwinCallPreservedMask
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Definition: AArch64RegisterInfo.cpp:182
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:366
llvm::AArch64_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: AArch64MCTargetDesc.cpp:63
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1210
llvm::AArch64Subtarget::getNumXRegisterReserved
unsigned getNumXRegisterReserved() const
Definition: AArch64Subtarget.h:354
llvm::AArch64RegisterInfo::getOffsetOpcodes
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Definition: AArch64RegisterInfo.cpp:599
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
uint16_t
llvm::AArch64FunctionInfo::getStackSizeSVE
uint64_t getStackSizeSVE() const
Definition: AArch64MachineFunctionInfo.h:182
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
MachineFrameInfo.h
DiagnosticInfo.h
Function.h
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::AArch64RegisterInfo::getWindowsStackProbePreservedMask
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
Definition: AArch64RegisterInfo.cpp:299
llvm::MachineFunction::hasEHFunclets
bool hasEHFunclets() const
Definition: MachineFunction.h:965
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
AArch64Subtarget.h
llvm::AArch64RegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: AArch64RegisterInfo.cpp:559
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::AArch64RegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: AArch64RegisterInfo.cpp:359
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:151
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl< uint64_t >
llvm::AArch64RegisterInfo::getTLSCallPreservedMask
const uint32_t * getTLSCallPreservedMask() const
Definition: AArch64RegisterInfo.cpp:251
llvm::AArch64RegisterInfo::regNeedsCFI
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
Definition: AArch64RegisterInfo.cpp:48
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:598
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:664
RegisterScavenging.h
llvm::AArch64RegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:420
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
raw_ostream.h
llvm::AArch64RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:373
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64RegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:415
llvm::AArch64RegisterInfo::getDarwinCalleeSavedRegs
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
Definition: AArch64RegisterInfo.cpp:115
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AArch64RegisterInfo::isReservedReg
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
Definition: AArch64RegisterInfo.cpp:331
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22