LLVM 20.0.0git
AArch64RegisterInfo.cpp
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1//===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64RegisterInfo.h"
16#include "AArch64InstrInfo.h"
18#include "AArch64Subtarget.h"
21#include "llvm/ADT/BitVector.h"
30#include "llvm/IR/Function.h"
34
35using namespace llvm;
36
37#define GET_CC_REGISTER_LISTS
38#include "AArch64GenCallingConv.inc"
39#define GET_REGINFO_TARGET_DESC
40#include "AArch64GenRegisterInfo.inc"
41
43 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
45}
46
47/// Return whether the register needs a CFI entry. Not all unwinders may know
48/// about SVE registers, so we assume the lowest common denominator, i.e. the
49/// callee-saves required by the base ABI. For the SVE registers z8-z15 only the
50/// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is
51/// returned in \p RegToUseForCFI.
53 unsigned &RegToUseForCFI) const {
54 if (AArch64::PPRRegClass.contains(Reg))
55 return false;
56
57 if (AArch64::ZPRRegClass.contains(Reg)) {
58 RegToUseForCFI = getSubReg(Reg, AArch64::dsub);
59 for (int I = 0; CSR_AArch64_AAPCS_SaveList[I]; ++I) {
60 if (CSR_AArch64_AAPCS_SaveList[I] == RegToUseForCFI)
61 return true;
62 }
63 return false;
64 }
65
66 RegToUseForCFI = Reg;
67 return true;
68}
69
70const MCPhysReg *
72 assert(MF && "Invalid MachineFunction pointer.");
73
75 // GHC set of callee saved regs is empty as all those regs are
76 // used for passing STG regs around
77 return CSR_AArch64_NoRegs_SaveList;
79 return CSR_AArch64_NoneRegs_SaveList;
81 return CSR_AArch64_AllRegs_SaveList;
82
84 return CSR_Win_AArch64_Arm64EC_Thunk_SaveList;
85
86 // Darwin has its own CSR_AArch64_AAPCS_SaveList, which means most CSR save
87 // lists depending on that will need to have their Darwin variant as well.
89 return getDarwinCalleeSavedRegs(MF);
90
92 return CSR_Win_AArch64_CFGuard_Check_SaveList;
97 Attribute::SwiftError))
98 return CSR_Win_AArch64_AAPCS_SwiftError_SaveList;
100 return CSR_Win_AArch64_AAPCS_SwiftTail_SaveList;
101 return CSR_Win_AArch64_AAPCS_SaveList;
102 }
104 return CSR_AArch64_AAVPCS_SaveList;
106 return CSR_AArch64_SVE_AAPCS_SaveList;
107 if (MF->getFunction().getCallingConv() ==
110 "Calling convention "
111 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is only "
112 "supported to improve calls to SME ACLE save/restore/disable-za "
113 "functions, and is not intended to be used beyond that scope.");
114 if (MF->getFunction().getCallingConv() ==
117 "Calling convention "
118 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1 is "
119 "only supported to improve calls to SME ACLE __arm_get_current_vg "
120 "function, and is not intended to be used beyond that scope.");
121 if (MF->getFunction().getCallingConv() ==
124 "Calling convention "
125 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
126 "only supported to improve calls to SME ACLE __arm_sme_state "
127 "and is not intended to be used beyond that scope.");
129 ->supportSwiftError() &&
131 Attribute::SwiftError))
132 return CSR_AArch64_AAPCS_SwiftError_SaveList;
134 return CSR_AArch64_AAPCS_SwiftTail_SaveList;
136 return CSR_AArch64_RT_MostRegs_SaveList;
138 return CSR_AArch64_RT_AllRegs_SaveList;
140 // This is for OSes other than Windows; Windows is a separate case further
141 // above.
142 return CSR_AArch64_AAPCS_X18_SaveList;
143 if (MF->getInfo<AArch64FunctionInfo>()->isSVECC())
144 return CSR_AArch64_SVE_AAPCS_SaveList;
145 return CSR_AArch64_AAPCS_SaveList;
146}
147
148const MCPhysReg *
150 assert(MF && "Invalid MachineFunction pointer.");
152 "Invalid subtarget for getDarwinCalleeSavedRegs");
153
156 "Calling convention CFGuard_Check is unsupported on Darwin.");
158 return CSR_Darwin_AArch64_AAVPCS_SaveList;
161 "Calling convention SVE_VectorCall is unsupported on Darwin.");
162 if (MF->getFunction().getCallingConv() ==
165 "Calling convention "
166 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
167 "only supported to improve calls to SME ACLE save/restore/disable-za "
168 "functions, and is not intended to be used beyond that scope.");
169 if (MF->getFunction().getCallingConv() ==
172 "Calling convention "
173 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1 is "
174 "only supported to improve calls to SME ACLE __arm_get_current_vg "
175 "function, and is not intended to be used beyond that scope.");
176 if (MF->getFunction().getCallingConv() ==
179 "Calling convention "
180 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
181 "only supported to improve calls to SME ACLE __arm_sme_state "
182 "and is not intended to be used beyond that scope.");
184 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()
185 ? CSR_Darwin_AArch64_CXX_TLS_PE_SaveList
186 : CSR_Darwin_AArch64_CXX_TLS_SaveList;
188 ->supportSwiftError() &&
190 Attribute::SwiftError))
191 return CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList;
193 return CSR_Darwin_AArch64_AAPCS_SwiftTail_SaveList;
195 return CSR_Darwin_AArch64_RT_MostRegs_SaveList;
197 return CSR_Darwin_AArch64_RT_AllRegs_SaveList;
199 return CSR_Darwin_AArch64_AAPCS_Win64_SaveList;
200 return CSR_Darwin_AArch64_AAPCS_SaveList;
201}
202
204 const MachineFunction *MF) const {
205 assert(MF && "Invalid MachineFunction pointer.");
208 return CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList;
209 return nullptr;
210}
211
213 MachineFunction &MF) const {
214 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
215 SmallVector<MCPhysReg, 32> UpdatedCSRs;
216 for (const MCPhysReg *I = CSRs; *I; ++I)
217 UpdatedCSRs.push_back(*I);
218
219 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
221 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
222 }
223 }
224 // Register lists are zero-terminated.
225 UpdatedCSRs.push_back(0);
226 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
227}
228
231 unsigned Idx) const {
232 // edge case for GPR/FPR register classes
233 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
234 return &AArch64::FPR32RegClass;
235 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
236 return &AArch64::FPR64RegClass;
237
238 // Forward to TableGen's default version.
239 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
240}
241
242const uint32_t *
244 CallingConv::ID CC) const {
246 "Invalid subtarget for getDarwinCallPreservedMask");
247
249 return CSR_Darwin_AArch64_CXX_TLS_RegMask;
251 return CSR_Darwin_AArch64_AAVPCS_RegMask;
254 "Calling convention SVE_VectorCall is unsupported on Darwin.");
256 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
258 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1_RegMask;
260 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2_RegMask;
263 "Calling convention CFGuard_Check is unsupported on Darwin.");
266 ->supportSwiftError() &&
267 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
268 return CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask;
270 return CSR_Darwin_AArch64_AAPCS_SwiftTail_RegMask;
272 return CSR_Darwin_AArch64_RT_MostRegs_RegMask;
274 return CSR_Darwin_AArch64_RT_AllRegs_RegMask;
275 return CSR_Darwin_AArch64_AAPCS_RegMask;
276}
277
278const uint32_t *
280 CallingConv::ID CC) const {
281 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
282 if (CC == CallingConv::GHC)
283 // This is academic because all GHC calls are (supposed to be) tail calls
284 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
286 return SCS ? CSR_AArch64_NoneRegs_SCS_RegMask
287 : CSR_AArch64_NoneRegs_RegMask;
288 if (CC == CallingConv::AnyReg)
289 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
290
291 // All the following calling conventions are handled differently on Darwin.
293 if (SCS)
294 report_fatal_error("ShadowCallStack attribute not supported on Darwin.");
295 return getDarwinCallPreservedMask(MF, CC);
296 }
297
299 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
301 return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
302 : CSR_AArch64_SVE_AAPCS_RegMask;
304 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
306 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1_RegMask;
308 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2_RegMask;
310 return CSR_Win_AArch64_CFGuard_Check_RegMask;
312 ->supportSwiftError() &&
313 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
314 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
315 : CSR_AArch64_AAPCS_SwiftError_RegMask;
316 if (CC == CallingConv::SwiftTail) {
317 if (SCS)
318 report_fatal_error("ShadowCallStack attribute not supported with swifttail");
319 return CSR_AArch64_AAPCS_SwiftTail_RegMask;
320 }
322 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
323 : CSR_AArch64_RT_MostRegs_RegMask;
325 return SCS ? CSR_AArch64_RT_AllRegs_SCS_RegMask
326 : CSR_AArch64_RT_AllRegs_RegMask;
327
328 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
329}
330
332 const MachineFunction &MF) const {
334 return CSR_AArch64_AAPCS_RegMask;
335
336 return nullptr;
337}
338
340 if (TT.isOSDarwin())
341 return CSR_Darwin_AArch64_TLS_RegMask;
342
343 assert(TT.isOSBinFormatELF() && "Invalid target");
344 return CSR_AArch64_TLS_ELF_RegMask;
345}
346
348 const uint32_t **Mask) const {
349 uint32_t *UpdatedMask = MF.allocateRegMask();
350 unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
351 memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
352
353 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
355 for (MCPhysReg SubReg :
356 subregs_inclusive(AArch64::GPR64commonRegClass.getRegister(i))) {
357 // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
358 // register mask.
359 UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32);
360 }
361 }
362 }
363 *Mask = UpdatedMask;
364}
365
367 return CSR_AArch64_SMStartStop_RegMask;
368}
369
370const uint32_t *
372 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
373}
374
376 return CSR_AArch64_NoRegs_RegMask;
377}
378
379const uint32_t *
381 CallingConv::ID CC) const {
382 // This should return a register mask that is the same as that returned by
383 // getCallPreservedMask but that additionally preserves the register used for
384 // the first i64 argument (which must also be the register used to return a
385 // single i64 return value)
386 //
387 // In case that the calling convention does not use the same register for
388 // both, the function should return NULL (does not currently apply)
389 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
391 return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
392 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
393}
394
396 return CSR_AArch64_StackProbe_Windows_RegMask;
397}
398
399std::optional<std::string>
401 MCRegister PhysReg) const {
402 if (hasBasePointer(MF) && MCRegisterInfo::regsOverlap(PhysReg, AArch64::X19))
403 return std::string("X19 is used as the frame base pointer register.");
404
406 bool warn = false;
407 if (MCRegisterInfo::regsOverlap(PhysReg, AArch64::X13) ||
408 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X14) ||
409 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X23) ||
410 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X24) ||
411 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X28))
412 warn = true;
413
414 for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
415 if (MCRegisterInfo::regsOverlap(PhysReg, i))
416 warn = true;
417
418 if (warn)
419 return std::string(AArch64InstPrinter::getRegisterName(PhysReg)) +
420 " is clobbered by asynchronous signals when using Arm64EC.";
421 }
422
423 return {};
424}
425
428 const AArch64FrameLowering *TFI = getFrameLowering(MF);
429
430 // FIXME: avoid re-calculating this every time.
431 BitVector Reserved(getNumRegs());
432 markSuperRegs(Reserved, AArch64::WSP);
433 markSuperRegs(Reserved, AArch64::WZR);
434
435 if (TFI->hasFP(MF) || TT.isOSDarwin())
436 markSuperRegs(Reserved, AArch64::W29);
437
439 // x13, x14, x23, x24, x28, and v16-v31 are clobbered by asynchronous
440 // signals, so we can't ever use them.
441 markSuperRegs(Reserved, AArch64::W13);
442 markSuperRegs(Reserved, AArch64::W14);
443 markSuperRegs(Reserved, AArch64::W23);
444 markSuperRegs(Reserved, AArch64::W24);
445 markSuperRegs(Reserved, AArch64::W28);
446 for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
447 markSuperRegs(Reserved, i);
448 }
449
450 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
452 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
453 }
454
455 if (hasBasePointer(MF))
456 markSuperRegs(Reserved, AArch64::W19);
457
458 // SLH uses register W16/X16 as the taint register.
459 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
460 markSuperRegs(Reserved, AArch64::W16);
461
462 // FFR is modelled as global state that cannot be allocated.
463 if (MF.getSubtarget<AArch64Subtarget>().hasSVE())
464 Reserved.set(AArch64::FFR);
465
466 // SME tiles are not allocatable.
467 if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
468 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA))
469 Reserved.set(SubReg);
470 }
471
472 // VG cannot be allocated
473 Reserved.set(AArch64::VG);
474
475 if (MF.getSubtarget<AArch64Subtarget>().hasSME2()) {
476 for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true);
477 SubReg.isValid(); ++SubReg)
478 Reserved.set(*SubReg);
479 }
480
481 markSuperRegs(Reserved, AArch64::FPCR);
482 markSuperRegs(Reserved, AArch64::FPMR);
483 markSuperRegs(Reserved, AArch64::FPSR);
484
486 markSuperRegs(Reserved, AArch64::X27);
487 markSuperRegs(Reserved, AArch64::X28);
488 markSuperRegs(Reserved, AArch64::W27);
489 markSuperRegs(Reserved, AArch64::W28);
490 }
491
492 assert(checkAllSuperRegsMarked(Reserved));
493 return Reserved;
494}
495
499
500 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
502 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
503 }
504
506 // In order to prevent the register allocator from using LR, we need to
507 // mark it as reserved. However we don't want to keep it reserved throughout
508 // the pipeline since it prevents other infrastructure from reasoning about
509 // it's liveness. We use the NoVRegs property instead of IsSSA because
510 // IsSSA is removed before VirtRegRewriter runs.
511 if (!MF.getProperties().hasProperty(
513 markSuperRegs(Reserved, AArch64::LR);
514 }
515
516 assert(checkAllSuperRegsMarked(Reserved));
517 return Reserved;
518}
519
521 MCRegister Reg) const {
522 return getReservedRegs(MF)[Reg];
523}
524
526 MCRegister Reg) const {
527 return getStrictlyReservedRegs(MF)[Reg];
528}
529
531 return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
532 return isStrictlyReservedReg(MF, r);
533 });
534}
535
537 const MachineFunction &MF) const {
538 const Function &F = MF.getFunction();
539 F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
540 " function calls if any of the argument registers is reserved.")});
541}
542
544 MCRegister PhysReg) const {
545 // SLH uses register X16 as the taint register but it will fallback to a different
546 // method if the user clobbers it. So X16 is not reserved for inline asm but is
547 // for normal codegen.
548 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
549 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
550 return true;
551
552 // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
553 if (PhysReg == AArch64::ZA || PhysReg == AArch64::ZT0)
554 return true;
555
556 return !isReservedReg(MF, PhysReg);
557}
558
561 unsigned Kind) const {
562 return &AArch64::GPR64spRegClass;
563}
564
567 if (RC == &AArch64::CCRRegClass)
568 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
569 return RC;
570}
571
572unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
573
575 const MachineFrameInfo &MFI = MF.getFrameInfo();
576
577 // In the presence of variable sized objects or funclets, if the fixed stack
578 // size is large enough that referencing from the FP won't result in things
579 // being in range relatively often, we can use a base pointer to allow access
580 // from the other direction like the SP normally works.
581 //
582 // Furthermore, if both variable sized objects are present, and the
583 // stack needs to be dynamically re-aligned, the base pointer is the only
584 // reliable way to reference the locals.
585 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
586 if (hasStackRealignment(MF))
587 return true;
588
589 auto &ST = MF.getSubtarget<AArch64Subtarget>();
590 if (ST.hasSVE() || ST.isStreaming()) {
592 // Frames that have variable sized objects and scalable SVE objects,
593 // should always use a basepointer.
594 if (!AFI->hasCalculatedStackSizeSVE() || AFI->getStackSizeSVE())
595 return true;
596 }
597
598 // Conservatively estimate whether the negative offset from the frame
599 // pointer will be sufficient to reach. If a function has a smallish
600 // frame, it's less likely to have lots of spills and callee saved
601 // space, so it's all more likely to be within range of the frame pointer.
602 // If it's wrong, we'll materialize the constant and still get to the
603 // object; it's just suboptimal. Negative offsets use the unscaled
604 // load/store instructions, which have a 9-bit signed immediate.
605 return MFI.getLocalFrameSize() >= 256;
606 }
607
608 return false;
609}
610
612 MCRegister Reg) const {
615 bool IsVarArg = STI.isCallingConvWin64(MF.getFunction().getCallingConv(),
616 MF.getFunction().isVarArg());
617
618 auto HasReg = [](ArrayRef<MCRegister> RegList, MCRegister Reg) {
619 return llvm::is_contained(RegList, Reg);
620 };
621
622 switch (CC) {
623 default:
624 report_fatal_error("Unsupported calling convention.");
625 case CallingConv::GHC:
626 return HasReg(CC_AArch64_GHC_ArgRegs, Reg);
628 if (!MF.getFunction().isVarArg())
629 return HasReg(CC_AArch64_Preserve_None_ArgRegs, Reg);
630 [[fallthrough]];
631 case CallingConv::C:
639 if (STI.isTargetWindows()) {
640 if (IsVarArg)
641 return HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
642 switch (CC) {
643 default:
644 return HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
647 return HasReg(CC_AArch64_Win64PCS_Swift_ArgRegs, Reg) ||
648 HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
649 }
650 }
651 if (!STI.isTargetDarwin()) {
652 switch (CC) {
653 default:
654 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
657 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg) ||
658 HasReg(CC_AArch64_AAPCS_Swift_ArgRegs, Reg);
659 }
660 }
661 if (!IsVarArg) {
662 switch (CC) {
663 default:
664 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg);
667 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg) ||
668 HasReg(CC_AArch64_DarwinPCS_Swift_ArgRegs, Reg);
669 }
670 }
671 if (STI.isTargetILP32())
672 return HasReg(CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs, Reg);
673 return HasReg(CC_AArch64_DarwinPCS_VarArg_ArgRegs, Reg);
675 if (IsVarArg)
676 HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
677 return HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
679 return HasReg(CC_AArch64_Win64_CFGuard_Check_ArgRegs, Reg);
685 if (STI.isTargetWindows())
686 return HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
687 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
688 }
689}
690
693 const AArch64FrameLowering *TFI = getFrameLowering(MF);
694 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
695}
696
698 const MachineFunction &MF) const {
699 return true;
700}
701
703 const MachineFunction &MF) const {
704 return true;
705}
706
707bool
709 // This function indicates whether the emergency spillslot should be placed
710 // close to the beginning of the stackframe (closer to FP) or the end
711 // (closer to SP).
712 //
713 // The beginning works most reliably if we have a frame pointer.
714 // In the presence of any non-constant space between FP and locals,
715 // (e.g. in case of stack realignment or a scalable SVE area), it is
716 // better to use SP or BP.
717 const AArch64FrameLowering &TFI = *getFrameLowering(MF);
719 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() ||
721 "Expected SVE area to be calculated by this point");
722 return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE();
723}
724
726 const MachineFunction &MF) const {
727 return true;
728}
729
730bool
732 const MachineFrameInfo &MFI = MF.getFrameInfo();
734 return true;
735 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
736}
737
738/// needsFrameBaseReg - Returns true if the instruction's frame index
739/// reference would be better served by a base register other than FP
740/// or SP. Used by LocalStackFrameAllocation to determine which frame index
741/// references it should create new base registers for.
743 int64_t Offset) const {
744 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
745 assert(i < MI->getNumOperands() &&
746 "Instr doesn't have FrameIndex operand!");
747
748 // It's the load/store FI references that cause issues, as it can be difficult
749 // to materialize the offset if it won't fit in the literal field. Estimate
750 // based on the size of the local frame and some conservative assumptions
751 // about the rest of the stack frame (note, this is pre-regalloc, so
752 // we don't know everything for certain yet) whether this offset is likely
753 // to be out of range of the immediate. Return true if so.
754
755 // We only generate virtual base registers for loads and stores, so
756 // return false for everything else.
757 if (!MI->mayLoad() && !MI->mayStore())
758 return false;
759
760 // Without a virtual base register, if the function has variable sized
761 // objects, all fixed-size local references will be via the frame pointer,
762 // Approximate the offset and see if it's legal for the instruction.
763 // Note that the incoming offset is based on the SP value at function entry,
764 // so it'll be negative.
765 MachineFunction &MF = *MI->getParent()->getParent();
766 const AArch64FrameLowering *TFI = getFrameLowering(MF);
767 MachineFrameInfo &MFI = MF.getFrameInfo();
768
769 // Estimate an offset from the frame pointer.
770 // Conservatively assume all GPR callee-saved registers get pushed.
771 // FP, LR, X19-X28, D8-D15. 64-bits each.
772 int64_t FPOffset = Offset - 16 * 20;
773 // Estimate an offset from the stack pointer.
774 // The incoming offset is relating to the SP at the start of the function,
775 // but when we access the local it'll be relative to the SP after local
776 // allocation, so adjust our SP-relative offset by that allocation size.
777 Offset += MFI.getLocalFrameSize();
778 // Assume that we'll have at least some spill slots allocated.
779 // FIXME: This is a total SWAG number. We should run some statistics
780 // and pick a real one.
781 Offset += 128; // 128 bytes of spill slots
782
783 // If there is a frame pointer, try using it.
784 // The FP is only available if there is no dynamic realignment. We
785 // don't know for sure yet whether we'll need that, so we guess based
786 // on whether there are any local variables that would trigger it.
787 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
788 return false;
789
790 // If we can reference via the stack pointer or base pointer, try that.
791 // FIXME: This (and the code that resolves the references) can be improved
792 // to only disallow SP relative references in the live range of
793 // the VLA(s). In practice, it's unclear how much difference that
794 // would make, but it may be worth doing.
795 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
796 return false;
797
798 // If even offset 0 is illegal, we don't want a virtual base register.
799 if (!isFrameOffsetLegal(MI, AArch64::SP, 0))
800 return false;
801
802 // The offset likely isn't legal; we want to allocate a virtual base register.
803 return true;
804}
805
807 Register BaseReg,
808 int64_t Offset) const {
809 assert(MI && "Unable to get the legal offset for nil instruction.");
812}
813
814/// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
815/// at the beginning of the basic block.
818 int FrameIdx,
819 int64_t Offset) const {
821 DebugLoc DL; // Defaults to "unknown"
822 if (Ins != MBB->end())
823 DL = Ins->getDebugLoc();
824 const MachineFunction &MF = *MBB->getParent();
825 const AArch64InstrInfo *TII =
826 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
827 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
829 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
830 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
831 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
832
833 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
834 .addFrameIndex(FrameIdx)
835 .addImm(Offset)
836 .addImm(Shifter);
837
838 return BaseReg;
839}
840
842 int64_t Offset) const {
843 // ARM doesn't need the general 64-bit offsets
845
846 unsigned i = 0;
847 while (!MI.getOperand(i).isFI()) {
848 ++i;
849 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
850 }
851
852 const MachineFunction *MF = MI.getParent()->getParent();
853 const AArch64InstrInfo *TII =
854 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
855 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
856 assert(Done && "Unable to resolve frame index!");
857 (void)Done;
858}
859
860// Create a scratch register for the frame index elimination in an instruction.
861// This function has special handling of stack tagging loop pseudos, in which
862// case it can also change the instruction opcode.
863static Register
865 const AArch64InstrInfo *TII) {
866 // ST*Gloop have a reserved scratch register in operand 1. Use it, and also
867 // replace the instruction with the writeback variant because it will now
868 // satisfy the operand constraints for it.
869 Register ScratchReg;
870 if (MI.getOpcode() == AArch64::STGloop ||
871 MI.getOpcode() == AArch64::STZGloop) {
872 assert(FIOperandNum == 3 &&
873 "Wrong frame index operand for STGloop/STZGloop");
874 unsigned Op = MI.getOpcode() == AArch64::STGloop ? AArch64::STGloop_wback
875 : AArch64::STZGloop_wback;
876 ScratchReg = MI.getOperand(1).getReg();
877 MI.getOperand(3).ChangeToRegister(ScratchReg, false, false, true);
878 MI.setDesc(TII->get(Op));
879 MI.tieOperands(1, 3);
880 } else {
881 ScratchReg =
882 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
883 MI.getOperand(FIOperandNum)
884 .ChangeToRegister(ScratchReg, false, false, true);
885 }
886 return ScratchReg;
887}
888
890 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
891 // The smallest scalable element supported by scaled SVE addressing
892 // modes are predicates, which are 2 scalable bytes in size. So the scalable
893 // byte offset must always be a multiple of 2.
894 assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset");
895
896 // Add fixed-sized offset using existing DIExpression interface.
897 DIExpression::appendOffset(Ops, Offset.getFixed());
898
899 unsigned VG = getDwarfRegNum(AArch64::VG, true);
900 int64_t VGSized = Offset.getScalable() / 2;
901 if (VGSized > 0) {
902 Ops.push_back(dwarf::DW_OP_constu);
903 Ops.push_back(VGSized);
904 Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
905 Ops.push_back(dwarf::DW_OP_mul);
906 Ops.push_back(dwarf::DW_OP_plus);
907 } else if (VGSized < 0) {
908 Ops.push_back(dwarf::DW_OP_constu);
909 Ops.push_back(-VGSized);
910 Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
911 Ops.push_back(dwarf::DW_OP_mul);
912 Ops.push_back(dwarf::DW_OP_minus);
913 }
914}
915
917 int SPAdj, unsigned FIOperandNum,
918 RegScavenger *RS) const {
919 assert(SPAdj == 0 && "Unexpected");
920
921 MachineInstr &MI = *II;
922 MachineBasicBlock &MBB = *MI.getParent();
924 const MachineFrameInfo &MFI = MF.getFrameInfo();
925 const AArch64InstrInfo *TII =
926 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
927 const AArch64FrameLowering *TFI = getFrameLowering(MF);
928 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
929 bool Tagged =
930 MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
931 Register FrameReg;
932
933 // Special handling of dbg_value, stackmap patchpoint statepoint instructions.
934 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
935 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
936 MI.getOpcode() == TargetOpcode::STATEPOINT) {
938 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
939 /*PreferFP=*/true,
940 /*ForSimm=*/false);
941 Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
942 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
943 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
944 return false;
945 }
946
947 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
948 MachineOperand &FI = MI.getOperand(FIOperandNum);
950 assert(!Offset.getScalable() &&
951 "Frame offsets with a scalable component are not supported");
952 FI.ChangeToImmediate(Offset.getFixed());
953 return false;
954 }
955
957 if (MI.getOpcode() == AArch64::TAGPstack) {
958 // TAGPstack must use the virtual frame register in its 3rd operand.
960 FrameReg = MI.getOperand(3).getReg();
963 } else if (Tagged) {
965 MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize());
966 if (MFI.hasVarSizedObjects() ||
967 isAArch64FrameOffsetLegal(MI, SPOffset, nullptr, nullptr, nullptr) !=
969 // Can't update to SP + offset in place. Precalculate the tagged pointer
970 // in a scratch register.
972 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
973 Register ScratchReg =
974 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
975 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
976 TII);
977 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
978 .addReg(ScratchReg)
979 .addReg(ScratchReg)
980 .addImm(0);
981 MI.getOperand(FIOperandNum)
982 .ChangeToRegister(ScratchReg, false, false, true);
983 return false;
984 }
985 FrameReg = AArch64::SP;
987 (int64_t)MFI.getStackSize());
988 } else {
990 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
991 }
992
993 // Modify MI as necessary to handle as much of 'Offset' as possible
994 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
995 return true;
996
997 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
998 "Emergency spill slot is out of reach");
999
1000 // If we get here, the immediate doesn't fit into the instruction. We folded
1001 // as much as possible above. Handle the rest, providing a register that is
1002 // SP+LargeImm.
1003 Register ScratchReg =
1005 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
1006 return false;
1007}
1008
1010 MachineFunction &MF) const {
1011 const AArch64FrameLowering *TFI = getFrameLowering(MF);
1012
1013 switch (RC->getID()) {
1014 default:
1015 return 0;
1016 case AArch64::GPR32RegClassID:
1017 case AArch64::GPR32spRegClassID:
1018 case AArch64::GPR32allRegClassID:
1019 case AArch64::GPR64spRegClassID:
1020 case AArch64::GPR64allRegClassID:
1021 case AArch64::GPR64RegClassID:
1022 case AArch64::GPR32commonRegClassID:
1023 case AArch64::GPR64commonRegClassID:
1024 return 32 - 1 // XZR/SP
1025 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
1027 - hasBasePointer(MF); // X19
1028 case AArch64::FPR8RegClassID:
1029 case AArch64::FPR16RegClassID:
1030 case AArch64::FPR32RegClassID:
1031 case AArch64::FPR64RegClassID:
1032 case AArch64::FPR128RegClassID:
1033 return 32;
1034
1035 case AArch64::MatrixIndexGPR32_8_11RegClassID:
1036 case AArch64::MatrixIndexGPR32_12_15RegClassID:
1037 return 4;
1038
1039 case AArch64::DDRegClassID:
1040 case AArch64::DDDRegClassID:
1041 case AArch64::DDDDRegClassID:
1042 case AArch64::QQRegClassID:
1043 case AArch64::QQQRegClassID:
1044 case AArch64::QQQQRegClassID:
1045 return 32;
1046
1047 case AArch64::FPR128_loRegClassID:
1048 case AArch64::FPR64_loRegClassID:
1049 case AArch64::FPR16_loRegClassID:
1050 return 16;
1051 case AArch64::FPR128_0to7RegClassID:
1052 return 8;
1053 }
1054}
1055
1057 const MachineFunction &MF) const {
1058 const auto &MFI = MF.getFrameInfo();
1059 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
1060 return AArch64::SP;
1061 else if (hasStackRealignment(MF))
1062 return getBaseRegister();
1063 return getFrameRegister(MF);
1064}
1065
1066/// SrcRC and DstRC will be morphed into NewRC if this returns true
1068 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
1069 const TargetRegisterClass *DstRC, unsigned DstSubReg,
1070 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
1071 MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
1072
1073 if (MI->isCopy() &&
1074 ((DstRC->getID() == AArch64::GPR64RegClassID) ||
1075 (DstRC->getID() == AArch64::GPR64commonRegClassID)) &&
1076 MI->getOperand(0).getSubReg() && MI->getOperand(1).getSubReg())
1077 // Do not coalesce in the case of a 32-bit subregister copy
1078 // which implements a 32 to 64 bit zero extension
1079 // which relies on the upper 32 bits being zeroed.
1080 return false;
1081
1082 auto IsCoalescerBarrier = [](const MachineInstr &MI) {
1083 switch (MI.getOpcode()) {
1084 case AArch64::COALESCER_BARRIER_FPR16:
1085 case AArch64::COALESCER_BARRIER_FPR32:
1086 case AArch64::COALESCER_BARRIER_FPR64:
1087 case AArch64::COALESCER_BARRIER_FPR128:
1088 return true;
1089 default:
1090 return false;
1091 }
1092 };
1093
1094 // For calls that temporarily have to toggle streaming mode as part of the
1095 // call-sequence, we need to be more careful when coalescing copy instructions
1096 // so that we don't end up coalescing the NEON/FP result or argument register
1097 // with a whole Z-register, such that after coalescing the register allocator
1098 // will try to spill/reload the entire Z register.
1099 //
1100 // We do this by checking if the node has any defs/uses that are
1101 // COALESCER_BARRIER pseudos. These are 'nops' in practice, but they exist to
1102 // instruct the coalescer to avoid coalescing the copy.
1103 if (MI->isCopy() && SubReg != DstSubReg &&
1104 (AArch64::ZPRRegClass.hasSubClassEq(DstRC) ||
1105 AArch64::ZPRRegClass.hasSubClassEq(SrcRC))) {
1106 unsigned SrcReg = MI->getOperand(1).getReg();
1107 if (any_of(MRI.def_instructions(SrcReg), IsCoalescerBarrier))
1108 return false;
1109 unsigned DstReg = MI->getOperand(0).getReg();
1110 if (any_of(MRI.use_nodbg_instructions(DstReg), IsCoalescerBarrier))
1111 return false;
1112 }
1113
1114 return true;
1115}
1116
1118 MCRegister R) const {
1119 return R == AArch64::VG;
1120}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
static Register createScratchRegisterForInstruction(MachineInstr &MI, unsigned FIOperandNum, const AArch64InstrInfo *TII)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
uint64_t IntrinsicInst * II
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:195
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
AArch64RegisterInfo(const Triple &TT)
bool isAnyArgRegReserved(const MachineFunction &MF) const
void emitReservedArgRegCallError(const MachineFunction &MF) const
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getTLSCallPreservedMask() const
const uint32_t * getNoPreservedMask() const override
Register getFrameRegister(const MachineFunction &MF) const override
bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * SMEABISupportRoutinesCallPreservedMaskFromX0() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
unsigned getLocalAddressRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
const uint32_t * getSMStartStopCallPreservedMask() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool isLRReservedForRA() const
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
const AArch64TargetLowering * getTargetLowering() const override
bool isXRegCustomCalleeSaved(size_t i) const
bool isXRegisterReserved(size_t i) const
bool isCallingConvWin64(CallingConv::ID CC, bool IsVarArg) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:281
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:357
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:232
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:743
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSubRegIterator enumerates all sub-registers of Reg.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
int64_t getLocalFrameSize() const
Get the size of the local object blob.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned getID() const
Return the register class ID number.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:558
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
@ AArch64_VectorCall
Used between AArch64 Advanced SIMD functions.
Definition: CallingConv.h:221
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ AArch64_SVE_VectorCall
Used between AArch64 SVE functions.
Definition: CallingConv.h:224
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:82
@ PreserveMost
Used for runtime calls that preserves most registers.
Definition: CallingConv.h:63
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
Definition: CallingConv.h:60
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2
Preserve X2-X15, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:241
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0
Preserve X0-X13, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:238
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1
Preserve X1-X15, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:271
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ PreserveNone
Used for runtime calls that preserves none general registers.
Definition: CallingConv.h:90
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:159
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ GRAAL
Used by GraalVM. Two additional registers are reserved.
Definition: CallingConv.h:255
@ ARM64EC_Thunk_X64
Calling convention used in the ARM64EC ABI to implement calls between x64 code and thunks.
Definition: CallingConv.h:260
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
@ Done
Definition: Threading.h:61
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1886