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36 #define GET_REGINFO_TARGET_DESC
37 #include "AArch64GenRegisterInfo.inc"
50 unsigned &RegToUseForCFI)
const {
55 RegToUseForCFI = getSubReg(
Reg, AArch64::dsub);
56 for (
int I = 0; CSR_AArch64_AAPCS_SaveList[
I]; ++
I) {
57 if (CSR_AArch64_AAPCS_SaveList[
I] == RegToUseForCFI)
69 return isa<ScalableVectorType>(
F.getReturnType()) ||
71 return isa<ScalableVectorType>(Arg.getType());
77 assert(MF &&
"Invalid MachineFunction pointer.");
82 return CSR_AArch64_NoRegs_SaveList;
84 return CSR_AArch64_AllRegs_SaveList;
92 return CSR_Win_AArch64_CFGuard_Check_SaveList;
94 return CSR_Win_AArch64_AAPCS_SaveList;
96 return CSR_AArch64_AAVPCS_SaveList;
98 return CSR_AArch64_SVE_AAPCS_SaveList;
102 Attribute::SwiftError))
103 return CSR_AArch64_AAPCS_SwiftError_SaveList;
105 return CSR_AArch64_AAPCS_SwiftTail_SaveList;
107 return CSR_AArch64_RT_MostRegs_SaveList;
111 return CSR_AArch64_AAPCS_X18_SaveList;
113 return CSR_AArch64_SVE_AAPCS_SaveList;
114 return CSR_AArch64_AAPCS_SaveList;
119 assert(MF &&
"Invalid MachineFunction pointer.");
121 "Invalid subtarget for getDarwinCalleeSavedRegs");
125 "Calling convention CFGuard_Check is unsupported on Darwin.");
127 return CSR_Darwin_AArch64_AAVPCS_SaveList;
130 "Calling convention SVE_VectorCall is unsupported on Darwin.");
133 ? CSR_Darwin_AArch64_CXX_TLS_PE_SaveList
134 : CSR_Darwin_AArch64_CXX_TLS_SaveList;
138 Attribute::SwiftError))
139 return CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList;
141 return CSR_Darwin_AArch64_AAPCS_SwiftTail_SaveList;
143 return CSR_Darwin_AArch64_RT_MostRegs_SaveList;
144 return CSR_Darwin_AArch64_AAPCS_SaveList;
149 assert(MF &&
"Invalid MachineFunction pointer.");
152 return CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList;
161 UpdatedCSRs.push_back(*
I);
163 for (
size_t i = 0;
i < AArch64::GPR64commonRegClass.getNumRegs(); ++
i) {
165 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(
i));
169 UpdatedCSRs.push_back(0);
175 unsigned Idx)
const {
177 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
178 return &AArch64::FPR32RegClass;
179 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
180 return &AArch64::FPR64RegClass;
183 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
190 "Invalid subtarget for getDarwinCallPreservedMask");
193 return CSR_Darwin_AArch64_CXX_TLS_RegMask;
195 return CSR_Darwin_AArch64_AAVPCS_RegMask;
198 "Calling convention SVE_VectorCall is unsupported on Darwin.");
201 "Calling convention CFGuard_Check is unsupported on Darwin.");
206 return CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask;
208 return CSR_Darwin_AArch64_AAPCS_SwiftTail_RegMask;
210 return CSR_Darwin_AArch64_RT_MostRegs_RegMask;
211 return CSR_Darwin_AArch64_AAPCS_RegMask;
220 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
222 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
232 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
234 return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
235 : CSR_AArch64_SVE_AAPCS_RegMask;
237 return CSR_Win_AArch64_CFGuard_Check_RegMask;
241 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
242 : CSR_AArch64_AAPCS_SwiftError_RegMask;
246 return CSR_AArch64_AAPCS_SwiftTail_RegMask;
249 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
250 : CSR_AArch64_RT_MostRegs_RegMask;
252 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
258 return CSR_AArch64_AAPCS_RegMask;
265 return CSR_Darwin_AArch64_TLS_RegMask;
268 return CSR_AArch64_TLS_ELF_RegMask;
275 memcpy(UpdatedMask, *
Mask,
sizeof(UpdatedMask[0]) * RegMaskSize);
277 for (
size_t i = 0;
i < AArch64::GPR64commonRegClass.getNumRegs(); ++
i) {
292 return CSR_AArch64_NoRegs_RegMask;
307 return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
308 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
312 return CSR_AArch64_StackProbe_Windows_RegMask;
321 markSuperRegs(Reserved, AArch64::WSP);
322 markSuperRegs(Reserved, AArch64::WZR);
325 markSuperRegs(Reserved, AArch64::W29);
327 for (
size_t i = 0;
i < AArch64::GPR32commonRegClass.getNumRegs(); ++
i) {
329 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(
i));
333 markSuperRegs(Reserved, AArch64::W19);
337 markSuperRegs(Reserved, AArch64::W16);
339 assert(checkAllSuperRegsMarked(Reserved));
358 " function calls if any of the argument registers is reserved.")});
367 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
372 unsigned Kind)
const {
373 return &AArch64::GPR64spRegClass;
378 if (RC == &AArch64::CCRRegClass)
379 return &AArch64::GPR64RegClass;
397 if (hasStackRealignment(MF))
424 return TFI->
hasFP(MF) ? AArch64::FP : AArch64::SP;
451 "Expected SVE area to be calculated by this point");
473 int64_t Offset)
const {
474 for (
unsigned i = 0; !
MI->getOperand(
i).isFI(); ++
i)
475 assert(i < MI->getNumOperands() &&
476 "Instr doesn't have FrameIndex operand!");
487 if (!
MI->mayLoad() && !
MI->mayStore())
502 int64_t FPOffset = Offset - 16 * 20;
538 int64_t Offset)
const {
539 assert(
MI &&
"Unable to get the legal offset for nil instruction.");
549 int64_t Offset)
const {
553 DL =
Ins->getDebugLoc();
572 int64_t Offset)
const {
577 while (!
MI.getOperand(
i).isFI()) {
579 assert(
i <
MI.getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
586 assert(Done &&
"Unable to resolve frame index!");
600 if (
MI.getOpcode() == AArch64::STGloop ||
601 MI.getOpcode() == AArch64::STZGloop) {
602 assert(FIOperandNum == 3 &&
603 "Wrong frame index operand for STGloop/STZGloop");
604 unsigned Op =
MI.getOpcode() == AArch64::STGloop ? AArch64::STGloop_wback
605 : AArch64::STZGloop_wback;
606 ScratchReg =
MI.getOperand(1).getReg();
607 MI.getOperand(3).ChangeToRegister(ScratchReg,
false,
false,
true);
609 MI.tieOperands(1, 3);
612 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
613 MI.getOperand(FIOperandNum)
614 .ChangeToRegister(ScratchReg,
false,
false,
true);
624 assert(Offset.getScalable() % 2 == 0 &&
"Invalid frame offset");
630 int64_t VGSized = Offset.getScalable() / 2;
632 Ops.push_back(dwarf::DW_OP_constu);
633 Ops.push_back(VGSized);
634 Ops.
append({dwarf::DW_OP_bregx, VG, 0ULL});
635 Ops.push_back(dwarf::DW_OP_mul);
636 Ops.push_back(dwarf::DW_OP_plus);
637 }
else if (VGSized < 0) {
638 Ops.push_back(dwarf::DW_OP_constu);
639 Ops.push_back(-VGSized);
640 Ops.
append({dwarf::DW_OP_bregx, VG, 0ULL});
641 Ops.push_back(dwarf::DW_OP_mul);
642 Ops.push_back(dwarf::DW_OP_minus);
647 int SPAdj,
unsigned FIOperandNum,
649 assert(SPAdj == 0 &&
"Unexpected");
658 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
664 if (
MI.getOpcode() == TargetOpcode::STACKMAP ||
665 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
666 MI.getOpcode() == TargetOpcode::STATEPOINT) {
672 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false );
673 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
677 if (
MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
680 assert(!Offset.getScalable() &&
681 "Frame offsets with a scalable component are not supported");
687 if (
MI.getOpcode() == AArch64::TAGPstack) {
690 FrameReg =
MI.getOperand(3).getReg();
711 MI.getOperand(FIOperandNum)
712 .ChangeToRegister(ScratchReg,
false,
false,
true);
715 FrameReg = AArch64::SP;
728 "Emergency spill slot is out of reach");
742 switch (RC->
getID()) {
745 case AArch64::GPR32RegClassID:
746 case AArch64::GPR32spRegClassID:
747 case AArch64::GPR32allRegClassID:
748 case AArch64::GPR64spRegClassID:
749 case AArch64::GPR64allRegClassID:
750 case AArch64::GPR64RegClassID:
751 case AArch64::GPR32commonRegClassID:
752 case AArch64::GPR64commonRegClassID:
757 case AArch64::FPR8RegClassID:
758 case AArch64::FPR16RegClassID:
759 case AArch64::FPR32RegClassID:
760 case AArch64::FPR64RegClassID:
761 case AArch64::FPR128RegClassID:
764 case AArch64::MatrixIndexGPR32_12_15RegClassID:
767 case AArch64::DDRegClassID:
768 case AArch64::DDDRegClassID:
769 case AArch64::DDDDRegClassID:
770 case AArch64::QQRegClassID:
771 case AArch64::QQQRegClassID:
772 case AArch64::QQQQRegClassID:
775 case AArch64::FPR128_loRegClassID:
776 case AArch64::FPR64_loRegClassID:
777 case AArch64::FPR16_loRegClassID:
787 else if (hasStackRealignment(MF))
798 ((DstRC->
getID() == AArch64::GPR64RegClassID) ||
799 (DstRC->
getID() == AArch64::GPR64commonRegClassID)) &&
800 MI->getOperand(0).getSubReg() &&
MI->getOperand(1).getSubReg())
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
This class represents an incoming formal argument to a Function.
bool isTargetWindows() const
static Register createScratchRegisterForInstruction(MachineInstr &MI, unsigned FIOperandNum, const AArch64InstrInfo *TII)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
Diagnostic information for unsupported feature in backend.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
return AArch64::GPR64RegClass contains(Reg)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
unsigned getBaseRegister() const
Reg
All possible values of the reg field in the ModR/M byte.
bool isAnyArgRegReserved(const MachineFunction &MF) const
const uint32_t * getNoPreservedMask() const override
bool isTargetDarwin() const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Triple - Helper class for working with autoconf configuration names.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
ScalarTy getFixed() const
Register getFrameRegister(const MachineFunction &MF) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool isXRegCustomCalleeSaved(size_t i) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
const AArch64TargetLowering * getTargetLowering() const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
bool cannotEliminateFrame(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
static bool hasSVEArgsOrReturn(const MachineFunction *MF)
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const HexagonInstrInfo * TII
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
AttributeList getAttributes() const
Return the attribute list for this Function.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
@ AArch64FrameOffsetIsLegal
Offset is legal.
StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
AArch64RegisterInfo(const Triple &TT)
const MachineInstrBuilder & addFrameIndex(int Idx) const
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Representation of each machine instruction.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
unsigned getTaggedBasePointerOffset() const
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
bool isConstantPhysReg(MCRegister PhysReg) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isTargetLinux() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
BitVector getReservedRegs(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
bool isXRegisterReserved(size_t i) const
unsigned getLocalAddressRegister(const MachineFunction &MF) const
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool hasCalculatedStackSizeSVE() const
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
@ AArch64_SVE_VectorCall
Calling convention between AArch64 SVE functions.
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
void emitReservedArgRegCallError(const MachineFunction &MF) const
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
unsigned getNumXRegisterReserved() const
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Function & getFunction()
Return the LLVM function that this machine code represents.
uint64_t getStackSizeSVE() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
bool hasEHFunclets() const
MCSubRegIterator enumerates all sub-registers of Reg.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
const uint32_t * getTLSCallPreservedMask() const
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool hasBasePointer(const MachineFunction &MF) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
Wrapper class representing physical registers. Should be passed by value.