61#define GET_INSTRINFO_CTOR_DTOR
62#include "AArch64GenInstrInfo.inc"
66 cl::desc(
"Restrict range of TB[N]Z instructions (DEBUG)"));
70 cl::desc(
"Restrict range of CB[N]Z instructions (DEBUG)"));
74 cl::desc(
"Restrict range of Bcc instructions (DEBUG)"));
78 cl::desc(
"Restrict range of B instructions (DEBUG)"));
83 RI(STI.getTargetTriple()), Subtarget(STI) {}
94 auto Op =
MI.getOpcode();
95 if (
Op == AArch64::INLINEASM ||
Op == AArch64::INLINEASM_BR)
96 return getInlineAsmLength(
MI.getOperand(0).getSymbolName(), *MAI);
100 if (
MI.isMetaInstruction())
105 unsigned NumBytes = 0;
111 switch (
Desc.getOpcode()) {
114 return Desc.getSize();
121 case TargetOpcode::STACKMAP:
124 assert(NumBytes % 4 == 0 &&
"Invalid number of NOP bytes requested!");
126 case TargetOpcode::PATCHPOINT:
129 assert(NumBytes % 4 == 0 &&
"Invalid number of NOP bytes requested!");
131 case TargetOpcode::STATEPOINT:
133 assert(NumBytes % 4 == 0 &&
"Invalid number of NOP bytes requested!");
138 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
143 F.getFnAttributeAsParsedInteger(
"patchable-function-entry", 9) * 4;
145 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
146 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
150 case TargetOpcode::PATCHABLE_EVENT_CALL:
156 NumBytes =
MI.getOperand(1).getImm();
158 case TargetOpcode::BUNDLE:
159 NumBytes = getInstBundleLength(
MI);
166unsigned AArch64InstrInfo::getInstBundleLength(
const MachineInstr &
MI)
const {
170 while (++
I != E &&
I->isInsideBundle()) {
171 assert(!
I->isBundle() &&
"No nested bundle!");
230 int64_t BrOffset)
const {
232 assert(Bits >= 3 &&
"max branch displacement must be enough to jump"
233 "over conditional branch expansion");
234 return isIntN(Bits, BrOffset / 4);
239 switch (
MI.getOpcode()) {
243 return MI.getOperand(0).getMBB();
248 return MI.getOperand(2).getMBB();
254 return MI.getOperand(1).getMBB();
264 assert(RS &&
"RegScavenger required for long branching");
266 "new block should be inserted for expanding unconditional branch");
269 "restore block should be inserted for restoring clobbered registers");
274 if (!isInt<33>(BrOffset))
276 "Branch offsets outside of the signed 33-bit range not supported");
290 constexpr Register Reg = AArch64::X16;
292 insertUnconditionalBranch(
MBB, &NewDestBB,
DL);
300 if (Scavenged != AArch64::NoRegister &&
302 buildIndirectBranch(Scavenged, NewDestBB);
312 "Unable to insert indirect branch inside function that has red zone");
335 bool AllowModify)
const {
342 if (
I->getOpcode() == AArch64::SpeculationBarrierISBDSBEndBB ||
343 I->getOpcode() == AArch64::SpeculationBarrierSBEndBB) {
347 if (!isUnpredicatedTerminator(*
I))
354 unsigned LastOpc = LastInst->
getOpcode();
355 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
370 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
377 LastInst = SecondLastInst;
379 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
384 SecondLastInst = &*
I;
385 SecondLastOpc = SecondLastInst->
getOpcode();
396 LastInst = SecondLastInst;
398 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
400 "unreachable unconditional branches removed above");
409 SecondLastInst = &*
I;
410 SecondLastOpc = SecondLastInst->
getOpcode();
414 if (SecondLastInst &&
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
430 I->eraseFromParent();
439 I->eraseFromParent();
448 MachineBranchPredicate &MBP,
449 bool AllowModify)
const {
459 if (
I->getOpcode() == AArch64::SpeculationBarrierISBDSBEndBB ||
460 I->getOpcode() == AArch64::SpeculationBarrierSBEndBB) {
464 if (!isUnpredicatedTerminator(*
I))
469 unsigned LastOpc = LastInst->
getOpcode();
484 assert(MBP.TrueDest &&
"expected!");
487 MBP.ConditionDef =
nullptr;
488 MBP.SingleUseCondition =
false;
492 MBP.Predicate = LastOpc == AArch64::CBNZX ? MachineBranchPredicate::PRED_NE
493 : MachineBranchPredicate::PRED_EQ;
499 if (
Cond[0].getImm() != -1) {
505 switch (
Cond[1].getImm()) {
509 Cond[1].setImm(AArch64::CBNZW);
512 Cond[1].setImm(AArch64::CBZW);
515 Cond[1].setImm(AArch64::CBNZX);
518 Cond[1].setImm(AArch64::CBZX);
521 Cond[1].setImm(AArch64::TBNZW);
524 Cond[1].setImm(AArch64::TBZW);
527 Cond[1].setImm(AArch64::TBNZX);
530 Cond[1].setImm(AArch64::TBZX);
539 int *BytesRemoved)
const {
549 I->eraseFromParent();
566 I->eraseFromParent();
573void AArch64InstrInfo::instantiateCondBranch(
576 if (
Cond[0].getImm() != -1) {
594 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
633 unsigned *NewVReg =
nullptr) {
638 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(
MRI.getRegClass(VReg));
641 unsigned SrcOpNum = 0;
643 case AArch64::ADDSXri:
644 case AArch64::ADDSWri:
650 case AArch64::ADDXri:
651 case AArch64::ADDWri:
657 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
660 case AArch64::ORNXrr:
661 case AArch64::ORNWrr: {
664 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
667 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
671 case AArch64::SUBSXrr:
672 case AArch64::SUBSWrr:
678 case AArch64::SUBXrr:
679 case AArch64::SUBWrr: {
682 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
685 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
691 assert(Opc && SrcOpNum &&
"Missing parameters");
703 int &FalseCycles)
const {
707 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
714 if (!RI.getCommonSubClass(RC,
MRI.getRegClass(DstReg)))
718 unsigned ExtraCondLat =
Cond.size() != 1;
722 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
723 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
725 CondCycles = 1 + ExtraCondLat;
726 TrueCycles = FalseCycles = 1;
736 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
737 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
738 CondCycles = 5 + ExtraCondLat;
739 TrueCycles = FalseCycles = 2;
756 switch (
Cond.size()) {
765 switch (
Cond[1].getImm()) {
788 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
794 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
804 switch (
Cond[1].getImm()) {
817 if (
Cond[1].getImm() == AArch64::TBZW ||
Cond[1].getImm() == AArch64::TBNZW)
833 bool TryFold =
false;
834 if (
MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
835 RC = &AArch64::GPR64RegClass;
836 Opc = AArch64::CSELXr;
838 }
else if (
MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
839 RC = &AArch64::GPR32RegClass;
840 Opc = AArch64::CSELWr;
842 }
else if (
MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
843 RC = &AArch64::FPR64RegClass;
844 Opc = AArch64::FCSELDrrr;
845 }
else if (
MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
846 RC = &AArch64::FPR32RegClass;
847 Opc = AArch64::FCSELSrrr;
849 assert(RC &&
"Unsupported regclass");
853 unsigned NewVReg = 0;
868 MRI.clearKillFlags(NewVReg);
873 MRI.constrainRegClass(TrueReg, RC);
874 MRI.constrainRegClass(FalseReg, RC);
889 assert(BitSize == 64 &&
"Only bit sizes of 32 or 64 allowed");
894 return Is.
size() <= 2;
900 if (Subtarget.hasExynosCheapAsMoveHandling()) {
901 if (isExynosCheapAsMove(
MI))
903 return MI.isAsCheapAsAMove();
906 switch (
MI.getOpcode()) {
908 return MI.isAsCheapAsAMove();
910 case AArch64::ADDWrs:
911 case AArch64::ADDXrs:
912 case AArch64::SUBWrs:
913 case AArch64::SUBXrs:
914 return Subtarget.hasALULSLFast() &&
MI.getOperand(3).getImm() <= 4;
919 case AArch64::MOVi32imm:
921 case AArch64::MOVi64imm:
927 switch (
MI.getOpcode()) {
931 case AArch64::ADDWrs:
932 case AArch64::ADDXrs:
933 case AArch64::ADDSWrs:
934 case AArch64::ADDSXrs: {
935 unsigned Imm =
MI.getOperand(3).getImm();
942 case AArch64::ADDWrx:
943 case AArch64::ADDXrx:
944 case AArch64::ADDXrx64:
945 case AArch64::ADDSWrx:
946 case AArch64::ADDSXrx:
947 case AArch64::ADDSXrx64: {
948 unsigned Imm =
MI.getOperand(3).getImm();
960 case AArch64::SUBWrs:
961 case AArch64::SUBSWrs: {
962 unsigned Imm =
MI.getOperand(3).getImm();
964 return ShiftVal == 0 ||
968 case AArch64::SUBXrs:
969 case AArch64::SUBSXrs: {
970 unsigned Imm =
MI.getOperand(3).getImm();
972 return ShiftVal == 0 ||
976 case AArch64::SUBWrx:
977 case AArch64::SUBXrx:
978 case AArch64::SUBXrx64:
979 case AArch64::SUBSWrx:
980 case AArch64::SUBSXrx:
981 case AArch64::SUBSXrx64: {
982 unsigned Imm =
MI.getOperand(3).getImm();
994 case AArch64::LDRBBroW:
995 case AArch64::LDRBBroX:
996 case AArch64::LDRBroW:
997 case AArch64::LDRBroX:
998 case AArch64::LDRDroW:
999 case AArch64::LDRDroX:
1000 case AArch64::LDRHHroW:
1001 case AArch64::LDRHHroX:
1002 case AArch64::LDRHroW:
1003 case AArch64::LDRHroX:
1004 case AArch64::LDRQroW:
1005 case AArch64::LDRQroX:
1006 case AArch64::LDRSBWroW:
1007 case AArch64::LDRSBWroX:
1008 case AArch64::LDRSBXroW:
1009 case AArch64::LDRSBXroX:
1010 case AArch64::LDRSHWroW:
1011 case AArch64::LDRSHWroX:
1012 case AArch64::LDRSHXroW:
1013 case AArch64::LDRSHXroX:
1014 case AArch64::LDRSWroW:
1015 case AArch64::LDRSWroX:
1016 case AArch64::LDRSroW:
1017 case AArch64::LDRSroX:
1018 case AArch64::LDRWroW:
1019 case AArch64::LDRWroX:
1020 case AArch64::LDRXroW:
1021 case AArch64::LDRXroX:
1022 case AArch64::PRFMroW:
1023 case AArch64::PRFMroX:
1024 case AArch64::STRBBroW:
1025 case AArch64::STRBBroX:
1026 case AArch64::STRBroW:
1027 case AArch64::STRBroX:
1028 case AArch64::STRDroW:
1029 case AArch64::STRDroX:
1030 case AArch64::STRHHroW:
1031 case AArch64::STRHHroX:
1032 case AArch64::STRHroW:
1033 case AArch64::STRHroX:
1034 case AArch64::STRQroW:
1035 case AArch64::STRQroX:
1036 case AArch64::STRSroW:
1037 case AArch64::STRSroX:
1038 case AArch64::STRWroW:
1039 case AArch64::STRWroX:
1040 case AArch64::STRXroW:
1041 case AArch64::STRXroX: {
1042 unsigned IsSigned =
MI.getOperand(3).getImm();
1049 unsigned Opc =
MI.getOpcode();
1053 case AArch64::SEH_StackAlloc:
1054 case AArch64::SEH_SaveFPLR:
1055 case AArch64::SEH_SaveFPLR_X:
1056 case AArch64::SEH_SaveReg:
1057 case AArch64::SEH_SaveReg_X:
1058 case AArch64::SEH_SaveRegP:
1059 case AArch64::SEH_SaveRegP_X:
1060 case AArch64::SEH_SaveFReg:
1061 case AArch64::SEH_SaveFReg_X:
1062 case AArch64::SEH_SaveFRegP:
1063 case AArch64::SEH_SaveFRegP_X:
1064 case AArch64::SEH_SetFP:
1065 case AArch64::SEH_AddFP:
1066 case AArch64::SEH_Nop:
1067 case AArch64::SEH_PrologEnd:
1068 case AArch64::SEH_EpilogStart:
1069 case AArch64::SEH_EpilogEnd:
1070 case AArch64::SEH_PACSignLR:
1071 case AArch64::SEH_SaveAnyRegQP:
1072 case AArch64::SEH_SaveAnyRegQPX:
1079 unsigned &SubIdx)
const {
1080 switch (
MI.getOpcode()) {
1083 case AArch64::SBFMXri:
1084 case AArch64::UBFMXri:
1087 if (
MI.getOperand(2).getImm() != 0 ||
MI.getOperand(3).getImm() != 31)
1090 SrcReg =
MI.getOperand(1).getReg();
1091 DstReg =
MI.getOperand(0).getReg();
1092 SubIdx = AArch64::sub_32;
1101 int64_t OffsetA = 0, OffsetB = 0;
1102 TypeSize WidthA(0,
false), WidthB(0,
false);
1103 bool OffsetAIsScalable =
false, OffsetBIsScalable =
false;
1124 OffsetAIsScalable == OffsetBIsScalable) {
1125 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1126 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1127 TypeSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1128 if (LowWidth.
isScalable() == OffsetAIsScalable &&
1146 switch (
MI.getOpcode()) {
1149 if (
MI.getOperand(0).getImm() == 0x14)
1156 case AArch64::MSRpstatesvcrImm1:
1163 auto Next = std::next(
MI.getIterator());
1164 return Next !=
MBB->
end() && Next->isCFIInstruction();
1171 Register &SrcReg2, int64_t &CmpMask,
1172 int64_t &CmpValue)
const {
1175 assert(
MI.getNumOperands() >= 2 &&
"All AArch64 cmps should have 2 operands");
1176 if (!
MI.getOperand(1).isReg())
1179 switch (
MI.getOpcode()) {
1182 case AArch64::PTEST_PP:
1183 case AArch64::PTEST_PP_ANY:
1184 SrcReg =
MI.getOperand(0).getReg();
1185 SrcReg2 =
MI.getOperand(1).getReg();
1190 case AArch64::SUBSWrr:
1191 case AArch64::SUBSWrs:
1192 case AArch64::SUBSWrx:
1193 case AArch64::SUBSXrr:
1194 case AArch64::SUBSXrs:
1195 case AArch64::SUBSXrx:
1196 case AArch64::ADDSWrr:
1197 case AArch64::ADDSWrs:
1198 case AArch64::ADDSWrx:
1199 case AArch64::ADDSXrr:
1200 case AArch64::ADDSXrs:
1201 case AArch64::ADDSXrx:
1203 SrcReg =
MI.getOperand(1).getReg();
1204 SrcReg2 =
MI.getOperand(2).getReg();
1208 case AArch64::SUBSWri:
1209 case AArch64::ADDSWri:
1210 case AArch64::SUBSXri:
1211 case AArch64::ADDSXri:
1212 SrcReg =
MI.getOperand(1).getReg();
1215 CmpValue =
MI.getOperand(2).getImm();
1217 case AArch64::ANDSWri:
1218 case AArch64::ANDSXri:
1221 SrcReg =
MI.getOperand(1).getReg();
1225 MI.getOperand(2).getImm(),
1226 MI.getOpcode() == AArch64::ANDSWri ? 32 : 64);
1235 assert(
MBB &&
"Can't get MachineBasicBlock here");
1237 assert(MF &&
"Can't get MachineFunction here");
1242 for (
unsigned OpIdx = 0, EndIdx = Instr.getNumOperands(); OpIdx < EndIdx;
1246 Instr.getRegClassConstraint(OpIdx,
TII,
TRI);
1249 if (!OpRegCstraints)
1257 "Operand has register constraints without being a register!");
1260 if (Reg.isPhysical()) {
1261 if (!OpRegCstraints->
contains(Reg))
1264 !
MRI->constrainRegClass(Reg, OpRegCstraints))
1277 bool MIDefinesZeroReg =
false;
1278 if (
MI.definesRegister(AArch64::WZR) ||
MI.definesRegister(AArch64::XZR))
1279 MIDefinesZeroReg =
true;
1281 switch (
MI.getOpcode()) {
1283 return MI.getOpcode();
1284 case AArch64::ADDSWrr:
1285 return AArch64::ADDWrr;
1286 case AArch64::ADDSWri:
1287 return MIDefinesZeroReg ? AArch64::ADDSWri : AArch64::ADDWri;
1288 case AArch64::ADDSWrs:
1289 return MIDefinesZeroReg ? AArch64::ADDSWrs : AArch64::ADDWrs;
1290 case AArch64::ADDSWrx:
1291 return AArch64::ADDWrx;
1292 case AArch64::ADDSXrr:
1293 return AArch64::ADDXrr;
1294 case AArch64::ADDSXri:
1295 return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri;
1296 case AArch64::ADDSXrs:
1297 return MIDefinesZeroReg ? AArch64::ADDSXrs : AArch64::ADDXrs;
1298 case AArch64::ADDSXrx:
1299 return AArch64::ADDXrx;
1300 case AArch64::SUBSWrr:
1301 return AArch64::SUBWrr;
1302 case AArch64::SUBSWri:
1303 return MIDefinesZeroReg ? AArch64::SUBSWri : AArch64::SUBWri;
1304 case AArch64::SUBSWrs:
1305 return MIDefinesZeroReg ? AArch64::SUBSWrs : AArch64::SUBWrs;
1306 case AArch64::SUBSWrx:
1307 return AArch64::SUBWrx;
1308 case AArch64::SUBSXrr:
1309 return AArch64::SUBXrr;
1310 case AArch64::SUBSXri:
1311 return MIDefinesZeroReg ? AArch64::SUBSXri : AArch64::SUBXri;
1312 case AArch64::SUBSXrs:
1313 return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs;
1314 case AArch64::SUBSXrx:
1315 return AArch64::SUBXrx;
1330 if (To == To->getParent()->begin())
1335 if (To->getParent() !=
From->getParent())
1347 Instr.modifiesRegister(AArch64::NZCV,
TRI)) ||
1348 ((AccessToCheck &
AK_Read) && Instr.readsRegister(AArch64::NZCV,
TRI)))
1356bool AArch64InstrInfo::optimizePTestInstr(
1357 MachineInstr *PTest,
unsigned MaskReg,
unsigned PredReg,
1359 auto *
Mask =
MRI->getUniqueVRegDef(MaskReg);
1360 auto *Pred =
MRI->getUniqueVRegDef(PredReg);
1361 auto NewOp = Pred->getOpcode();
1362 bool OpChanged =
false;
1364 unsigned MaskOpcode =
Mask->getOpcode();
1365 unsigned PredOpcode = Pred->getOpcode();
1369 if (
isPTrueOpcode(MaskOpcode) && (PredIsPTestLike || PredIsWhileLike) &&
1372 Mask->getOperand(1).getImm() == 31) {
1381 if (PredIsPTestLike) {
1382 auto PTestLikeMask =
MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
1383 if (Mask != PTestLikeMask && PTest->
getOpcode() != AArch64::PTEST_PP_ANY)
1388 }
else if ((Mask == Pred) && (PredIsPTestLike || PredIsWhileLike) &&
1389 PTest->
getOpcode() == AArch64::PTEST_PP_ANY) {
1395 }
else if (PredIsPTestLike) {
1418 auto PTestLikeMask =
MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
1420 if ((Mask != PTestLikeMask) ||
1422 PTest->
getOpcode() != AArch64::PTEST_PP_ANY))
1429 switch (PredOpcode) {
1430 case AArch64::AND_PPzPP:
1431 case AArch64::BIC_PPzPP:
1432 case AArch64::EOR_PPzPP:
1433 case AArch64::NAND_PPzPP:
1434 case AArch64::NOR_PPzPP:
1435 case AArch64::ORN_PPzPP:
1436 case AArch64::ORR_PPzPP:
1437 case AArch64::BRKA_PPzP:
1438 case AArch64::BRKPA_PPzPP:
1439 case AArch64::BRKB_PPzP:
1440 case AArch64::BRKPB_PPzPP:
1441 case AArch64::RDFFR_PPz: {
1444 auto *PredMask =
MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
1445 if (Mask != PredMask)
1449 case AArch64::BRKN_PPzP: {
1453 if ((MaskOpcode != AArch64::PTRUE_B) ||
1454 (
Mask->getOperand(1).getImm() != 31))
1458 case AArch64::PTRUE_B:
1481 Pred->setDesc(
get(NewOp));
1486 assert(succeeded &&
"Operands have incompatible register classes!");
1487 Pred->addRegisterDefined(AArch64::NZCV,
TRI);
1491 if (Pred->registerDefIsDead(AArch64::NZCV,
TRI)) {
1492 unsigned i = 0,
e = Pred->getNumOperands();
1493 for (; i !=
e; ++i) {
1523 if (DeadNZCVIdx != -1) {
1538 assert(succeeded &&
"Some operands reg class are incompatible!");
1542 if (CmpInstr.
getOpcode() == AArch64::PTEST_PP ||
1543 CmpInstr.
getOpcode() == AArch64::PTEST_PP_ANY)
1544 return optimizePTestInstr(&CmpInstr, SrcReg, SrcReg2,
MRI);
1553 if (CmpValue == 0 && substituteCmpToZero(CmpInstr, SrcReg, *
MRI))
1555 return (CmpValue == 0 || CmpValue == 1) &&
1556 removeCmpToZeroOrOne(CmpInstr, SrcReg, CmpValue, *
MRI);
1564 switch (Instr.getOpcode()) {
1566 return AArch64::INSTRUCTION_LIST_END;
1568 case AArch64::ADDSWrr:
1569 case AArch64::ADDSWri:
1570 case AArch64::ADDSXrr:
1571 case AArch64::ADDSXri:
1572 case AArch64::SUBSWrr:
1573 case AArch64::SUBSWri:
1574 case AArch64::SUBSXrr:
1575 case AArch64::SUBSXri:
1576 return Instr.getOpcode();
1578 case AArch64::ADDWrr:
1579 return AArch64::ADDSWrr;
1580 case AArch64::ADDWri:
1581 return AArch64::ADDSWri;
1582 case AArch64::ADDXrr:
1583 return AArch64::ADDSXrr;
1584 case AArch64::ADDXri:
1585 return AArch64::ADDSXri;
1586 case AArch64::ADCWr:
1587 return AArch64::ADCSWr;
1588 case AArch64::ADCXr:
1589 return AArch64::ADCSXr;
1590 case AArch64::SUBWrr:
1591 return AArch64::SUBSWrr;
1592 case AArch64::SUBWri:
1593 return AArch64::SUBSWri;
1594 case AArch64::SUBXrr:
1595 return AArch64::SUBSXrr;
1596 case AArch64::SUBXri:
1597 return AArch64::SUBSXri;
1598 case AArch64::SBCWr:
1599 return AArch64::SBCSWr;
1600 case AArch64::SBCXr:
1601 return AArch64::SBCSXr;
1602 case AArch64::ANDWri:
1603 return AArch64::ANDSWri;
1604 case AArch64::ANDXri:
1605 return AArch64::ANDSXri;
1612 if (BB->isLiveIn(AArch64::NZCV))
1621 switch (Instr.getOpcode()) {
1625 case AArch64::Bcc: {
1626 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1631 case AArch64::CSINVWr:
1632 case AArch64::CSINVXr:
1633 case AArch64::CSINCWr:
1634 case AArch64::CSINCXr:
1635 case AArch64::CSELWr:
1636 case AArch64::CSELXr:
1637 case AArch64::CSNEGWr:
1638 case AArch64::CSNEGXr:
1639 case AArch64::FCSELSrrr:
1640 case AArch64::FCSELDrrr: {
1641 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1654 Instr.getOperand(CCIdx).getImm())
1707std::optional<UsedNZCV>
1712 if (
MI.getParent() != CmpParent)
1713 return std::nullopt;
1716 return std::nullopt;
1721 if (Instr.readsRegister(AArch64::NZCV, &
TRI)) {
1724 return std::nullopt;
1729 if (Instr.modifiesRegister(AArch64::NZCV, &
TRI))
1732 return NZCVUsedAfterCmp;
1736 return Opcode == AArch64::ADDSWri || Opcode == AArch64::ADDSXri;
1740 return Opcode == AArch64::SUBSWri || Opcode == AArch64::SUBSXri;
1762 const unsigned CmpOpcode = CmpInstr.
getOpcode();
1768 "Caller guarantees that CmpInstr compares with constant 0");
1771 if (!NZVCUsed || NZVCUsed->C)
1793bool AArch64InstrInfo::substituteCmpToZero(
1804 if (NewOpc == AArch64::INSTRUCTION_LIST_END)
1811 MI->setDesc(
get(NewOpc));
1815 assert(succeeded &&
"Some operands reg class are incompatible!");
1816 MI->addRegisterDefined(AArch64::NZCV, &
TRI);
1828 assert((CmpValue == 0 || CmpValue == 1) &&
1829 "Only comparisons to 0 or 1 considered for removal!");
1832 unsigned MIOpc =
MI.getOpcode();
1833 if (MIOpc == AArch64::CSINCWr) {
1834 if (
MI.getOperand(1).getReg() != AArch64::WZR ||
1835 MI.getOperand(2).getReg() != AArch64::WZR)
1837 }
else if (MIOpc == AArch64::CSINCXr) {
1838 if (
MI.getOperand(1).getReg() != AArch64::XZR ||
1839 MI.getOperand(2).getReg() != AArch64::XZR)
1849 if (
MI.findRegisterDefOperandIdx(AArch64::NZCV,
true) != -1)
1853 const unsigned CmpOpcode = CmpInstr.
getOpcode();
1855 if (CmpValue && !IsSubsRegImm)
1857 if (!CmpValue && !IsSubsRegImm && !
isADDSRegImm(CmpOpcode))
1862 if (MIUsedNZCV.
C || MIUsedNZCV.
V)
1865 std::optional<UsedNZCV> NZCVUsedAfterCmp =
1869 if (!NZCVUsedAfterCmp || NZCVUsedAfterCmp->C || NZCVUsedAfterCmp->V)
1872 if ((MIUsedNZCV.
Z && NZCVUsedAfterCmp->N) ||
1873 (MIUsedNZCV.
N && NZCVUsedAfterCmp->Z))
1876 if (MIUsedNZCV.
N && !CmpValue)
1918bool AArch64InstrInfo::removeCmpToZeroOrOne(
1926 bool IsInvertCC =
false;
1936 assert(
Idx >= 0 &&
"Unexpected instruction using CC.");
1947 if (
MI.getOpcode() != TargetOpcode::LOAD_STACK_GUARD &&
1948 MI.getOpcode() != AArch64::CATCHRET)
1956 if (
MI.getOpcode() == AArch64::CATCHRET) {
1965 FirstEpilogSEH = std::prev(FirstEpilogSEH);
1967 FirstEpilogSEH = std::next(FirstEpilogSEH);
1981 if (M.getStackProtectorGuard() ==
"sysreg") {
1991 int Offset = M.getStackProtectorGuardOffset();
2043 cast<GlobalValue>((*
MI.memoperands_begin())->getValue());
2052 unsigned Reg32 =
TRI->getSubReg(Reg, AArch64::sub_32);
2094 unsigned Reg32 =
TRI->getSubReg(Reg, AArch64::sub_32);
2117 switch (
MI.getOpcode()) {
2120 case AArch64::MOVZWi:
2121 case AArch64::MOVZXi:
2122 if (
MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) {
2123 assert(
MI.getDesc().getNumOperands() == 3 &&
2124 MI.getOperand(2).getImm() == 0 &&
"invalid MOVZi operands");
2128 case AArch64::ANDWri:
2129 return MI.getOperand(1).getReg() == AArch64::WZR;
2130 case AArch64::ANDXri:
2131 return MI.getOperand(1).getReg() == AArch64::XZR;
2132 case TargetOpcode::COPY:
2133 return MI.getOperand(1).getReg() == AArch64::WZR;
2141 switch (
MI.getOpcode()) {
2144 case TargetOpcode::COPY: {
2147 return (AArch64::GPR32RegClass.
contains(DstReg) ||
2148 AArch64::GPR64RegClass.
contains(DstReg));
2150 case AArch64::ORRXrs:
2151 if (
MI.getOperand(1).getReg() == AArch64::XZR) {
2152 assert(
MI.getDesc().getNumOperands() == 4 &&
2153 MI.getOperand(3).getImm() == 0 &&
"invalid ORRrs operands");
2157 case AArch64::ADDXri:
2158 if (
MI.getOperand(2).getImm() == 0) {
2159 assert(
MI.getDesc().getNumOperands() == 4 &&
2160 MI.getOperand(3).getImm() == 0 &&
"invalid ADDXri operands");
2171 switch (
MI.getOpcode()) {
2174 case TargetOpcode::COPY: {
2176 return AArch64::FPR128RegClass.contains(DstReg);
2178 case AArch64::ORRv16i8:
2179 if (
MI.getOperand(1).getReg() ==
MI.getOperand(2).getReg()) {
2180 assert(
MI.getDesc().getNumOperands() == 3 &&
MI.getOperand(0).isReg() &&
2181 "invalid ORRv16i8 operands");
2190 int &FrameIndex)
const {
2191 switch (
MI.getOpcode()) {
2194 case AArch64::LDRWui:
2195 case AArch64::LDRXui:
2196 case AArch64::LDRBui:
2197 case AArch64::LDRHui:
2198 case AArch64::LDRSui:
2199 case AArch64::LDRDui:
2200 case AArch64::LDRQui:
2201 case AArch64::LDR_PXI:
2202 if (
MI.getOperand(0).getSubReg() == 0 &&
MI.getOperand(1).isFI() &&
2203 MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
2204 FrameIndex =
MI.getOperand(1).getIndex();
2205 return MI.getOperand(0).getReg();
2214 int &FrameIndex)
const {
2215 switch (
MI.getOpcode()) {
2218 case AArch64::STRWui:
2219 case AArch64::STRXui:
2220 case AArch64::STRBui:
2221 case AArch64::STRHui:
2222 case AArch64::STRSui:
2223 case AArch64::STRDui:
2224 case AArch64::STRQui:
2225 case AArch64::STR_PXI:
2226 if (
MI.getOperand(0).getSubReg() == 0 &&
MI.getOperand(1).isFI() &&
2227 MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
2228 FrameIndex =
MI.getOperand(1).getIndex();
2229 return MI.getOperand(0).getReg();
2239 return MMO->getFlags() & MOSuppressPair;
2245 if (
MI.memoperands_empty())
2253 return MMO->getFlags() & MOStridedAccess;
2261 case AArch64::STURSi:
2262 case AArch64::STRSpre:
2263 case AArch64::STURDi:
2264 case AArch64::STRDpre:
2265 case AArch64::STURQi:
2266 case AArch64::STRQpre:
2267 case AArch64::STURBBi:
2268 case AArch64::STURHHi:
2269 case AArch64::STURWi:
2270 case AArch64::STRWpre:
2271 case AArch64::STURXi:
2272 case AArch64::STRXpre:
2273 case AArch64::LDURSi:
2274 case AArch64::LDRSpre:
2275 case AArch64::LDURDi:
2276 case AArch64::LDRDpre:
2277 case AArch64::LDURQi:
2278 case AArch64::LDRQpre:
2279 case AArch64::LDURWi:
2280 case AArch64::LDRWpre:
2281 case AArch64::LDURXi:
2282 case AArch64::LDRXpre:
2283 case AArch64::LDRSWpre:
2284 case AArch64::LDURSWi:
2285 case AArch64::LDURHHi:
2286 case AArch64::LDURBBi:
2287 case AArch64::LDURSBWi:
2288 case AArch64::LDURSHWi:
2296 case AArch64::PRFMui:
return AArch64::PRFUMi;
2297 case AArch64::LDRXui:
return AArch64::LDURXi;
2298 case AArch64::LDRWui:
return AArch64::LDURWi;
2299 case AArch64::LDRBui:
return AArch64::LDURBi;
2300 case AArch64::LDRHui:
return AArch64::LDURHi;
2301 case AArch64::LDRSui:
return AArch64::LDURSi;
2302 case AArch64::LDRDui:
return AArch64::LDURDi;
2303 case AArch64::LDRQui:
return AArch64::LDURQi;
2304 case AArch64::LDRBBui:
return AArch64::LDURBBi;
2305 case AArch64::LDRHHui:
return AArch64::LDURHHi;
2306 case AArch64::LDRSBXui:
return AArch64::LDURSBXi;
2307 case AArch64::LDRSBWui:
return AArch64::LDURSBWi;
2308 case AArch64::LDRSHXui:
return AArch64::LDURSHXi;
2309 case AArch64::LDRSHWui:
return AArch64::LDURSHWi;
2310 case AArch64::LDRSWui:
return AArch64::LDURSWi;
2311 case AArch64::STRXui:
return AArch64::STURXi;
2312 case AArch64::STRWui:
return AArch64::STURWi;
2313 case AArch64::STRBui:
return AArch64::STURBi;
2314 case AArch64::STRHui:
return AArch64::STURHi;
2315 case AArch64::STRSui:
return AArch64::STURSi;
2316 case AArch64::STRDui:
return AArch64::STURDi;
2317 case AArch64::STRQui:
return AArch64::STURQi;
2318 case AArch64::STRBBui:
return AArch64::STURBBi;
2319 case AArch64::STRHHui:
return AArch64::STURHHi;
2327 case AArch64::LDPXi:
2328 case AArch64::LDPDi:
2329 case AArch64::STPXi:
2330 case AArch64::STPDi:
2331 case AArch64::LDNPXi:
2332 case AArch64::LDNPDi:
2333 case AArch64::STNPXi:
2334 case AArch64::STNPDi:
2335 case AArch64::LDPQi:
2336 case AArch64::STPQi:
2337 case AArch64::LDNPQi:
2338 case AArch64::STNPQi:
2339 case AArch64::LDPWi:
2340 case AArch64::LDPSi:
2341 case AArch64::STPWi:
2342 case AArch64::STPSi:
2343 case AArch64::LDNPWi:
2344 case AArch64::LDNPSi:
2345 case AArch64::STNPWi:
2346 case AArch64::STNPSi:
2348 case AArch64::STGPi:
2350 case AArch64::LD1B_IMM:
2351 case AArch64::LD1B_H_IMM:
2352 case AArch64::LD1B_S_IMM:
2353 case AArch64::LD1B_D_IMM:
2354 case AArch64::LD1SB_H_IMM:
2355 case AArch64::LD1SB_S_IMM:
2356 case AArch64::LD1SB_D_IMM:
2357 case AArch64::LD1H_IMM:
2358 case AArch64::LD1H_S_IMM:
2359 case AArch64::LD1H_D_IMM:
2360 case AArch64::LD1SH_S_IMM:
2361 case AArch64::LD1SH_D_IMM:
2362 case AArch64::LD1W_IMM:
2363 case AArch64::LD1W_D_IMM:
2364 case AArch64::LD1SW_D_IMM:
2365 case AArch64::LD1D_IMM:
2367 case AArch64::LD2B_IMM:
2368 case AArch64::LD2H_IMM:
2369 case AArch64::LD2W_IMM:
2370 case AArch64::LD2D_IMM:
2371 case AArch64::LD3B_IMM:
2372 case AArch64::LD3H_IMM:
2373 case AArch64::LD3W_IMM:
2374 case AArch64::LD3D_IMM:
2375 case AArch64::LD4B_IMM:
2376 case AArch64::LD4H_IMM:
2377 case AArch64::LD4W_IMM:
2378 case AArch64::LD4D_IMM:
2380 case AArch64::ST1B_IMM:
2381 case AArch64::ST1B_H_IMM:
2382 case AArch64::ST1B_S_IMM:
2383 case AArch64::ST1B_D_IMM:
2384 case AArch64::ST1H_IMM:
2385 case AArch64::ST1H_S_IMM:
2386 case AArch64::ST1H_D_IMM:
2387 case AArch64::ST1W_IMM:
2388 case AArch64::ST1W_D_IMM:
2389 case AArch64::ST1D_IMM:
2391 case AArch64::ST2B_IMM:
2392 case AArch64::ST2H_IMM:
2393 case AArch64::ST2W_IMM:
2394 case AArch64::ST2D_IMM:
2395 case AArch64::ST3B_IMM:
2396 case AArch64::ST3H_IMM:
2397 case AArch64::ST3W_IMM:
2398 case AArch64::ST3D_IMM:
2399 case AArch64::ST4B_IMM:
2400 case AArch64::ST4H_IMM:
2401 case AArch64::ST4W_IMM:
2402 case AArch64::ST4D_IMM:
2404 case AArch64::LD1RB_IMM:
2405 case AArch64::LD1RB_H_IMM:
2406 case AArch64::LD1RB_S_IMM:
2407 case AArch64::LD1RB_D_IMM:
2408 case AArch64::LD1RSB_H_IMM:
2409 case AArch64::LD1RSB_S_IMM:
2410 case AArch64::LD1RSB_D_IMM:
2411 case AArch64::LD1RH_IMM:
2412 case AArch64::LD1RH_S_IMM:
2413 case AArch64::LD1RH_D_IMM:
2414 case AArch64::LD1RSH_S_IMM:
2415 case AArch64::LD1RSH_D_IMM:
2416 case AArch64::LD1RW_IMM:
2417 case AArch64::LD1RW_D_IMM:
2418 case AArch64::LD1RSW_IMM:
2419 case AArch64::LD1RD_IMM:
2421 case AArch64::LDNT1B_ZRI:
2422 case AArch64::LDNT1H_ZRI:
2423 case AArch64::LDNT1W_ZRI:
2424 case AArch64::LDNT1D_ZRI:
2425 case AArch64::STNT1B_ZRI:
2426 case AArch64::STNT1H_ZRI:
2427 case AArch64::STNT1W_ZRI:
2428 case AArch64::STNT1D_ZRI:
2430 case AArch64::LDNF1B_IMM:
2431 case AArch64::LDNF1B_H_IMM:
2432 case AArch64::LDNF1B_S_IMM:
2433 case AArch64::LDNF1B_D_IMM:
2434 case AArch64::LDNF1SB_H_IMM:
2435 case AArch64::LDNF1SB_S_IMM:
2436 case AArch64::LDNF1SB_D_IMM:
2437 case AArch64::LDNF1H_IMM:
2438 case AArch64::LDNF1H_S_IMM:
2439 case AArch64::LDNF1H_D_IMM:
2440 case AArch64::LDNF1SH_S_IMM:
2441 case AArch64::LDNF1SH_D_IMM:
2442 case AArch64::LDNF1W_IMM:
2443 case AArch64::LDNF1W_D_IMM:
2444 case AArch64::LDNF1SW_D_IMM:
2445 case AArch64::LDNF1D_IMM:
2449 case AArch64::LDR_PXI:
2450 case AArch64::STR_PXI:
2456 switch (
MI.getOpcode()) {
2460 case AArch64::STRSui:
2461 case AArch64::STRDui:
2462 case AArch64::STRQui:
2463 case AArch64::STRXui:
2464 case AArch64::STRWui:
2465 case AArch64::LDRSui:
2466 case AArch64::LDRDui:
2467 case AArch64::LDRQui:
2468 case AArch64::LDRXui:
2469 case AArch64::LDRWui:
2470 case AArch64::LDRSWui:
2472 case AArch64::STURSi:
2473 case AArch64::STRSpre:
2474 case AArch64::STURDi:
2475 case AArch64::STRDpre:
2476 case AArch64::STURQi:
2477 case AArch64::STRQpre:
2478 case AArch64::STURWi:
2479 case AArch64::STRWpre:
2480 case AArch64::STURXi:
2481 case AArch64::STRXpre:
2482 case AArch64::LDURSi:
2483 case AArch64::LDRSpre:
2484 case AArch64::LDURDi:
2485 case AArch64::LDRDpre:
2486 case AArch64::LDURQi:
2487 case AArch64::LDRQpre:
2488 case AArch64::LDURWi:
2489 case AArch64::LDRWpre:
2490 case AArch64::LDURXi:
2491 case AArch64::LDRXpre:
2492 case AArch64::LDURSWi:
2493 case AArch64::LDRSWpre:
2499 switch (
MI.getOpcode()) {
2502 "Unexpected instruction - was a new tail call opcode introduced?");
2504 case AArch64::TCRETURNdi:
2505 case AArch64::TCRETURNri:
2506 case AArch64::TCRETURNrix16x17:
2507 case AArch64::TCRETURNrix17:
2508 case AArch64::TCRETURNrinotx16:
2509 case AArch64::TCRETURNriALL:
2519 case AArch64::ADDWri:
2520 return AArch64::ADDSWri;
2521 case AArch64::ADDWrr:
2522 return AArch64::ADDSWrr;
2523 case AArch64::ADDWrs:
2524 return AArch64::ADDSWrs;
2525 case AArch64::ADDWrx:
2526 return AArch64::ADDSWrx;
2527 case AArch64::ANDWri:
2528 return AArch64::ANDSWri;
2529 case AArch64::ANDWrr:
2530 return AArch64::ANDSWrr;
2531 case AArch64::ANDWrs:
2532 return AArch64::ANDSWrs;
2533 case AArch64::BICWrr:
2534 return AArch64::BICSWrr;
2535 case AArch64::BICWrs:
2536 return AArch64::BICSWrs;
2537 case AArch64::SUBWri:
2538 return AArch64::SUBSWri;
2539 case AArch64::SUBWrr:
2540 return AArch64::SUBSWrr;
2541 case AArch64::SUBWrs:
2542 return AArch64::SUBSWrs;
2543 case AArch64::SUBWrx:
2544 return AArch64::SUBSWrx;
2546 case AArch64::ADDXri:
2547 return AArch64::ADDSXri;
2548 case AArch64::ADDXrr:
2549 return AArch64::ADDSXrr;
2550 case AArch64::ADDXrs:
2551 return AArch64::ADDSXrs;
2552 case AArch64::ADDXrx:
2553 return AArch64::ADDSXrx;
2554 case AArch64::ANDXri:
2555 return AArch64::ANDSXri;
2556 case AArch64::ANDXrr:
2557 return AArch64::ANDSXrr;
2558 case AArch64::ANDXrs:
2559 return AArch64::ANDSXrs;
2560 case AArch64::BICXrr:
2561 return AArch64::BICSXrr;
2562 case AArch64::BICXrs:
2563 return AArch64::BICSXrs;
2564 case AArch64::SUBXri:
2565 return AArch64::SUBSXri;
2566 case AArch64::SUBXrr:
2567 return AArch64::SUBSXrr;
2568 case AArch64::SUBXrs:
2569 return AArch64::SUBSXrs;
2570 case AArch64::SUBXrx:
2571 return AArch64::SUBSXrx;
2573 case AArch64::AND_PPzPP:
2574 return AArch64::ANDS_PPzPP;
2575 case AArch64::BIC_PPzPP:
2576 return AArch64::BICS_PPzPP;
2577 case AArch64::EOR_PPzPP:
2578 return AArch64::EORS_PPzPP;
2579 case AArch64::NAND_PPzPP:
2580 return AArch64::NANDS_PPzPP;
2581 case AArch64::NOR_PPzPP:
2582 return AArch64::NORS_PPzPP;
2583 case AArch64::ORN_PPzPP:
2584 return AArch64::ORNS_PPzPP;
2585 case AArch64::ORR_PPzPP:
2586 return AArch64::ORRS_PPzPP;
2587 case AArch64::BRKA_PPzP:
2588 return AArch64::BRKAS_PPzP;
2589 case AArch64::BRKPA_PPzPP:
2590 return AArch64::BRKPAS_PPzPP;
2591 case AArch64::BRKB_PPzP:
2592 return AArch64::BRKBS_PPzP;
2593 case AArch64::BRKPB_PPzPP:
2594 return AArch64::BRKPBS_PPzPP;
2595 case AArch64::BRKN_PPzP:
2596 return AArch64::BRKNS_PPzP;
2597 case AArch64::RDFFR_PPz:
2598 return AArch64::RDFFRS_PPz;
2599 case AArch64::PTRUE_B:
2600 return AArch64::PTRUES_B;
2611 if (
MI.hasOrderedMemoryRef())
2616 assert((
MI.getOperand(IsPreLdSt ? 2 : 1).isReg() ||
2617 MI.getOperand(IsPreLdSt ? 2 : 1).isFI()) &&
2618 "Expected a reg or frame index operand.");
2622 bool IsImmPreLdSt = IsPreLdSt &&
MI.getOperand(3).isImm();
2624 if (!
MI.getOperand(2).isImm() && !IsImmPreLdSt)
2637 if (
MI.getOperand(1).isReg() && !IsPreLdSt) {
2638 Register BaseReg =
MI.getOperand(1).getReg();
2640 if (
MI.modifiesRegister(BaseReg,
TRI))
2653 const MCAsmInfo *MAI =
MI.getMF()->getTarget().getMCAsmInfo();
2655 MI.getMF()->getFunction().needsUnwindTableEntry();
2661 if (Subtarget.isPaired128Slow()) {
2662 switch (
MI.getOpcode()) {
2665 case AArch64::LDURQi:
2666 case AArch64::STURQi:
2667 case AArch64::LDRQui:
2668 case AArch64::STRQui:
2695std::optional<ExtAddrMode>
2700 bool OffsetIsScalable;
2701 if (!getMemOperandWithOffset(MemI,
Base,
Offset, OffsetIsScalable,
TRI))
2702 return std::nullopt;
2705 return std::nullopt;
2720 int64_t OffsetScale = 1;
2725 case AArch64::LDURQi:
2726 case AArch64::STURQi:
2730 case AArch64::LDURDi:
2731 case AArch64::STURDi:
2732 case AArch64::LDURXi:
2733 case AArch64::STURXi:
2737 case AArch64::LDURWi:
2738 case AArch64::LDURSWi:
2739 case AArch64::STURWi:
2743 case AArch64::LDURHi:
2744 case AArch64::STURHi:
2745 case AArch64::LDURHHi:
2746 case AArch64::STURHHi:
2747 case AArch64::LDURSHXi:
2748 case AArch64::LDURSHWi:
2752 case AArch64::LDRBroX:
2753 case AArch64::LDRBBroX:
2754 case AArch64::LDRSBXroX:
2755 case AArch64::LDRSBWroX:
2756 case AArch64::STRBroX:
2757 case AArch64::STRBBroX:
2758 case AArch64::LDURBi:
2759 case AArch64::LDURBBi:
2760 case AArch64::LDURSBXi:
2761 case AArch64::LDURSBWi:
2762 case AArch64::STURBi:
2763 case AArch64::STURBBi:
2764 case AArch64::LDRBui:
2765 case AArch64::LDRBBui:
2766 case AArch64::LDRSBXui:
2767 case AArch64::LDRSBWui:
2768 case AArch64::STRBui:
2769 case AArch64::STRBBui:
2773 case AArch64::LDRQroX:
2774 case AArch64::STRQroX:
2775 case AArch64::LDRQui:
2776 case AArch64::STRQui:
2781 case AArch64::LDRDroX:
2782 case AArch64::STRDroX:
2783 case AArch64::LDRXroX:
2784 case AArch64::STRXroX:
2785 case AArch64::LDRDui:
2786 case AArch64::STRDui:
2787 case AArch64::LDRXui:
2788 case AArch64::STRXui:
2793 case AArch64::LDRWroX:
2794 case AArch64::LDRSWroX:
2795 case AArch64::STRWroX:
2796 case AArch64::LDRWui:
2797 case AArch64::LDRSWui:
2798 case AArch64::STRWui:
2803 case AArch64::LDRHroX:
2804 case AArch64::STRHroX:
2805 case AArch64::LDRHHroX:
2806 case AArch64::STRHHroX:
2807 case AArch64::LDRSHXroX:
2808 case AArch64::LDRSHWroX:
2809 case AArch64::LDRHui:
2810 case AArch64::STRHui:
2811 case AArch64::LDRHHui:
2812 case AArch64::STRHHui:
2813 case AArch64::LDRSHXui:
2814 case AArch64::LDRSHWui:
2822 if (BaseRegOp.
isReg() && BaseRegOp.
getReg() == Reg)
2846 case AArch64::SBFMXri:
2859 AM.
Scale = OffsetScale;
2864 case TargetOpcode::SUBREG_TO_REG: {
2877 if (!OffsetReg.
isVirtual() || !
MRI.hasOneNonDBGUse(OffsetReg))
2881 if (
DefMI.getOpcode() != AArch64::ORRWrs ||
2883 DefMI.getOperand(3).getImm() != 0)
2890 AM.
Scale = OffsetScale;
2901 auto validateOffsetForLDP = [](
unsigned NumBytes, int64_t OldOffset,
2902 int64_t NewOffset) ->
bool {
2903 int64_t MinOffset, MaxOffset;
2920 return OldOffset < MinOffset || OldOffset > MaxOffset ||
2921 (NewOffset >= MinOffset && NewOffset <= MaxOffset);
2923 auto canFoldAddSubImmIntoAddrMode = [&](int64_t Disp) ->
bool {
2925 int64_t NewOffset = OldOffset + Disp;
2930 if (!validateOffsetForLDP(NumBytes, OldOffset, NewOffset))
2940 auto canFoldAddRegIntoAddrMode =
2957 return (Opcode == AArch64::STURQi || Opcode == AArch64::STRQui) &&
2958 Subtarget.isSTRQroSlow();
2967 case AArch64::ADDXri:
2973 return canFoldAddSubImmIntoAddrMode(Disp);
2975 case AArch64::SUBXri:
2981 return canFoldAddSubImmIntoAddrMode(-Disp);
2983 case AArch64::ADDXrs: {
2996 if (Shift != 2 && Shift != 3 && Subtarget.hasAddrLSLSlow14())
2998 if (avoidSlowSTRQ(MemI))
3001 return canFoldAddRegIntoAddrMode(1ULL << Shift);
3004 case AArch64::ADDXrr:
3012 if (!OptSize && avoidSlowSTRQ(MemI))
3014 return canFoldAddRegIntoAddrMode(1);
3016 case AArch64::ADDXrx:
3024 if (!OptSize && avoidSlowSTRQ(MemI))
3033 return canFoldAddRegIntoAddrMode(
3048 case AArch64::LDURQi:
3049 case AArch64::LDRQui:
3050 return AArch64::LDRQroX;
3051 case AArch64::STURQi:
3052 case AArch64::STRQui:
3053 return AArch64::STRQroX;
3054 case AArch64::LDURDi:
3055 case AArch64::LDRDui:
3056 return AArch64::LDRDroX;
3057 case AArch64::STURDi:
3058 case AArch64::STRDui:
3059 return AArch64::STRDroX;
3060 case AArch64::LDURXi:
3061 case AArch64::LDRXui:
3062 return AArch64::LDRXroX;
3063 case AArch64::STURXi:
3064 case AArch64::STRXui:
3065 return AArch64::STRXroX;
3066 case AArch64::LDURWi:
3067 case AArch64::LDRWui:
3068 return AArch64::LDRWroX;
3069 case AArch64::LDURSWi:
3070 case AArch64::LDRSWui:
3071 return AArch64::LDRSWroX;
3072 case AArch64::STURWi:
3073 case AArch64::STRWui:
3074 return AArch64::STRWroX;
3075 case AArch64::LDURHi:
3076 case AArch64::LDRHui:
3077 return AArch64::LDRHroX;
3078 case AArch64::STURHi:
3079 case AArch64::STRHui:
3080 return AArch64::STRHroX;
3081 case AArch64::LDURHHi:
3082 case AArch64::LDRHHui:
3083 return AArch64::LDRHHroX;
3084 case AArch64::STURHHi:
3085 case AArch64::STRHHui:
3086 return AArch64::STRHHroX;
3087 case AArch64::LDURSHXi:
3088 case AArch64::LDRSHXui:
3089 return AArch64::LDRSHXroX;
3090 case AArch64::LDURSHWi:
3091 case AArch64::LDRSHWui:
3092 return AArch64::LDRSHWroX;
3093 case AArch64::LDURBi:
3094 case AArch64::LDRBui:
3095 return AArch64::LDRBroX;
3096 case AArch64::LDURBBi:
3097 case AArch64::LDRBBui:
3098 return AArch64::LDRBBroX;
3099 case AArch64::LDURSBXi:
3100 case AArch64::LDRSBXui:
3101 return AArch64::LDRSBXroX;
3102 case AArch64::LDURSBWi:
3103 case AArch64::LDRSBWui:
3104 return AArch64::LDRSBWroX;
3105 case AArch64::STURBi:
3106 case AArch64::STRBui:
3107 return AArch64::STRBroX;
3108 case AArch64::STURBBi:
3109 case AArch64::STRBBui:
3110 return AArch64::STRBBroX;
3122 case AArch64::LDURQi:
3124 return AArch64::LDRQui;
3125 case AArch64::STURQi:
3127 return AArch64::STRQui;
3128 case AArch64::LDURDi:
3130 return AArch64::LDRDui;
3131 case AArch64::STURDi:
3133 return AArch64::STRDui;
3134 case AArch64::LDURXi:
3136 return AArch64::LDRXui;
3137 case AArch64::STURXi:
3139 return AArch64::STRXui;
3140 case AArch64::LDURWi:
3142 return AArch64::LDRWui;
3143 case AArch64::LDURSWi:
3145 return AArch64::LDRSWui;
3146 case AArch64::STURWi:
3148 return AArch64::STRWui;
3149 case AArch64::LDURHi:
3151 return AArch64::LDRHui;
3152 case AArch64::STURHi:
3154 return AArch64::STRHui;
3155 case AArch64::LDURHHi:
3157 return AArch64::LDRHHui;
3158 case AArch64::STURHHi:
3160 return AArch64::STRHHui;
3161 case AArch64::LDURSHXi:
3163 return AArch64::LDRSHXui;
3164 case AArch64::LDURSHWi:
3166 return AArch64::LDRSHWui;
3167 case AArch64::LDURBi:
3169 return AArch64::LDRBui;
3170 case AArch64::LDURBBi:
3172 return AArch64::LDRBBui;
3173 case AArch64::LDURSBXi:
3175 return AArch64::LDRSBXui;
3176 case AArch64::LDURSBWi:
3178 return AArch64::LDRSBWui;
3179 case AArch64::STURBi:
3181 return AArch64::STRBui;
3182 case AArch64::STURBBi:
3184 return AArch64::STRBBui;
3185 case AArch64::LDRQui:
3186 case AArch64::STRQui:
3189 case AArch64::LDRDui:
3190 case AArch64::STRDui:
3191 case AArch64::LDRXui:
3192 case AArch64::STRXui:
3195 case AArch64::LDRWui:
3196 case AArch64::LDRSWui:
3197 case AArch64::STRWui:
3200 case AArch64::LDRHui:
3201 case AArch64::STRHui:
3202 case AArch64::LDRHHui:
3203 case AArch64::STRHHui:
3204 case AArch64::LDRSHXui:
3205 case AArch64::LDRSHWui:
3208 case AArch64::LDRBui:
3209 case AArch64::LDRBBui:
3210 case AArch64::LDRSBXui:
3211 case AArch64::LDRSBWui:
3212 case AArch64::STRBui:
3213 case AArch64::STRBBui:
3227 case AArch64::LDURQi:
3228 case AArch64::STURQi:
3229 case AArch64::LDURDi:
3230 case AArch64::STURDi:
3231 case AArch64::LDURXi:
3232 case AArch64::STURXi:
3233 case AArch64::LDURWi:
3234 case AArch64::LDURSWi:
3235 case AArch64::STURWi:
3236 case AArch64::LDURHi:
3237 case AArch64::STURHi:
3238 case AArch64::LDURHHi:
3239 case AArch64::STURHHi:
3240 case AArch64::LDURSHXi:
3241 case AArch64::LDURSHWi:
3242 case AArch64::LDURBi:
3243 case AArch64::STURBi:
3244 case AArch64::LDURBBi:
3245 case AArch64::STURBBi:
3246 case AArch64::LDURSBWi:
3247 case AArch64::LDURSBXi:
3249 case AArch64::LDRQui:
3250 return AArch64::LDURQi;
3251 case AArch64::STRQui:
3252 return AArch64::STURQi;
3253 case AArch64::LDRDui:
3254 return AArch64::LDURDi;
3255 case AArch64::STRDui:
3256 return AArch64::STURDi;
3257 case AArch64::LDRXui:
3258 return AArch64::LDURXi;
3259 case AArch64::STRXui:
3260 return AArch64::STURXi;
3261 case AArch64::LDRWui:
3262 return AArch64::LDURWi;
3263 case AArch64::LDRSWui:
3264 return AArch64::LDURSWi;
3265 case AArch64::STRWui:
3266 return AArch64::STURWi;
3267 case AArch64::LDRHui:
3268 return AArch64::LDURHi;
3269 case AArch64::STRHui:
3270 return AArch64::STURHi;
3271 case AArch64::LDRHHui:
3272 return AArch64::LDURHHi;
3273 case AArch64::STRHHui:
3274 return AArch64::STURHHi;
3275 case AArch64::LDRSHXui:
3276 return AArch64::LDURSHXi;
3277 case AArch64::LDRSHWui:
3278 return AArch64::LDURSHWi;
3279 case AArch64::LDRBBui:
3280 return AArch64::LDURBBi;
3281 case AArch64::LDRBui:
3282 return AArch64::LDURBi;
3283 case AArch64::STRBBui:
3284 return AArch64::STURBBi;
3285 case AArch64::STRBui:
3286 return AArch64::STURBi;
3287 case AArch64::LDRSBWui:
3288 return AArch64::LDURSBWi;
3289 case AArch64::LDRSBXui:
3290 return AArch64::LDURSBXi;
3303 case AArch64::LDRQroX:
3304 case AArch64::LDURQi:
3305 case AArch64::LDRQui:
3306 return AArch64::LDRQroW;
3307 case AArch64::STRQroX:
3308 case AArch64::STURQi:
3309 case AArch64::STRQui:
3310 return AArch64::STRQroW;
3311 case AArch64::LDRDroX:
3312 case AArch64::LDURDi:
3313 case AArch64::LDRDui:
3314 return AArch64::LDRDroW;
3315 case AArch64::STRDroX:
3316 case AArch64::STURDi:
3317 case AArch64::STRDui:
3318 return AArch64::STRDroW;
3319 case AArch64::LDRXroX:
3320 case AArch64::LDURXi:
3321 case AArch64::LDRXui:
3322 return AArch64::LDRXroW;
3323 case AArch64::STRXroX:
3324 case AArch64::STURXi:
3325 case AArch64::STRXui:
3326 return AArch64::STRXroW;
3327 case AArch64::LDRWroX:
3328 case AArch64::LDURWi:
3329 case AArch64::LDRWui:
3330 return AArch64::LDRWroW;
3331 case AArch64::LDRSWroX:
3332 case AArch64::LDURSWi:
3333 case AArch64::LDRSWui:
3334 return AArch64::LDRSWroW;
3335 case AArch64::STRWroX:
3336 case AArch64::STURWi:
3337 case AArch64::STRWui:
3338 return AArch64::STRWroW;
3339 case AArch64::LDRHroX:
3340 case AArch64::LDURHi:
3341 case AArch64::LDRHui:
3342 return AArch64::LDRHroW;
3343 case AArch64::STRHroX:
3344 case AArch64::STURHi:
3345 case AArch64::STRHui:
3346 return AArch64::STRHroW;
3347 case AArch64::LDRHHroX:
3348 case AArch64::LDURHHi:
3349 case AArch64::LDRHHui:
3350 return AArch64::LDRHHroW;
3351 case AArch64::STRHHroX:
3352 case AArch64::STURHHi:
3353 case AArch64::STRHHui:
3354 return AArch64::STRHHroW;
3355 case AArch64::LDRSHXroX:
3356 case AArch64::LDURSHXi:
3357 case AArch64::LDRSHXui:
3358 return AArch64::LDRSHXroW;
3359 case AArch64::LDRSHWroX:
3360 case AArch64::LDURSHWi:
3361 case AArch64::LDRSHWui:
3362 return AArch64::LDRSHWroW;
3363 case AArch64::LDRBroX:
3364 case AArch64::LDURBi:
3365 case AArch64::LDRBui:
3366 return AArch64::LDRBroW;
3367 case AArch64::LDRBBroX:
3368 case AArch64::LDURBBi:
3369 case AArch64::LDRBBui:
3370 return AArch64::LDRBBroW;
3371 case AArch64::LDRSBXroX:
3372 case AArch64::LDURSBXi:
3373 case AArch64::LDRSBXui:
3374 return AArch64::LDRSBXroW;
3375 case AArch64::LDRSBWroX:
3376 case AArch64::LDURSBWi:
3377 case AArch64::LDRSBWui:
3378 return AArch64::LDRSBWroW;
3379 case AArch64::STRBroX:
3380 case AArch64::STURBi:
3381 case AArch64::STRBui:
3382 return AArch64::STRBroW;
3383 case AArch64::STRBBroX:
3384 case AArch64::STURBBi:
3385 case AArch64::STRBBui:
3386 return AArch64::STRBBroW;
3401 MRI.constrainRegClass(AM.
BaseReg, &AArch64::GPR64spRegClass);
3411 return B.getInstr();
3415 "Addressing mode not supported for folding");
3432 return B.getInstr();
3439 "Address offset can be a register or an immediate, but not both");
3441 MRI.constrainRegClass(AM.
BaseReg, &AArch64::GPR64spRegClass);
3446 OffsetReg =
MRI.createVirtualRegister(&AArch64::GPR32RegClass);
3460 return B.getInstr();
3464 "Function must not be called with an addressing mode it can't handle");
3469 bool &OffsetIsScalable,
TypeSize &Width,
3490 int64_t Dummy1, Dummy2;
3509 if (!BaseOp->
isReg() && !BaseOp->
isFI())
3519 assert(OfsOp.
isImm() &&
"Offset operand wasn't immediate.");
3524 TypeSize &Width, int64_t &MinOffset,
3525 int64_t &MaxOffset) {
3531 MinOffset = MaxOffset = 0;
3533 case AArch64::STRWpost:
3534 case AArch64::LDRWpost:
3540 case AArch64::LDURQi:
3541 case AArch64::STURQi:
3547 case AArch64::PRFUMi:
3548 case AArch64::LDURXi:
3549 case AArch64::LDURDi:
3550 case AArch64::LDAPURXi:
3551 case AArch64::STURXi:
3552 case AArch64::STURDi:
3553 case AArch64::STLURXi:
3559 case AArch64::LDURWi:
3560 case AArch64::LDURSi:
3561 case AArch64::LDURSWi:
3562 case AArch64::LDAPURi:
3563 case AArch64::LDAPURSWi:
3564 case AArch64::STURWi:
3565 case AArch64::STURSi:
3566 case AArch64::STLURWi:
3572 case AArch64::LDURHi:
3573 case AArch64::LDURHHi:
3574 case AArch64::LDURSHXi:
3575 case AArch64::LDURSHWi:
3576 case AArch64::LDAPURHi:
3577 case AArch64::LDAPURSHWi:
3578 case AArch64::LDAPURSHXi:
3579 case AArch64::STURHi:
3580 case AArch64::STURHHi:
3581 case AArch64::STLURHi:
3587 case AArch64::LDURBi:
3588 case AArch64::LDURBBi:
3589 case AArch64::LDURSBXi:
3590 case AArch64::LDURSBWi:
3591 case AArch64::LDAPURBi:
3592 case AArch64::LDAPURSBWi:
3593 case AArch64::LDAPURSBXi:
3594 case AArch64::STURBi:
3595 case AArch64::STURBBi:
3596 case AArch64::STLURBi:
3602 case AArch64::LDPQi:
3603 case AArch64::LDNPQi:
3604 case AArch64::STPQi:
3605 case AArch64::STNPQi:
3611 case AArch64::LDRQui:
3612 case AArch64::STRQui:
3618 case AArch64::LDPXi:
3619 case AArch64::LDPDi:
3620 case AArch64::LDNPXi:
3621 case AArch64::LDNPDi:
3622 case AArch64::STPXi:
3623 case AArch64::STPDi:
3624 case AArch64::STNPXi:
3625 case AArch64::STNPDi:
3631 case AArch64::PRFMui:
3632 case AArch64::LDRXui:
3633 case AArch64::LDRDui:
3634 case AArch64::STRXui:
3635 case AArch64::STRDui:
3641 case AArch64::StoreSwiftAsyncContext:
3648 case AArch64::LDPWi:
3649 case AArch64::LDPSi:
3650 case AArch64::LDNPWi:
3651 case AArch64::LDNPSi:
3652 case AArch64::STPWi:
3653 case AArch64::STPSi:
3654 case AArch64::STNPWi:
3655 case AArch64::STNPSi:
3661 case AArch64::LDRWui:
3662 case AArch64::LDRSui:
3663 case AArch64::LDRSWui:
3664 case AArch64::STRWui:
3665 case AArch64::STRSui:
3671 case AArch64::LDRHui:
3672 case AArch64::LDRHHui:
3673 case AArch64::LDRSHWui:
3674 case AArch64::LDRSHXui:
3675 case AArch64::STRHui:
3676 case AArch64::STRHHui:
3682 case AArch64::LDRBui:
3683 case AArch64::LDRBBui:
3684 case AArch64::LDRSBWui:
3685 case AArch64::LDRSBXui:
3686 case AArch64::STRBui:
3687 case AArch64::STRBBui:
3693 case AArch64::STPXpre:
3694 case AArch64::LDPXpost:
3695 case AArch64::STPDpre:
3696 case AArch64::LDPDpost:
3702 case AArch64::STPQpre:
3703 case AArch64::LDPQpost:
3709 case AArch64::STRXpre:
3710 case AArch64::STRDpre:
3711 case AArch64::LDRXpost:
3712 case AArch64::LDRDpost:
3718 case AArch64::STRQpre:
3719 case AArch64::LDRQpost:
3731 case AArch64::TAGPstack:
3741 case AArch64::STZGi:
3747 case AArch64::STR_ZZZZXI:
3748 case AArch64::LDR_ZZZZXI:
3754 case AArch64::STR_ZZZXI:
3755 case AArch64::LDR_ZZZXI:
3761 case AArch64::STR_ZZXI:
3762 case AArch64::LDR_ZZXI:
3768 case AArch64::LDR_PXI:
3769 case AArch64::STR_PXI:
3775 case AArch64::LDR_PPXI:
3776 case AArch64::STR_PPXI:
3782 case AArch64::LDR_ZXI:
3783 case AArch64::STR_ZXI:
3789 case AArch64::LD1B_IMM:
3790 case AArch64::LD1H_IMM:
3791 case AArch64::LD1W_IMM:
3792 case AArch64::LD1D_IMM:
3793 case AArch64::LDNT1B_ZRI:
3794 case AArch64::LDNT1H_ZRI:
3795 case AArch64::LDNT1W_ZRI:
3796 case AArch64::LDNT1D_ZRI:
3797 case AArch64::ST1B_IMM:
3798 case AArch64::ST1H_IMM:
3799 case AArch64::ST1W_IMM:
3800 case AArch64::ST1D_IMM:
3801 case AArch64::STNT1B_ZRI:
3802 case AArch64::STNT1H_ZRI:
3803 case AArch64::STNT1W_ZRI:
3804 case AArch64::STNT1D_ZRI:
3805 case AArch64::LDNF1B_IMM:
3806 case AArch64::LDNF1H_IMM:
3807 case AArch64::LDNF1W_IMM:
3808 case AArch64::LDNF1D_IMM:
3816 case AArch64::LD2B_IMM:
3817 case AArch64::LD2H_IMM:
3818 case AArch64::LD2W_IMM:
3819 case AArch64::LD2D_IMM:
3820 case AArch64::ST2B_IMM:
3821 case AArch64::ST2H_IMM:
3822 case AArch64::ST2W_IMM:
3823 case AArch64::ST2D_IMM:
3829 case AArch64::LD3B_IMM:
3830 case AArch64::LD3H_IMM:
3831 case AArch64::LD3W_IMM:
3832 case AArch64::LD3D_IMM:
3833 case AArch64::ST3B_IMM:
3834 case AArch64::ST3H_IMM:
3835 case AArch64::ST3W_IMM:
3836 case AArch64::ST3D_IMM:
3842 case AArch64::LD4B_IMM:
3843 case AArch64::LD4H_IMM:
3844 case AArch64::LD4W_IMM:
3845 case AArch64::LD4D_IMM:
3846 case AArch64::ST4B_IMM:
3847 case AArch64::ST4H_IMM:
3848 case AArch64::ST4W_IMM:
3849 case AArch64::ST4D_IMM:
3855 case AArch64::LD1B_H_IMM:
3856 case AArch64::LD1SB_H_IMM:
3857 case AArch64::LD1H_S_IMM:
3858 case AArch64::LD1SH_S_IMM:
3859 case AArch64::LD1W_D_IMM:
3860 case AArch64::LD1SW_D_IMM:
3861 case AArch64::ST1B_H_IMM:
3862 case AArch64::ST1H_S_IMM:
3863 case AArch64::ST1W_D_IMM:
3864 case AArch64::LDNF1B_H_IMM:
3865 case AArch64::LDNF1SB_H_IMM:
3866 case AArch64::LDNF1H_S_IMM:
3867 case AArch64::LDNF1SH_S_IMM:
3868 case AArch64::LDNF1W_D_IMM:
3869 case AArch64::LDNF1SW_D_IMM:
3877 case AArch64::LD1B_S_IMM:
3878 case AArch64::LD1SB_S_IMM:
3879 case AArch64::LD1H_D_IMM:
3880 case AArch64::LD1SH_D_IMM:
3881 case AArch64::ST1B_S_IMM:
3882 case AArch64::ST1H_D_IMM:
3883 case AArch64::LDNF1B_S_IMM:
3884 case AArch64::LDNF1SB_S_IMM:
3885 case AArch64::LDNF1H_D_IMM:
3886 case AArch64::LDNF1SH_D_IMM:
3894 case AArch64::LD1B_D_IMM:
3895 case AArch64::LD1SB_D_IMM:
3896 case AArch64::ST1B_D_IMM:
3897 case AArch64::LDNF1B_D_IMM:
3898 case AArch64::LDNF1SB_D_IMM:
3906 case AArch64::ST2Gi:
3907 case AArch64::STZ2Gi:
3913 case AArch64::STGPi:
3919 case AArch64::LD1RB_IMM:
3920 case AArch64::LD1RB_H_IMM:
3921 case AArch64::LD1RB_S_IMM:
3922 case AArch64::LD1RB_D_IMM:
3923 case AArch64::LD1RSB_H_IMM:
3924 case AArch64::LD1RSB_S_IMM:
3925 case AArch64::LD1RSB_D_IMM:
3931 case AArch64::LD1RH_IMM:
3932 case AArch64::LD1RH_S_IMM:
3933 case AArch64::LD1RH_D_IMM:
3934 case AArch64::LD1RSH_S_IMM:
3935 case AArch64::LD1RSH_D_IMM:
3941 case AArch64::LD1RW_IMM:
3942 case AArch64::LD1RW_D_IMM:
3943 case AArch64::LD1RSW_IMM:
3949 case AArch64::LD1RD_IMM:
3965 case AArch64::LDRBBui:
3966 case AArch64::LDURBBi:
3967 case AArch64::LDRSBWui:
3968 case AArch64::LDURSBWi:
3969 case AArch64::STRBBui:
3970 case AArch64::STURBBi:
3972 case AArch64::LDRHHui:
3973 case AArch64::LDURHHi:
3974 case AArch64::LDRSHWui:
3975 case AArch64::LDURSHWi:
3976 case AArch64::STRHHui:
3977 case AArch64::STURHHi:
3979 case AArch64::LDRSui:
3980 case AArch64::LDURSi:
3981 case AArch64::LDRSpre:
3982 case AArch64::LDRSWui:
3983 case AArch64::LDURSWi:
3984 case AArch64::LDRSWpre:
3985 case AArch64::LDRWpre:
3986 case AArch64::LDRWui:
3987 case AArch64::LDURWi:
3988 case AArch64::STRSui:
3989 case AArch64::STURSi:
3990 case AArch64::STRSpre:
3991 case AArch64::STRWui:
3992 case AArch64::STURWi:
3993 case AArch64::STRWpre:
3994 case AArch64::LDPSi:
3995 case AArch64::LDPSWi:
3996 case AArch64::LDPWi:
3997 case AArch64::STPSi:
3998 case AArch64::STPWi:
4000 case AArch64::LDRDui:
4001 case AArch64::LDURDi:
4002 case AArch64::LDRDpre:
4003 case AArch64::LDRXui:
4004 case AArch64::LDURXi:
4005 case AArch64::LDRXpre:
4006 case AArch64::STRDui:
4007 case AArch64::STURDi:
4008 case AArch64::STRDpre:
4009 case AArch64::STRXui:
4010 case AArch64::STURXi:
4011 case AArch64::STRXpre:
4012 case AArch64::LDPDi:
4013 case AArch64::LDPXi:
4014 case AArch64::STPDi:
4015 case AArch64::STPXi:
4017 case AArch64::LDRQui:
4018 case AArch64::LDURQi:
4019 case AArch64::STRQui:
4020 case AArch64::STURQi:
4021 case AArch64::STRQpre:
4022 case AArch64::LDPQi:
4023 case AArch64::LDRQpre:
4024 case AArch64::STPQi:
4026 case AArch64::STZGi:
4027 case AArch64::ST2Gi:
4028 case AArch64::STZ2Gi:
4029 case AArch64::STGPi:
4035 switch (
MI.getOpcode()) {
4038 case AArch64::LDRWpre:
4039 case AArch64::LDRXpre:
4040 case AArch64::LDRSWpre:
4041 case AArch64::LDRSpre:
4042 case AArch64::LDRDpre:
4043 case AArch64::LDRQpre:
4049 switch (
MI.getOpcode()) {
4052 case AArch64::STRWpre:
4053 case AArch64::STRXpre:
4054 case AArch64::STRSpre:
4055 case AArch64::STRDpre:
4056 case AArch64::STRQpre:
4066 switch (
MI.getOpcode()) {
4069 case AArch64::LDPSi:
4070 case AArch64::LDPSWi:
4071 case AArch64::LDPDi:
4072 case AArch64::LDPQi:
4073 case AArch64::LDPWi:
4074 case AArch64::LDPXi:
4075 case AArch64::STPSi:
4076 case AArch64::STPDi:
4077 case AArch64::STPQi:
4078 case AArch64::STPWi:
4079 case AArch64::STPXi:
4080 case AArch64::STGPi:
4089 return MI.getOperand(
Idx);
4097 return MI.getOperand(
Idx);
4102 if (
MI.getParent() ==
nullptr)
4112 auto Reg =
Op.getReg();
4113 if (Reg.isPhysical())
4114 return AArch64::FPR16RegClass.
contains(Reg);
4116 return TRC == &AArch64::FPR16RegClass ||
4117 TRC == &AArch64::FPR16_loRegClass;
4126 auto Reg =
Op.getReg();
4127 if (Reg.isPhysical())
4128 return AArch64::FPR128RegClass.
contains(Reg);
4130 return TRC == &AArch64::FPR128RegClass ||
4131 TRC == &AArch64::FPR128_loRegClass;
4137 switch (
MI.getOpcode()) {
4140 case AArch64::PACIASP:
4141 case AArch64::PACIBSP:
4144 case AArch64::PAUTH_PROLOGUE:
4147 case AArch64::HINT: {
4148 unsigned Imm =
MI.getOperand(0).getImm();
4150 if (Imm == 32 || Imm == 34 || Imm == 36 || Imm == 38)
4153 if (Imm == 25 || Imm == 27)
4166 auto Reg =
Op.getReg();
4167 if (Reg.isPhysical())
4168 return AArch64::FPR128RegClass.
contains(Reg) ||
4169 AArch64::FPR64RegClass.contains(Reg) ||
4170 AArch64::FPR32RegClass.contains(Reg) ||
4171 AArch64::FPR16RegClass.contains(Reg) ||
4172 AArch64::FPR8RegClass.contains(Reg);
4175 return TRC == &AArch64::FPR128RegClass ||
4176 TRC == &AArch64::FPR128_loRegClass ||
4177 TRC == &AArch64::FPR64RegClass ||
4178 TRC == &AArch64::FPR64_loRegClass ||
4179 TRC == &AArch64::FPR32RegClass || TRC == &AArch64::FPR16RegClass ||
4180 TRC == &AArch64::FPR8RegClass;
4202 if (FirstOpc == SecondOpc)
4208 case AArch64::STRSui:
4209 case AArch64::STURSi:
4210 return SecondOpc == AArch64::STRSui || SecondOpc == AArch64::STURSi;
4211 case AArch64::STRDui:
4212 case AArch64::STURDi:
4213 return SecondOpc == AArch64::STRDui || SecondOpc == AArch64::STURDi;
4214 case AArch64::STRQui:
4215 case AArch64::STURQi:
4216 return SecondOpc == AArch64::STRQui || SecondOpc == AArch64::STURQi;
4217 case AArch64::STRWui:
4218 case AArch64::STURWi:
4219 return SecondOpc == AArch64::STRWui || SecondOpc == AArch64::STURWi;
4220 case AArch64::STRXui:
4221 case AArch64::STURXi:
4222 return SecondOpc == AArch64::STRXui || SecondOpc == AArch64::STURXi;
4223 case AArch64::LDRSui:
4224 case AArch64::LDURSi:
4225 return SecondOpc == AArch64::LDRSui || SecondOpc == AArch64::LDURSi;
4226 case AArch64::LDRDui:
4227 case AArch64::LDURDi:
4228 return SecondOpc == AArch64::LDRDui || SecondOpc == AArch64::LDURDi;
4229 case AArch64::LDRQui:
4230 case AArch64::LDURQi:
4231 return SecondOpc == AArch64::LDRQui || SecondOpc == AArch64::LDURQi;
4232 case AArch64::LDRWui:
4233 case AArch64::LDURWi:
4234 return SecondOpc == AArch64::LDRSWui || SecondOpc == AArch64::LDURSWi;
4235 case AArch64::LDRSWui:
4236 case AArch64::LDURSWi:
4237 return SecondOpc == AArch64::LDRWui || SecondOpc == AArch64::LDURWi;
4238 case AArch64::LDRXui:
4239 case AArch64::LDURXi:
4240 return SecondOpc == AArch64::LDRXui || SecondOpc == AArch64::LDURXi;
4247 int64_t Offset1,
unsigned Opcode1,
int FI2,
4248 int64_t Offset2,
unsigned Opcode2) {
4254 assert(ObjectOffset1 <= ObjectOffset2 &&
"Object offsets are not ordered.");
4257 if (ObjectOffset1 % Scale1 != 0)
4259 ObjectOffset1 /= Scale1;
4261 if (ObjectOffset2 % Scale2 != 0)
4263 ObjectOffset2 /= Scale2;
4264 ObjectOffset1 += Offset1;
4265 ObjectOffset2 += Offset2;
4266 return ObjectOffset1 + 1 == ObjectOffset2;
4278 int64_t OpOffset2,
bool OffsetIsScalable2,
unsigned ClusterSize,
4279 unsigned NumBytes)
const {
4289 "Only base registers and frame indices are supported.");
4296 if (ClusterSize > 2)
4303 unsigned FirstOpc = FirstLdSt.
getOpcode();
4304 unsigned SecondOpc = SecondLdSt.
getOpcode();
4324 if (Offset1 > 63 || Offset1 < -64)
4329 if (BaseOp1.
isFI()) {
4331 "Caller should have ordered offsets.");
4336 BaseOp2.
getIndex(), Offset2, SecondOpc);
4339 assert(Offset1 <= Offset2 &&
"Caller should have ordered offsets.");
4341 return Offset1 + 1 == Offset2;
4345 unsigned Reg,
unsigned SubIdx,
4349 return MIB.
addReg(Reg, State);
4352 return MIB.
addReg(
TRI->getSubReg(Reg, SubIdx), State);
4353 return MIB.
addReg(Reg, State, SubIdx);
4360 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
4369 assert(Subtarget.hasNEON() &&
"Unexpected register copy without NEON");
4371 uint16_t DestEncoding =
TRI->getEncodingValue(DestReg);
4372 uint16_t SrcEncoding =
TRI->getEncodingValue(SrcReg);
4373 unsigned NumRegs = Indices.
size();
4375 int SubReg = 0,
End = NumRegs, Incr = 1;
4393 unsigned SrcReg,
bool KillSrc,
4394 unsigned Opcode,
unsigned ZeroReg,
4397 unsigned NumRegs = Indices.
size();
4400 uint16_t DestEncoding =
TRI->getEncodingValue(DestReg);
4401 uint16_t SrcEncoding =
TRI->getEncodingValue(SrcReg);
4402 assert(DestEncoding % NumRegs == 0 && SrcEncoding % NumRegs == 0 &&
4403 "GPR reg sequences should not be able to overlap");
4419 if (AArch64::GPR32spRegClass.
contains(DestReg) &&
4420 (AArch64::GPR32spRegClass.
contains(SrcReg) || SrcReg == AArch64::WZR)) {
4423 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
4425 if (Subtarget.hasZeroCycleRegMove()) {
4428 DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
4430 SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
4446 }
else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGP()) {
4451 if (Subtarget.hasZeroCycleRegMove()) {
4454 DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
4456 SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
4476 if (AArch64::PPRRegClass.
contains(DestReg) &&
4477 AArch64::PPRRegClass.
contains(SrcReg)) {
4488 bool DestIsPNR = AArch64::PNRRegClass.contains(DestReg);
4489 bool SrcIsPNR = AArch64::PNRRegClass.contains(SrcReg);
4490 if (DestIsPNR || SrcIsPNR) {
4491 assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4492 "Unexpected predicate-as-counter register.");
4494 return (R - AArch64::PN0) + AArch64::P0;
4496 MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg;
4497 MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg;
4499 if (PPRSrcReg != PPRDestReg) {
4511 if (AArch64::ZPRRegClass.
contains(DestReg) &&
4512 AArch64::ZPRRegClass.
contains(SrcReg)) {
4521 if ((AArch64::ZPR2RegClass.
contains(DestReg) ||
4522 AArch64::ZPR2StridedOrContiguousRegClass.
contains(DestReg)) &&
4523 (AArch64::ZPR2RegClass.
contains(SrcReg) ||
4524 AArch64::ZPR2StridedOrContiguousRegClass.
contains(SrcReg))) {
4526 static const unsigned Indices[] = {AArch64::zsub0, AArch64::zsub1};
4533 if (AArch64::ZPR3RegClass.
contains(DestReg) &&
4534 AArch64::ZPR3RegClass.
contains(SrcReg)) {
4536 static const unsigned Indices[] = {AArch64::zsub0, AArch64::zsub1,
4544 if ((AArch64::ZPR4RegClass.
contains(DestReg) ||
4545 AArch64::ZPR4StridedOrContiguousRegClass.
contains(DestReg)) &&
4546 (AArch64::ZPR4RegClass.
contains(SrcReg) ||
4547 AArch64::ZPR4StridedOrContiguousRegClass.
contains(SrcReg))) {
4549 static const unsigned Indices[] = {AArch64::zsub0, AArch64::zsub1,
4550 AArch64::zsub2, AArch64::zsub3};
4556 if (AArch64::GPR64spRegClass.
contains(DestReg) &&
4557 (AArch64::GPR64spRegClass.
contains(SrcReg) || SrcReg == AArch64::XZR)) {
4558 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
4564 }
else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) {
4578 if (AArch64::DDDDRegClass.
contains(DestReg) &&
4579 AArch64::DDDDRegClass.
contains(SrcReg)) {
4580 static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1,
4581 AArch64::dsub2, AArch64::dsub3};
4588 if (AArch64::DDDRegClass.
contains(DestReg) &&
4589 AArch64::DDDRegClass.
contains(SrcReg)) {
4590 static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1,
4598 if (AArch64::DDRegClass.
contains(DestReg) &&
4599 AArch64::DDRegClass.
contains(SrcReg)) {
4600 static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1};
4607 if (AArch64::QQQQRegClass.
contains(DestReg) &&
4608 AArch64::QQQQRegClass.
contains(SrcReg)) {
4609 static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
4610 AArch64::qsub2, AArch64::qsub3};
4617 if (AArch64::QQQRegClass.
contains(DestReg) &&
4618 AArch64::QQQRegClass.
contains(SrcReg)) {
4619 static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
4627 if (AArch64::QQRegClass.
contains(DestReg) &&
4628 AArch64::QQRegClass.
contains(SrcReg)) {
4629 static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1};
4635 if (AArch64::XSeqPairsClassRegClass.
contains(DestReg) &&
4636 AArch64::XSeqPairsClassRegClass.
contains(SrcReg)) {
4637 static const unsigned Indices[] = {AArch64::sube64, AArch64::subo64};
4639 AArch64::XZR, Indices);
4643 if (AArch64::WSeqPairsClassRegClass.
contains(DestReg) &&
4644 AArch64::WSeqPairsClassRegClass.
contains(SrcReg)) {
4645 static const unsigned Indices[] = {AArch64::sube32, AArch64::subo32};
4647 AArch64::WZR, Indices);
4651 if (AArch64::FPR128RegClass.
contains(DestReg) &&
4652 AArch64::FPR128RegClass.
contains(SrcReg)) {
4656 .
addReg(AArch64::Z0 + (SrcReg - AArch64::Q0))
4657 .
addReg(AArch64::Z0 + (SrcReg - AArch64::Q0));
4658 else if (Subtarget.hasNEON())
4677 if (AArch64::FPR64RegClass.
contains(DestReg) &&
4678 AArch64::FPR64RegClass.
contains(SrcReg)) {
4684 if (AArch64::FPR32RegClass.
contains(DestReg) &&
4685 AArch64::FPR32RegClass.
contains(SrcReg)) {
4691 if (AArch64::FPR16RegClass.
contains(DestReg) &&
4692 AArch64::FPR16RegClass.
contains(SrcReg)) {
4694 RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass);
4696 RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass);
4702 if (AArch64::FPR8RegClass.
contains(DestReg) &&
4703 AArch64::FPR8RegClass.
contains(SrcReg)) {
4705 RI.getMatchingSuperReg(DestReg, AArch64::bsub, &AArch64::FPR32RegClass);
4707 RI.getMatchingSuperReg(SrcReg, AArch64::bsub, &AArch64::FPR32RegClass);
4714 if (AArch64::FPR64RegClass.
contains(DestReg) &&
4715 AArch64::GPR64RegClass.
contains(SrcReg)) {
4720 if (AArch64::GPR64RegClass.
contains(DestReg) &&
4721 AArch64::FPR64RegClass.
contains(SrcReg)) {
4727 if (AArch64::FPR32RegClass.
contains(DestReg) &&
4728 AArch64::GPR32RegClass.
contains(SrcReg)) {
4733 if (AArch64::GPR32RegClass.
contains(DestReg) &&
4734 AArch64::FPR32RegClass.
contains(SrcReg)) {
4740 if (DestReg == AArch64::NZCV) {
4741 assert(AArch64::GPR64RegClass.
contains(SrcReg) &&
"Invalid NZCV copy");
4743 .
addImm(AArch64SysReg::NZCV)
4749 if (SrcReg == AArch64::NZCV) {
4750 assert(AArch64::GPR64RegClass.
contains(DestReg) &&
"Invalid NZCV copy");
4752 .
addImm(AArch64SysReg::NZCV)
4759 errs() <<
TRI.getRegAsmName(DestReg) <<
" = COPY "
4760 <<
TRI.getRegAsmName(SrcReg) <<
"\n";
4770 unsigned SubIdx0,
unsigned SubIdx1,
int FI,
4775 SrcReg0 =
TRI.getSubReg(SrcReg, SubIdx0);
4777 SrcReg1 =
TRI.getSubReg(SrcReg, SubIdx1);
4790 Register SrcReg,
bool isKill,
int FI,
4805 switch (
TRI->getSpillSize(*RC)) {
4807 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
4808 Opc = AArch64::STRBui;
4811 bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
4812 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
4813 Opc = AArch64::STRHui;
4814 else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
4816 "Unexpected register store without SVE store instructions");
4817 assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4818 "Unexpected register store without SVE2p1 or SME2");
4819 Opc = AArch64::STR_PXI;
4825 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
4826 Opc = AArch64::STRWui;
4830 assert(SrcReg != AArch64::WSP);
4831 }
else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
4832 Opc = AArch64::STRSui;
4833 else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
4834 Opc = AArch64::STR_PPXI;
4839 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
4840 Opc = AArch64::STRXui;
4844 assert(SrcReg != AArch64::SP);
4845 }
else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
4846 Opc = AArch64::STRDui;
4847 }
else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
4849 get(AArch64::STPWi), SrcReg, isKill,
4850 AArch64::sube32, AArch64::subo32, FI, MMO);
4855 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
4856 Opc = AArch64::STRQui;
4857 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
4858 assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
4859 Opc = AArch64::ST1Twov1d;
4861 }
else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
4863 get(AArch64::STPXi), SrcReg, isKill,
4864 AArch64::sube64, AArch64::subo64, FI, MMO);
4866 }
else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
4868 "Unexpected register store without SVE store instructions");
4869 Opc = AArch64::STR_ZXI;
4874 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
4875 assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
4876 Opc = AArch64::ST1Threev1d;
4881 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
4882 assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
4883 Opc = AArch64::ST1Fourv1d;
4885 }
else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
4886 assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
4887 Opc = AArch64::ST1Twov2d;
4889 }
else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
4890 AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
4892 "Unexpected register store without SVE store instructions");
4893 Opc = AArch64::STR_ZZXI;
4898 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
4899 assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
4900 Opc = AArch64::ST1Threev2d;
4902 }
else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
4904 "Unexpected register store without SVE store instructions");
4905 Opc = AArch64::STR_ZZZXI;
4910 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
4911 assert(Subtarget.hasNEON() &&
"Unexpected register store without NEON");
4912 Opc = AArch64::ST1Fourv2d;
4914 }
else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
4915 AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
4917 "Unexpected register store without SVE store instructions");
4918 Opc = AArch64::STR_ZZZZXI;
4923 assert(Opc &&
"Unknown register class");
4934 MI.addMemOperand(MMO);
4941 Register DestReg,
unsigned SubIdx0,
4942 unsigned SubIdx1,
int FI,
4946 bool IsUndef =
true;
4948 DestReg0 =
TRI.getSubReg(DestReg, SubIdx0);
4950 DestReg1 =
TRI.getSubReg(DestReg, SubIdx1);
4979 switch (
TRI->getSpillSize(*RC)) {
4981 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
4982 Opc = AArch64::LDRBui;
4985 bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
4986 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
4987 Opc = AArch64::LDRHui;
4988 else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
4990 "Unexpected register load without SVE load instructions");
4991 assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
4992 "Unexpected register load without SVE2p1 or SME2");
4995 Opc = AArch64::LDR_PXI;
5001 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
5002 Opc = AArch64::LDRWui;
5006 assert(DestReg != AArch64::WSP);
5007 }
else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
5008 Opc = AArch64::LDRSui;
5009 else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
5010 Opc = AArch64::LDR_PPXI;
5015 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
5016 Opc = AArch64::LDRXui;
5020 assert(DestReg != AArch64::SP);
5021 }
else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
5022 Opc = AArch64::LDRDui;
5023 }
else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
5025 get(AArch64::LDPWi), DestReg, AArch64::sube32,
5026 AArch64::subo32, FI, MMO);
5031 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
5032 Opc = AArch64::LDRQui;
5033 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
5034 assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
5035 Opc = AArch64::LD1Twov1d;
5037 }
else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
5039 get(AArch64::LDPXi), DestReg, AArch64::sube64,
5040 AArch64::subo64, FI, MMO);
5042 }
else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
5044 "Unexpected register load without SVE load instructions");
5045 Opc = AArch64::LDR_ZXI;
5050 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
5051 assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
5052 Opc = AArch64::LD1Threev1d;
5057 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
5058 assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
5059 Opc = AArch64::LD1Fourv1d;
5061 }
else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
5062 assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
5063 Opc = AArch64::LD1Twov2d;
5065 }
else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
5066 AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
5068 "Unexpected register load without SVE load instructions");
5069 Opc = AArch64::LDR_ZZXI;
5074 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
5075 assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
5076 Opc = AArch64::LD1Threev2d;
5078 }
else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
5080 "Unexpected register load without SVE load instructions");
5081 Opc = AArch64::LDR_ZZZXI;
5086 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
5087 assert(Subtarget.hasNEON() &&
"Unexpected register load without NEON");
5088 Opc = AArch64::LD1Fourv2d;
5090 }
else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
5091 AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
5093 "Unexpected register load without SVE load instructions");
5094 Opc = AArch64::LDR_ZZZZXI;
5100 assert(Opc &&
"Unknown register class");
5110 MI.addMemOperand(MMO);
5121 UseMI.getIterator()),
5123 return I.modifiesRegister(AArch64::NZCV, TRI) ||
5124 I.readsRegister(AArch64::NZCV, TRI);
5133 assert(
Offset.getScalable() % 2 == 0 &&
"Invalid frame offset");
5140 ByteSized =
Offset.getFixed();
5141 VGSized =
Offset.getScalable() / 2;
5149 int64_t &NumDataVectors) {
5153 assert(
Offset.getScalable() % 2 == 0 &&
"Invalid frame offset");
5155 NumBytes =
Offset.getFixed();
5157 NumPredicateVectors =
Offset.getScalable() / 2;
5162 if (NumPredicateVectors % 8 == 0 || NumPredicateVectors < -64 ||
5163 NumPredicateVectors > 62) {
5164 NumDataVectors = NumPredicateVectors / 8;
5165 NumPredicateVectors -= NumDataVectors * 8;
5172 int NumVGScaledBytes,
unsigned VG,
5179 Expr.
push_back((uint8_t)dwarf::DW_OP_plus);
5180 Comment << (NumBytes < 0 ?
" - " :
" + ") << std::abs(NumBytes);
5183 if (NumVGScaledBytes) {
5184 Expr.
push_back((uint8_t)dwarf::DW_OP_consts);
5187 Expr.
push_back((uint8_t)dwarf::DW_OP_bregx);
5191 Expr.
push_back((uint8_t)dwarf::DW_OP_mul);
5192 Expr.
push_back((uint8_t)dwarf::DW_OP_plus);
5194 Comment << (NumVGScaledBytes < 0 ?
" - " :
" + ")
5195 << std::abs(NumVGScaledBytes) <<
" * VG";
5204 int64_t NumBytes, NumVGScaledBytes;
5207 std::string CommentBuffer;
5210 if (Reg == AArch64::SP)
5212 else if (Reg == AArch64::FP)
5219 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
5220 Expr.
push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
5223 TRI.getDwarfRegNum(AArch64::VG,
true), Comment);
5227 DefCfaExpr.
push_back(dwarf::DW_CFA_def_cfa_expression);
5236 unsigned FrameReg,
unsigned Reg,
5238 bool LastAdjustmentWasScalable) {
5239 if (
Offset.getScalable())
5242 if (FrameReg == Reg && !LastAdjustmentWasScalable)
5245 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
5252 int64_t NumBytes, NumVGScaledBytes;
5254 OffsetFromDefCFA, NumBytes, NumVGScaledBytes);
5256 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
5259 if (!NumVGScaledBytes)
5262 std::string CommentBuffer;
5269 TRI.getDwarfRegNum(AArch64::VG,
true), Comment);
5273 CfaExpr.
push_back(dwarf::DW_CFA_expression);
5289 unsigned SrcReg, int64_t
Offset,
unsigned Opc,
5292 bool *HasWinCFI,
bool EmitCFAOffset,
5295 unsigned MaxEncoding, ShiftSize;
5297 case AArch64::ADDXri:
5298 case AArch64::ADDSXri:
5299 case AArch64::SUBXri:
5300 case AArch64::SUBSXri:
5301 MaxEncoding = 0xfff;
5304 case AArch64::ADDVL_XXI:
5305 case AArch64::ADDPL_XXI:
5306 case AArch64::ADDSVL_XXI:
5307 case AArch64::ADDSPL_XXI:
5322 if (Opc == AArch64::ADDVL_XXI || Opc == AArch64::ADDSVL_XXI)
5324 else if (Opc == AArch64::ADDPL_XXI || Opc == AArch64::ADDSPL_XXI)
5338 const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
5340 if (TmpReg == AArch64::XZR)
5342 &AArch64::GPR64RegClass);
5344 uint64_t ThisVal = std::min<uint64_t>(
Offset, MaxEncodableValue);
5345 unsigned LocalShiftSize = 0;
5346 if (ThisVal > MaxEncoding) {
5347 ThisVal = ThisVal >> ShiftSize;
5348 LocalShiftSize = ShiftSize;
5350 assert((ThisVal >> ShiftSize) <= MaxEncoding &&
5351 "Encoding cannot handle value that big");
5353 Offset -= ThisVal << LocalShiftSize;
5358 .
addImm(Sign * (
int)ThisVal);
5368 if (Sign == -1 || Opc == AArch64::SUBXri || Opc == AArch64::SUBSXri)
5369 CFAOffset += Change;
5371 CFAOffset -= Change;
5372 if (EmitCFAOffset && DestReg == TmpReg) {
5385 assert(Sign == 1 &&
"SEH directives should always have a positive sign");
5386 int Imm = (int)(ThisVal << LocalShiftSize);
5387 if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) ||
5388 (SrcReg == AArch64::FP && DestReg == AArch64::SP)) {
5397 assert(
Offset == 0 &&
"Expected remaining offset to be zero to "
5398 "emit a single SEH directive");
5399 }
else if (DestReg == AArch64::SP) {
5402 assert(SrcReg == AArch64::SP &&
"Unexpected SrcReg for SEH_StackAlloc");
5415 unsigned DestReg,
unsigned SrcReg,
5418 bool NeedsWinCFI,
bool *HasWinCFI,
5420 unsigned FrameReg) {
5427 bool UseSVL =
F.hasFnAttribute(
"aarch64_pstate_sm_body");
5429 int64_t Bytes, NumPredicateVectors, NumDataVectors;
5431 Offset, Bytes, NumPredicateVectors, NumDataVectors);
5434 if (Bytes || (!
Offset && SrcReg != DestReg)) {
5435 assert((DestReg != AArch64::SP || Bytes % 8 == 0) &&
5436 "SP increment/decrement not 8-byte aligned");
5437 unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri;
5440 Opc = SetNZCV ? AArch64::SUBSXri : AArch64::SUBXri;
5443 NeedsWinCFI, HasWinCFI, EmitCFAOffset, CFAOffset,
5445 CFAOffset += (Opc == AArch64::ADDXri || Opc == AArch64::ADDSXri)
5452 assert(!(SetNZCV && (NumPredicateVectors || NumDataVectors)) &&
5453 "SetNZCV not supported with SVE vectors");
5454 assert(!(NeedsWinCFI && (NumPredicateVectors || NumDataVectors)) &&
5455 "WinCFI not supported with SVE vectors");
5457 if (NumDataVectors) {
5459 UseSVL ? AArch64::ADDSVL_XXI : AArch64::ADDVL_XXI,
5460 TII, Flag, NeedsWinCFI,
nullptr, EmitCFAOffset,
5461 CFAOffset, FrameReg);
5466 if (NumPredicateVectors) {
5467 assert(DestReg != AArch64::SP &&
"Unaligned access to SP");
5469 UseSVL ? AArch64::ADDSPL_XXI : AArch64::ADDPL_XXI,
5470 TII, Flag, NeedsWinCFI,
nullptr, EmitCFAOffset,
5471 CFAOffset, FrameReg);
5489 if (
MI.isFullCopy()) {
5492 if (SrcReg == AArch64::SP && DstReg.
isVirtual()) {
5496 if (DstReg == AArch64::SP && SrcReg.
isVirtual()) {
5501 if (SrcReg == AArch64::NZCV || DstReg == AArch64::NZCV)
5529 if (
MI.isCopy() && Ops.
size() == 1 &&
5531 (Ops[0] == 0 || Ops[0] == 1)) {
5532 bool IsSpill = Ops[0] == 0;
5533 bool IsFill = !IsSpill;
5545 :
TRI.getMinimalPhysRegClass(Reg);
5551 "Mismatched register size in non subreg COPY");
5558 return &*--InsertPt;
5570 if (IsSpill && DstMO.
isUndef() && SrcReg == AArch64::WZR &&
5573 "Unexpected subreg on physical register");
5575 FrameIndex, &AArch64::GPR64RegClass, &
TRI,
5577 return &*--InsertPt;
5595 case AArch64::sub_32:
5596 FillRC = &AArch64::GPR32RegClass;
5599 FillRC = &AArch64::FPR32RegClass;
5602 FillRC = &AArch64::FPR64RegClass;
5608 TRI.getRegSizeInBits(*FillRC) &&
5609 "Mismatched regclass size on folded subreg COPY");
5628 bool *OutUseUnscaledOp,
5629 unsigned *OutUnscaledOp,
5630 int64_t *EmittableOffset) {
5632 if (EmittableOffset)
5633 *EmittableOffset = 0;
5634 if (OutUseUnscaledOp)
5635 *OutUseUnscaledOp =
false;
5641 switch (
MI.getOpcode()) {
5644 case AArch64::LD1Rv1d:
5645 case AArch64::LD1Rv2s:
5646 case AArch64::LD1Rv2d:
5647 case AArch64::LD1Rv4h:
5648 case AArch64::LD1Rv4s:
5649 case AArch64::LD1Rv8b:
5650 case AArch64::LD1Rv8h:
5651 case AArch64::LD1Rv16b:
5652 case AArch64::LD1Twov2d:
5653 case AArch64::LD1Threev2d:
5654 case AArch64::LD1Fourv2d:
5655 case AArch64::LD1Twov1d:
5656 case AArch64::LD1Threev1d:
5657 case AArch64::LD1Fourv1d:
5658 case AArch64::ST1Twov2d:
5659 case AArch64::ST1Threev2d:
5660 case AArch64::ST1Fourv2d:
5661 case AArch64::ST1Twov1d:
5662 case AArch64::ST1Threev1d:
5663 case AArch64::ST1Fourv1d:
5664 case AArch64::ST1i8:
5665 case AArch64::ST1i16:
5666 case AArch64::ST1i32:
5667 case AArch64::ST1i64:
5669 case AArch64::IRGstack:
5670 case AArch64::STGloop:
5671 case AArch64::STZGloop:
5676 TypeSize ScaleValue(0U,
false), Width(0U,
false);
5677 int64_t MinOff, MaxOff;
5683 bool IsMulVL = ScaleValue.isScalable();
5684 unsigned Scale = ScaleValue.getKnownMinValue();
5694 std::optional<unsigned> UnscaledOp =
5696 bool useUnscaledOp = UnscaledOp && (
Offset % Scale ||
Offset < 0);
5697 if (useUnscaledOp &&
5702 Scale = ScaleValue.getKnownMinValue();
5703 assert(IsMulVL == ScaleValue.isScalable() &&
5704 "Unscaled opcode has different value for scalable");
5706 int64_t Remainder =
Offset % Scale;
5707 assert(!(Remainder && useUnscaledOp) &&
5708 "Cannot have remainder when using unscaled op");
5710 assert(MinOff < MaxOff &&
"Unexpected Min/Max offsets");
5711 int64_t NewOffset =
Offset / Scale;
5712 if (MinOff <= NewOffset && NewOffset <= MaxOff)
5715 NewOffset = NewOffset < 0 ? MinOff : MaxOff;
5719 if (EmittableOffset)
5720 *EmittableOffset = NewOffset;
5721 if (OutUseUnscaledOp)
5722 *OutUseUnscaledOp = useUnscaledOp;
5723 if (OutUnscaledOp && UnscaledOp)
5724 *OutUnscaledOp = *UnscaledOp;
5737 unsigned Opcode =
MI.getOpcode();
5738 unsigned ImmIdx = FrameRegIdx + 1;
5740 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
5745 MI.eraseFromParent();
5751 unsigned UnscaledOp;
5754 &UnscaledOp, &NewOffset);
5758 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg,
false);
5760 MI.setDesc(
TII->get(UnscaledOp));
5762 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
5785 case AArch64::ADDSWrr:
5786 case AArch64::ADDSWri:
5787 case AArch64::ADDSXrr:
5788 case AArch64::ADDSXri:
5789 case AArch64::SUBSWrr:
5790 case AArch64::SUBSXrr:
5792 case AArch64::SUBSWri:
5793 case AArch64::SUBSXri:
5804 case AArch64::ADDWrr:
5805 case AArch64::ADDWri:
5806 case AArch64::SUBWrr:
5807 case AArch64::ADDSWrr:
5808 case AArch64::ADDSWri:
5809 case AArch64::SUBSWrr:
5811 case AArch64::SUBWri:
5812 case AArch64::SUBSWri:
5823 case AArch64::ADDXrr:
5824 case AArch64::ADDXri:
5825 case AArch64::SUBXrr:
5826 case AArch64::ADDSXrr:
5827 case AArch64::ADDSXri:
5828 case AArch64::SUBSXrr:
5830 case AArch64::SUBXri:
5831 case AArch64::SUBSXri:
5832 case AArch64::ADDv8i8:
5833 case AArch64::ADDv16i8:
5834 case AArch64::ADDv4i16:
5835 case AArch64::ADDv8i16:
5836 case AArch64::ADDv2i32:
5837 case AArch64::ADDv4i32:
5838 case AArch64::SUBv8i8:
5839 case AArch64::SUBv16i8:
5840 case AArch64::SUBv4i16:
5841 case AArch64::SUBv8i16:
5842 case AArch64::SUBv2i32:
5843 case AArch64::SUBv4i32:
5856 case AArch64::FADDHrr:
5857 case AArch64::FADDSrr:
5858 case AArch64::FADDDrr:
5859 case AArch64::FADDv4f16:
5860 case AArch64::FADDv8f16:
5861 case AArch64::FADDv2f32:
5862 case AArch64::FADDv2f64:
5863 case AArch64::FADDv4f32:
5864 case AArch64::FSUBHrr:
5865 case AArch64::FSUBSrr:
5866 case AArch64::FSUBDrr:
5867 case AArch64::FSUBv4f16:
5868 case AArch64::FSUBv8f16:
5869 case AArch64::FSUBv2f32:
5870 case AArch64::FSUBv2f64:
5871 case AArch64::FSUBv4f32:
5875 return Options.UnsafeFPMath ||
5892 unsigned CombineOpc,
unsigned ZeroReg = 0,
5893 bool CheckZeroReg =
false) {
5900 if (!
MI ||
MI->getParent() != &
MBB || (
unsigned)
MI->getOpcode() != CombineOpc)
5903 if (!
MRI.hasOneNonDBGUse(
MI->getOperand(0).getReg()))
5907 assert(
MI->getNumOperands() >= 4 &&
MI->getOperand(0).isReg() &&
5908 MI->getOperand(1).isReg() &&
MI->getOperand(2).isReg() &&
5909 MI->getOperand(3).isReg() &&
"MAdd/MSub must have a least 4 regs");
5911 if (
MI->getOperand(3).getReg() != ZeroReg)
5916 MI->findRegisterDefOperandIdx(AArch64::NZCV,
true) == -1)
5925 unsigned MulOpc,
unsigned ZeroReg) {
5941 bool Invert)
const {
5947 case AArch64::FADDHrr:
5948 case AArch64::FADDSrr:
5949 case AArch64::FADDDrr:
5950 case AArch64::FMULHrr:
5951 case AArch64::FMULSrr:
5952 case AArch64::FMULDrr:
5953 case AArch64::FMULX16:
5954 case AArch64::FMULX32:
5955 case AArch64::FMULX64:
5957 case AArch64::FADDv4f16:
5958 case AArch64::FADDv8f16:
5959 case AArch64::FADDv2f32:
5960 case AArch64::FADDv4f32:
5961 case AArch64::FADDv2f64:
5962 case AArch64::FMULv4f16:
5963 case AArch64::FMULv8f16:
5964 case AArch64::FMULv2f32:
5965 case AArch64::FMULv4f32:
5966 case AArch64::FMULv2f64:
5967 case AArch64::FMULXv4f16:
5968 case AArch64::FMULXv8f16:
5969 case AArch64::FMULXv2f32:
5970 case AArch64::FMULXv4f32:
5971 case AArch64::FMULXv2f64:
5975 case AArch64::FADD_ZZZ_H:
5976 case AArch64::FADD_ZZZ_S:
5977 case AArch64::FADD_ZZZ_D:
5978 case AArch64::FMUL_ZZZ_H:
5979 case AArch64::FMUL_ZZZ_S:
5980 case AArch64::FMUL_ZZZ_D:
5992 case AArch64::ADDWrr:
5993 case AArch64::ADDXrr:
5994 case AArch64::ANDWrr:
5995 case AArch64::ANDXrr:
5996 case AArch64::ORRWrr:
5997 case AArch64::ORRXrr:
5998 case AArch64::EORWrr:
5999 case AArch64::EORXrr:
6000 case AArch64::EONWrr:
6001 case AArch64::EONXrr:
6005 case AArch64::ADDv8i8:
6006 case AArch64::ADDv16i8:
6007 case AArch64::ADDv4i16:
6008 case AArch64::ADDv8i16:
6009 case AArch64::ADDv2i32:
6010 case AArch64::ADDv4i32:
6011 case AArch64::ADDv1i64:
6012 case AArch64::ADDv2i64:
6013 case AArch64::MULv8i8:
6014 case AArch64::MULv16i8:
6015 case AArch64::MULv4i16:
6016 case AArch64::MULv8i16:
6017 case AArch64::MULv2i32:
6018 case AArch64::MULv4i32:
6019 case AArch64::ANDv8i8:
6020 case AArch64::ANDv16i8:
6021 case AArch64::ORRv8i8:
6022 case AArch64::ORRv16i8:
6023 case AArch64::EORv8i8:
6024 case AArch64::EORv16i8:
6026 case AArch64::ADD_ZZZ_B:
6027 case AArch64::ADD_ZZZ_H:
6028 case AArch64::ADD_ZZZ_S:
6029 case AArch64::ADD_ZZZ_D:
6030 case AArch64::MUL_ZZZ_B:
6031 case AArch64::MUL_ZZZ_H:
6032 case AArch64::MUL_ZZZ_S:
6033 case AArch64::MUL_ZZZ_D:
6034 case AArch64::AND_ZZZ:
6035 case AArch64::ORR_ZZZ:
6036 case AArch64::EOR_ZZZ:
6066 auto setFound = [&](
int Opcode,
int Operand,
unsigned ZeroReg,
6074 auto setVFound = [&](
int Opcode,
int Operand,
unsigned Pattern) {
6086 case AArch64::ADDWrr:
6088 "ADDWrr does not have register operands");
6089 setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULADDW_OP1);
6090 setFound(AArch64::MADDWrrr, 2, AArch64::WZR, MCP::MULADDW_OP2);
6092 case AArch64::ADDXrr:
6093 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULADDX_OP1);
6094 setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULADDX_OP2);
6096 case AArch64::SUBWrr:
6097 setFound(AArch64::MADDWrrr, 2, AArch64::WZR, MCP::MULSUBW_OP2);
6098 setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULSUBW_OP1);
6100 case AArch64::SUBXrr:
6101 setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULSUBX_OP2);
6102 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBX_OP1);
6104 case AArch64::ADDWri:
6105 setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULADDWI_OP1);
6107 case AArch64::ADDXri:
6108 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULADDXI_OP1);
6110 case AArch64::SUBWri:
6111 setFound(AArch64::MADDWrrr, 1, AArch64::WZR, MCP::MULSUBWI_OP1);
6113 case AArch64::SUBXri:
6114 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBXI_OP1);
6116 case AArch64::ADDv8i8:
6117 setVFound(AArch64::MULv8i8, 1, MCP::MULADDv8i8_OP1);
6118 setVFound(AArch64::MULv8i8, 2, MCP::MULADDv8i8_OP2);
6120 case AArch64::ADDv16i8:
6121 setVFound(AArch64::MULv16i8, 1, MCP::MULADDv16i8_OP1);
6122 setVFound(AArch64::MULv16i8, 2, MCP::MULADDv16i8_OP2);
6124 case AArch64::ADDv4i16:
6125 setVFound(AArch64::MULv4i16, 1, MCP::MULADDv4i16_OP1);
6126 setVFound(AArch64::MULv4i16, 2, MCP::MULADDv4i16_OP2);
6127 setVFound(AArch64::MULv4i16_indexed, 1, MCP::MULADDv4i16_indexed_OP1);
6128 setVFound(AArch64::MULv4i16_indexed, 2, MCP::MULADDv4i16_indexed_OP2);
6130 case AArch64::ADDv8i16:
6131 setVFound(AArch64::MULv8i16, 1, MCP::MULADDv8i16_OP1);
6132 setVFound(AArch64::MULv8i16, 2, MCP::MULADDv8i16_OP2);
6133 setVFound(AArch64::MULv8i16_indexed, 1, MCP::MULADDv8i16_indexed_OP1);
6134 setVFound(AArch64::MULv8i16_indexed, 2, MCP::MULADDv8i16_indexed_OP2);
6136 case AArch64::ADDv2i32:
6137 setVFound(AArch64::MULv2i32, 1, MCP::MULADDv2i32_OP1);
6138 setVFound(AArch64::MULv2i32, 2, MCP::MULADDv2i32_OP2);
6139 setVFound(AArch64::MULv2i32_indexed, 1, MCP::MULADDv2i32_indexed_OP1);
6140 setVFound(AArch64::MULv2i32_indexed, 2, MCP::MULADDv2i32_indexed_OP2);
6142 case AArch64::ADDv4i32:
6143 setVFound(AArch64::MULv4i32, 1, MCP::MULADDv4i32_OP1);
6144 setVFound(AArch64::MULv4i32, 2, MCP::MULADDv4i32_OP2);
6145 setVFound(AArch64::MULv4i32_indexed, 1, MCP::MULADDv4i32_indexed_OP1);
6146 setVFound(AArch64::MULv4i32_indexed, 2, MCP::MULADDv4i32_indexed_OP2);
6148 case AArch64::SUBv8i8:
6149 setVFound(AArch64::MULv8i8, 1, MCP::MULSUBv8i8_OP1);
6150 setVFound(AArch64::MULv8i8, 2, MCP::MULSUBv8i8_OP2);
6152 case AArch64::SUBv16i8:
6153 setVFound(AArch64::MULv16i8, 1, MCP::MULSUBv16i8_OP1);
6154 setVFound(AArch64::MULv16i8, 2, MCP::MULSUBv16i8_OP2);
6156 case AArch64::SUBv4i16:
6157 setVFound(AArch64::MULv4i16, 1, MCP::MULSUBv4i16_OP1);
6158 setVFound(AArch64::MULv4i16, 2, MCP::MULSUBv4i16_OP2);
6159 setVFound(AArch64::MULv4i16_indexed, 1, MCP::MULSUBv4i16_indexed_OP1);
6160 setVFound(AArch64::MULv4i16_indexed, 2, MCP::MULSUBv4i16_indexed_OP2);
6162 case AArch64::SUBv8i16:
6163 setVFound(AArch64::MULv8i16, 1, MCP::MULSUBv8i16_OP1);
6164 setVFound(AArch64::MULv8i16, 2, MCP::MULSUBv8i16_OP2);
6165 setVFound(AArch64::MULv8i16_indexed, 1, MCP::MULSUBv8i16_indexed_OP1);
6166 setVFound(AArch64::MULv8i16_indexed, 2, MCP::MULSUBv8i16_indexed_OP2);
6168 case AArch64::SUBv2i32:
6169 setVFound(AArch64::MULv2i32, 1, MCP::MULSUBv2i32_OP1);
6170 setVFound(AArch64::MULv2i32, 2, MCP::MULSUBv2i32_OP2);
6171 setVFound(AArch64::MULv2i32_indexed, 1, MCP::MULSUBv2i32_indexed_OP1);
6172 setVFound(AArch64::MULv2i32_indexed, 2, MCP::MULSUBv2i32_indexed_OP2);
6174 case AArch64::SUBv4i32:
6175 setVFound(AArch64::MULv4i32, 1, MCP::MULSUBv4i32_OP1);
6176 setVFound(AArch64::MULv4i32, 2, MCP::MULSUBv4i32_OP2);
6177 setVFound(AArch64::MULv4i32_indexed, 1, MCP::MULSUBv4i32_indexed_OP1);
6178 setVFound(AArch64::MULv4i32_indexed, 2, MCP::MULSUBv4i32_indexed_OP2);
6195 auto Match = [&](
int Opcode,
int Operand,
unsigned Pattern) ->
bool {
6207 assert(
false &&
"Unsupported FP instruction in combiner\n");
6209 case AArch64::FADDHrr:
6211 "FADDHrr does not have register operands");
6213 Found =
Match(AArch64::FMULHrr, 1, MCP::FMULADDH_OP1);
6214 Found |=
Match(AArch64::FMULHrr, 2, MCP::FMULADDH_OP2);
6216 case AArch64::FADDSrr:
6218 "FADDSrr does not have register operands");
6220 Found |=
Match(AArch64::FMULSrr, 1, MCP::FMULADDS_OP1) ||
6221 Match(AArch64::FMULv1i32_indexed, 1, MCP::FMLAv1i32_indexed_OP1);
6223 Found |=
Match(AArch64::FMULSrr, 2, MCP::FMULADDS_OP2) ||
6224 Match(AArch64::FMULv1i32_indexed, 2, MCP::FMLAv1i32_indexed_OP2);
6226 case AArch64::FADDDrr:
6227 Found |=
Match(AArch64::FMULDrr, 1, MCP::FMULADDD_OP1) ||
6228 Match(AArch64::FMULv1i64_indexed, 1, MCP::FMLAv1i64_indexed_OP1);
6230 Found |=
Match(AArch64::FMULDrr, 2, MCP::FMULADDD_OP2) ||
6231 Match(AArch64::FMULv1i64_indexed, 2, MCP::FMLAv1i64_indexed_OP2);
6233 case AArch64::FADDv4f16:
6234 Found |=
Match(AArch64::FMULv4i16_indexed, 1, MCP::FMLAv4i16_indexed_OP1) ||
6235 Match(AArch64::FMULv4f16, 1, MCP::FMLAv4f16_OP1);
6237 Found |=
Match(AArch64::FMULv4i16_indexed, 2, MCP::FMLAv4i16_indexed_OP2) ||
6238 Match(AArch64::FMULv4f16, 2, MCP::FMLAv4f16_OP2);
6240 case AArch64::FADDv8f16:
6241 Found |=
Match(AArch64::FMULv8i16_indexed, 1, MCP::FMLAv8i16_indexed_OP1) ||
6242 Match(AArch64::FMULv8f16, 1, MCP::FMLAv8f16_OP1);
6244 Found |=
Match(AArch64::FMULv8i16_indexed, 2, MCP::FMLAv8i16_indexed_OP2) ||
6245 Match(AArch64::FMULv8f16, 2, MCP::FMLAv8f16_OP2);
6247 case AArch64::FADDv2f32:
6248 Found |=
Match(AArch64::FMULv2i32_indexed, 1, MCP::FMLAv2i32_indexed_OP1) ||
6249 Match(AArch64::FMULv2f32, 1, MCP::FMLAv2f32_OP1);
6251 Found |=
Match(AArch64::FMULv2i32_indexed, 2, MCP::FMLAv2i32_indexed_OP2) ||
6252 Match(AArch64::FMULv2f32, 2, MCP::FMLAv2f32_OP2);
6254 case AArch64::FADDv2f64:
6255 Found |=
Match(AArch64::FMULv2i64_indexed, 1, MCP::FMLAv2i64_indexed_OP1) ||
6256 Match(AArch64::FMULv2f64, 1, MCP::FMLAv2f64_OP1);
6258 Found |=
Match(AArch64::FMULv2i64_indexed, 2, MCP::FMLAv2i64_indexed_OP2) ||
6259 Match(AArch64::FMULv2f64, 2, MCP::FMLAv2f64_OP2);
6261 case AArch64::FADDv4f32:
6262 Found |=
Match(AArch64::FMULv4i32_indexed, 1, MCP::FMLAv4i32_indexed_OP1) ||
6263 Match(AArch64::FMULv4f32, 1, MCP::FMLAv4f32_OP1);
6265 Found |=
Match(AArch64::FMULv4i32_indexed, 2, MCP::FMLAv4i32_indexed_OP2) ||
6266 Match(AArch64::FMULv4f32, 2, MCP::FMLAv4f32_OP2);
6268 case AArch64::FSUBHrr:
6269 Found =
Match(AArch64::FMULHrr, 1, MCP::FMULSUBH_OP1);
6270 Found |=
Match(AArch64::FMULHrr, 2, MCP::FMULSUBH_OP2);
6271 Found |=
Match(AArch64::FNMULHrr, 1, MCP::FNMULSUBH_OP1);
6273 case AArch64::FSUBSrr:
6274 Found =
Match(AArch64::FMULSrr, 1, MCP::FMULSUBS_OP1);
6276 Found |=
Match(AArch64::FMULSrr, 2, MCP::FMULSUBS_OP2) ||
6277 Match(AArch64::FMULv1i32_indexed, 2, MCP::FMLSv1i32_indexed_OP2);
6279 Found |=
Match(AArch64::FNMULSrr, 1, MCP::FNMULSUBS_OP1);
6281 case AArch64::FSUBDrr:
6282 Found =
Match(AArch64::FMULDrr, 1, MCP::FMULSUBD_OP1);
6284 Found |=
Match(AArch64::FMULDrr, 2, MCP::FMULSUBD_OP2) ||
6285 Match(AArch64::FMULv1i64_indexed, 2, MCP::FMLSv1i64_indexed_OP2);
6287 Found |=
Match(AArch64::FNMULDrr, 1, MCP::FNMULSUBD_OP1);
6289 case AArch64::FSUBv4f16:
6290 Found |=
Match(AArch64::FMULv4i16_indexed, 2, MCP::FMLSv4i16_indexed_OP2) ||
6291 Match(AArch64::FMULv4f16, 2, MCP::FMLSv4f16_OP2);
6293 Found |=
Match(AArch64::FMULv4i16_indexed, 1, MCP::FMLSv4i16_indexed_OP1) ||
6294 Match(AArch64::FMULv4f16, 1, MCP::FMLSv4f16_OP1);
6296 case AArch64::FSUBv8f16:
6297 Found |=
Match(AArch64::FMULv8i16_indexed, 2, MCP::FMLSv8i16_indexed_OP2) ||
6298 Match(AArch64::FMULv8f16, 2, MCP::FMLSv8f16_OP2);
6300 Found |=
Match(AArch64::FMULv8i16_indexed, 1, MCP::FMLSv8i16_indexed_OP1) ||
6301 Match(AArch64::FMULv8f16, 1, MCP::FMLSv8f16_OP1);
6303 case AArch64::FSUBv2f32:
6304 Found |=
Match(AArch64::FMULv2i32_indexed, 2, MCP::FMLSv2i32_indexed_OP2) ||
6305 Match(AArch64::FMULv2f32, 2, MCP::FMLSv2f32_OP2);
6307 Found |=
Match(AArch64::FMULv2i32_indexed, 1, MCP::FMLSv2i32_indexed_OP1) ||
6308 Match(AArch64::FMULv2f32, 1, MCP::FMLSv2f32_OP1);
6310 case AArch64::FSUBv2f64:
6311 Found |=
Match(AArch64::FMULv2i64_indexed, 2, MCP::FMLSv2i64_indexed_OP2) ||
6312 Match(AArch64::FMULv2f64, 2, MCP::FMLSv2f64_OP2);
6314 Found |=
Match(AArch64::FMULv2i64_indexed, 1, MCP::FMLSv2i64_indexed_OP1) ||
6315 Match(AArch64::FMULv2f64, 1, MCP::FMLSv2f64_OP1);
6317 case AArch64::FSUBv4f32:
6318 Found |=
Match(AArch64::FMULv4i32_indexed, 2, MCP::FMLSv4i32_indexed_OP2) ||
6319 Match(AArch64::FMULv4f32, 2, MCP::FMLSv4f32_OP2);
6321 Found |=
Match(AArch64::FMULv4i32_indexed, 1, MCP::FMLSv4i32_indexed_OP1) ||
6322 Match(AArch64::FMULv4f32, 1, MCP::FMLSv4f32_OP1);
6333 auto Match = [&](
unsigned Opcode,
int Operand,
unsigned Pattern) ->
bool {
6340 if (
MI &&
MI->getOpcode() == TargetOpcode::COPY &&
6341 MI->getOperand(1).getReg().isVirtual())
6342 MI =
MRI.getUniqueVRegDef(
MI->getOperand(1).getReg());
6343 if (
MI &&
MI->getOpcode() == Opcode) {
6355 case AArch64::FMULv2f32:
6356 Found =
Match(AArch64::DUPv2i32lane, 1, MCP::FMULv2i32_indexed_OP1);
6357 Found |=
Match(AArch64::DUPv2i32lane, 2, MCP::FMULv2i32_indexed_OP2);
6359 case AArch64::FMULv2f64:
6360 Found =
Match(AArch64::DUPv2i64lane, 1, MCP::FMULv2i64_indexed_OP1);
6361 Found |=
Match(AArch64::DUPv2i64lane, 2, MCP::FMULv2i64_indexed_OP2);
6363 case AArch64::FMULv4f16:
6364 Found =
Match(AArch64::DUPv4i16lane, 1, MCP::FMULv4i16_indexed_OP1);
6365 Found |=
Match(AArch64::DUPv4i16lane, 2, MCP::FMULv4i16_indexed_OP2);
6367 case AArch64::FMULv4f32:
6368 Found =
Match(AArch64::DUPv4i32lane, 1, MCP::FMULv4i32_indexed_OP1);
6369 Found |=
Match(AArch64::DUPv4i32lane, 2, MCP::FMULv4i32_indexed_OP2);
6371 case AArch64::FMULv8f16:
6372 Found =
Match(AArch64::DUPv8i16lane, 1, MCP::FMULv8i16_indexed_OP1);
6373 Found |=
Match(AArch64::DUPv8i16lane, 2, MCP::FMULv8i16_indexed_OP2);
6386 auto Match = [&](
unsigned Opcode,
unsigned Pattern) ->
bool {
6389 if (
MI !=
nullptr && (
MI->getOpcode() == Opcode) &&
6390 MRI.hasOneNonDBGUse(
MI->getOperand(0).getReg()) &&
6404 case AArch64::FNEGDr:
6406 case AArch64::FNEGSr:
6538 case AArch64::SUBWrr:
6539 case AArch64::SUBSWrr:
6540 case AArch64::SUBXrr:
6541 case AArch64::SUBSXrr:
6582 bool DoRegPressureReduce)
const {
6599 DoRegPressureReduce);
6628 const Register *ReplacedAddend =
nullptr) {
6629 assert(IdxMulOpd == 1 || IdxMulOpd == 2);
6631 unsigned IdxOtherOpd = IdxMulOpd == 1 ? 2 : 1;
6634 Register SrcReg0 = MUL->getOperand(1).getReg();
6635 bool Src0IsKill = MUL->getOperand(1).isKill();
6636 Register SrcReg1 = MUL->getOperand(2).getReg();
6637 bool Src1IsKill = MUL->getOperand(2).isKill();
6641 if (ReplacedAddend) {
6643 SrcReg2 = *ReplacedAddend;
6651 MRI.constrainRegClass(ResultReg, RC);
6653 MRI.constrainRegClass(SrcReg0, RC);
6655 MRI.constrainRegClass(SrcReg1, RC);
6657 MRI.constrainRegClass(SrcReg2, RC);
6660 if (kind == FMAInstKind::Default)
6665 else if (kind == FMAInstKind::Indexed)
6670 .
addImm(MUL->getOperand(3).getImm());
6671 else if (kind == FMAInstKind::Accumulator)
6677 assert(
false &&
"Invalid FMA instruction kind \n");
6691 if (AArch64::FPR32RegClass.hasSubClassEq(RC))
6692 Opc = AArch64::FNMADDSrrr;
6693 else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
6694 Opc = AArch64::FNMADDDrrr;
6706 MRI.constrainRegClass(ResultReg, RC);
6708 MRI.constrainRegClass(SrcReg0, RC);
6710 MRI.constrainRegClass(SrcReg1, RC);
6712 MRI.constrainRegClass(SrcReg2, RC);
6728 unsigned IdxDupOp,
unsigned MulOpc,
6730 assert(((IdxDupOp == 1) || (IdxDupOp == 2)) &&
6731 "Invalid index of FMUL operand");
6739 if (Dup->
getOpcode() == TargetOpcode::COPY)
6743 MRI.clearKillFlags(DupSrcReg);
6744 MRI.constrainRegClass(DupSrcReg, RC);
6748 unsigned IdxMulOp = IdxDupOp == 1 ? 2 : 1;
6772 FMAInstKind::Accumulator);
6789 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
6804 genNeg(MF,
MRI,
TII, Root, InsInstrs, InstrIdxForVirtReg, MnegOpc, RC);
6806 FMAInstKind::Accumulator, &NewVR);
6818 FMAInstKind::Indexed);
6831 genNeg(MF,
MRI,
TII, Root, InsInstrs, InstrIdxForVirtReg, MnegOpc, RC);
6834 FMAInstKind::Indexed, &NewVR);
6859 unsigned IdxMulOpd,
unsigned MaddOpc,
unsigned VR,
6861 assert(IdxMulOpd == 1 || IdxMulOpd == 2);
6865 Register SrcReg0 = MUL->getOperand(1).getReg();
6866 bool Src0IsKill = MUL->getOperand(1).isKill();
6867 Register SrcReg1 = MUL->getOperand(2).getReg();
6868 bool Src1IsKill = MUL->getOperand(2).isKill();
6871 MRI.constrainRegClass(ResultReg, RC);
6873 MRI.constrainRegClass(SrcReg0, RC);
6875 MRI.constrainRegClass(SrcReg1, RC);
6877 MRI.constrainRegClass(VR, RC);
6899 assert(IdxOpd1 == 1 || IdxOpd1 == 2);
6900 unsigned IdxOtherOpd = IdxOpd1 == 1 ? 2 : 1;
6910 Register NewVR =
MRI.createVirtualRegister(
MRI.getRegClass(RegA));
6913 if (Opcode == AArch64::SUBSWrr)
6914 Opcode = AArch64::SUBWrr;
6915 else if (Opcode == AArch64::SUBSXrr)
6916 Opcode = AArch64::SUBXrr;
6918 assert((Opcode == AArch64::SUBWrr || Opcode == AArch64::SUBXrr) &&
6919 "Unexpected instruction opcode.");
6930 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
6956 DelInstrs, InstrIdxForVirtReg);
6962 InstrIdxForVirtReg);
6968 InstrIdxForVirtReg);
6977 Opc = AArch64::MADDWrrr;
6978 RC = &AArch64::GPR32RegClass;
6980 Opc = AArch64::MADDXrrr;
6981 RC = &AArch64::GPR64RegClass;
6992 Opc = AArch64::MADDWrrr;
6993 RC = &AArch64::GPR32RegClass;
6995 Opc = AArch64::MADDXrrr;
6996 RC = &AArch64::GPR64RegClass;
7008 unsigned BitSize, OrrOpc, ZeroReg;
7010 OrrOpc = AArch64::ORRWri;
7011 OrrRC = &AArch64::GPR32spRegClass;
7013 ZeroReg = AArch64::WZR;
7014 Opc = AArch64::MADDWrrr;
7015 RC = &AArch64::GPR32RegClass;
7017 OrrOpc = AArch64::ORRXri;
7018 OrrRC = &AArch64::GPR64spRegClass;
7020 ZeroReg = AArch64::XZR;
7021 Opc = AArch64::MADDXrrr;
7022 RC = &AArch64::GPR64RegClass;
7024 Register NewVR =
MRI.createVirtualRegister(OrrRC);
7035 if (
Insn.size() != 1)
7037 auto MovI =
Insn.begin();
7040 if (MovI->Opcode == OrrOpc)
7046 assert((MovI->Opcode == AArch64::MOVNWi ||
7047 MovI->Opcode == AArch64::MOVZWi) &&
7050 assert((MovI->Opcode == AArch64::MOVNXi ||
7051 MovI->Opcode == AArch64::MOVZXi) &&
7058 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7059 MUL =
genMaddR(MF,
MRI,
TII, Root, InsInstrs, 1, Opc, NewVR, RC);
7070 unsigned SubOpc, ZeroReg;
7072 SubOpc = AArch64::SUBWrr;
7073 SubRC = &AArch64::GPR32spRegClass;
7074 ZeroReg = AArch64::WZR;
7075 Opc = AArch64::MADDWrrr;
7076 RC = &AArch64::GPR32RegClass;
7078 SubOpc = AArch64::SUBXrr;
7079 SubRC = &AArch64::GPR64spRegClass;
7080 ZeroReg = AArch64::XZR;
7081 Opc = AArch64::MADDXrrr;
7082 RC = &AArch64::GPR64RegClass;
7084 Register NewVR =
MRI.createVirtualRegister(SubRC);
7091 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7092 MUL =
genMaddR(MF,
MRI,
TII, Root, InsInstrs, 1, Opc, NewVR, RC);
7102 Opc = AArch64::MSUBWrrr;
7103 RC = &AArch64::GPR32RegClass;
7105 Opc = AArch64::MSUBXrrr;
7106 RC = &AArch64::GPR64RegClass;
7118 unsigned BitSize, OrrOpc, ZeroReg;
7120 OrrOpc = AArch64::ORRWri;
7121 OrrRC = &AArch64::GPR32spRegClass;
7123 ZeroReg = AArch64::WZR;
7124 Opc = AArch64::MADDWrrr;
7125 RC = &AArch64::GPR32RegClass;
7127 OrrOpc = AArch64::ORRXri;
7128 OrrRC = &AArch64::GPR64spRegClass;
7130 ZeroReg = AArch64::XZR;
7131 Opc = AArch64::MADDXrrr;
7132 RC = &AArch64::GPR64RegClass;
7134 Register NewVR =
MRI.createVirtualRegister(OrrRC);
7144 if (
Insn.size() != 1)
7146 auto MovI =
Insn.begin();
7149 if (MovI->Opcode == OrrOpc)
7155 assert((MovI->Opcode == AArch64::MOVNWi ||
7156 MovI->Opcode == AArch64::MOVZWi) &&
7159 assert((MovI->Opcode == AArch64::MOVNXi ||
7160 MovI->Opcode == AArch64::MOVZXi) &&
7167 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7168 MUL =
genMaddR(MF,
MRI,
TII, Root, InsInstrs, 1, Opc, NewVR, RC);
7173 Opc = AArch64::MLAv8i8;
7174 RC = &AArch64::FPR64RegClass;
7178 Opc = AArch64::MLAv8i8;
7179 RC = &AArch64::FPR64RegClass;
7183 Opc = AArch64::MLAv16i8;
7184 RC = &AArch64::FPR128RegClass;
7188 Opc = AArch64::MLAv16i8;
7189 RC = &AArch64::FPR128RegClass;
7193 Opc = AArch64::MLAv4i16;
7194 RC = &AArch64::FPR64RegClass;
7198 Opc = AArch64::MLAv4i16;
7199 RC = &AArch64::FPR64RegClass;
7203 Opc = AArch64::MLAv8i16;
7204 RC = &AArch64::FPR128RegClass;
7208 Opc = AArch64::MLAv8i16;
7209 RC = &AArch64::FPR128RegClass;
7213 Opc = AArch64::MLAv2i32;
7214 RC = &AArch64::FPR64RegClass;
7218 Opc = AArch64::MLAv2i32;
7219 RC = &AArch64::FPR64RegClass;
7223 Opc = AArch64::MLAv4i32;
7224 RC = &AArch64::FPR128RegClass;
7228 Opc = AArch64::MLAv4i32;
7229 RC = &AArch64::FPR128RegClass;
7234 Opc = AArch64::MLAv8i8;
7235 RC = &AArch64::FPR64RegClass;
7237 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i8,
7241 Opc = AArch64::MLSv8i8;
7242 RC = &AArch64::FPR64RegClass;
7246 Opc = AArch64::MLAv16i8;
7247 RC = &AArch64::FPR128RegClass;
7249 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv16i8,
7253 Opc = AArch64::MLSv16i8;
7254 RC = &AArch64::FPR128RegClass;
7258 Opc = AArch64::MLAv4i16;
7259 RC = &AArch64::FPR64RegClass;
7261 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16,
7265 Opc = AArch64::MLSv4i16;
7266 RC = &AArch64::FPR64RegClass;
7270 Opc = AArch64::MLAv8i16;
7271 RC = &AArch64::FPR128RegClass;
7273 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16,
7277 Opc = AArch64::MLSv8i16;
7278 RC = &AArch64::FPR128RegClass;
7282 Opc = AArch64::MLAv2i32;
7283 RC = &AArch64::FPR64RegClass;
7285 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32,
7289 Opc = AArch64::MLSv2i32;
7290 RC = &AArch64::FPR64RegClass;
7294 Opc = AArch64::MLAv4i32;
7295 RC = &AArch64::FPR128RegClass;
7297 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32,
7301 Opc = AArch64::MLSv4i32;
7302 RC = &AArch64::FPR128RegClass;
7307 Opc = AArch64::MLAv4i16_indexed;
7308 RC = &AArch64::FPR64RegClass;
7312 Opc = AArch64::MLAv4i16_indexed;
7313 RC = &AArch64::FPR64RegClass;
7317 Opc = AArch64::MLAv8i16_indexed;
7318 RC = &AArch64::FPR128RegClass;
7322 Opc = AArch64::MLAv8i16_indexed;
7323 RC = &AArch64::FPR128RegClass;
7327 Opc = AArch64::MLAv2i32_indexed;
7328 RC = &AArch64::FPR64RegClass;
7332 Opc = AArch64::MLAv2i32_indexed;
7333 RC = &AArch64::FPR64RegClass;
7337 Opc = AArch64::MLAv4i32_indexed;
7338 RC = &AArch64::FPR128RegClass;
7342 Opc = AArch64::MLAv4i32_indexed;
7343 RC = &AArch64::FPR128RegClass;
7348 Opc = AArch64::MLAv4i16_indexed;
7349 RC = &AArch64::FPR64RegClass;
7351 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16,
7355 Opc = AArch64::MLSv4i16_indexed;
7356 RC = &AArch64::FPR64RegClass;
7360 Opc = AArch64::MLAv8i16_indexed;
7361 RC = &AArch64::FPR128RegClass;
7363 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16,
7367 Opc = AArch64::MLSv8i16_indexed;
7368 RC = &AArch64::FPR128RegClass;
7372 Opc = AArch64::MLAv2i32_indexed;
7373 RC = &AArch64::FPR64RegClass;
7375 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32,
7379 Opc = AArch64::MLSv2i32_indexed;
7380 RC = &AArch64::FPR64RegClass;
7384 Opc = AArch64::MLAv4i32_indexed;
7385 RC = &AArch64::FPR128RegClass;
7387 InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32,
7391 Opc = AArch64::MLSv4i32_indexed;
7392 RC = &AArch64::FPR128RegClass;
7398 Opc = AArch64::FMADDHrrr;
7399 RC = &AArch64::FPR16RegClass;
7403 Opc = AArch64::FMADDSrrr;
7404 RC = &AArch64::FPR32RegClass;
7408 Opc = AArch64::FMADDDrrr;
7409 RC = &AArch64::FPR64RegClass;
7414 Opc = AArch64::FMADDHrrr;
7415 RC = &AArch64::FPR16RegClass;
7419 Opc = AArch64::FMADDSrrr;
7420 RC = &AArch64::FPR32RegClass;
7424 Opc = AArch64::FMADDDrrr;
7425 RC = &AArch64::FPR64RegClass;
7430 Opc = AArch64::FMLAv1i32_indexed;
7431 RC = &AArch64::FPR32RegClass;
7433 FMAInstKind::Indexed);
7436 Opc = AArch64::FMLAv1i32_indexed;
7437 RC = &AArch64::FPR32RegClass;
7439 FMAInstKind::Indexed);
7443 Opc = AArch64::FMLAv1i64_indexed;
7444 RC = &AArch64::FPR64RegClass;
7446 FMAInstKind::Indexed);
7449 Opc = AArch64::FMLAv1i64_indexed;
7450 RC = &AArch64::FPR64RegClass;
7452 FMAInstKind::Indexed);
7456 RC = &AArch64::FPR64RegClass;
7457 Opc = AArch64::FMLAv4i16_indexed;
7459 FMAInstKind::Indexed);
7462 RC = &AArch64::FPR64RegClass;
7463 Opc = AArch64::FMLAv4f16;
7465 FMAInstKind::Accumulator);
7468 RC = &AArch64::FPR64RegClass;
7469 Opc = AArch64::FMLAv4i16_indexed;
7471 FMAInstKind::Indexed);
7474 RC = &AArch64::FPR64RegClass;
7475 Opc = AArch64::FMLAv4f16;
7477 FMAInstKind::Accumulator);
7482 RC = &AArch64::FPR64RegClass;
7484 Opc = AArch64::FMLAv2i32_indexed;
7486 FMAInstKind::Indexed);
7488 Opc = AArch64::FMLAv2f32;
7490 FMAInstKind::Accumulator);
7495 RC = &AArch64::FPR64RegClass;
7497 Opc = AArch64::FMLAv2i32_indexed;
7499 FMAInstKind::Indexed);
7501 Opc = AArch64::FMLAv2f32;
7503 FMAInstKind::Accumulator);
7508 RC = &AArch64::FPR128RegClass;
7509 Opc = AArch64::FMLAv8i16_indexed;
7511 FMAInstKind::Indexed);
7514 RC = &AArch64::FPR128RegClass;
7515 Opc = AArch64::FMLAv8f16;
7517 FMAInstKind::Accumulator);
7520 RC = &AArch64::FPR128RegClass;
7521 Opc = AArch64::FMLAv8i16_indexed;
7523 FMAInstKind::Indexed);
7526 RC = &AArch64::FPR128RegClass;
7527 Opc = AArch64::FMLAv8f16;
7529 FMAInstKind::Accumulator);
7534 RC = &AArch64::FPR128RegClass;
7536 Opc = AArch64::FMLAv2i64_indexed;
7538 FMAInstKind::Indexed);
7540 Opc = AArch64::FMLAv2f64;
7542 FMAInstKind::Accumulator);
7547 RC = &AArch64::FPR128RegClass;
7549 Opc = AArch64::FMLAv2i64_indexed;
7551 FMAInstKind::Indexed);
7553 Opc = AArch64::FMLAv2f64;
7555 FMAInstKind::Accumulator);
7561 RC = &AArch64::FPR128RegClass;
7563 Opc = AArch64::FMLAv4i32_indexed;
7565 FMAInstKind::Indexed);
7567 Opc = AArch64::FMLAv4f32;
7569 FMAInstKind::Accumulator);
7575 RC = &AArch64::FPR128RegClass;
7577 Opc = AArch64::FMLAv4i32_indexed;
7579 FMAInstKind::Indexed);
7581 Opc = AArch64::FMLAv4f32;
7583 FMAInstKind::Accumulator);
7588 Opc = AArch64::FNMSUBHrrr;
7589 RC = &AArch64::FPR16RegClass;
7593 Opc = AArch64::FNMSUBSrrr;
7594 RC = &AArch64::FPR32RegClass;
7598 Opc = AArch64::FNMSUBDrrr;
7599 RC = &AArch64::FPR64RegClass;
7604 Opc = AArch64::FNMADDHrrr;
7605 RC = &AArch64::FPR16RegClass;
7609 Opc = AArch64::FNMADDSrrr;
7610 RC = &AArch64::FPR32RegClass;
7614 Opc = AArch64::FNMADDDrrr;
7615 RC = &AArch64::FPR64RegClass;
7620 Opc = AArch64::FMSUBHrrr;
7621 RC = &AArch64::FPR16RegClass;
7625 Opc = AArch64::FMSUBSrrr;
7626 RC = &AArch64::FPR32RegClass;
7630 Opc = AArch64::FMSUBDrrr;
7631 RC = &AArch64::FPR64RegClass;
7636 Opc = AArch64::FMLSv1i32_indexed;
7637 RC = &AArch64::FPR32RegClass;
7639 FMAInstKind::Indexed);
7643 Opc = AArch64::FMLSv1i64_indexed;
7644 RC = &AArch64::FPR64RegClass;
7646 FMAInstKind::Indexed);
7651 RC = &AArch64::FPR64RegClass;
7657 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7659 Opc = AArch64::FMLAv4f16;
7661 FMAInstKind::Accumulator, &NewVR);
7663 Opc = AArch64::FMLAv4i16_indexed;
7665 FMAInstKind::Indexed, &NewVR);
7670 RC = &AArch64::FPR64RegClass;
7671 Opc = AArch64::FMLSv4f16;
7673 FMAInstKind::Accumulator);
7676 RC = &AArch64::FPR64RegClass;
7677 Opc = AArch64::FMLSv4i16_indexed;
7679 FMAInstKind::Indexed);
7684 RC = &AArch64::FPR64RegClass;
7686 Opc = AArch64::FMLSv2i32_indexed;
7688 FMAInstKind::Indexed);
7690 Opc = AArch64::FMLSv2f32;
7692 FMAInstKind::Accumulator);
7698 RC = &AArch64::FPR128RegClass;
7704 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7706 Opc = AArch64::FMLAv8f16;
7708 FMAInstKind::Accumulator, &NewVR);
7710 Opc = AArch64::FMLAv8i16_indexed;
7712 FMAInstKind::Indexed, &NewVR);
7717 RC = &AArch64::FPR128RegClass;
7718 Opc = AArch64::FMLSv8f16;
7720 FMAInstKind::Accumulator);
7723 RC = &AArch64::FPR128RegClass;
7724 Opc = AArch64::FMLSv8i16_indexed;
7726 FMAInstKind::Indexed);
7731 RC = &AArch64::FPR128RegClass;
7733 Opc = AArch64::FMLSv2i64_indexed;
7735 FMAInstKind::Indexed);
7737 Opc = AArch64::FMLSv2f64;
7739 FMAInstKind::Accumulator);
7745 RC = &AArch64::FPR128RegClass;
7747 Opc = AArch64::FMLSv4i32_indexed;
7749 FMAInstKind::Indexed);
7751 Opc = AArch64::FMLSv4f32;
7753 FMAInstKind::Accumulator);
7758 RC = &AArch64::FPR64RegClass;
7764 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7766 Opc = AArch64::FMLAv2i32_indexed;
7768 FMAInstKind::Indexed, &NewVR);
7770 Opc = AArch64::FMLAv2f32;
7772 FMAInstKind::Accumulator, &NewVR);
7778 RC = &AArch64::FPR128RegClass;
7784 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7786 Opc = AArch64::FMLAv4i32_indexed;
7788 FMAInstKind::Indexed, &NewVR);
7790 Opc = AArch64::FMLAv4f32;
7792 FMAInstKind::Accumulator, &NewVR);
7798 RC = &AArch64::FPR128RegClass;
7804 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
7806 Opc = AArch64::FMLAv2i64_indexed;
7808 FMAInstKind::Indexed, &NewVR);
7810 Opc = AArch64::FMLAv2f64;
7812 FMAInstKind::Accumulator, &NewVR);
7822 &AArch64::FPR128RegClass,
MRI);
7831 &AArch64::FPR128RegClass,
MRI);
7840 &AArch64::FPR128_loRegClass,
MRI);
7849 &AArch64::FPR128RegClass,
MRI);
7858 &AArch64::FPR128_loRegClass,
MRI);
7877 for (
auto *
MI : InsInstrs)
7878 MI->setFlags(Flags);
7919 bool IsNegativeBranch =
false;
7920 bool IsTestAndBranch =
false;
7921 unsigned TargetBBInMI = 0;
7922 switch (
MI.getOpcode()) {
7931 case AArch64::CBNZW:
7932 case AArch64::CBNZX:
7934 IsNegativeBranch =
true;
7939 IsTestAndBranch =
true;
7941 case AArch64::TBNZW:
7942 case AArch64::TBNZX:
7944 IsNegativeBranch =
true;
7945 IsTestAndBranch =
true;
7951 if (IsTestAndBranch &&
MI.getOperand(1).getImm())
7955 assert(
MI.getParent() &&
"Incomplete machine instruciton\n");
7968 if (!
MRI->hasOneNonDBGUse(CopyVReg))
7970 if (!
MRI->hasOneDef(CopyVReg))
7979 case AArch64::ANDWri:
7980 case AArch64::ANDXri: {
7981 if (IsTestAndBranch)
7985 if (!
MRI->hasOneNonDBGUse(VReg))
7999 assert(!
MRI->def_empty(NewReg) &&
"Register must be defined.");
8005 unsigned Opc = (Imm < 32)
8006 ? (IsNegativeBranch ? AArch64::TBNZW : AArch64::TBZW)
8007 : (IsNegativeBranch ? AArch64::TBNZX : AArch64::TBZX);
8020 if (!Is32Bit && Imm < 32)
8022 MI.eraseFromParent();
8026 case AArch64::CSINCWr:
8027 case AArch64::CSINCXr: {
8046 if (IsNegativeBranch)
8049 MI.eraseFromParent();
8055std::pair<unsigned, unsigned>
8058 return std::make_pair(TF & Mask, TF & ~Mask);
8063 using namespace AArch64II;
8065 static const std::pair<unsigned, const char *> TargetFlags[] = {
8066 {MO_PAGE,
"aarch64-page"}, {MO_PAGEOFF,
"aarch64-pageoff"},
8067 {MO_G3,
"aarch64-g3"}, {MO_G2,
"aarch64-g2"},
8068 {MO_G1,
"aarch64-g1"}, {MO_G0,
"aarch64-g0"},
8069 {MO_HI12,
"aarch64-hi12"}};
8075 using namespace AArch64II;
8077 static const std::pair<unsigned, const char *> TargetFlags[] = {
8078 {MO_COFFSTUB,
"aarch64-coffstub"},
8079 {MO_GOT,
"aarch64-got"},
8080 {MO_NC,
"aarch64-nc"},
8081 {MO_S,
"aarch64-s"},
8082 {MO_TLS,
"aarch64-tls"},
8083 {MO_DLLIMPORT,
"aarch64-dllimport"},
8084 {MO_PREL,
"aarch64-prel"},
8085 {MO_TAGGED,
"aarch64-tagged"},
8086 {MO_ARM64EC_CALLMANGLE,
"aarch64-arm64ec-callmangle"},
8093 static const std::pair<MachineMemOperand::Flags, const char *> TargetFlags[] =
8201 for (
unsigned Reg : AArch64::GPR64RegClass) {
8203 Reg != AArch64::LR &&
8204 Reg != AArch64::X16 &&
8205 Reg != AArch64::X17 &&
8206 C.isAvailableAcrossAndOutOfSeq(
Reg,
TRI) &&
8207 C.isAvailableInsideSeq(
Reg,
TRI))
8238 return SubtargetA.hasV8_3aOps() == SubtargetB.hasV8_3aOps();
8241std::optional<outliner::OutlinedFunction>
8243 std::vector<outliner::Candidate> &RepeatedSequenceLocs)
const {
8246 unsigned SequenceSize = 0;
8247 for (
auto &
MI : FirstCand)
8250 unsigned NumBytesToCreateFrame = 0;
8260 if (std::adjacent_find(
8261 RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
8265 if (outliningCandidatesSigningScopeConsensus(a, b) &&
8266 outliningCandidatesSigningKeyConsensus(a, b) &&
8267 outliningCandidatesV8_3OpsConsensus(a, b)) {
8271 }) != RepeatedSequenceLocs.end()) {
8272 return std::nullopt;
8289 unsigned NumBytesToCheckLRInTCEpilogue = 0;
8290 if (FirstCand.getMF()
8294 NumBytesToCreateFrame += 8;
8297 auto LRCheckMethod = Subtarget.getAuthenticatedLRCheckMethod();
8298 NumBytesToCheckLRInTCEpilogue =
8302 if (isTailCallReturnInst(RepeatedSequenceLocs[0].back()))
8303 SequenceSize += NumBytesToCheckLRInTCEpilogue;
8311 for (
auto &
MI :
C) {
8312 if (
MI.modifiesRegister(AArch64::SP, &
TRI)) {
8313 switch (
MI.getOpcode()) {
8314 case AArch64::ADDXri:
8315 case AArch64::ADDWri:
8316 assert(
MI.getNumOperands() == 4 &&
"Wrong number of operands");
8318 "Expected operand to be immediate");
8320 "Expected operand to be a register");
8324 if (
MI.getOperand(1).getReg() == AArch64::SP)
8325 SPValue +=
MI.getOperand(2).getImm();
8329 case AArch64::SUBXri:
8330 case AArch64::SUBWri:
8331 assert(
MI.getNumOperands() == 4 &&
"Wrong number of operands");
8333 "Expected operand to be immediate");
8335 "Expected operand to be a register");
8339 if (
MI.getOperand(1).getReg() == AArch64::SP)
8340 SPValue -=
MI.getOperand(2).getImm();
8357 if (RepeatedSequenceLocs.size() < 2)
8358 return std::nullopt;
8362 unsigned FlagsSetInAll = 0xF;
8366 FlagsSetInAll &=
C.Flags;
8368 unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back().getOpcode();
8371 auto SetCandidateCallInfo =
8372 [&RepeatedSequenceLocs](
unsigned CallID,
unsigned NumBytesForCall) {
8374 C.setCallInfo(CallID, NumBytesForCall);
8378 NumBytesToCreateFrame += 4;
8381 return C.getMF()->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement();
8386 unsigned CFICount = 0;
8387 for (
auto &
I : RepeatedSequenceLocs[0]) {
8388 if (
I.isCFIInstruction())
8398 std::vector<MCCFIInstruction> CFIInstructions =
8399 C.getMF()->getFrameInstructions();
8401 if (CFICount > 0 && CFICount != CFIInstructions.size())
8402 return std::nullopt;
8410 if (!
MI.modifiesRegister(AArch64::SP, &
TRI) &&
8411 !
MI.readsRegister(AArch64::SP, &
TRI))
8417 if (
MI.modifiesRegister(AArch64::SP, &
TRI))
8422 if (
MI.mayLoadOrStore()) {
8425 bool OffsetIsScalable;
8429 if (!getMemOperandWithOffset(
MI,
Base,
Offset, OffsetIsScalable, &
TRI) ||
8430 !
Base->isReg() ||
Base->getReg() != AArch64::SP)
8434 if (OffsetIsScalable)
8442 TypeSize Scale(0U,
false), DummyWidth(0U,
false);
8443 getMemOpInfo(
MI.getOpcode(), Scale, DummyWidth, MinOffset, MaxOffset);
8446 if (
Offset < MinOffset * (int64_t)Scale.getFixedValue() ||
8447 Offset > MaxOffset * (int64_t)Scale.getFixedValue())
8462 bool AllStackInstrsSafe =
llvm::all_of(FirstCand, IsSafeToFixup);
8466 if (RepeatedSequenceLocs[0].back().isTerminator()) {
8468 NumBytesToCreateFrame = 0;
8469 unsigned NumBytesForCall = 4 + NumBytesToCheckLRInTCEpilogue;
8473 else if (LastInstrOpcode == AArch64::BL ||
8474 ((LastInstrOpcode == AArch64::BLR ||
8475 LastInstrOpcode == AArch64::BLRNoIP) &&
8479 NumBytesToCreateFrame = NumBytesToCheckLRInTCEpilogue;
8487 unsigned NumBytesNoStackCalls = 0;
8488 std::vector<outliner::Candidate> CandidatesWithoutStackFixups;
8493 (
C.Flags & MachineOutlinerMBBFlags::LRUnavailableSomewhere)
8494 ?
C.isAvailableAcrossAndOutOfSeq(AArch64::LR,
TRI)
8503 C.getMF()->getFunction().hasFnAttribute(Attribute::NoReturn);
8506 if (LRAvailable && !IsNoReturn) {
8507 NumBytesNoStackCalls += 4;
8509 CandidatesWithoutStackFixups.push_back(
C);
8514 else if (findRegisterToSaveLRTo(
C)) {
8515 NumBytesNoStackCalls += 12;
8517 CandidatesWithoutStackFixups.push_back(
C);
8522 else if (
C.isAvailableInsideSeq(AArch64::SP,
TRI)) {
8523 NumBytesNoStackCalls += 12;
8525 CandidatesWithoutStackFixups.push_back(
C);
8531 NumBytesNoStackCalls += SequenceSize;
8538 if (!AllStackInstrsSafe ||
8539 NumBytesNoStackCalls <= RepeatedSequenceLocs.size() * 12) {
8540 RepeatedSequenceLocs = CandidatesWithoutStackFixups;
8590 if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) {
8594 (!
C.isAvailableAcrossAndOutOfSeq(AArch64::LR,
TRI) ||
8595 !findRegisterToSaveLRTo(
C));
8601 if (RepeatedSequenceLocs.size() < 2) {
8602 RepeatedSequenceLocs.clear();
8603 return std::nullopt;
8609 if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) {
8612 bool ModStackToSaveLR =
false;
8613 if (std::any_of(FirstCand.begin(), std::prev(FirstCand.end()),
8615 ModStackToSaveLR =
true;
8624 ModStackToSaveLR =
true;
8626 if (ModStackToSaveLR) {
8628 if (!AllStackInstrsSafe) {
8629 RepeatedSequenceLocs.clear();
8630 return std::nullopt;
8634 NumBytesToCreateFrame += 8;
8641 return std::nullopt;
8644 NumBytesToCreateFrame, FrameID);
8648 Function &
F, std::vector<outliner::Candidate> &Candidates)
const {
8652 const auto &CFn = Candidates.front().getMF()->getFunction();
8656 if (CFn.hasFnAttribute(
"sign-return-address"))
8657 F.addFnAttr(CFn.getFnAttribute(
"sign-return-address"));
8658 if (CFn.hasFnAttribute(
"sign-return-address-key"))
8659 F.addFnAttr(CFn.getFnAttribute(
"sign-return-address-key"));
8661 AArch64GenInstrInfo::mergeOutliningCandidateAttributes(
F, Candidates);
8669 if (!OutlineFromLinkOnceODRs &&
F.hasLinkOnceODRLinkage())
8683 if (!AFI || AFI->
hasRedZone().value_or(
true))
8696 unsigned &Flags)
const {
8698 "Must track liveness!");
8700 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
8715 auto AreAllUnsafeRegsDead = [&LRU]() {
8732 bool LRAvailableEverywhere =
true;
8737 if (
MI.isCall() && !
MI.isTerminator())
8738 Flags |= MachineOutlinerMBBFlags::HasCalls;
8743 auto CreateNewRangeStartingAt =
8744 [&RangeBegin, &RangeEnd,
8746 RangeBegin = NewBegin;
8747 RangeEnd = std::next(RangeBegin);
8750 auto SaveRangeIfNonEmpty = [&RangeLen, &Ranges, &RangeBegin, &RangeEnd]() {
8755 Ranges.push_back(std::make_pair(RangeBegin, RangeEnd));
8763 for (; FirstPossibleEndPt !=
MBB.
instr_rend(); ++FirstPossibleEndPt) {
8767 UpdateWholeMBBFlags(*FirstPossibleEndPt);
8768 if (AreAllUnsafeRegsDead())
8775 CreateNewRangeStartingAt(FirstPossibleEndPt->getIterator());
8781 UpdateWholeMBBFlags(
MI);
8782 if (!AreAllUnsafeRegsDead()) {
8783 SaveRangeIfNonEmpty();
8784 CreateNewRangeStartingAt(
MI.getIterator());
8787 LRAvailableEverywhere &= LRU.
available(AArch64::LR);
8788 RangeBegin =
MI.getIterator();
8793 if (AreAllUnsafeRegsDead())
8794 SaveRangeIfNonEmpty();
8799 std::reverse(Ranges.begin(), Ranges.end());
8802 if (!LRAvailableEverywhere)
8803 Flags |= MachineOutlinerMBBFlags::LRUnavailableSomewhere;
8809 unsigned Flags)
const {
8817 switch (
MI.getOpcode()) {
8819 case AArch64::PACIASP:
8820 case AArch64::PACIBSP:
8821 case AArch64::PACIASPPC:
8822 case AArch64::PACIBSPPC:
8823 case AArch64::AUTIASP:
8824 case AArch64::AUTIBSP:
8825 case AArch64::AUTIASPPCi:
8826 case AArch64::AUTIASPPCr:
8827 case AArch64::AUTIBSPPCi:
8828 case AArch64::AUTIBSPPCr:
8829 case AArch64::RETAA:
8830 case AArch64::RETAB:
8831 case AArch64::RETAASPPCi:
8832 case AArch64::RETAASPPCr:
8833 case AArch64::RETABSPPCi:
8834 case AArch64::RETABSPPCr:
8835 case AArch64::EMITBKEY:
8836 case AArch64::PAUTH_PROLOGUE:
8837 case AArch64::PAUTH_EPILOGUE:
8851 if (
MI.isCFIInstruction())
8855 if (
MI.isTerminator())
8864 assert(!MOP.isCFIIndex());
8867 if (MOP.isReg() && !MOP.isImplicit() &&
8868 (MOP.getReg() == AArch64::LR || MOP.getReg() == AArch64::W30))
8875 if (
MI.getOpcode() == AArch64::ADRP)
8896 if (MOP.isGlobal()) {
8897 Callee = dyn_cast<Function>(MOP.getGlobal());
8904 if (Callee && Callee->getName() ==
"\01_mcount")
8912 if (
MI.getOpcode() == AArch64::BLR ||
8913 MI.getOpcode() == AArch64::BLRNoIP ||
MI.getOpcode() == AArch64::BL)
8917 return UnknownCallOutlineType;
8925 return UnknownCallOutlineType;
8933 return UnknownCallOutlineType;
8958 bool OffsetIsScalable;
8961 if (!
MI.mayLoadOrStore() ||
8964 (
Base->isReg() &&
Base->getReg() != AArch64::SP))
8969 int64_t Dummy1, Dummy2;
8972 assert(StackOffsetOperand.
isImm() &&
"Stack offset wasn't immediate!");
8974 assert(Scale != 0 &&
"Unexpected opcode!");
8975 assert(!OffsetIsScalable &&
"Expected offset to be a byte offset");
8980 int64_t NewImm = (
Offset + 16) / (int64_t)Scale.getFixedValue();
8981 StackOffsetOperand.
setImm(NewImm);
8987 bool ShouldSignReturnAddr) {
8988 if (!ShouldSignReturnAddr)
8994 TII->get(AArch64::PAUTH_EPILOGUE))
9010 unsigned TailOpcode;
9011 if (Call->getOpcode() == AArch64::BL) {
9012 TailOpcode = AArch64::TCRETURNdi;
9014 assert(Call->getOpcode() == AArch64::BLR ||
9015 Call->getOpcode() == AArch64::BLRNoIP);
9016 TailOpcode = AArch64::TCRETURNriALL;
9019 .
add(Call->getOperand(0))
9022 Call->eraseFromParent();
9027 bool IsLeafFunction =
true;
9031 return MI.isCall() && !
MI.isReturn();
9041 "Can only fix up stack references once");
9042 fixupPostOutline(
MBB);
9044 IsLeafFunction =
false;
9055 Et = std::prev(
MBB.
end());
9068 unsigned DwarfReg =
MRI->getDwarfRegNum(AArch64::LR,
true);
9071 int64_t StackPosEntry =
9124 fixupPostOutline(
MBB);
9135 .addGlobalAddress(M.getNamedValue(MF.
getName()))
9145 .addGlobalAddress(M.getNamedValue(MF.
getName())));
9160 Register Reg = findRegisterToSaveLRTo(
C);
9161 assert(Reg &&
"No callee-saved register available?");
9195 .addGlobalAddress(M.getNamedValue(MF.
getName())));
9211 bool AllowSideEffects)
const {
9216 if (
TRI.isGeneralPurposeRegister(MF, Reg)) {
9218 }
else if (STI.hasSVE()) {
9228std::optional<DestSourcePair>
9233 if (
MI.getOpcode() == AArch64::ORRWrs &&
9234 MI.getOperand(1).getReg() == AArch64::WZR &&
9235 MI.getOperand(3).getImm() == 0x0 &&
9237 (!
MI.getOperand(0).getReg().isVirtual() ||
9238 MI.getOperand(0).getSubReg() == 0) &&
9239 (!
MI.getOperand(0).getReg().isPhysical() ||
9240 MI.findRegisterDefOperandIdx(
MI.getOperand(0).getReg() - AArch64::W0 +
9241 AArch64::X0) == -1))
9244 if (
MI.getOpcode() == AArch64::ORRXrs &&
9245 MI.getOperand(1).getReg() == AArch64::XZR &&
9246 MI.getOperand(3).getImm() == 0x0)
9249 return std::nullopt;
9252std::optional<DestSourcePair>
9254 if (
MI.getOpcode() == AArch64::ORRWrs &&
9255 MI.getOperand(1).getReg() == AArch64::WZR &&
9256 MI.getOperand(3).getImm() == 0x0)
9258 return std::nullopt;
9261std::optional<RegImmPair>
9270 return std::nullopt;
9272 switch (
MI.getOpcode()) {
9274 return std::nullopt;
9275 case AArch64::SUBWri:
9276 case AArch64::SUBXri:
9277 case AArch64::SUBSWri:
9278 case AArch64::SUBSXri:
9281 case AArch64::ADDSWri:
9282 case AArch64::ADDSXri:
9283 case AArch64::ADDWri:
9284 case AArch64::ADDXri: {
9286 if (!
MI.getOperand(0).isReg() || !
MI.getOperand(1).isReg() ||
9287 !
MI.getOperand(2).isImm())
9288 return std::nullopt;
9289 int Shift =
MI.getOperand(3).getImm();
9290 assert((Shift == 0 || Shift == 12) &&
"Shift can be either 0 or 12");
9291 Offset = Sign * (
MI.getOperand(2).getImm() << Shift);
9300static std::optional<ParamLoadedValue>
9304 auto DestSrc =
TII->isCopyLikeInstr(
MI);
9306 return std::nullopt;
9308 Register DestReg = DestSrc->Destination->getReg();
9309 Register SrcReg = DestSrc->Source->getReg();
9314 if (DestReg == DescribedReg)
9318 if (
MI.getOpcode() == AArch64::ORRWrs &&
9319 TRI->isSuperRegister(DestReg, DescribedReg))
9323 if (
MI.getOpcode() == AArch64::ORRXrs &&
9324 TRI->isSubRegister(DestReg, DescribedReg)) {
9325 Register SrcSubReg =
TRI->getSubReg(SrcReg, AArch64::sub_32);
9329 assert(!
TRI->isSuperOrSubRegisterEq(DestReg, DescribedReg) &&
9330 "Unhandled ORR[XW]rs copy case");
9332 return std::nullopt;
9351 return MI.getOpcode() == AArch64::INLINEASM_BR;
9369 switch (
MI.getOpcode()) {
9370 case TargetOpcode::G_BRJT:
9371 case AArch64::JumpTableDest32:
9372 case AArch64::JumpTableDest16:
9373 case AArch64::JumpTableDest8:
9384std::optional<ParamLoadedValue>
9389 switch (
MI.getOpcode()) {
9390 case AArch64::MOVZWi:
9391 case AArch64::MOVZXi: {
9394 if (!
TRI->isSuperRegisterEq(
MI.getOperand(0).getReg(), Reg))
9395 return std::nullopt;
9397 if (!
MI.getOperand(1).isImm())
9398 return std::nullopt;
9399 int64_t Immediate =
MI.getOperand(1).getImm();
9400 int Shift =
MI.getOperand(2).getImm();
9404 case AArch64::ORRWrs:
9405 case AArch64::ORRXrs:
9415 ExtMI.
getOpcode() == TargetOpcode::G_ZEXT ||
9416 ExtMI.
getOpcode() == TargetOpcode::G_ANYEXT);
9419 if (ExtMI.
getOpcode() == TargetOpcode::G_ANYEXT)
9423 if (!
MRI.hasOneNonDBGUse(DefReg))
9428 auto *UserMI = &*
MRI.use_instr_nodbg_begin(DefReg);
9429 return UserMI->getOpcode() == TargetOpcode::G_PTR_ADD;
9450 unsigned Scale)
const {
9461 unsigned Shift =
Log2_64(NumBytes);
9462 if (NumBytes &&
Offset > 0 && (
Offset / NumBytes) <= (1LL << 12) - 1 &&
9470 return Scale == 1 || (Scale > 0 && Scale == NumBytes);
9475 return AArch64::BLRNoIP;
9477 return AArch64::BLR;
9482 Register TargetReg,
bool FrameSetup)
const {
9483 assert(TargetReg != AArch64::SP &&
"New top of stack cannot aleady be in SP");
9495 MF.
insert(MBBInsertPoint, LoopTestMBB);
9498 MF.
insert(MBBInsertPoint, LoopBodyMBB);
9500 MF.
insert(MBBInsertPoint, ExitMBB);
9510 BuildMI(*LoopTestMBB, LoopTestMBB->
end(),
DL,
TII->get(AArch64::SUBSXrx64),
9524 BuildMI(*LoopBodyMBB, LoopBodyMBB->
end(),
DL,
TII->get(AArch64::STRXui))
9537 BuildMI(*ExitMBB, ExitMBB->
end(),
DL,
TII->get(AArch64::ADDXri), AArch64::SP)
9562 return ExitMBB->
begin();
9573 : PredBranch(PredBranch),
Cond(
Cond.begin(),
Cond.end()) {}
9575 bool shouldIgnoreForPipelining(
const MachineInstr *
MI)
const override {
9578 return MI == PredBranch;
9581 std::optional<bool> createTripCountGreaterCondition(
9593 void adjustTripCount(
int TripCountAdjust)
override {}
9595 void disposed()
override {}
9603 case AArch64::CBNZW:
9604 case AArch64::CBNZX:
9607 case AArch64::TBNZW:
9608 case AArch64::TBNZX:
9614std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
9622 if (
TBB == LoopBB && FBB == LoopBB)
9629 assert((
TBB == LoopBB || FBB == LoopBB) &&
9630 "The Loop must be a single-basic-block loop");
9641 if (CondBranch->
getOpcode() == AArch64::Bcc) {
9643 if (
MI.modifiesRegister(AArch64::NZCV, &
TRI)) {
9653 if (!Reg.isVirtual())
9655 PredBranch =
MRI.getVRegDef(Reg);
9658 if (PredBranch->
isPHI())
9667 return std::make_unique<AArch64PipelinerLoopInfo>(PredBranch,
Cond);
9670#define GET_INSTRINFO_HELPERS
9671#define GET_INSTRMAP_INFO
9672#include "AArch64GenInstrInfo.inc"
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
static cl::opt< unsigned > BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
static void genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, unsigned IdxOpd1, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg)
Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.
static bool getMaddPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
Find instructions that can be turned into madd.
static AArch64CC::CondCode findCondCodeUsedByInstr(const MachineInstr &Instr)
Find a condition code used by the instruction.
static MachineInstr * genFusedMultiplyAcc(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.
static bool isCombineInstrCandidate64(unsigned Opc)
static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg)
static bool areCFlagsAccessedBetweenInstrs(MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
True when condition flags are accessed (either by writing or reading) on the instruction trace starti...
static bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
Floating-Point Support.
static bool isADDSRegImm(unsigned Opcode)
static MachineInstr * genFusedMultiplyIdxNeg(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional...
static bool isCompareAndBranch(unsigned Opcode)
static unsigned sForm(MachineInstr &Instr)
Get opcode of S version of Instr.
static bool isCombineInstrSettingFlag(unsigned Opc)
static bool getFNEGPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static bool canPairLdStOpc(unsigned FirstOpc, unsigned SecondOpc)
static int findCondCodeUseOperandIdxForBranchOrSelect(const MachineInstr &Instr)
static unsigned getBranchDisplacementBits(unsigned Opc)
static std::optional< ParamLoadedValue > describeORRLoadedValue(const MachineInstr &MI, Register DescribedReg, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
If the given ORR instruction is a copy, and DescribedReg overlaps with the destination register then,...
static bool getFMULPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static MachineInstr * genFusedMultiplyAccNeg(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional...
static void appendVGScaledOffsetExpr(SmallVectorImpl< char > &Expr, int NumBytes, int NumVGScaledBytes, unsigned VG, llvm::raw_string_ostream &Comment)
static MachineInstr * genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example ...
static bool scaleOffset(unsigned Opc, int64_t &Offset)
static bool canCombineWithFMUL(MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
unsigned scaledOffsetOpcode(unsigned Opcode, unsigned &Scale)
static MachineInstr * genFusedMultiplyIdx(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.
static MachineInstr * genIndexedMultiply(MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxDupOp, unsigned MulOpc, const TargetRegisterClass *RC, MachineRegisterInfo &MRI)
Fold (FMUL x (DUP y lane)) into (FMUL_indexed x y lane)
static bool isSUBSRegImm(unsigned Opcode)
static bool UpdateOperandRegClass(MachineInstr &Instr)
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
static bool canCmpInstrBeRemoved(MachineInstr &MI, MachineInstr &CmpInstr, int CmpValue, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > &CCUseInstrs, bool &IsInvertCC)
unsigned unscaledOffsetOpcode(unsigned Opcode)
static bool canInstrSubstituteCmpInstr(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI)
Check if CmpInstr can be substituted by MI.
static UsedNZCV getUsedNZCV(AArch64CC::CondCode CC)
static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg, unsigned MnegOpc, const TargetRegisterClass *RC)
genNeg - Helper to generate an intermediate negation of the second operand of Root
static bool isCombineInstrCandidateFP(const MachineInstr &Inst)
static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
static unsigned convertToNonFlagSettingOpc(const MachineInstr &MI)
Return the opcode that does not set flags when possible - otherwise return the original opcode.
static const MachineInstrBuilder & AddSubReg(const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
static bool outliningCandidatesV8_3OpsConsensus(const outliner::Candidate &a, const outliner::Candidate &b)
static bool isCombineInstrCandidate32(unsigned Opc)
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned offsetExtendOpcode(unsigned Opcode)
static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register DestReg, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static bool getMiscPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
Find other MI combine patterns.
static bool outliningCandidatesSigningKeyConsensus(const outliner::Candidate &a, const outliner::Candidate &b)
static bool outliningCandidatesSigningScopeConsensus(const outliner::Candidate &a, const outliner::Candidate &b)
static bool shouldClusterFI(const MachineFrameInfo &MFI, int FI1, int64_t Offset1, unsigned Opcode1, int FI2, int64_t Offset2, unsigned Opcode2)
static cl::opt< unsigned > TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
static MachineInstr * genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind=FMAInstKind::Default, const Register *ReplacedAddend=nullptr)
genFusedMultiply - Generate fused multiply instructions.
static bool isCombineInstrCandidate(unsigned Opc)
static unsigned regOffsetOpcode(unsigned Opcode)
MachineOutlinerClass
Constants defining how certain sequences should be outlined.
@ MachineOutlinerTailCall
Emit a save, restore, call, and return.
@ MachineOutlinerRegSave
Emit a call and tail-call.
@ MachineOutlinerNoLRSave
Only emit a branch.
@ MachineOutlinerThunk
Emit a call and return.
static cl::opt< unsigned > BDisplacementBits("aarch64-b-offset-bits", cl::Hidden, cl::init(26), cl::desc("Restrict range of B instructions (DEBUG)"))
static bool areCFlagsAliveInSuccessors(const MachineBasicBlock *MBB)
Check if AArch64::NZCV should be alive in successors of MBB.
static void emitFrameOffsetAdj(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int64_t Offset, unsigned Opc, const TargetInstrInfo *TII, MachineInstr::MIFlag Flag, bool NeedsWinCFI, bool *HasWinCFI, bool EmitCFAOffset, StackOffset CFAOffset, unsigned FrameReg)
static bool isCheapImmediate(const MachineInstr &MI, unsigned BitSize)
static cl::opt< unsigned > CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewVReg=nullptr)
static void signOutlinedFunction(MachineFunction &MF, MachineBasicBlock &MBB, const AArch64InstrInfo *TII, bool ShouldSignReturnAddr)
static MachineInstr * genFNegatedMAD(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs)
static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
static void storeRegPairToStackSlot(const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register SrcReg, bool IsKill, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
bool shouldSignReturnAddress(const MachineFunction &MF) const
const SetOfInstructions & getLOHRelated() const
bool needsDwarfUnwindInfo(const MachineFunction &MF) const
void setOutliningStyle(std::string Style)
std::optional< bool > hasRedZone() const
bool shouldSignWithBKey() const
static bool isHForm(const MachineInstr &MI)
Returns whether the instruction is in H form (16 bit operands)
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool hasBTISemantics(const MachineInstr &MI)
Returns whether the instruction can be compatible with non-zero BTYPE.
static bool isQForm(const MachineInstr &MI)
Returns whether the instruction is in Q form (128 bit operands)
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
static bool isTailCallReturnInst(const MachineInstr &MI)
Returns true if MI is one of the TCRETURN* instructions.
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
static unsigned convertToFlagSettingOpc(unsigned Opc)
Return the opcode that set flags when possible.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the immediate offset operator of a load/store.
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
static std::optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
AArch64InstrInfo(const AArch64Subtarget &STI)
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, TypeSize &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
static bool isFpOrNEON(const MachineInstr &MI)
Returns whether the instruction is FP or NEON.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isThroughputPattern(unsigned Pattern) const override
Return true when a code sequence can improve throughput.
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
bool isFunctionSafeToSplit(const MachineFunction &MF) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
Return true when Inst is associative and commutative so that it can be reassociated.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock::iterator probedStackAlloc(MachineBasicBlock::iterator MBBI, Register TargetReg, bool FrameSetup) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
CombinerObjective getCombinerObjective(unsigned Pattern) const override
bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset, unsigned Scale) const
std::optional< DestSourcePair > isCopyLikeInstrImpl(const MachineInstr &MI) const override
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MCInst getNop() const override
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
const AArch64RegisterInfo * getRegisterInfo() const override
bool isTargetILP32() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & front() const
front - Get the first element.
size_t size() const
size - Get the array size.
This class represents an Operation in the Expression.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Module * getParent()
Get the module that this global value is contained inside of...
A set of register units used to track register liveness.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
static LocationSize precise(uint64_t Value)
This class is intended to be used as a base class for asm properties and features specific to the tar...
bool usesWindowsCFI() const
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
constexpr bool isValid() const
static constexpr unsigned NoRegister
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
reverse_instr_iterator instr_rbegin()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
MBBSectionID getSectionID() const
Returns the section ID of this basic block.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
reverse_instr_iterator instr_rend()
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
Instructions::iterator instr_iterator
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
instr_iterator instr_end()
Instructions::const_iterator const_instr_iterator
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
iterator_range< succ_iterator > successors()
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
void setStackID(int ObjectIdx, uint8_t ID)
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getNumObjects() const
Return the number of objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
const MachineBasicBlock * getParent() const
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
uint32_t getFlags() const
Return the MI flags bitvector.
const std::vector< MachineJumpTableEntry > & getJumpTables() const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineFunction * getMachineFunction(const Function &F) const
Returns the MachineFunction associated to IR function F if there is one, otherwise nullptr.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
void setIsDead(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachineOperand CreateImm(int64_t Val)
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
A Module instance is used to store all the information related to an LLVM module.
MI-level patchpoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Represents a location in source code.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void append(StringRef RHS)
Append from a StringRef.
StringRef str() const
Explicit conversion to StringRef.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level stackmap operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
int64_t getScalable() const
Returns the scalable component of the stack.
static StackOffset get(int64_t Fixed, int64_t Scalable)
static StackOffset getScalable(int64_t Scalable)
static StackOffset getFixed(int64_t Fixed)
MI-level Statepoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given statepoint should emit.
Object returned by analyzeLoopForPipelining.
TargetInstrInfo - Interface to description of machine instruction set.
virtual void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual CombinerObjective getCombinerObjective(unsigned Pattern) const
Return the objective of a combiner pattern.
virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const
Return true if the function is a viable candidate for machine function splitting.
Primary interface to the complete machine description for the target machine.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
static constexpr TypeSize getScalable(ScalarTy MinimumSize)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static CondCode getInvertedCondCode(CondCode Code)
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
unsigned getCheckerSizeInBytes(AuthCheckMethod Method)
Returns the number of bytes added by checkAuthenticatedRegister.
const SysReg * lookupSysRegByName(StringRef)
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
static unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm)
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit...
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
static uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize)
encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of th...
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl< ImmInsnModel > &Insn)
Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more real move-immediate instructions to...
static const uint64_t InstrFlagIsWhile
static const uint64_t InstrFlagIsPTestLike
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ C
The default llvm calling convention, compatible with C.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Renamable
Register that may be renamed.
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
static bool isCondBranchOpcode(int Opc)
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)
static bool isPTrueOpcode(unsigned Opc)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
static bool isIndirectBranchOpcode(int Opc)
MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
AArch64MachineCombinerPattern
@ MULSUBv2i32_indexed_OP1
@ MULADDv4i16_indexed_OP2
@ MULSUBv8i16_indexed_OP2
@ MULSUBv4i16_indexed_OP2
@ MULSUBv4i32_indexed_OP2
@ MULADDv2i32_indexed_OP1
@ MULADDv4i32_indexed_OP1
@ MULADDv2i32_indexed_OP2
@ MULSUBv4i16_indexed_OP1
@ MULADDv4i32_indexed_OP2
@ MULSUBv8i16_indexed_OP1
@ MULSUBv2i32_indexed_OP2
@ MULADDv8i16_indexed_OP1
@ MULSUBv4i32_indexed_OP1
@ MULADDv8i16_indexed_OP2
@ MULADDv4i16_indexed_OP1
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
CombinerObjective
The combiner's goal may differ based on which pattern it is attempting to optimize.
std::optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)
CodeGenOptLevel
Code generation optimization level.
auto instructionsWithoutDebug(IterT It, IterT End, bool SkipPseudoOp=true)
Construct a range iterator which begins at It and moves forwards until End is reached,...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getUndefRegState(bool B)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
DWARFExpression::Operation Op
static bool isUncondBranchOpcode(int Opc)
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
static const MachineMemOperand::Flags MOSuppressPair
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
static const MachineMemOperand::Flags MOStridedAccess
@ Default
The result values are uniform if and only if all operands are uniform.
void fullyRecomputeLiveIns(ArrayRef< MachineBasicBlock * > MBBs)
Convenience function for recomputing live-in's for a set of MBBs until the computation converges.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Description of the encoding of one expression Op.
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
static const MBBSectionID ColdSectionID
MachineJumpTableEntry - One jump table in the jump table info.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Used to describe a register and immediate addition.
An individual sequence of instructions to be replaced with a call to an outlined function.
MachineFunction * getMF() const
The information necessary to create an outlined function for some class of candidate.
unsigned FrameConstructionID
Target-defined identifier for constructing a frame for this function.