LLVM  16.0.0git
GCNRegPressure.h
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1 //===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the GCNRegPressure class, which tracks registry pressure
11 /// by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs. It
12 /// also implements a compare function, which compares different register
13 /// pressures, and declares one with max occupancy as winner.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
18 #define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
19 
20 #include "GCNSubtarget.h"
22 #include <algorithm>
23 
24 namespace llvm {
25 
26 class MachineRegisterInfo;
27 class raw_ostream;
28 class SlotIndex;
29 
31  enum RegKind {
39  };
40 
42  clear();
43  }
44 
45  bool empty() const { return getSGPRNum() == 0 && getVGPRNum(false) == 0; }
46 
47  void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
48 
49  unsigned getSGPRNum() const { return Value[SGPR32]; }
50  unsigned getVGPRNum(bool UnifiedVGPRFile) const {
51  if (UnifiedVGPRFile) {
52  return Value[AGPR32] ? alignTo(Value[VGPR32], 4) + Value[AGPR32]
53  : Value[VGPR32] + Value[AGPR32];
54  }
55  return std::max(Value[VGPR32], Value[AGPR32]);
56  }
57  unsigned getAGPRNum() const { return Value[AGPR32]; }
58 
59  unsigned getVGPRTuplesWeight() const { return std::max(Value[VGPR_TUPLE],
60  Value[AGPR_TUPLE]); }
61  unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
62 
63  unsigned getOccupancy(const GCNSubtarget &ST) const {
64  return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
65  ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
66  }
67 
68  void inc(unsigned Reg,
69  LaneBitmask PrevMask,
70  LaneBitmask NewMask,
71  const MachineRegisterInfo &MRI);
72 
73  bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure& O) const {
74  return getOccupancy(ST) > O.getOccupancy(ST);
75  }
76 
77  bool less(const GCNSubtarget &ST, const GCNRegPressure& O,
78  unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
79 
80  bool operator==(const GCNRegPressure &O) const {
81  return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
82  }
83 
84  bool operator!=(const GCNRegPressure &O) const {
85  return !(*this == O);
86  }
87 
88  void dump() const;
89 
90 private:
91  unsigned Value[TOTAL_KINDS];
92 
93  static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
94 
95  friend GCNRegPressure max(const GCNRegPressure &P1,
96  const GCNRegPressure &P2);
97 
98  friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST);
99 };
100 
101 inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
102  GCNRegPressure Res;
103  for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
104  Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
105  return Res;
106 }
107 
109 public:
111 
112 protected:
116  const MachineInstr *LastTrackedMI = nullptr;
117  mutable const MachineRegisterInfo *MRI = nullptr;
118 
119  GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
120 
121  void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy,
122  bool After);
123 
124 public:
125  // live regs for the current state
126  const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
127  const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
128 
130 
131  // returns MaxPressure, resetting it
133  auto Res = MaxPressure;
134  MaxPressure.clear();
135  return Res;
136  }
137 
138  decltype(LiveRegs) moveLiveRegs() {
139  return std::move(LiveRegs);
140  }
141 };
142 
144 public:
146 
147  // reset tracker to the point just below MI
148  // filling live regs upon this point using LIS
149  void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
150 
151  // move to the state just above the MI
152  void recede(const MachineInstr &MI);
153 
154  // checks whether the tracker's state after receding MI corresponds
155  // to reported by LIS
156  bool isValid() const;
157 };
158 
160  // Last position of reset or advanceBeforeNext
162 
164 
165 public:
167 
168  MachineBasicBlock::const_iterator getNext() const { return NextMI; }
169 
170  // Reset tracker to the point before the MI
171  // filling live regs upon this point using LIS.
172  // Returns false if block is empty except debug values.
173  bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
174 
175  // Move to the state right before the next MI or after the end of MBB.
176  // Returns false if reached end of the block.
177  bool advanceBeforeNext();
178 
179  // Move to the state at the MI, advanceBeforeNext has to be called first.
180  void advanceToNext();
181 
182  // Move to the state at the next MI. Returns false if reached end of block.
183  bool advance();
184 
185  // Advance instructions until before End.
187 
188  // Reset to Begin and advance to End.
191  const LiveRegSet *LiveRegsCopy = nullptr);
192 };
193 
194 LaneBitmask getLiveLaneMask(unsigned Reg,
195  SlotIndex SI,
196  const LiveIntervals &LIS,
197  const MachineRegisterInfo &MRI);
198 
200  const LiveIntervals &LIS,
201  const MachineRegisterInfo &MRI);
202 
203 /// creates a map MachineInstr -> LiveRegSet
204 /// R - range of iterators on instructions
205 /// After - upon entry or exit of every instruction
206 /// Note: there is no entry in the map for instructions with empty live reg set
207 /// Complexity = O(NumVirtRegs * averageLiveRangeSegmentsPerReg * lg(R))
208 template <typename Range>
209 DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
210 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
211  std::vector<SlotIndex> Indexes;
212  Indexes.reserve(std::distance(R.begin(), R.end()));
213  auto &SII = *LIS.getSlotIndexes();
214  for (MachineInstr *I : R) {
215  auto SI = SII.getInstructionIndex(*I);
216  Indexes.push_back(After ? SI.getDeadSlot() : SI.getBaseIndex());
217  }
218  llvm::sort(Indexes);
219 
220  auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
222  SmallVector<SlotIndex, 32> LiveIdxs, SRLiveIdxs;
223  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
224  auto Reg = Register::index2VirtReg(I);
225  if (!LIS.hasInterval(Reg))
226  continue;
227  auto &LI = LIS.getInterval(Reg);
228  LiveIdxs.clear();
229  if (!LI.findIndexesLiveAt(Indexes, std::back_inserter(LiveIdxs)))
230  continue;
231  if (!LI.hasSubRanges()) {
232  for (auto SI : LiveIdxs)
233  LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] =
235  } else
236  for (const auto &S : LI.subranges()) {
237  // constrain search for subranges by indexes live at main range
238  SRLiveIdxs.clear();
239  S.findIndexesLiveAt(LiveIdxs, std::back_inserter(SRLiveIdxs));
240  for (auto SI : SRLiveIdxs)
241  LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] |= S.LaneMask;
242  }
243  }
244  return LiveRegMap;
245 }
246 
248  const LiveIntervals &LIS) {
249  return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
250  MI.getParent()->getParent()->getRegInfo());
251 }
252 
254  const LiveIntervals &LIS) {
255  return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
256  MI.getParent()->getParent()->getRegInfo());
257 }
258 
259 template <typename Range>
261  Range &&LiveRegs) {
262  GCNRegPressure Res;
263  for (const auto &RM : LiveRegs)
264  Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
265  return Res;
266 }
267 
268 bool isEqual(const GCNRPTracker::LiveRegSet &S1,
269  const GCNRPTracker::LiveRegSet &S2);
270 
271 Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr);
272 
273 Printable print(const GCNRPTracker::LiveRegSet &LiveRegs,
274  const MachineRegisterInfo &MRI);
275 
276 Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
277  const GCNRPTracker::LiveRegSet &TrackedL,
278  const TargetRegisterInfo *TRI);
279 
280 } // end namespace llvm
281 
282 #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::GCNRegPressure::getSGPRTuplesWeight
unsigned getSGPRTuplesWeight() const
Definition: GCNRegPressure.h:61
llvm::GCNUpwardRPTracker::reset
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
Definition: GCNRegPressure.cpp:265
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::GCNRegPressure
Definition: GCNRegPressure.h:30
llvm::GCNRPTracker::LiveRegs
LiveRegSet LiveRegs
Definition: GCNRegPressure.h:114
llvm::getLiveRegsBefore
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
Definition: GCNRegPressure.h:253
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:209
llvm::GCNRPTracker::getLiveRegs
const decltype(LiveRegs) & getLiveRegs() const
Definition: GCNRegPressure.h:126
llvm::GCNRegPressure::max
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
Definition: GCNRegPressure.h:101
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::getRegPressure
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Definition: GCNRegPressure.h:260
llvm::getLiveRegMap
DenseMap< MachineInstr *, GCNRPTracker::LiveRegSet > getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS)
creates a map MachineInstr -> LiveRegSet R - range of iterators on instructions After - upon entry or...
Definition: GCNRegPressure.h:210
llvm::getLiveLaneMask
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:215
llvm::GCNRegPressure::operator!=
bool operator!=(const GCNRegPressure &O) const
Definition: GCNRegPressure.h:84
llvm::GCNRegPressure::RegKind
RegKind
Definition: GCNRegPressure.h:31
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::GCNRPTracker::GCNRPTracker
GCNRPTracker(const LiveIntervals &LIS_)
Definition: GCNRegPressure.h:119
llvm::max
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
Definition: GCNRegPressure.h:101
llvm::GCNRPTracker::clearMaxPressure
void clearMaxPressure()
Definition: GCNRegPressure.h:129
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:770
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::GCNRegPressure::less
bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
Definition: GCNRegPressure.cpp:89
llvm::getLiveRegsAfter
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
Definition: GCNRegPressure.h:247
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::GCNRegPressure::getVGPRTuplesWeight
unsigned getVGPRTuplesWeight() const
Definition: GCNRegPressure.h:59
llvm::isEqual
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
Definition: GCNRegPressure.cpp:21
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:220
llvm::GCNDownwardRPTracker
Definition: GCNRegPressure.h:159
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
llvm::GCNUpwardRPTracker::recede
void recede(const MachineInstr &MI)
Definition: GCNRegPressure.cpp:270
llvm::GCNRegPressure::AGPR_TUPLE
@ AGPR_TUPLE
Definition: GCNRegPressure.h:37
llvm::GCNRPTracker::moveMaxPressure
decltype(MaxPressure) moveMaxPressure()
Definition: GCNRegPressure.h:132
llvm::GCNRPTracker
Definition: GCNRegPressure.h:108
llvm::GCNRegPressure::inc
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:50
llvm::GCNRPTracker::getLastTrackedMI
const MachineInstr * getLastTrackedMI() const
Definition: GCNRegPressure.h:127
GCNSubtarget.h
llvm::GCNRegPressure::getSGPRNum
unsigned getSGPRNum() const
Definition: GCNRegPressure.h:49
llvm::GCNDownwardRPTracker::advanceBeforeNext
bool advanceBeforeNext()
Definition: GCNRegPressure.cpp:326
llvm::AArch64::RP
@ RP
Definition: AArch64ISelLowering.h:486
P2
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill if only one byte chunk is bring in zeros the one element instead of elements This can be used to simplify a variety of shuffle where the elements are fixed zeros This code generates ugly probably due to costs being off or< 4 x float > * P2
Definition: README-SSE.txt:278
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::GCNRPTracker::MaxPressure
GCNRegPressure MaxPressure
Definition: GCNRegPressure.h:115
llvm::GCNRegPressure::getOccupancy
unsigned getOccupancy(const GCNSubtarget &ST) const
Definition: GCNRegPressure.h:63
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::LaneBitmask::getNone
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
llvm::GCNRegPressure::VGPR32
@ VGPR32
Definition: GCNRegPressure.h:34
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:264
llvm::GCNUpwardRPTracker
Definition: GCNRegPressure.h:143
llvm::GCNRPTracker::MRI
const MachineRegisterInfo * MRI
Definition: GCNRegPressure.h:117
llvm::GCNDownwardRPTracker::GCNDownwardRPTracker
GCNDownwardRPTracker(const LiveIntervals &LIS_)
Definition: GCNRegPressure.h:166
llvm::reportMismatch
Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedL, const TargetRegisterInfo *TRI)
Definition: GCNRegPressure.cpp:408
llvm::GCNDownwardRPTracker::advance
bool advance()
Definition: GCNRegPressure.cpp:385
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1682
llvm::SlotIndex::getBaseIndex
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:246
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
llvm::GCNUpwardRPTracker::GCNUpwardRPTracker
GCNUpwardRPTracker(const LiveIntervals &LIS_)
Definition: GCNRegPressure.h:145
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::DenseMap< unsigned, LaneBitmask >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GCNRegPressure::empty
bool empty() const
Definition: GCNRegPressure.h:45
llvm::GCNRegPressure::print
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST)
llvm::GCNRegPressure::SGPR32
@ SGPR32
Definition: GCNRegPressure.h:32
llvm::GCNRegPressure::dump
void dump() const
Definition: GCNRegPressure.cpp:472
llvm::GCNDownwardRPTracker::reset
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
Definition: GCNRegPressure.cpp:313
llvm::GCNRegPressure::AGPR32
@ AGPR32
Definition: GCNRegPressure.h:36
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:112
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::GCNRegPressure::GCNRegPressure
GCNRegPressure()
Definition: GCNRegPressure.h:41
llvm::GCNRegPressure::TOTAL_KINDS
@ TOTAL_KINDS
Definition: GCNRegPressure.h:38
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:805
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::GCNRPTracker::moveLiveRegs
decltype(LiveRegs) moveLiveRegs()
Definition: GCNRegPressure.h:138
llvm::LiveRegSet
A set of live virtual registers and physical register units.
Definition: RegisterPressure.h:259
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GCNDownwardRPTracker::getNext
MachineBasicBlock::const_iterator getNext() const
Definition: GCNRegPressure.h:168
llvm::GCNRegPressure::SGPR_TUPLE
@ SGPR_TUPLE
Definition: GCNRegPressure.h:33
llvm::GCNRPTracker::LiveRegSet
DenseMap< unsigned, LaneBitmask > LiveRegSet
Definition: GCNRegPressure.h:110
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:495
llvm::GCNRegPressure::getVGPRNum
unsigned getVGPRNum(bool UnifiedVGPRFile) const
Definition: GCNRegPressure.h:50
llvm::GCNUpwardRPTracker::isValid
bool isValid() const
Definition: GCNRegPressure.cpp:433
llvm::GCNRegPressure::higherOccupancy
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure &O) const
Definition: GCNRegPressure.h:73
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:614
llvm::GCNDownwardRPTracker::advanceToNext
void advanceToNext()
Definition: GCNRegPressure.cpp:365
llvm::GCNRPTracker::LIS
const LiveIntervals & LIS
Definition: GCNRegPressure.h:113
llvm::GCNRegPressure::VGPR_TUPLE
@ VGPR_TUPLE
Definition: GCNRegPressure.h:35
llvm::GCNRegPressure::operator==
bool operator==(const GCNRegPressure &O) const
Definition: GCNRegPressure.h:80
llvm::GCNRPTracker::reset
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
Definition: GCNRegPressure.cpp:249
llvm::GCNRPTracker::CurPressure
GCNRegPressure CurPressure
Definition: GCNRegPressure.h:115
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
llvm::GCNRegPressure::clear
void clear()
Definition: GCNRegPressure.h:47
llvm::getLiveRegs
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:234
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:123
llvm::GCNRPTracker::LastTrackedMI
const MachineInstr * LastTrackedMI
Definition: GCNRegPressure.h:116
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::GCNRegPressure::getAGPRNum
unsigned getAGPRNum() const
Definition: GCNRegPressure.h:57