LLVM 19.0.0git
GCNRegPressure.h
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1//===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the GCNRegPressure class, which tracks registry pressure
11/// by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs. It
12/// also implements a compare function, which compares different register
13/// pressures, and declares one with max occupancy as winner.
14///
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
18#define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
19
20#include "GCNSubtarget.h"
22#include <algorithm>
23
24namespace llvm {
25
26class MachineRegisterInfo;
27class raw_ostream;
28class SlotIndex;
29
31 enum RegKind {
39 };
40
42 clear();
43 }
44
45 bool empty() const { return getSGPRNum() == 0 && getVGPRNum(false) == 0; }
46
47 void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
48
49 unsigned getSGPRNum() const { return Value[SGPR32]; }
50 unsigned getVGPRNum(bool UnifiedVGPRFile) const {
51 if (UnifiedVGPRFile) {
52 return Value[AGPR32] ? alignTo(Value[VGPR32], 4) + Value[AGPR32]
54 }
55 return std::max(Value[VGPR32], Value[AGPR32]);
56 }
57 unsigned getAGPRNum() const { return Value[AGPR32]; }
58
59 unsigned getVGPRTuplesWeight() const { return std::max(Value[VGPR_TUPLE],
60 Value[AGPR_TUPLE]); }
61 unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
62
63 unsigned getOccupancy(const GCNSubtarget &ST) const {
64 return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
65 ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
66 }
67
68 void inc(unsigned Reg,
69 LaneBitmask PrevMask,
70 LaneBitmask NewMask,
72
73 bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure& O) const {
74 return getOccupancy(ST) > O.getOccupancy(ST);
75 }
76
77 /// Compares \p this GCNRegpressure to \p O, returning true if \p this is
78 /// less. Since GCNRegpressure contains different types of pressures, and due
79 /// to target-specific pecularities (e.g. we care about occupancy rather than
80 /// raw register usage), we determine if \p this GCNRegPressure is less than
81 /// \p O based on the following tiered comparisons (in order order of
82 /// precedence):
83 /// 1. Better occupancy
84 /// 2. Less spilling (first preference to VGPR spills, then to SGPR spills)
85 /// 3. Less tuple register pressure (first preference to VGPR tuples if we
86 /// determine that SGPR pressure is not important)
87 /// 4. Less raw register pressure (first preference to VGPR tuples if we
88 /// determine that SGPR pressure is not important)
89 bool less(const MachineFunction &MF, const GCNRegPressure &O,
90 unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
91
92 bool operator==(const GCNRegPressure &O) const {
93 return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
94 }
95
96 bool operator!=(const GCNRegPressure &O) const {
97 return !(*this == O);
98 }
99
101 for (unsigned I = 0; I < TOTAL_KINDS; ++I)
102 Value[I] += RHS.Value[I];
103 return *this;
104 }
105
107 for (unsigned I = 0; I < TOTAL_KINDS; ++I)
108 Value[I] -= RHS.Value[I];
109 return *this;
110 }
111
112 void dump() const;
113
114private:
115 unsigned Value[TOTAL_KINDS];
116
117 static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
118
119 friend GCNRegPressure max(const GCNRegPressure &P1,
120 const GCNRegPressure &P2);
121
122 friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST);
123};
124
125inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
126 GCNRegPressure Res;
127 for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
128 Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
129 return Res;
130}
131
133 const GCNRegPressure &P2) {
134 GCNRegPressure Sum = P1;
135 Sum += P2;
136 return Sum;
137}
138
140 const GCNRegPressure &P2) {
141 GCNRegPressure Diff = P1;
142 Diff -= P2;
143 return Diff;
144}
145
147public:
149
150protected:
154 const MachineInstr *LastTrackedMI = nullptr;
155 mutable const MachineRegisterInfo *MRI = nullptr;
156
157 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
158
159 void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy,
160 bool After);
161
162public:
163 // live regs for the current state
164 const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
165 const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
166
168
170
171 decltype(LiveRegs) moveLiveRegs() {
172 return std::move(LiveRegs);
173 }
174};
175
176GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
177 const MachineRegisterInfo &MRI);
178
180public:
182
183 // reset tracker and set live register set to the specified value.
184 void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_);
185
186 // reset tracker at the specified slot index.
189 }
190
191 // reset tracker to the end of the MBB.
193 reset(MBB.getParent()->getRegInfo(),
195 }
196
197 // reset tracker to the point just after MI (in program order).
198 void reset(const MachineInstr &MI) {
199 reset(MI.getMF()->getRegInfo(), LIS.getInstructionIndex(MI).getDeadSlot());
200 }
201
202 // move to the state just before the MI (in program order).
203 void recede(const MachineInstr &MI);
204
205 // checks whether the tracker's state after receding MI corresponds
206 // to reported by LIS.
207 bool isValid() const;
208
209 const GCNRegPressure &getMaxPressure() const { return MaxPressure; }
210
212
216 return RP;
217 }
218};
219
221 // Last position of reset or advanceBeforeNext
223
225
226public:
228
230
231 // Return MaxPressure and clear it.
233 auto Res = MaxPressure;
235 return Res;
236 }
237
238 // Reset tracker to the point before the MI
239 // filling live regs upon this point using LIS.
240 // Returns false if block is empty except debug values.
241 bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
242
243 // Move to the state right before the next MI or after the end of MBB.
244 // Returns false if reached end of the block.
245 bool advanceBeforeNext();
246
247 // Move to the state at the MI, advanceBeforeNext has to be called first.
248 void advanceToNext();
249
250 // Move to the state at the next MI. Returns false if reached end of block.
251 bool advance();
252
253 // Advance instructions until before End.
255
256 // Reset to Begin and advance to End.
259 const LiveRegSet *LiveRegsCopy = nullptr);
260};
261
262LaneBitmask getLiveLaneMask(unsigned Reg,
263 SlotIndex SI,
264 const LiveIntervals &LIS,
265 const MachineRegisterInfo &MRI);
266
267LaneBitmask getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
268 const MachineRegisterInfo &MRI);
269
270GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
271 const MachineRegisterInfo &MRI);
272
273/// creates a map MachineInstr -> LiveRegSet
274/// R - range of iterators on instructions
275/// After - upon entry or exit of every instruction
276/// Note: there is no entry in the map for instructions with empty live reg set
277/// Complexity = O(NumVirtRegs * averageLiveRangeSegmentsPerReg * lg(R))
278template <typename Range>
279DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
280getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
281 std::vector<SlotIndex> Indexes;
282 Indexes.reserve(std::distance(R.begin(), R.end()));
283 auto &SII = *LIS.getSlotIndexes();
284 for (MachineInstr *I : R) {
285 auto SI = SII.getInstructionIndex(*I);
286 Indexes.push_back(After ? SI.getDeadSlot() : SI.getBaseIndex());
287 }
288 llvm::sort(Indexes);
289
290 auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
292 SmallVector<SlotIndex, 32> LiveIdxs, SRLiveIdxs;
293 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
295 if (!LIS.hasInterval(Reg))
296 continue;
297 auto &LI = LIS.getInterval(Reg);
298 LiveIdxs.clear();
299 if (!LI.findIndexesLiveAt(Indexes, std::back_inserter(LiveIdxs)))
300 continue;
301 if (!LI.hasSubRanges()) {
302 for (auto SI : LiveIdxs)
303 LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] =
304 MRI.getMaxLaneMaskForVReg(Reg);
305 } else
306 for (const auto &S : LI.subranges()) {
307 // constrain search for subranges by indexes live at main range
308 SRLiveIdxs.clear();
309 S.findIndexesLiveAt(LiveIdxs, std::back_inserter(SRLiveIdxs));
310 for (auto SI : SRLiveIdxs)
311 LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] |= S.LaneMask;
312 }
313 }
314 return LiveRegMap;
315}
316
318 const LiveIntervals &LIS) {
320 MI.getParent()->getParent()->getRegInfo());
321}
322
324 const LiveIntervals &LIS) {
326 MI.getParent()->getParent()->getRegInfo());
327}
328
329template <typename Range>
331 Range &&LiveRegs) {
332 GCNRegPressure Res;
333 for (const auto &RM : LiveRegs)
334 Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
335 return Res;
336}
337
339 const GCNRPTracker::LiveRegSet &S2);
340
341Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr);
342
343Printable print(const GCNRPTracker::LiveRegSet &LiveRegs,
344 const MachineRegisterInfo &MRI);
345
346Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
347 const GCNRPTracker::LiveRegSet &TrackedL,
348 const TargetRegisterInfo *TRI, StringRef Pfx = " ");
349
351 static char ID;
352
353public:
355
356 bool runOnMachineFunction(MachineFunction &MF) override;
357
358 void getAnalysisUsage(AnalysisUsage &AU) const override {
360 AU.setPreservesAll();
362 }
363};
364
365} // end namespace llvm
366
367#endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static const LLT S1
static const Function * getParent(const Value *V)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool End
Definition: ELF_riscv.cpp:480
AMD GCN specific subclass of TargetSubtarget.
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Value * RHS
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
GCNRegPressure moveMaxPressure()
MachineBasicBlock::const_iterator getNext() const
GCNDownwardRPTracker(const LiveIntervals &LIS_)
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
GCNRegPressure getPressure() const
const decltype(LiveRegs) & getLiveRegs() const
const MachineInstr * LastTrackedMI
decltype(LiveRegs) moveLiveRegs()
GCNRegPressure CurPressure
DenseMap< unsigned, LaneBitmask > LiveRegSet
GCNRPTracker(const LiveIntervals &LIS_)
GCNRegPressure MaxPressure
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
const MachineInstr * getLastTrackedMI() const
const MachineRegisterInfo * MRI
const LiveIntervals & LIS
GCNUpwardRPTracker(const LiveIntervals &LIS_)
GCNRegPressure getMaxPressureAndReset()
void reset(const MachineRegisterInfo &MRI, SlotIndex SI)
void recede(const MachineInstr &MI)
void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_)
const GCNRegPressure & getMaxPressure() const
void reset(const MachineBasicBlock &MBB)
void reset(const MachineInstr &MI)
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
bool hasInterval(Register Reg) const
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveInterval & getInterval(Register Reg)
A set of live virtual registers and physical register units.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:245
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:227
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:462
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1656
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
APInt operator-(APInt)
Definition: APInt.h:2111
DenseMap< MachineInstr *, GCNRPTracker::LiveRegSet > getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS)
creates a map MachineInstr -> LiveRegSet R - range of iterators on instructions After - upon entry or...
APInt operator+(APInt a, const APInt &b)
Definition: APInt.h:2116
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedL, const TargetRegisterInfo *TRI, StringRef Pfx=" ")
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool operator!=(const GCNRegPressure &O) const
GCNRegPressure & operator+=(const GCNRegPressure &RHS)
unsigned getVGPRTuplesWeight() const
unsigned getOccupancy(const GCNSubtarget &ST) const
GCNRegPressure & operator-=(const GCNRegPressure &RHS)
unsigned getVGPRNum(bool UnifiedVGPRFile) const
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure &O) const
unsigned getAGPRNum() const
unsigned getSGPRNum() const
unsigned getSGPRTuplesWeight() const
bool operator==(const GCNRegPressure &O) const
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST)
bool less(const MachineFunction &MF, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
Compares this GCNRegpressure to O, returning true if this is less.
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81