LLVM 20.0.0git
GCNRegPressure.h
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1//===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the GCNRegPressure class, which tracks registry pressure
11/// by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs. It
12/// also implements a compare function, which compares different register
13/// pressures, and declares one with max occupancy as winner.
14///
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
18#define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
19
20#include "GCNSubtarget.h"
22#include <algorithm>
23
24namespace llvm {
25
26class MachineRegisterInfo;
27class raw_ostream;
28class SlotIndex;
29
31 enum RegKind {
39 };
40
42 clear();
43 }
44
45 bool empty() const { return getSGPRNum() == 0 && getVGPRNum(false) == 0; }
46
47 void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
48
49 /// \returns the SGPR32 pressure
50 unsigned getSGPRNum() const { return Value[SGPR32]; }
51 /// \returns the aggregated ArchVGPR32, AccVGPR32 pressure dependent upon \p
52 /// UnifiedVGPRFile
53 unsigned getVGPRNum(bool UnifiedVGPRFile) const {
54 if (UnifiedVGPRFile) {
55 return Value[AGPR32] ? alignTo(Value[VGPR32], 4) + Value[AGPR32]
57 }
58 return std::max(Value[VGPR32], Value[AGPR32]);
59 }
60 /// \returns the ArchVGPR32 pressure
61 unsigned getArchVGPRNum() const { return Value[VGPR32]; }
62 /// \returns the AccVGPR32 pressure
63 unsigned getAGPRNum() const { return Value[AGPR32]; }
64
65 unsigned getVGPRTuplesWeight() const { return std::max(Value[VGPR_TUPLE],
66 Value[AGPR_TUPLE]); }
67 unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
68
69 unsigned getOccupancy(const GCNSubtarget &ST) const {
70 return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
71 ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
72 }
73
74 void inc(unsigned Reg,
75 LaneBitmask PrevMask,
76 LaneBitmask NewMask,
78
79 bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure& O) const {
80 return getOccupancy(ST) > O.getOccupancy(ST);
81 }
82
83 /// Compares \p this GCNRegpressure to \p O, returning true if \p this is
84 /// less. Since GCNRegpressure contains different types of pressures, and due
85 /// to target-specific pecularities (e.g. we care about occupancy rather than
86 /// raw register usage), we determine if \p this GCNRegPressure is less than
87 /// \p O based on the following tiered comparisons (in order order of
88 /// precedence):
89 /// 1. Better occupancy
90 /// 2. Less spilling (first preference to VGPR spills, then to SGPR spills)
91 /// 3. Less tuple register pressure (first preference to VGPR tuples if we
92 /// determine that SGPR pressure is not important)
93 /// 4. Less raw register pressure (first preference to VGPR tuples if we
94 /// determine that SGPR pressure is not important)
95 bool less(const MachineFunction &MF, const GCNRegPressure &O,
96 unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
97
98 bool operator==(const GCNRegPressure &O) const {
99 return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
100 }
101
102 bool operator!=(const GCNRegPressure &O) const {
103 return !(*this == O);
104 }
105
107 for (unsigned I = 0; I < TOTAL_KINDS; ++I)
108 Value[I] += RHS.Value[I];
109 return *this;
110 }
111
113 for (unsigned I = 0; I < TOTAL_KINDS; ++I)
114 Value[I] -= RHS.Value[I];
115 return *this;
116 }
117
118 void dump() const;
119
120private:
121 unsigned Value[TOTAL_KINDS];
122
123 static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
124
125 friend GCNRegPressure max(const GCNRegPressure &P1,
126 const GCNRegPressure &P2);
127
128 friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST);
129};
130
131inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
132 GCNRegPressure Res;
133 for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
134 Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
135 return Res;
136}
137
139 const GCNRegPressure &P2) {
140 GCNRegPressure Sum = P1;
141 Sum += P2;
142 return Sum;
143}
144
146 const GCNRegPressure &P2) {
147 GCNRegPressure Diff = P1;
148 Diff -= P2;
149 return Diff;
150}
151
153public:
155
156protected:
160 const MachineInstr *LastTrackedMI = nullptr;
161 mutable const MachineRegisterInfo *MRI = nullptr;
162
163 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
164
165 void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy,
166 bool After);
167
168public:
169 // live regs for the current state
170 const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
171 const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
172
174
176
177 decltype(LiveRegs) moveLiveRegs() {
178 return std::move(LiveRegs);
179 }
180};
181
182GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
183 const MachineRegisterInfo &MRI);
184
186public:
188
189 // reset tracker and set live register set to the specified value.
190 void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_);
191
192 // reset tracker at the specified slot index.
195 }
196
197 // reset tracker to the end of the MBB.
199 reset(MBB.getParent()->getRegInfo(),
201 }
202
203 // reset tracker to the point just after MI (in program order).
204 void reset(const MachineInstr &MI) {
205 reset(MI.getMF()->getRegInfo(), LIS.getInstructionIndex(MI).getDeadSlot());
206 }
207
208 // move to the state just before the MI (in program order).
209 void recede(const MachineInstr &MI);
210
211 // checks whether the tracker's state after receding MI corresponds
212 // to reported by LIS.
213 bool isValid() const;
214
215 const GCNRegPressure &getMaxPressure() const { return MaxPressure; }
216
218
222 return RP;
223 }
224};
225
227 // Last position of reset or advanceBeforeNext
229
231
232public:
234
236
237 // Return MaxPressure and clear it.
239 auto Res = MaxPressure;
241 return Res;
242 }
243
244 // Reset tracker to the point before the MI
245 // filling live regs upon this point using LIS.
246 // Returns false if block is empty except debug values.
247 bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
248
249 // Move to the state right before the next MI or after the end of MBB.
250 // Returns false if reached end of the block.
251 bool advanceBeforeNext();
252
253 // Move to the state at the MI, advanceBeforeNext has to be called first.
254 void advanceToNext();
255
256 // Move to the state at the next MI. Returns false if reached end of block.
257 bool advance();
258
259 // Advance instructions until before End.
261
262 // Reset to Begin and advance to End.
265 const LiveRegSet *LiveRegsCopy = nullptr);
266};
267
268LaneBitmask getLiveLaneMask(unsigned Reg,
269 SlotIndex SI,
270 const LiveIntervals &LIS,
271 const MachineRegisterInfo &MRI);
272
273LaneBitmask getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
274 const MachineRegisterInfo &MRI);
275
276GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
277 const MachineRegisterInfo &MRI);
278
279/// creates a map MachineInstr -> LiveRegSet
280/// R - range of iterators on instructions
281/// After - upon entry or exit of every instruction
282/// Note: there is no entry in the map for instructions with empty live reg set
283/// Complexity = O(NumVirtRegs * averageLiveRangeSegmentsPerReg * lg(R))
284template <typename Range>
285DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
287 std::vector<SlotIndex> Indexes;
288 Indexes.reserve(std::distance(R.begin(), R.end()));
289 auto &SII = *LIS.getSlotIndexes();
290 for (MachineInstr *I : R) {
291 auto SI = SII.getInstructionIndex(*I);
292 Indexes.push_back(After ? SI.getDeadSlot() : SI.getBaseIndex());
293 }
294 llvm::sort(Indexes);
295
296 auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
298 SmallVector<SlotIndex, 32> LiveIdxs, SRLiveIdxs;
299 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
301 if (!LIS.hasInterval(Reg))
302 continue;
303 auto &LI = LIS.getInterval(Reg);
304 LiveIdxs.clear();
305 if (!LI.findIndexesLiveAt(Indexes, std::back_inserter(LiveIdxs)))
306 continue;
307 if (!LI.hasSubRanges()) {
308 for (auto SI : LiveIdxs)
309 LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] =
310 MRI.getMaxLaneMaskForVReg(Reg);
311 } else
312 for (const auto &S : LI.subranges()) {
313 // constrain search for subranges by indexes live at main range
314 SRLiveIdxs.clear();
315 S.findIndexesLiveAt(LiveIdxs, std::back_inserter(SRLiveIdxs));
316 for (auto SI : SRLiveIdxs)
317 LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] |= S.LaneMask;
318 }
319 }
320 return LiveRegMap;
321}
322
324 const LiveIntervals &LIS) {
326 MI.getParent()->getParent()->getRegInfo());
327}
328
330 const LiveIntervals &LIS) {
332 MI.getParent()->getParent()->getRegInfo());
333}
334
335template <typename Range>
337 Range &&LiveRegs) {
338 GCNRegPressure Res;
339 for (const auto &RM : LiveRegs)
340 Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
341 return Res;
342}
343
345 const GCNRPTracker::LiveRegSet &S2);
346
347Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr);
348
349Printable print(const GCNRPTracker::LiveRegSet &LiveRegs,
350 const MachineRegisterInfo &MRI);
351
352Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
353 const GCNRPTracker::LiveRegSet &TrackedL,
354 const TargetRegisterInfo *TRI, StringRef Pfx = " ");
355
357 static char ID;
358
359public:
361
362 bool runOnMachineFunction(MachineFunction &MF) override;
363
364 void getAnalysisUsage(AnalysisUsage &AU) const override {
366 AU.setPreservesAll();
368 }
369};
370
371} // end namespace llvm
372
373#endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
unsigned const MachineRegisterInfo * MRI
static const LLT S1
MachineBasicBlock & MBB
static const Function * getParent(const Value *V)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool End
Definition: ELF_riscv.cpp:480
AMD GCN specific subclass of TargetSubtarget.
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
Value * RHS
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
GCNRegPressure moveMaxPressure()
MachineBasicBlock::const_iterator getNext() const
GCNDownwardRPTracker(const LiveIntervals &LIS_)
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
GCNRegPressure getPressure() const
const decltype(LiveRegs) & getLiveRegs() const
const MachineInstr * LastTrackedMI
decltype(LiveRegs) moveLiveRegs()
GCNRegPressure CurPressure
DenseMap< unsigned, LaneBitmask > LiveRegSet
GCNRPTracker(const LiveIntervals &LIS_)
GCNRegPressure MaxPressure
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
const MachineInstr * getLastTrackedMI() const
const MachineRegisterInfo * MRI
const LiveIntervals & LIS
GCNUpwardRPTracker(const LiveIntervals &LIS_)
GCNRegPressure getMaxPressureAndReset()
void reset(const MachineRegisterInfo &MRI, SlotIndex SI)
void recede(const MachineInstr &MI)
void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_)
const GCNRegPressure & getMaxPressure() const
void reset(const MachineBasicBlock &MBB)
void reset(const MachineInstr &MI)
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:656
bool hasInterval(Register Reg) const
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveInterval & getInterval(Register Reg)
A set of live virtual registers and physical register units.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:65
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:242
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:224
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:470
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1647
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
APInt operator-(APInt)
Definition: APInt.h:2137
DenseMap< MachineInstr *, GCNRPTracker::LiveRegSet > getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS)
creates a map MachineInstr -> LiveRegSet R - range of iterators on instructions After - upon entry or...
APInt operator+(APInt a, const APInt &b)
Definition: APInt.h:2142
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedL, const TargetRegisterInfo *TRI, StringRef Pfx=" ")
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool operator!=(const GCNRegPressure &O) const
GCNRegPressure & operator+=(const GCNRegPressure &RHS)
unsigned getVGPRTuplesWeight() const
unsigned getOccupancy(const GCNSubtarget &ST) const
GCNRegPressure & operator-=(const GCNRegPressure &RHS)
unsigned getVGPRNum(bool UnifiedVGPRFile) const
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure &O) const
unsigned getArchVGPRNum() const
unsigned getAGPRNum() const
unsigned getSGPRNum() const
unsigned getSGPRTuplesWeight() const
bool operator==(const GCNRegPressure &O) const
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST)
bool less(const MachineFunction &MF, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
Compares this GCNRegpressure to O, returning true if this is less.
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81