LLVM  16.0.0git
AArch64InstPrinter.cpp
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1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an AArch64 MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64InstPrinter.h"
15 #include "Utils/AArch64BaseInfo.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/Format.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <string>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "asm-printer"
36 
37 #define GET_INSTRUCTION_NAME
38 #define PRINT_ALIAS_INSTR
39 #include "AArch64GenAsmWriter.inc"
40 #define GET_INSTRUCTION_NAME
41 #define PRINT_ALIAS_INSTR
42 #include "AArch64GenAsmWriter1.inc"
43 
45  const MCInstrInfo &MII,
46  const MCRegisterInfo &MRI)
47  : MCInstPrinter(MAI, MII, MRI) {}
48 
50  const MCInstrInfo &MII,
51  const MCRegisterInfo &MRI)
52  : AArch64InstPrinter(MAI, MII, MRI) {}
53 
55  if (Opt == "no-aliases") {
56  PrintAliases = false;
57  return true;
58  }
59  return false;
60 }
61 
62 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
63  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
64 }
65 
67  unsigned AltIdx) const {
68  OS << markup("<reg:") << getRegisterName(RegNo, AltIdx) << markup(">");
69 }
70 
72  StringRef Annot, const MCSubtargetInfo &STI,
73  raw_ostream &O) {
74  // Check for special encodings and print the canonical alias instead.
75 
76  unsigned Opcode = MI->getOpcode();
77 
78  if (Opcode == AArch64::SYSxt)
79  if (printSysAlias(MI, STI, O)) {
80  printAnnotation(O, Annot);
81  return;
82  }
83 
84  // SBFM/UBFM should print to a nicer aliased form if possible.
85  if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
86  Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
87  const MCOperand &Op0 = MI->getOperand(0);
88  const MCOperand &Op1 = MI->getOperand(1);
89  const MCOperand &Op2 = MI->getOperand(2);
90  const MCOperand &Op3 = MI->getOperand(3);
91 
92  bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
93  bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
94  if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
95  const char *AsmMnemonic = nullptr;
96 
97  switch (Op3.getImm()) {
98  default:
99  break;
100  case 7:
101  if (IsSigned)
102  AsmMnemonic = "sxtb";
103  else if (!Is64Bit)
104  AsmMnemonic = "uxtb";
105  break;
106  case 15:
107  if (IsSigned)
108  AsmMnemonic = "sxth";
109  else if (!Is64Bit)
110  AsmMnemonic = "uxth";
111  break;
112  case 31:
113  // *xtw is only valid for signed 64-bit operations.
114  if (Is64Bit && IsSigned)
115  AsmMnemonic = "sxtw";
116  break;
117  }
118 
119  if (AsmMnemonic) {
120  O << '\t' << AsmMnemonic << '\t';
121  printRegName(O, Op0.getReg());
122  O << ", ";
124  printAnnotation(O, Annot);
125  return;
126  }
127  }
128 
129  // All immediate shifts are aliases, implemented using the Bitfield
130  // instruction. In all cases the immediate shift amount shift must be in
131  // the range 0 to (reg.size -1).
132  if (Op2.isImm() && Op3.isImm()) {
133  const char *AsmMnemonic = nullptr;
134  int shift = 0;
135  int64_t immr = Op2.getImm();
136  int64_t imms = Op3.getImm();
137  if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
138  AsmMnemonic = "lsl";
139  shift = 31 - imms;
140  } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
141  ((imms + 1 == immr))) {
142  AsmMnemonic = "lsl";
143  shift = 63 - imms;
144  } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
145  AsmMnemonic = "lsr";
146  shift = immr;
147  } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
148  AsmMnemonic = "lsr";
149  shift = immr;
150  } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
151  AsmMnemonic = "asr";
152  shift = immr;
153  } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
154  AsmMnemonic = "asr";
155  shift = immr;
156  }
157  if (AsmMnemonic) {
158  O << '\t' << AsmMnemonic << '\t';
159  printRegName(O, Op0.getReg());
160  O << ", ";
161  printRegName(O, Op1.getReg());
162  O << ", " << markup("<imm:") << "#" << shift << markup(">");
163  printAnnotation(O, Annot);
164  return;
165  }
166  }
167 
168  // SBFIZ/UBFIZ aliases
169  if (Op2.getImm() > Op3.getImm()) {
170  O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
171  printRegName(O, Op0.getReg());
172  O << ", ";
173  printRegName(O, Op1.getReg());
174  O << ", " << markup("<imm:") << "#" << (Is64Bit ? 64 : 32) - Op2.getImm()
175  << markup(">") << ", " << markup("<imm:") << "#" << Op3.getImm() + 1
176  << markup(">");
177  printAnnotation(O, Annot);
178  return;
179  }
180 
181  // Otherwise SBFX/UBFX is the preferred form
182  O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
183  printRegName(O, Op0.getReg());
184  O << ", ";
185  printRegName(O, Op1.getReg());
186  O << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
187  << markup("<imm:") << "#" << Op3.getImm() - Op2.getImm() + 1
188  << markup(">");
189  printAnnotation(O, Annot);
190  return;
191  }
192 
193  if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
194  const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
195  const MCOperand &Op2 = MI->getOperand(2);
196  int ImmR = MI->getOperand(3).getImm();
197  int ImmS = MI->getOperand(4).getImm();
198 
199  if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
200  (ImmR == 0 || ImmS < ImmR) &&
201  STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
202  // BFC takes precedence over its entire range, sligtly differently to BFI.
203  int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
204  int LSB = (BitWidth - ImmR) % BitWidth;
205  int Width = ImmS + 1;
206 
207  O << "\tbfc\t";
208  printRegName(O, Op0.getReg());
209  O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
210  << markup("<imm:") << "#" << Width << markup(">");
211  printAnnotation(O, Annot);
212  return;
213  } else if (ImmS < ImmR) {
214  // BFI alias
215  int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
216  int LSB = (BitWidth - ImmR) % BitWidth;
217  int Width = ImmS + 1;
218 
219  O << "\tbfi\t";
220  printRegName(O, Op0.getReg());
221  O << ", ";
222  printRegName(O, Op2.getReg());
223  O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
224  << markup("<imm:") << "#" << Width << markup(">");
225  printAnnotation(O, Annot);
226  return;
227  }
228 
229  int LSB = ImmR;
230  int Width = ImmS - ImmR + 1;
231  // Otherwise BFXIL the preferred form
232  O << "\tbfxil\t";
233  printRegName(O, Op0.getReg());
234  O << ", ";
235  printRegName(O, Op2.getReg());
236  O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
237  << markup("<imm:") << "#" << Width << markup(">");
238  printAnnotation(O, Annot);
239  return;
240  }
241 
242  // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
243  // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
244  // printed.
245  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
246  Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
247  MI->getOperand(1).isExpr()) {
248  if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
249  O << "\tmovz\t";
250  else
251  O << "\tmovn\t";
252 
253  printRegName(O, MI->getOperand(0).getReg());
254  O << ", " << markup("<imm:") << "#";
255  MI->getOperand(1).getExpr()->print(O, &MAI);
256  O << markup(">");
257  return;
258  }
259 
260  if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
261  MI->getOperand(2).isExpr()) {
262  O << "\tmovk\t";
263  printRegName(O, MI->getOperand(0).getReg());
264  O << ", " << markup("<imm:") << "#";
265  MI->getOperand(2).getExpr()->print(O, &MAI);
266  O << markup(">");
267  return;
268  }
269 
270  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
271  // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
272  // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
273  // that can represent the move is the MOV alias, and the rest get printed
274  // normally.
275  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
276  MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
277  int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
278  int Shift = MI->getOperand(2).getImm();
279  uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
280 
282  Opcode == AArch64::MOVZXi ? 64 : 32)) {
283  O << "\tmov\t";
284  printRegName(O, MI->getOperand(0).getReg());
285  O << ", " << markup("<imm:") << "#"
286  << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
287  return;
288  }
289  }
290 
291  if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
292  MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
293  int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
294  int Shift = MI->getOperand(2).getImm();
295  uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
296  if (RegWidth == 32)
297  Value = Value & 0xffffffff;
298 
299  if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
300  O << "\tmov\t";
301  printRegName(O, MI->getOperand(0).getReg());
302  O << ", " << markup("<imm:") << "#"
303  << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
304  return;
305  }
306  }
307 
308  if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
309  (MI->getOperand(1).getReg() == AArch64::XZR ||
310  MI->getOperand(1).getReg() == AArch64::WZR) &&
311  MI->getOperand(2).isImm()) {
312  int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
314  MI->getOperand(2).getImm(), RegWidth);
315  if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
316  O << "\tmov\t";
317  printRegName(O, MI->getOperand(0).getReg());
318  O << ", " << markup("<imm:") << "#"
319  << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
320  return;
321  }
322  }
323 
324  if (Opcode == AArch64::CompilerBarrier) {
325  O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
326  printAnnotation(O, Annot);
327  return;
328  }
329 
330  if (Opcode == AArch64::SPACE) {
331  O << '\t' << MAI.getCommentString() << " SPACE "
332  << MI->getOperand(1).getImm();
333  printAnnotation(O, Annot);
334  return;
335  }
336 
337  // Instruction TSB is specified as a one operand instruction, but 'csync' is
338  // not encoded, so for printing it is treated as a special case here:
339  if (Opcode == AArch64::TSB) {
340  O << "\ttsb\tcsync";
341  return;
342  }
343 
344  if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
345  printInstruction(MI, Address, STI, O);
346 
347  printAnnotation(O, Annot);
348 
349  if (atomicBarrierDroppedOnZero(Opcode) &&
350  (MI->getOperand(0).getReg() == AArch64::XZR ||
351  MI->getOperand(0).getReg() == AArch64::WZR)) {
352  printAnnotation(O, "acquire semantics dropped since destination is zero");
353  }
354 }
355 
356 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
357  bool &IsTbx) {
358  switch (Opcode) {
359  case AArch64::TBXv8i8One:
360  case AArch64::TBXv8i8Two:
361  case AArch64::TBXv8i8Three:
362  case AArch64::TBXv8i8Four:
363  IsTbx = true;
364  Layout = ".8b";
365  return true;
366  case AArch64::TBLv8i8One:
367  case AArch64::TBLv8i8Two:
368  case AArch64::TBLv8i8Three:
369  case AArch64::TBLv8i8Four:
370  IsTbx = false;
371  Layout = ".8b";
372  return true;
373  case AArch64::TBXv16i8One:
374  case AArch64::TBXv16i8Two:
375  case AArch64::TBXv16i8Three:
376  case AArch64::TBXv16i8Four:
377  IsTbx = true;
378  Layout = ".16b";
379  return true;
380  case AArch64::TBLv16i8One:
381  case AArch64::TBLv16i8Two:
382  case AArch64::TBLv16i8Three:
383  case AArch64::TBLv16i8Four:
384  IsTbx = false;
385  Layout = ".16b";
386  return true;
387  default:
388  return false;
389  }
390 }
391 
393  unsigned Opcode;
394  const char *Mnemonic;
395  const char *Layout;
397  bool HasLane;
399 };
400 
401 static const LdStNInstrDesc LdStNInstInfo[] = {
402  { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
403  { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
404  { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
405  { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
406  { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
407  { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
408  { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
409  { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
410  { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
411  { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
412  { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
413  { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
414  { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
415  { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
416  { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
417  { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
418  { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
419  { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
420  { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
421  { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
422  { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
423  { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
424  { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
425  { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
426  { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
427  { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
428  { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
429  { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
430  { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
431  { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
432  { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
433  { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
434  { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
435  { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
436  { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
437  { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
438  { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
439  { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
440  { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
441  { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
442  { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
443  { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
444  { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
445  { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
446  { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
447  { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
448  { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
449  { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
450  { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
451  { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
452  { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
453  { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
454  { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
455  { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
456  { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
457  { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
458  { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
459  { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
460  { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
461  { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
462  { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
463  { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
464  { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
465  { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
466  { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
467  { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
468  { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
469  { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
470  { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
471  { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
472  { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
473  { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
474  { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
475  { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
476  { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
477  { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
478  { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
479  { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
480  { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
481  { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
482  { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
483  { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
484  { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
485  { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
486  { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
487  { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
488  { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
489  { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
490  { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
491  { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
492  { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
493  { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
494  { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
495  { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
496  { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
497  { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
498  { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
499  { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
500  { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
501  { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
502  { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
503  { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
504  { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
505  { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
506  { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
507  { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
508  { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
509  { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
510  { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
511  { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
512  { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
513  { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
514  { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
515  { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
516  { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
517  { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
518  { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
519  { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
520  { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
521  { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
522  { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
523  { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
524  { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
525  { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
526  { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
527  { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
528  { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
529  { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
530  { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
531  { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
532  { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
533  { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
534  { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
535  { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
536  { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
537  { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
538  { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
539  { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
540  { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
541  { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
542  { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
543  { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
544  { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
545  { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
546  { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
547  { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
548  { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
549  { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
550  { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
551  { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
552  { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
553  { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
554  { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
555  { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
556  { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
557  { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
558  { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
559  { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
560  { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
561  { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
562  { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
563  { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
564  { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
565  { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
566  { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
567  { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
568  { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
569  { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
570  { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
571  { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
572  { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
573  { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
574  { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
575  { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
576  { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
577  { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
578  { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
579  { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
580  { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
581  { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
582  { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
583  { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
584  { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
585  { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
586  { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
587  { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
588  { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
589  { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
590  { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
591  { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
592  { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
593  { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
594  { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
595  { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
596  { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
597  { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
598  { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
599  { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
600  { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
601  { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
602  { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
603  { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
604  { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
605  { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
606  { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
607  { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
608  { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
609  { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
610  { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
611  { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
612  { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
613  { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
614  { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
615  { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
616  { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
617  { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
618  { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
619  { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
620  { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
621  { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
622  { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
623  { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
624  { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
625  { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
626  { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
627  { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
628  { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
629  { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
630  { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
631  { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
632  { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
633  { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
634  { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
635  { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
636  { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
637  { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
638  { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
639  { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
640  { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
641  { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
642  { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
643  { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
644  { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
645  { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
646  { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
647  { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
648  { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
649  { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
650  { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
651  { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
652  { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
653  { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
654  { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
655  { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
656  { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
657  { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
658  { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
659  { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
660  { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
661  { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
662  { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
663  { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
664  { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
665  { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
666  { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
667  { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
668  { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
669  { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
670  { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
671  { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
672  { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
673  { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
674  { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
675  { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
676  { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
677  { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
678  { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
679  { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
680  { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
681  { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
682  { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
683  { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
684  { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
685  { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
686  { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
687  { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
688  { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
689  { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
690  { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
691  { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
692  { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
693  { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
694  { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
695  { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
696  { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
697  { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
698  { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
699  { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
700  { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
701  { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
702  { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
703  { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
704  { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
705  { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
706  { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
707  { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
708  { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
709  { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
710  { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
711  { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
712  { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
713  { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
714  { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
715  { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
716  { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
717  { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
718  { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
719  { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
720  { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
721  { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
722  { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
723  { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
724  { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
725  { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
726  { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
727  { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
728  { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
729  { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
730  { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
731  { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
732  { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
733  { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
734  { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
735  { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
736  { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
737  { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
738  { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
739  { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
740  { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
741  { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
742 };
743 
744 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
745  for (const auto &Info : LdStNInstInfo)
746  if (Info.Opcode == Opcode)
747  return &Info;
748 
749  return nullptr;
750 }
751 
753  StringRef Annot,
754  const MCSubtargetInfo &STI,
755  raw_ostream &O) {
756  unsigned Opcode = MI->getOpcode();
757  StringRef Layout;
758 
759  bool IsTbx;
760  if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
761  O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
762  printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
763  O << ", ";
764 
765  unsigned ListOpNum = IsTbx ? 2 : 1;
766  printVectorList(MI, ListOpNum, STI, O, "");
767 
768  O << ", ";
769  printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
770  printAnnotation(O, Annot);
771  return;
772  }
773 
774  if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
775  O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
776 
777  // Now onto the operands: first a vector list with possible lane
778  // specifier. E.g. { v0 }[2]
779  int OpNum = LdStDesc->ListOperand;
780  printVectorList(MI, OpNum++, STI, O, "");
781 
782  if (LdStDesc->HasLane)
783  O << '[' << MI->getOperand(OpNum++).getImm() << ']';
784 
785  // Next the address: [xN]
786  unsigned AddrReg = MI->getOperand(OpNum++).getReg();
787  O << ", [";
788  printRegName(O, AddrReg);
789  O << ']';
790 
791  // Finally, there might be a post-indexed offset.
792  if (LdStDesc->NaturalOffset != 0) {
793  unsigned Reg = MI->getOperand(OpNum++).getReg();
794  if (Reg != AArch64::XZR) {
795  O << ", ";
796  printRegName(O, Reg);
797  } else {
798  assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
799  O << ", " << markup("<imm:") << "#" << LdStDesc->NaturalOffset
800  << markup(">");
801  }
802  }
803 
804  printAnnotation(O, Annot);
805  return;
806  }
807 
808  AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
809 }
810 
812  const MCSubtargetInfo &STI,
813  raw_ostream &O) {
814 #ifndef NDEBUG
815  unsigned Opcode = MI->getOpcode();
816  assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
817 #endif
818 
819  const MCOperand &Op1 = MI->getOperand(0);
820  const MCOperand &Cn = MI->getOperand(1);
821  const MCOperand &Cm = MI->getOperand(2);
822  const MCOperand &Op2 = MI->getOperand(3);
823 
824  unsigned Op1Val = Op1.getImm();
825  unsigned CnVal = Cn.getImm();
826  unsigned CmVal = Cm.getImm();
827  unsigned Op2Val = Op2.getImm();
828 
829  uint16_t Encoding = Op2Val;
830  Encoding |= CmVal << 3;
831  Encoding |= CnVal << 7;
832  Encoding |= Op1Val << 11;
833 
834  bool NeedsReg;
835  std::string Ins;
836  std::string Name;
837 
838  if (CnVal == 7) {
839  switch (CmVal) {
840  default: return false;
841  // Maybe IC, maybe Prediction Restriction
842  case 1:
843  switch (Op1Val) {
844  default: return false;
845  case 0: goto Search_IC;
846  case 3: goto Search_PRCTX;
847  }
848  // Prediction Restriction aliases
849  case 3: {
850  Search_PRCTX:
851  const AArch64PRCTX::PRCTX *PRCTX = AArch64PRCTX::lookupPRCTXByEncoding(Encoding >> 3);
852  if (!PRCTX || !PRCTX->haveFeatures(STI.getFeatureBits()))
853  return false;
854 
855  NeedsReg = PRCTX->NeedsReg;
856  switch (Op2Val) {
857  default: return false;
858  case 4: Ins = "cfp\t"; break;
859  case 5: Ins = "dvp\t"; break;
860  case 7: Ins = "cpp\t"; break;
861  }
862  Name = std::string(PRCTX->Name);
863  }
864  break;
865  // IC aliases
866  case 5: {
867  Search_IC:
868  const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
869  if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
870  return false;
871 
872  NeedsReg = IC->NeedsReg;
873  Ins = "ic\t";
874  Name = std::string(IC->Name);
875  }
876  break;
877  // DC aliases
878  case 4: case 6: case 10: case 11: case 12: case 13: case 14:
879  {
880  const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
881  if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
882  return false;
883 
884  NeedsReg = true;
885  Ins = "dc\t";
886  Name = std::string(DC->Name);
887  }
888  break;
889  // AT aliases
890  case 8: case 9: {
891  const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
892  if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
893  return false;
894 
895  NeedsReg = true;
896  Ins = "at\t";
897  Name = std::string(AT->Name);
898  }
899  break;
900  }
901  } else if (CnVal == 8 || CnVal == 9) {
902  // TLBI aliases
903  const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
904  if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
905  return false;
906 
907  NeedsReg = TLBI->NeedsReg;
908  Ins = "tlbi\t";
909  Name = std::string(TLBI->Name);
910  }
911  else
912  return false;
913 
914  std::string Str = Ins + Name;
915  std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
916 
917  O << '\t' << Str;
918  if (NeedsReg) {
919  O << ", ";
920  printRegName(O, MI->getOperand(4).getReg());
921  }
922 
923  return true;
924 }
925 
926 template <int EltSize>
927 void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
928  const MCSubtargetInfo &STI,
929  raw_ostream &O) {
930  const MCOperand &RegOp = MI->getOperand(OpNum);
931  assert(RegOp.isReg() && "Unexpected operand type!");
932 
933  printRegName(O, RegOp.getReg());
934  switch (EltSize) {
935  case 0:
936  break;
937  case 8:
938  O << ".b";
939  break;
940  case 16:
941  O << ".h";
942  break;
943  case 32:
944  O << ".s";
945  break;
946  case 64:
947  O << ".d";
948  break;
949  case 128:
950  O << ".q";
951  break;
952  default:
953  llvm_unreachable("Unsupported element size");
954  }
955 }
956 
957 template <bool IsVertical>
959  const MCSubtargetInfo &STI,
960  raw_ostream &O) {
961  const MCOperand &RegOp = MI->getOperand(OpNum);
962  assert(RegOp.isReg() && "Unexpected operand type!");
964 
965  // Insert the horizontal/vertical flag before the suffix.
966  StringRef Base, Suffix;
967  std::tie(Base, Suffix) = RegName.split('.');
968  O << Base << (IsVertical ? "v" : "h") << '.' << Suffix;
969 }
970 
971 void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
972  const MCSubtargetInfo &STI,
973  raw_ostream &O) {
974  const MCOperand &RegOp = MI->getOperand(OpNum);
975  assert(RegOp.isReg() && "Unexpected operand type!");
976  printRegName(O, RegOp.getReg());
977 }
978 
979 void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
980  const MCSubtargetInfo &STI,
981  raw_ostream &O) {
982  const MCOperand &MO = MI->getOperand(OpNum);
983  assert(MO.isImm() && "Unexpected operand type!");
984  unsigned svcrop = MO.getImm();
985  const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
986  assert(SVCR && "Unexpected SVCR operand!");
987  O << SVCR->Name;
988 }
989 
990 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
991  const MCSubtargetInfo &STI,
992  raw_ostream &O) {
993  const MCOperand &Op = MI->getOperand(OpNo);
994  if (Op.isReg()) {
995  unsigned Reg = Op.getReg();
996  printRegName(O, Reg);
997  } else if (Op.isImm()) {
998  printImm(MI, OpNo, STI, O);
999  } else {
1000  assert(Op.isExpr() && "unknown operand kind in printOperand");
1001  Op.getExpr()->print(O, &MAI);
1002  }
1003 }
1004 
1005 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
1006  const MCSubtargetInfo &STI,
1007  raw_ostream &O) {
1008  const MCOperand &Op = MI->getOperand(OpNo);
1009  O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
1010 }
1011 
1012 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
1013  const MCSubtargetInfo &STI,
1014  raw_ostream &O) {
1015  const MCOperand &Op = MI->getOperand(OpNo);
1016  O << markup("<imm:") << format("#%#llx", Op.getImm()) << markup(">");
1017 }
1018 
1019 template<int Size>
1020 void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1021  const MCSubtargetInfo &STI,
1022  raw_ostream &O) {
1023  const MCOperand &Op = MI->getOperand(OpNo);
1024  if (Size == 8)
1025  O << markup("<imm:") << "#" << formatImm((signed char)Op.getImm())
1026  << markup(">");
1027  else if (Size == 16)
1028  O << markup("<imm:") << "#" << formatImm((signed short)Op.getImm())
1029  << markup(">");
1030  else
1031  O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
1032 }
1033 
1035  unsigned Imm, raw_ostream &O) {
1036  const MCOperand &Op = MI->getOperand(OpNo);
1037  if (Op.isReg()) {
1038  unsigned Reg = Op.getReg();
1039  if (Reg == AArch64::XZR)
1040  O << markup("<imm:") << "#" << Imm << markup(">");
1041  else
1042  printRegName(O, Reg);
1043  } else
1044  llvm_unreachable("unknown operand kind in printPostIncOperand64");
1045 }
1046 
1048  const MCSubtargetInfo &STI,
1049  raw_ostream &O) {
1050  const MCOperand &Op = MI->getOperand(OpNo);
1051  assert(Op.isReg() && "Non-register vreg operand!");
1052  unsigned Reg = Op.getReg();
1053  printRegName(O, Reg, AArch64::vreg);
1054 }
1055 
1057  const MCSubtargetInfo &STI,
1058  raw_ostream &O) {
1059  const MCOperand &Op = MI->getOperand(OpNo);
1060  assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1061  O << "c" << Op.getImm();
1062 }
1063 
1064 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1065  const MCSubtargetInfo &STI,
1066  raw_ostream &O) {
1067  const MCOperand &MO = MI->getOperand(OpNum);
1068  if (MO.isImm()) {
1069  unsigned Val = (MO.getImm() & 0xfff);
1070  assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1071  unsigned Shift =
1072  AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1073  O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
1074  if (Shift != 0) {
1075  printShifter(MI, OpNum + 1, STI, O);
1076  if (CommentStream)
1077  *CommentStream << '=' << formatImm(Val << Shift) << '\n';
1078  }
1079  } else {
1080  assert(MO.isExpr() && "Unexpected operand type!");
1081  MO.getExpr()->print(O, &MAI);
1082  printShifter(MI, OpNum + 1, STI, O);
1083  }
1084 }
1085 
1086 template <typename T>
1087 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
1088  const MCSubtargetInfo &STI,
1089  raw_ostream &O) {
1090  uint64_t Val = MI->getOperand(OpNum).getImm();
1091  O << markup("<imm:") << "#0x";
1092  O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
1093  O << markup(">");
1094 }
1095 
1096 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1097  const MCSubtargetInfo &STI,
1098  raw_ostream &O) {
1099  unsigned Val = MI->getOperand(OpNum).getImm();
1100  // LSL #0 should not be printed.
1102  AArch64_AM::getShiftValue(Val) == 0)
1103  return;
1105  << " " << markup("<imm:") << "#" << AArch64_AM::getShiftValue(Val)
1106  << markup(">");
1107 }
1108 
1110  const MCSubtargetInfo &STI,
1111  raw_ostream &O) {
1112  printRegName(O, MI->getOperand(OpNum).getReg());
1113  printShifter(MI, OpNum + 1, STI, O);
1114 }
1115 
1117  const MCSubtargetInfo &STI,
1118  raw_ostream &O) {
1119  printRegName(O, MI->getOperand(OpNum).getReg());
1120  printArithExtend(MI, OpNum + 1, STI, O);
1121 }
1122 
1123 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1124  const MCSubtargetInfo &STI,
1125  raw_ostream &O) {
1126  unsigned Val = MI->getOperand(OpNum).getImm();
1128  unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1129 
1130  // If the destination or first source register operand is [W]SP, print
1131  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1132  // all.
1133  if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1134  unsigned Dest = MI->getOperand(0).getReg();
1135  unsigned Src1 = MI->getOperand(1).getReg();
1136  if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1137  ExtType == AArch64_AM::UXTX) ||
1138  ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1139  ExtType == AArch64_AM::UXTW) ) {
1140  if (ShiftVal != 0)
1141  O << ", lsl " << markup("<imm:") << "#" << ShiftVal << markup(">");
1142  return;
1143  }
1144  }
1145  O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1146  if (ShiftVal != 0)
1147  O << " " << markup("<imm:") << "#" << ShiftVal << markup(">");
1148 }
1149 
1150 static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width,
1151  char SrcRegKind, raw_ostream &O,
1152  bool UseMarkup) {
1153  // sxtw, sxtx, uxtw or lsl (== uxtx)
1154  bool IsLSL = !SignExtend && SrcRegKind == 'x';
1155  if (IsLSL)
1156  O << "lsl";
1157  else
1158  O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1159 
1160  if (DoShift || IsLSL) {
1161  O << " ";
1162  if (UseMarkup)
1163  O << "<imm:";
1164  O << " #" << Log2_32(Width / 8);
1165  if (UseMarkup)
1166  O << ">";
1167  }
1168 }
1169 
1170 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1171  raw_ostream &O, char SrcRegKind,
1172  unsigned Width) {
1173  bool SignExtend = MI->getOperand(OpNum).getImm();
1174  bool DoShift = MI->getOperand(OpNum + 1).getImm();
1175  printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O, UseMarkup);
1176 }
1177 
1178 template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1180  unsigned OpNum,
1181  const MCSubtargetInfo &STI,
1182  raw_ostream &O) {
1183  printOperand(MI, OpNum, STI, O);
1184  if (Suffix == 's' || Suffix == 'd')
1185  O << '.' << Suffix;
1186  else
1187  assert(Suffix == 0 && "Unsupported suffix size");
1188 
1189  bool DoShift = ExtWidth != 8;
1190  if (SignExtend || DoShift || SrcRegKind == 'w') {
1191  O << ", ";
1192  printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O, UseMarkup);
1193  }
1194 }
1195 
1196 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1197  const MCSubtargetInfo &STI,
1198  raw_ostream &O) {
1199  AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1201 }
1202 
1204  const MCSubtargetInfo &STI,
1205  raw_ostream &O) {
1206  AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1208 }
1209 
1210 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1211  const MCSubtargetInfo &STI,
1212  raw_ostream &O) {
1213  O << '[';
1214  printRegName(O, MI->getOperand(OpNum).getReg());
1215  O << ']';
1216 }
1217 
1218 template<int Scale>
1219 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1220  const MCSubtargetInfo &STI,
1221  raw_ostream &O) {
1222  O << markup("<imm:") << '#'
1223  << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
1224 }
1225 
1227  unsigned Scale, raw_ostream &O) {
1228  const MCOperand MO = MI->getOperand(OpNum);
1229  if (MO.isImm()) {
1230  O << markup("<imm:") << '#' << formatImm(MO.getImm() * Scale)
1231  << markup(">");
1232  } else {
1233  assert(MO.isExpr() && "Unexpected operand type!");
1234  MO.getExpr()->print(O, &MAI);
1235  }
1236 }
1237 
1238 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1239  unsigned Scale, raw_ostream &O) {
1240  const MCOperand MO1 = MI->getOperand(OpNum + 1);
1241  O << '[';
1242  printRegName(O, MI->getOperand(OpNum).getReg());
1243  if (MO1.isImm()) {
1244  O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
1245  << markup(">");
1246  } else {
1247  assert(MO1.isExpr() && "Unexpected operand type!");
1248  O << ", ";
1249  MO1.getExpr()->print(O, &MAI);
1250  }
1251  O << ']';
1252 }
1253 
1254 template <bool IsSVEPrefetch>
1255 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1256  const MCSubtargetInfo &STI,
1257  raw_ostream &O) {
1258  unsigned prfop = MI->getOperand(OpNum).getImm();
1259  if (IsSVEPrefetch) {
1260  if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1261  O << PRFM->Name;
1262  return;
1263  }
1264  } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
1265  O << PRFM->Name;
1266  return;
1267  }
1268 
1269  O << markup("<imm:") << '#' << formatImm(prfop) << markup(">");
1270 }
1271 
1272 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1273  const MCSubtargetInfo &STI,
1274  raw_ostream &O) {
1275  unsigned psbhintop = MI->getOperand(OpNum).getImm();
1276  auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1277  if (PSB)
1278  O << PSB->Name;
1279  else
1280  O << markup("<imm:") << '#' << formatImm(psbhintop) << markup(">");
1281 }
1282 
1283 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1284  const MCSubtargetInfo &STI,
1285  raw_ostream &O) {
1286  unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
1287  auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1288  if (BTI)
1289  O << BTI->Name;
1290  else
1291  O << markup("<imm:") << '#' << formatImm(btihintop) << markup(">");
1292 }
1293 
1295  const MCSubtargetInfo &STI,
1296  raw_ostream &O) {
1297  const MCOperand &MO = MI->getOperand(OpNum);
1298  float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm())
1300 
1301  // 8 decimal places are enough to perfectly represent permitted floats.
1302  O << markup("<imm:") << format("#%.8f", FPImm) << markup(">");
1303 }
1304 
1305 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1306  while (Stride--) {
1307  switch (Reg) {
1308  default:
1309  llvm_unreachable("Vector register expected!");
1310  case AArch64::Q0: Reg = AArch64::Q1; break;
1311  case AArch64::Q1: Reg = AArch64::Q2; break;
1312  case AArch64::Q2: Reg = AArch64::Q3; break;
1313  case AArch64::Q3: Reg = AArch64::Q4; break;
1314  case AArch64::Q4: Reg = AArch64::Q5; break;
1315  case AArch64::Q5: Reg = AArch64::Q6; break;
1316  case AArch64::Q6: Reg = AArch64::Q7; break;
1317  case AArch64::Q7: Reg = AArch64::Q8; break;
1318  case AArch64::Q8: Reg = AArch64::Q9; break;
1319  case AArch64::Q9: Reg = AArch64::Q10; break;
1320  case AArch64::Q10: Reg = AArch64::Q11; break;
1321  case AArch64::Q11: Reg = AArch64::Q12; break;
1322  case AArch64::Q12: Reg = AArch64::Q13; break;
1323  case AArch64::Q13: Reg = AArch64::Q14; break;
1324  case AArch64::Q14: Reg = AArch64::Q15; break;
1325  case AArch64::Q15: Reg = AArch64::Q16; break;
1326  case AArch64::Q16: Reg = AArch64::Q17; break;
1327  case AArch64::Q17: Reg = AArch64::Q18; break;
1328  case AArch64::Q18: Reg = AArch64::Q19; break;
1329  case AArch64::Q19: Reg = AArch64::Q20; break;
1330  case AArch64::Q20: Reg = AArch64::Q21; break;
1331  case AArch64::Q21: Reg = AArch64::Q22; break;
1332  case AArch64::Q22: Reg = AArch64::Q23; break;
1333  case AArch64::Q23: Reg = AArch64::Q24; break;
1334  case AArch64::Q24: Reg = AArch64::Q25; break;
1335  case AArch64::Q25: Reg = AArch64::Q26; break;
1336  case AArch64::Q26: Reg = AArch64::Q27; break;
1337  case AArch64::Q27: Reg = AArch64::Q28; break;
1338  case AArch64::Q28: Reg = AArch64::Q29; break;
1339  case AArch64::Q29: Reg = AArch64::Q30; break;
1340  case AArch64::Q30: Reg = AArch64::Q31; break;
1341  // Vector lists can wrap around.
1342  case AArch64::Q31:
1343  Reg = AArch64::Q0;
1344  break;
1345  case AArch64::Z0: Reg = AArch64::Z1; break;
1346  case AArch64::Z1: Reg = AArch64::Z2; break;
1347  case AArch64::Z2: Reg = AArch64::Z3; break;
1348  case AArch64::Z3: Reg = AArch64::Z4; break;
1349  case AArch64::Z4: Reg = AArch64::Z5; break;
1350  case AArch64::Z5: Reg = AArch64::Z6; break;
1351  case AArch64::Z6: Reg = AArch64::Z7; break;
1352  case AArch64::Z7: Reg = AArch64::Z8; break;
1353  case AArch64::Z8: Reg = AArch64::Z9; break;
1354  case AArch64::Z9: Reg = AArch64::Z10; break;
1355  case AArch64::Z10: Reg = AArch64::Z11; break;
1356  case AArch64::Z11: Reg = AArch64::Z12; break;
1357  case AArch64::Z12: Reg = AArch64::Z13; break;
1358  case AArch64::Z13: Reg = AArch64::Z14; break;
1359  case AArch64::Z14: Reg = AArch64::Z15; break;
1360  case AArch64::Z15: Reg = AArch64::Z16; break;
1361  case AArch64::Z16: Reg = AArch64::Z17; break;
1362  case AArch64::Z17: Reg = AArch64::Z18; break;
1363  case AArch64::Z18: Reg = AArch64::Z19; break;
1364  case AArch64::Z19: Reg = AArch64::Z20; break;
1365  case AArch64::Z20: Reg = AArch64::Z21; break;
1366  case AArch64::Z21: Reg = AArch64::Z22; break;
1367  case AArch64::Z22: Reg = AArch64::Z23; break;
1368  case AArch64::Z23: Reg = AArch64::Z24; break;
1369  case AArch64::Z24: Reg = AArch64::Z25; break;
1370  case AArch64::Z25: Reg = AArch64::Z26; break;
1371  case AArch64::Z26: Reg = AArch64::Z27; break;
1372  case AArch64::Z27: Reg = AArch64::Z28; break;
1373  case AArch64::Z28: Reg = AArch64::Z29; break;
1374  case AArch64::Z29: Reg = AArch64::Z30; break;
1375  case AArch64::Z30: Reg = AArch64::Z31; break;
1376  // Vector lists can wrap around.
1377  case AArch64::Z31:
1378  Reg = AArch64::Z0;
1379  break;
1380  }
1381  }
1382  return Reg;
1383 }
1384 
1385 template<unsigned size>
1387  unsigned OpNum,
1388  const MCSubtargetInfo &STI,
1389  raw_ostream &O) {
1390  static_assert(size == 64 || size == 32,
1391  "Template parameter must be either 32 or 64");
1392  unsigned Reg = MI->getOperand(OpNum).getReg();
1393 
1394  unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1395  unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1396 
1397  unsigned Even = MRI.getSubReg(Reg, Sube);
1398  unsigned Odd = MRI.getSubReg(Reg, Subo);
1399  printRegName(O, Even);
1400  O << ", ";
1401  printRegName(O, Odd);
1402 }
1403 
1405  const MCSubtargetInfo &STI,
1406  raw_ostream &O) {
1407  unsigned MaxRegs = 8;
1408  unsigned RegMask = MI->getOperand(OpNum).getImm();
1409 
1410  unsigned NumRegs = 0;
1411  for (unsigned I = 0; I < MaxRegs; ++I)
1412  if ((RegMask & (1 << I)) != 0)
1413  ++NumRegs;
1414 
1415  O << "{";
1416  unsigned Printed = 0;
1417  for (unsigned I = 0; I < MaxRegs; ++I) {
1418  unsigned Reg = RegMask & (1 << I);
1419  if (Reg == 0)
1420  continue;
1421  printRegName(O, AArch64::ZAD0 + I);
1422  if (Printed + 1 != NumRegs)
1423  O << ", ";
1424  ++Printed;
1425  }
1426  O << "}";
1427 }
1428 
1429 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1430  const MCSubtargetInfo &STI,
1431  raw_ostream &O,
1432  StringRef LayoutSuffix) {
1433  unsigned Reg = MI->getOperand(OpNum).getReg();
1434 
1435  O << "{ ";
1436 
1437  // Work out how many registers there are in the list (if there is an actual
1438  // list).
1439  unsigned NumRegs = 1;
1440  if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1441  MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1442  MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1443  NumRegs = 2;
1444  else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1445  MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1446  MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1447  NumRegs = 3;
1448  else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1449  MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1450  MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1451  NumRegs = 4;
1452 
1453  // Now forget about the list and find out what the first register is.
1454  if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1455  Reg = FirstReg;
1456  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1457  Reg = FirstReg;
1458  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1459  Reg = FirstReg;
1460 
1461  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1462  // printing (otherwise getRegisterName fails).
1463  if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1464  const MCRegisterClass &FPR128RC =
1465  MRI.getRegClass(AArch64::FPR128RegClassID);
1466  Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1467  }
1468 
1469  for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1470  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
1471  printRegName(O, Reg);
1472  else
1473  printRegName(O, Reg, AArch64::vreg);
1474  O << LayoutSuffix;
1475 
1476  if (i + 1 != NumRegs)
1477  O << ", ";
1478  }
1479 
1480  O << " }";
1481 }
1482 
1483 void
1485  unsigned OpNum,
1486  const MCSubtargetInfo &STI,
1487  raw_ostream &O) {
1488  printVectorList(MI, OpNum, STI, O, "");
1489 }
1490 
1491 template <unsigned NumLanes, char LaneKind>
1493  const MCSubtargetInfo &STI,
1494  raw_ostream &O) {
1495  std::string Suffix(".");
1496  if (NumLanes)
1497  Suffix += itostr(NumLanes) + LaneKind;
1498  else
1499  Suffix += LaneKind;
1500 
1501  printVectorList(MI, OpNum, STI, O, Suffix);
1502 }
1503 
1504 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1505  const MCSubtargetInfo &STI,
1506  raw_ostream &O) {
1507  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1508 }
1509 
1510 void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1511  const MCSubtargetInfo &STI,
1512  raw_ostream &O) {
1513  O << MI->getOperand(OpNum).getImm();
1514 }
1515 
1517  unsigned OpNum,
1518  const MCSubtargetInfo &STI,
1519  raw_ostream &O) {
1520  const MCOperand &Op = MI->getOperand(OpNum);
1521 
1522  // If the label has already been resolved to an immediate offset (say, when
1523  // we're running the disassembler), just print the immediate.
1524  if (Op.isImm()) {
1525  O << markup("<imm:");
1526  int64_t Offset = Op.getImm() * 4;
1528  O << formatHex(Address + Offset);
1529  else
1530  O << "#" << formatImm(Offset);
1531  O << markup(">");
1532  return;
1533  }
1534 
1535  // If the branch target is simply an address then print it in hex.
1536  const MCConstantExpr *BranchTarget =
1537  dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1538  int64_t TargetAddress;
1539  if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1540  O << formatHex(TargetAddress);
1541  } else {
1542  // Otherwise, just print the expression.
1543  MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1544  }
1545 }
1546 
1548  unsigned OpNum,
1549  const MCSubtargetInfo &STI,
1550  raw_ostream &O) {
1551  const MCOperand &Op = MI->getOperand(OpNum);
1552 
1553  // If the label has already been resolved to an immediate offset (say, when
1554  // we're running the disassembler), just print the immediate.
1555  if (Op.isImm()) {
1556  const int64_t Offset = Op.getImm() * 4096;
1557  O << markup("<imm:");
1559  O << formatHex((Address & -4096) + Offset);
1560  else
1561  O << "#" << Offset;
1562  O << markup(">");
1563  return;
1564  }
1565 
1566  // Otherwise, just print the expression.
1567  MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1568 }
1569 
1571  const MCSubtargetInfo &STI,
1572  raw_ostream &O) {
1573  unsigned Val = MI->getOperand(OpNo).getImm();
1574  unsigned Opcode = MI->getOpcode();
1575 
1576  StringRef Name;
1577  if (Opcode == AArch64::ISB) {
1578  auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1579  Name = ISB ? ISB->Name : "";
1580  } else if (Opcode == AArch64::TSB) {
1581  auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1582  Name = TSB ? TSB->Name : "";
1583  } else {
1584  auto DB = AArch64DB::lookupDBByEncoding(Val);
1585  Name = DB ? DB->Name : "";
1586  }
1587  if (!Name.empty())
1588  O << Name;
1589  else
1590  O << markup("<imm:") << "#" << Val << markup(">");
1591 }
1592 
1594  const MCSubtargetInfo &STI,
1595  raw_ostream &O) {
1596  unsigned Val = MI->getOperand(OpNo).getImm();
1597  assert(MI->getOpcode() == AArch64::DSBnXS);
1598 
1599  StringRef Name;
1600  auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1601  Name = DB ? DB->Name : "";
1602 
1603  if (!Name.empty())
1604  O << Name;
1605  else
1606  O << markup("<imm:") << "#" << Val << markup(">");
1607 }
1608 
1609 static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read,
1610  const MCSubtargetInfo &STI) {
1611  return (Reg && (Read ? Reg->Readable : Reg->Writeable) &&
1612  Reg->haveFeatures(STI.getFeatureBits()));
1613 }
1614 
1615 // Looks up a system register either by encoding or by name. Some system
1616 // registers share the same encoding between different architectures,
1617 // therefore a tablegen lookup by encoding will return an entry regardless
1618 // of the register's predication on a specific subtarget feature. To work
1619 // around this problem we keep an alternative name for such registers and
1620 // look them up by that name if the first lookup was unsuccessful.
1621 static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
1622  const MCSubtargetInfo &STI) {
1624 
1625  if (Reg && !isValidSysReg(Reg, Read, STI))
1627 
1628  return Reg;
1629 }
1630 
1632  const MCSubtargetInfo &STI,
1633  raw_ostream &O) {
1634  unsigned Val = MI->getOperand(OpNo).getImm();
1635 
1636  // Horrible hack for the one register that has identical encodings but
1637  // different names in MSR and MRS. Because of this, one of MRS and MSR is
1638  // going to get the wrong entry
1639  if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1640  O << "DBGDTRRX_EL0";
1641  return;
1642  }
1643 
1644  // Horrible hack for two different registers having the same encoding.
1645  if (Val == AArch64SysReg::TRCEXTINSELR) {
1646  O << "TRCEXTINSELR";
1647  return;
1648  }
1649 
1650  const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
1651 
1652  if (isValidSysReg(Reg, true /*Read*/, STI))
1653  O << Reg->Name;
1654  else
1656 }
1657 
1659  const MCSubtargetInfo &STI,
1660  raw_ostream &O) {
1661  unsigned Val = MI->getOperand(OpNo).getImm();
1662 
1663  // Horrible hack for the one register that has identical encodings but
1664  // different names in MSR and MRS. Because of this, one of MRS and MSR is
1665  // going to get the wrong entry
1666  if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1667  O << "DBGDTRTX_EL0";
1668  return;
1669  }
1670 
1671  // Horrible hack for two different registers having the same encoding.
1672  if (Val == AArch64SysReg::TRCEXTINSELR) {
1673  O << "TRCEXTINSELR";
1674  return;
1675  }
1676 
1677  const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
1678 
1679  if (isValidSysReg(Reg, false /*Read*/, STI))
1680  O << Reg->Name;
1681  else
1683 }
1684 
1686  const MCSubtargetInfo &STI,
1687  raw_ostream &O) {
1688  unsigned Val = MI->getOperand(OpNo).getImm();
1689 
1690  auto PState = AArch64PState::lookupPStateByEncoding(Val);
1691  if (PState && PState->haveFeatures(STI.getFeatureBits()))
1692  O << PState->Name;
1693  else
1694  O << "#" << formatImm(Val);
1695 }
1696 
1698  const MCSubtargetInfo &STI,
1699  raw_ostream &O) {
1700  unsigned RawVal = MI->getOperand(OpNo).getImm();
1702  O << markup("<imm:") << format("#%#016llx", Val) << markup(">");
1703 }
1704 
1705 template<int64_t Angle, int64_t Remainder>
1707  const MCSubtargetInfo &STI,
1708  raw_ostream &O) {
1709  unsigned Val = MI->getOperand(OpNo).getImm();
1710  O << markup("<imm:") << "#" << (Val * Angle) + Remainder << markup(">");
1711 }
1712 
1713 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1714  const MCSubtargetInfo &STI,
1715  raw_ostream &O) {
1716  unsigned Val = MI->getOperand(OpNum).getImm();
1717  if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1718  O << Pat->Name;
1719  else
1720  O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
1721 }
1722 
1723 template <char suffix>
1724 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
1725  const MCSubtargetInfo &STI,
1726  raw_ostream &O) {
1727  switch (suffix) {
1728  case 0:
1729  case 'b':
1730  case 'h':
1731  case 's':
1732  case 'd':
1733  case 'q':
1734  break;
1735  default: llvm_unreachable("Invalid kind specifier.");
1736  }
1737 
1738  unsigned Reg = MI->getOperand(OpNum).getReg();
1739  printRegName(O, Reg);
1740  if (suffix != 0)
1741  O << '.' << suffix;
1742 }
1743 
1744 template <typename T>
1746  std::make_unsigned_t<T> HexValue = Value;
1747 
1748  if (getPrintImmHex())
1749  O << markup("<imm:") << '#' << formatHex((uint64_t)HexValue) << markup(">");
1750  else
1751  O << markup("<imm:") << '#' << formatDec(Value) << markup(">");
1752 
1753  if (CommentStream) {
1754  // Do the opposite to that used for instruction operands.
1755  if (getPrintImmHex())
1756  *CommentStream << '=' << formatDec(HexValue) << '\n';
1757  else
1758  *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
1759  }
1760 }
1761 
1762 template <typename T>
1763 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
1764  const MCSubtargetInfo &STI,
1765  raw_ostream &O) {
1766  unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
1767  unsigned Shift = MI->getOperand(OpNum + 1).getImm();
1769  "Unexepected shift type!");
1770 
1771  // #0 lsl #8 is never pretty printed
1772  if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
1773  O << markup("<imm:") << '#' << formatImm(UnscaledVal) << markup(">");
1774  printShifter(MI, OpNum + 1, STI, O);
1775  return;
1776  }
1777 
1778  T Val;
1779  if (std::is_signed<T>())
1780  Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1781  else
1782  Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1783 
1784  printImmSVE(Val, O);
1785 }
1786 
1787 template <typename T>
1789  const MCSubtargetInfo &STI,
1790  raw_ostream &O) {
1791  typedef std::make_signed_t<T> SignedT;
1792  typedef std::make_unsigned_t<T> UnsignedT;
1793 
1794  uint64_t Val = MI->getOperand(OpNum).getImm();
1795  UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
1796 
1797  // Prefer the default format for 16bit values, hex otherwise.
1798  if ((int16_t)PrintVal == (SignedT)PrintVal)
1799  printImmSVE((T)PrintVal, O);
1800  else if ((uint16_t)PrintVal == PrintVal)
1801  printImmSVE(PrintVal, O);
1802  else
1803  O << markup("<imm:") << '#' << formatHex((uint64_t)PrintVal) << markup(">");
1804 }
1805 
1806 template <int Width>
1807 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
1808  const MCSubtargetInfo &STI,
1809  raw_ostream &O) {
1810  unsigned Base;
1811  switch (Width) {
1812  case 8: Base = AArch64::B0; break;
1813  case 16: Base = AArch64::H0; break;
1814  case 32: Base = AArch64::S0; break;
1815  case 64: Base = AArch64::D0; break;
1816  case 128: Base = AArch64::Q0; break;
1817  default:
1818  llvm_unreachable("Unsupported width");
1819  }
1820  unsigned Reg = MI->getOperand(OpNum).getReg();
1821  printRegName(O, Reg - AArch64::Z0 + Base);
1822 }
1823 
1824 template <unsigned ImmIs0, unsigned ImmIs1>
1825 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
1826  const MCSubtargetInfo &STI,
1827  raw_ostream &O) {
1828  auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
1829  auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
1830  unsigned Val = MI->getOperand(OpNum).getImm();
1831  O << markup("<imm:") << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr)
1832  << markup(">");
1833 }
1834 
1835 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
1836  const MCSubtargetInfo &STI,
1837  raw_ostream &O) {
1838  unsigned Reg = MI->getOperand(OpNum).getReg();
1840 }
1841 
1842 void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
1843  const MCSubtargetInfo &STI,
1844  raw_ostream &O) {
1845  unsigned Reg = MI->getOperand(OpNum).getReg();
1846  printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
1847 }
isValidSysReg
static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read, const MCSubtargetInfo &STI)
Definition: AArch64InstPrinter.cpp:1609
i
i
Definition: README.txt:29
llvm::AArch64InstPrinter::printMRSSystemRegister
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1631
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void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1056
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void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1516
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format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
Definition: MCInstPrinter.cpp:194
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void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
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const char * Mnemonic
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static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
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Definition: AArch64InstPrinter.cpp:927
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Definition: IRTranslator.cpp:108
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Definition: AArch64InstPrinter.cpp:1685
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Definition: AddressRanges.h:18
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StringRef getCommentString() const
Definition: MCAsmInfo.h:653
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Definition: AArch64InstPrinter.cpp:1621
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MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
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const SysReg * lookupSysRegByName(StringRef)
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Definition: X86DisassemblerDecoder.h:462
llvm::AArch64AppleInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AArch64InstPrinter.cpp:752
llvm::AArch64_AM::isMOVZMovAlias
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition: AArch64AddressingModes.h:818
llvm::AArch64InstPrinter::printArithExtend
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1123
llvm::AArch64InstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
AArch64BaseInfo.h
LdStNInstrDesc::HasLane
bool HasLane
Definition: AArch64InstPrinter.cpp:397
Shift
bool Shift
Definition: README.txt:468
llvm::AArch64InstPrinter::printMatrixTileList
void printMatrixTileList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1404
llvm::AArch64PRCTX::PRCTX
Definition: AArch64BaseInfo.h:697
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::AArch64SysReg::SysReg
Definition: AArch64BaseInfo.h:664
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Format.h
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:69
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::AArch64InstPrinter::printPrefetchOp
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1255
llvm::AArch64InstPrinter::printAddSubImm
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1064
llvm::AArch64InstPrinter::printImm8OptLsl
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1763
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AArch64InstPrinter::printShifter
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1096
LdStNInstrDesc::Opcode
unsigned Opcode
Definition: AArch64InstPrinter.cpp:393
llvm::MCInstPrinter::MRI
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:51
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:543
llvm::AArch64InstPrinter::printGPR64as32
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1835
llvm::AArch64_AM::isMOVNMovAlias
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition: AArch64AddressingModes.h:829
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::AArch64InstPrinter::printBarriernXSOption
void printBarriernXSOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1593
llvm::AArch64InstPrinter::printMemExtend
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
Definition: AArch64InstPrinter.cpp:1170
MCInst.h
llvm::AArch64InstPrinter::printAliasInstr
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:547
llvm::AArch64InstPrinter::printCondCode
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1196
MCSubtargetInfo.h
llvm::AArch64InstPrinter::printUImm12Offset
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1226
llvm::AArch64InstPrinter::printMatrixTileVector
void printMatrixTileVector(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:958
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
printMemExtendImpl
static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O, bool UseMarkup)
Definition: AArch64InstPrinter.cpp:1150
llvm::AArch64DC::DC
Definition: AArch64BaseInfo.h:437
llvm::AArch64IC::IC
Definition: AArch64BaseInfo.h:445
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::MCInstPrinter::UseMarkup
bool UseMarkup
True if we are printing marked up assembly.
Definition: MCInstPrinter.h:55
llvm::AArch64InstPrinter::printFPImmOperand
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1294
llvm::MCInstPrinter::CommentStream
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:48
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:53
llvm::AArch64InstPrinter::printMatrixTile
void printMatrixTile(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:971
llvm::AArch64_AM::getShiftValue
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
Definition: AArch64AddressingModes.h:86
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition: AArch64BaseInfo.h:281
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition: MCInstPrinter.cpp:50
llvm::AArch64InstPrinter::printExtendedRegister
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1116
llvm::AArch64InstPrinter::AArch64InstPrinter
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64InstPrinter.cpp:44
llvm::AArch64_AM::getArithExtendType
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
Definition: AArch64AddressingModes.h:139
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:129
llvm::AArch64InstPrinter::printRegName
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
Definition: AArch64InstPrinter.cpp:62
llvm::MCConstantExpr
Definition: MCExpr.h:144
AArch64AddressingModes.h
llvm::AArch64InstPrinter::printComplexRotationOp
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1706
llvm::AArch64InstPrinter::printSVELogicalImm
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1788
llvm::AArch64_AM::decodeLogicalImmediate
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
Definition: AArch64AddressingModes.h:294
llvm::AArch64InstPrinter::printAMNoIndex
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1210
llvm::AArch64InstPrinter::printBarrierOption
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1570
llvm::AArch64_AM::getShiftExtendName
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
Definition: AArch64AddressingModes.h:53
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
LdStNInstrDesc::NaturalOffset
int NaturalOffset
Definition: AArch64InstPrinter.cpp:398
llvm::AArch64InstPrinter::printPSBHintOp
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1272
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::AArch64InstPrinter::printAMIndexedWB
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1238
llvm::AArch64InstPrinter::printTypedVectorList
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1492
llvm::AArch64AT::AT
Definition: AArch64BaseInfo.h:413
llvm::AArch64InstPrinter::printOperand
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:990
uint64_t
LdStNInstrDesc::ListOperand
int ListOperand
Definition: AArch64InstPrinter.cpp:396
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
llvm::AArch64InstPrinter::printVectorList
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
Definition: AArch64InstPrinter.cpp:1429
llvm::AArch64AppleInstPrinter::AArch64AppleInstPrinter
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64InstPrinter.cpp:49
getNextVectorRegister
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride=1)
Definition: AArch64InstPrinter.cpp:1305
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SysAlias::Name
const char * Name
Definition: AArch64BaseInfo.h:372
StringExtras.h
llvm::MCInstPrinter::getPrintImmHex
bool getPrintImmHex() const
Definition: MCInstPrinter.h:121
llvm::AArch64InstPrinter::printSysAlias
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:811
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition: MCInstPrinter.cpp:198
MCRegisterInfo.h
llvm::AArch64InstPrinter::printAdrpLabel
void printAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1547
transform
instcombine should handle this transform
Definition: README.txt:262
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64InstPrinter::printRegWithShiftExtend
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1179
llvm::AArch64InstPrinter::printImmSVE
void printImmSVE(T Value, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1745
llvm::AArch64InstPrinter::printSVERegOp
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1724
llvm::AArch64InstPrinter::printPostIncOperand
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1034
llvm::AArch64InstPrinter::printImm
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1005
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:134
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1571
llvm::AArch64InstPrinter::printLogicalImm
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1087
llvm::AArch64InstPrinter::printMatrixIndex
void printMatrixIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1510
llvm::AArch64InstPrinter::printShiftedRegister
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1109
MCAsmInfo.h
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition: AArch64BaseInfo.h:207
AArch64InstPrinter.h
llvm::AArch64InstPrinter
Definition: AArch64InstPrinter.h:23
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
LdStNInstrDesc::Layout
const char * Layout
Definition: AArch64InstPrinter.cpp:395
DC
static ManagedStatic< DebugCounter > DC
Definition: DebugCounter.cpp:69
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::AArch64InstPrinter::printVRegOperand
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1047
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AArch64InstPrinter::printSVCROp
void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:979
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:718
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64InstPrinter::printInverseCondCode
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1203
llvm::AArch64_AM::ShiftExtendType
ShiftExtendType
Definition: AArch64AddressingModes.h:33
llvm::AArch64_AM::UXTX
@ UXTX
Definition: AArch64AddressingModes.h:44
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::AArch64SysReg::lookupSysRegByEncoding
const SysReg * lookupSysRegByEncoding(uint16_t)
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::AArch64InstPrinter::printMSRSystemRegister
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1658
uint16_t
llvm::SysAliasReg::NeedsReg
bool NeedsReg
Definition: AArch64BaseInfo.h:389
isTblTbxInstruction
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
Definition: AArch64InstPrinter.cpp:356
llvm::AArch64_AM::isAnyMOVWMovAlias
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
Definition: AArch64AddressingModes.h:841
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition: AArch64BaseInfo.cpp:154
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AArch64InstPrinter::printExactFPImm
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1825
llvm::AArch64_AM::decodeAdvSIMDModImmType10
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
Definition: AArch64AddressingModes.h:642
Casting.h
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::AArch64InstPrinter::printVectorIndex
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1504
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition: AArch64BaseInfo.h:303
llvm::AArch64InstPrinter::printImmScale
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1219
llvm::AArch64_AM::getShiftType
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
Definition: AArch64AddressingModes.h:74
llvm::AArch64_AM::UXTW
@ UXTW
Definition: AArch64AddressingModes.h:43
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
LdStNInstrDesc
Definition: AArch64InstPrinter.cpp:392
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MCInstPrinter::markup
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
Definition: MCInstPrinter.cpp:174
llvm::AArch64InstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AArch64InstPrinter.cpp:71
llvm::AArch64InstPrinter::printInstruction
virtual void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:49
llvm::MCExpr::print
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition: MCInst.h:100
llvm::getWRegFromXReg
static unsigned getWRegFromXReg(unsigned Reg)
Definition: AArch64BaseInfo.h:29
LdStNInstInfo
static const LdStNInstrDesc LdStNInstInfo[]
Definition: AArch64InstPrinter.cpp:401
getLdStNInstrDesc
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
Definition: AArch64InstPrinter.cpp:744
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
llvm::AArch64InstPrinter::applyTargetSpecificCLOption
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
Definition: AArch64InstPrinter.cpp:54
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:380
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
RegName
#define RegName(no)
llvm::AArch64CC::CondCode
CondCode
Definition: AArch64BaseInfo.h:254
llvm::AArch64InstPrinter::printGPRSeqPairsClassOperand
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1386
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AArch64InstPrinter::printBTIHintOp
void printBTIHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1283
raw_ostream.h
llvm::AArch64InstPrinter::printGPR64x8
void printGPR64x8(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1842
llvm::AArch64InstPrinter::printImmHex
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1012
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition: MCInst.h:64
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69