35 #define DEBUG_TYPE "asm-printer"
37 #define GET_INSTRUCTION_NAME
38 #define PRINT_ALIAS_INSTR
39 #include "AArch64GenAsmWriter.inc"
40 #define GET_INSTRUCTION_NAME
41 #define PRINT_ALIAS_INSTR
42 #include "AArch64GenAsmWriter1.inc"
55 if (Opt ==
"no-aliases") {
72 unsigned Opcode =
MI->getOpcode();
74 if (Opcode == AArch64::SYSxt)
81 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
82 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
88 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
89 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
91 const char *AsmMnemonic =
nullptr;
100 AsmMnemonic =
"uxtb";
104 AsmMnemonic =
"sxth";
106 AsmMnemonic =
"uxth";
110 if (Is64Bit && IsSigned)
111 AsmMnemonic =
"sxtw";
127 const char *AsmMnemonic =
nullptr;
129 int64_t immr = Op2.
getImm();
130 int64_t imms = Op3.
getImm();
131 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
134 }
else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
135 ((imms + 1 == immr))) {
138 }
else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
141 }
else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
144 }
else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
147 }
else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
161 O <<
'\t' << (IsSigned ?
"sbfiz" :
"ubfiz") <<
'\t'
163 <<
", #" << (Is64Bit ? 64 : 32) - Op2.
getImm() <<
", #" << Op3.
getImm() + 1;
169 O <<
'\t' << (IsSigned ?
"sbfx" :
"ubfx") <<
'\t'
176 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
179 int ImmR =
MI->getOperand(3).getImm();
180 int ImmS =
MI->getOperand(4).getImm();
182 if ((Op2.
getReg() == AArch64::WZR || Op2.
getReg() == AArch64::XZR) &&
183 (ImmR == 0 || ImmS < ImmR) &&
186 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
188 int Width = ImmS + 1;
191 <<
", #" << LSB <<
", #" <<
Width;
194 }
else if (ImmS < ImmR) {
196 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
198 int Width = ImmS + 1;
207 int Width = ImmS - ImmR + 1;
211 <<
", #" << LSB <<
", #" <<
Width;
219 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
220 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
221 MI->getOperand(1).isExpr()) {
222 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
232 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
233 MI->getOperand(2).isExpr()) {
244 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
245 MI->getOperand(1).isImm() &&
MI->getOperand(2).isImm()) {
246 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
247 int Shift =
MI->getOperand(2).getImm();
251 Opcode == AArch64::MOVZXi ? 64 : 32)) {
258 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
259 MI->getOperand(1).isImm() &&
MI->getOperand(2).isImm()) {
260 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
261 int Shift =
MI->getOperand(2).getImm();
273 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
274 (
MI->getOperand(1).getReg() == AArch64::XZR ||
275 MI->getOperand(1).getReg() == AArch64::WZR) &&
276 MI->getOperand(2).isImm()) {
277 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
279 MI->getOperand(2).getImm(), RegWidth);
287 if (Opcode == AArch64::CompilerBarrier) {
293 if (Opcode == AArch64::SPACE) {
295 <<
MI->getOperand(1).getImm();
302 if (Opcode == AArch64::TSB) {
313 (
MI->getOperand(0).getReg() == AArch64::XZR ||
314 MI->getOperand(0).getReg() == AArch64::WZR)) {
322 case AArch64::TBXv8i8One:
323 case AArch64::TBXv8i8Two:
324 case AArch64::TBXv8i8Three:
325 case AArch64::TBXv8i8Four:
329 case AArch64::TBLv8i8One:
330 case AArch64::TBLv8i8Two:
331 case AArch64::TBLv8i8Three:
332 case AArch64::TBLv8i8Four:
336 case AArch64::TBXv16i8One:
337 case AArch64::TBXv16i8Two:
338 case AArch64::TBXv16i8Three:
339 case AArch64::TBXv16i8Four:
343 case AArch64::TBLv16i8One:
344 case AArch64::TBLv16i8Two:
345 case AArch64::TBLv16i8Three:
346 case AArch64::TBLv16i8Four:
365 { AArch64::LD1i8,
"ld1",
".b", 1,
true, 0 },
366 { AArch64::LD1i16,
"ld1",
".h", 1,
true, 0 },
367 { AArch64::LD1i32,
"ld1",
".s", 1,
true, 0 },
368 { AArch64::LD1i64,
"ld1",
".d", 1,
true, 0 },
369 { AArch64::LD1i8_POST,
"ld1",
".b", 2,
true, 1 },
370 { AArch64::LD1i16_POST,
"ld1",
".h", 2,
true, 2 },
371 { AArch64::LD1i32_POST,
"ld1",
".s", 2,
true, 4 },
372 { AArch64::LD1i64_POST,
"ld1",
".d", 2,
true, 8 },
373 { AArch64::LD1Rv16b,
"ld1r",
".16b", 0,
false, 0 },
374 { AArch64::LD1Rv8h,
"ld1r",
".8h", 0,
false, 0 },
375 { AArch64::LD1Rv4s,
"ld1r",
".4s", 0,
false, 0 },
376 { AArch64::LD1Rv2d,
"ld1r",
".2d", 0,
false, 0 },
377 { AArch64::LD1Rv8b,
"ld1r",
".8b", 0,
false, 0 },
378 { AArch64::LD1Rv4h,
"ld1r",
".4h", 0,
false, 0 },
379 { AArch64::LD1Rv2s,
"ld1r",
".2s", 0,
false, 0 },
380 { AArch64::LD1Rv1d,
"ld1r",
".1d", 0,
false, 0 },
381 { AArch64::LD1Rv16b_POST,
"ld1r",
".16b", 1,
false, 1 },
382 { AArch64::LD1Rv8h_POST,
"ld1r",
".8h", 1,
false, 2 },
383 { AArch64::LD1Rv4s_POST,
"ld1r",
".4s", 1,
false, 4 },
384 { AArch64::LD1Rv2d_POST,
"ld1r",
".2d", 1,
false, 8 },
385 { AArch64::LD1Rv8b_POST,
"ld1r",
".8b", 1,
false, 1 },
386 { AArch64::LD1Rv4h_POST,
"ld1r",
".4h", 1,
false, 2 },
387 { AArch64::LD1Rv2s_POST,
"ld1r",
".2s", 1,
false, 4 },
388 { AArch64::LD1Rv1d_POST,
"ld1r",
".1d", 1,
false, 8 },
389 { AArch64::LD1Onev16b,
"ld1",
".16b", 0,
false, 0 },
390 { AArch64::LD1Onev8h,
"ld1",
".8h", 0,
false, 0 },
391 { AArch64::LD1Onev4s,
"ld1",
".4s", 0,
false, 0 },
392 { AArch64::LD1Onev2d,
"ld1",
".2d", 0,
false, 0 },
393 { AArch64::LD1Onev8b,
"ld1",
".8b", 0,
false, 0 },
394 { AArch64::LD1Onev4h,
"ld1",
".4h", 0,
false, 0 },
395 { AArch64::LD1Onev2s,
"ld1",
".2s", 0,
false, 0 },
396 { AArch64::LD1Onev1d,
"ld1",
".1d", 0,
false, 0 },
397 { AArch64::LD1Onev16b_POST,
"ld1",
".16b", 1,
false, 16 },
398 { AArch64::LD1Onev8h_POST,
"ld1",
".8h", 1,
false, 16 },
399 { AArch64::LD1Onev4s_POST,
"ld1",
".4s", 1,
false, 16 },
400 { AArch64::LD1Onev2d_POST,
"ld1",
".2d", 1,
false, 16 },
401 { AArch64::LD1Onev8b_POST,
"ld1",
".8b", 1,
false, 8 },
402 { AArch64::LD1Onev4h_POST,
"ld1",
".4h", 1,
false, 8 },
403 { AArch64::LD1Onev2s_POST,
"ld1",
".2s", 1,
false, 8 },
404 { AArch64::LD1Onev1d_POST,
"ld1",
".1d", 1,
false, 8 },
405 { AArch64::LD1Twov16b,
"ld1",
".16b", 0,
false, 0 },
406 { AArch64::LD1Twov8h,
"ld1",
".8h", 0,
false, 0 },
407 { AArch64::LD1Twov4s,
"ld1",
".4s", 0,
false, 0 },
408 { AArch64::LD1Twov2d,
"ld1",
".2d", 0,
false, 0 },
409 { AArch64::LD1Twov8b,
"ld1",
".8b", 0,
false, 0 },
410 { AArch64::LD1Twov4h,
"ld1",
".4h", 0,
false, 0 },
411 { AArch64::LD1Twov2s,
"ld1",
".2s", 0,
false, 0 },
412 { AArch64::LD1Twov1d,
"ld1",
".1d", 0,
false, 0 },
413 { AArch64::LD1Twov16b_POST,
"ld1",
".16b", 1,
false, 32 },
414 { AArch64::LD1Twov8h_POST,
"ld1",
".8h", 1,
false, 32 },
415 { AArch64::LD1Twov4s_POST,
"ld1",
".4s", 1,
false, 32 },
416 { AArch64::LD1Twov2d_POST,
"ld1",
".2d", 1,
false, 32 },
417 { AArch64::LD1Twov8b_POST,
"ld1",
".8b", 1,
false, 16 },
418 { AArch64::LD1Twov4h_POST,
"ld1",
".4h", 1,
false, 16 },
419 { AArch64::LD1Twov2s_POST,
"ld1",
".2s", 1,
false, 16 },
420 { AArch64::LD1Twov1d_POST,
"ld1",
".1d", 1,
false, 16 },
421 { AArch64::LD1Threev16b,
"ld1",
".16b", 0,
false, 0 },
422 { AArch64::LD1Threev8h,
"ld1",
".8h", 0,
false, 0 },
423 { AArch64::LD1Threev4s,
"ld1",
".4s", 0,
false, 0 },
424 { AArch64::LD1Threev2d,
"ld1",
".2d", 0,
false, 0 },
425 { AArch64::LD1Threev8b,
"ld1",
".8b", 0,
false, 0 },
426 { AArch64::LD1Threev4h,
"ld1",
".4h", 0,
false, 0 },
427 { AArch64::LD1Threev2s,
"ld1",
".2s", 0,
false, 0 },
428 { AArch64::LD1Threev1d,
"ld1",
".1d", 0,
false, 0 },
429 { AArch64::LD1Threev16b_POST,
"ld1",
".16b", 1,
false, 48 },
430 { AArch64::LD1Threev8h_POST,
"ld1",
".8h", 1,
false, 48 },
431 { AArch64::LD1Threev4s_POST,
"ld1",
".4s", 1,
false, 48 },
432 { AArch64::LD1Threev2d_POST,
"ld1",
".2d", 1,
false, 48 },
433 { AArch64::LD1Threev8b_POST,
"ld1",
".8b", 1,
false, 24 },
434 { AArch64::LD1Threev4h_POST,
"ld1",
".4h", 1,
false, 24 },
435 { AArch64::LD1Threev2s_POST,
"ld1",
".2s", 1,
false, 24 },
436 { AArch64::LD1Threev1d_POST,
"ld1",
".1d", 1,
false, 24 },
437 { AArch64::LD1Fourv16b,
"ld1",
".16b", 0,
false, 0 },
438 { AArch64::LD1Fourv8h,
"ld1",
".8h", 0,
false, 0 },
439 { AArch64::LD1Fourv4s,
"ld1",
".4s", 0,
false, 0 },
440 { AArch64::LD1Fourv2d,
"ld1",
".2d", 0,
false, 0 },
441 { AArch64::LD1Fourv8b,
"ld1",
".8b", 0,
false, 0 },
442 { AArch64::LD1Fourv4h,
"ld1",
".4h", 0,
false, 0 },
443 { AArch64::LD1Fourv2s,
"ld1",
".2s", 0,
false, 0 },
444 { AArch64::LD1Fourv1d,
"ld1",
".1d", 0,
false, 0 },
445 { AArch64::LD1Fourv16b_POST,
"ld1",
".16b", 1,
false, 64 },
446 { AArch64::LD1Fourv8h_POST,
"ld1",
".8h", 1,
false, 64 },
447 { AArch64::LD1Fourv4s_POST,
"ld1",
".4s", 1,
false, 64 },
448 { AArch64::LD1Fourv2d_POST,
"ld1",
".2d", 1,
false, 64 },
449 { AArch64::LD1Fourv8b_POST,
"ld1",
".8b", 1,
false, 32 },
450 { AArch64::LD1Fourv4h_POST,
"ld1",
".4h", 1,
false, 32 },
451 { AArch64::LD1Fourv2s_POST,
"ld1",
".2s", 1,
false, 32 },
452 { AArch64::LD1Fourv1d_POST,
"ld1",
".1d", 1,
false, 32 },
453 { AArch64::LD2i8,
"ld2",
".b", 1,
true, 0 },
454 { AArch64::LD2i16,
"ld2",
".h", 1,
true, 0 },
455 { AArch64::LD2i32,
"ld2",
".s", 1,
true, 0 },
456 { AArch64::LD2i64,
"ld2",
".d", 1,
true, 0 },
457 { AArch64::LD2i8_POST,
"ld2",
".b", 2,
true, 2 },
458 { AArch64::LD2i16_POST,
"ld2",
".h", 2,
true, 4 },
459 { AArch64::LD2i32_POST,
"ld2",
".s", 2,
true, 8 },
460 { AArch64::LD2i64_POST,
"ld2",
".d", 2,
true, 16 },
461 { AArch64::LD2Rv16b,
"ld2r",
".16b", 0,
false, 0 },
462 { AArch64::LD2Rv8h,
"ld2r",
".8h", 0,
false, 0 },
463 { AArch64::LD2Rv4s,
"ld2r",
".4s", 0,
false, 0 },
464 { AArch64::LD2Rv2d,
"ld2r",
".2d", 0,
false, 0 },
465 { AArch64::LD2Rv8b,
"ld2r",
".8b", 0,
false, 0 },
466 { AArch64::LD2Rv4h,
"ld2r",
".4h", 0,
false, 0 },
467 { AArch64::LD2Rv2s,
"ld2r",
".2s", 0,
false, 0 },
468 { AArch64::LD2Rv1d,
"ld2r",
".1d", 0,
false, 0 },
469 { AArch64::LD2Rv16b_POST,
"ld2r",
".16b", 1,
false, 2 },
470 { AArch64::LD2Rv8h_POST,
"ld2r",
".8h", 1,
false, 4 },
471 { AArch64::LD2Rv4s_POST,
"ld2r",
".4s", 1,
false, 8 },
472 { AArch64::LD2Rv2d_POST,
"ld2r",
".2d", 1,
false, 16 },
473 { AArch64::LD2Rv8b_POST,
"ld2r",
".8b", 1,
false, 2 },
474 { AArch64::LD2Rv4h_POST,
"ld2r",
".4h", 1,
false, 4 },
475 { AArch64::LD2Rv2s_POST,
"ld2r",
".2s", 1,
false, 8 },
476 { AArch64::LD2Rv1d_POST,
"ld2r",
".1d", 1,
false, 16 },
477 { AArch64::LD2Twov16b,
"ld2",
".16b", 0,
false, 0 },
478 { AArch64::LD2Twov8h,
"ld2",
".8h", 0,
false, 0 },
479 { AArch64::LD2Twov4s,
"ld2",
".4s", 0,
false, 0 },
480 { AArch64::LD2Twov2d,
"ld2",
".2d", 0,
false, 0 },
481 { AArch64::LD2Twov8b,
"ld2",
".8b", 0,
false, 0 },
482 { AArch64::LD2Twov4h,
"ld2",
".4h", 0,
false, 0 },
483 { AArch64::LD2Twov2s,
"ld2",
".2s", 0,
false, 0 },
484 { AArch64::LD2Twov16b_POST,
"ld2",
".16b", 1,
false, 32 },
485 { AArch64::LD2Twov8h_POST,
"ld2",
".8h", 1,
false, 32 },
486 { AArch64::LD2Twov4s_POST,
"ld2",
".4s", 1,
false, 32 },
487 { AArch64::LD2Twov2d_POST,
"ld2",
".2d", 1,
false, 32 },
488 { AArch64::LD2Twov8b_POST,
"ld2",
".8b", 1,
false, 16 },
489 { AArch64::LD2Twov4h_POST,
"ld2",
".4h", 1,
false, 16 },
490 { AArch64::LD2Twov2s_POST,
"ld2",
".2s", 1,
false, 16 },
491 { AArch64::LD3i8,
"ld3",
".b", 1,
true, 0 },
492 { AArch64::LD3i16,
"ld3",
".h", 1,
true, 0 },
493 { AArch64::LD3i32,
"ld3",
".s", 1,
true, 0 },
494 { AArch64::LD3i64,
"ld3",
".d", 1,
true, 0 },
495 { AArch64::LD3i8_POST,
"ld3",
".b", 2,
true, 3 },
496 { AArch64::LD3i16_POST,
"ld3",
".h", 2,
true, 6 },
497 { AArch64::LD3i32_POST,
"ld3",
".s", 2,
true, 12 },
498 { AArch64::LD3i64_POST,
"ld3",
".d", 2,
true, 24 },
499 { AArch64::LD3Rv16b,
"ld3r",
".16b", 0,
false, 0 },
500 { AArch64::LD3Rv8h,
"ld3r",
".8h", 0,
false, 0 },
501 { AArch64::LD3Rv4s,
"ld3r",
".4s", 0,
false, 0 },
502 { AArch64::LD3Rv2d,
"ld3r",
".2d", 0,
false, 0 },
503 { AArch64::LD3Rv8b,
"ld3r",
".8b", 0,
false, 0 },
504 { AArch64::LD3Rv4h,
"ld3r",
".4h", 0,
false, 0 },
505 { AArch64::LD3Rv2s,
"ld3r",
".2s", 0,
false, 0 },
506 { AArch64::LD3Rv1d,
"ld3r",
".1d", 0,
false, 0 },
507 { AArch64::LD3Rv16b_POST,
"ld3r",
".16b", 1,
false, 3 },
508 { AArch64::LD3Rv8h_POST,
"ld3r",
".8h", 1,
false, 6 },
509 { AArch64::LD3Rv4s_POST,
"ld3r",
".4s", 1,
false, 12 },
510 { AArch64::LD3Rv2d_POST,
"ld3r",
".2d", 1,
false, 24 },
511 { AArch64::LD3Rv8b_POST,
"ld3r",
".8b", 1,
false, 3 },
512 { AArch64::LD3Rv4h_POST,
"ld3r",
".4h", 1,
false, 6 },
513 { AArch64::LD3Rv2s_POST,
"ld3r",
".2s", 1,
false, 12 },
514 { AArch64::LD3Rv1d_POST,
"ld3r",
".1d", 1,
false, 24 },
515 { AArch64::LD3Threev16b,
"ld3",
".16b", 0,
false, 0 },
516 { AArch64::LD3Threev8h,
"ld3",
".8h", 0,
false, 0 },
517 { AArch64::LD3Threev4s,
"ld3",
".4s", 0,
false, 0 },
518 { AArch64::LD3Threev2d,
"ld3",
".2d", 0,
false, 0 },
519 { AArch64::LD3Threev8b,
"ld3",
".8b", 0,
false, 0 },
520 { AArch64::LD3Threev4h,
"ld3",
".4h", 0,
false, 0 },
521 { AArch64::LD3Threev2s,
"ld3",
".2s", 0,
false, 0 },
522 { AArch64::LD3Threev16b_POST,
"ld3",
".16b", 1,
false, 48 },
523 { AArch64::LD3Threev8h_POST,
"ld3",
".8h", 1,
false, 48 },
524 { AArch64::LD3Threev4s_POST,
"ld3",
".4s", 1,
false, 48 },
525 { AArch64::LD3Threev2d_POST,
"ld3",
".2d", 1,
false, 48 },
526 { AArch64::LD3Threev8b_POST,
"ld3",
".8b", 1,
false, 24 },
527 { AArch64::LD3Threev4h_POST,
"ld3",
".4h", 1,
false, 24 },
528 { AArch64::LD3Threev2s_POST,
"ld3",
".2s", 1,
false, 24 },
529 { AArch64::LD4i8,
"ld4",
".b", 1,
true, 0 },
530 { AArch64::LD4i16,
"ld4",
".h", 1,
true, 0 },
531 { AArch64::LD4i32,
"ld4",
".s", 1,
true, 0 },
532 { AArch64::LD4i64,
"ld4",
".d", 1,
true, 0 },
533 { AArch64::LD4i8_POST,
"ld4",
".b", 2,
true, 4 },
534 { AArch64::LD4i16_POST,
"ld4",
".h", 2,
true, 8 },
535 { AArch64::LD4i32_POST,
"ld4",
".s", 2,
true, 16 },
536 { AArch64::LD4i64_POST,
"ld4",
".d", 2,
true, 32 },
537 { AArch64::LD4Rv16b,
"ld4r",
".16b", 0,
false, 0 },
538 { AArch64::LD4Rv8h,
"ld4r",
".8h", 0,
false, 0 },
539 { AArch64::LD4Rv4s,
"ld4r",
".4s", 0,
false, 0 },
540 { AArch64::LD4Rv2d,
"ld4r",
".2d", 0,
false, 0 },
541 { AArch64::LD4Rv8b,
"ld4r",
".8b", 0,
false, 0 },
542 { AArch64::LD4Rv4h,
"ld4r",
".4h", 0,
false, 0 },
543 { AArch64::LD4Rv2s,
"ld4r",
".2s", 0,
false, 0 },
544 { AArch64::LD4Rv1d,
"ld4r",
".1d", 0,
false, 0 },
545 { AArch64::LD4Rv16b_POST,
"ld4r",
".16b", 1,
false, 4 },
546 { AArch64::LD4Rv8h_POST,
"ld4r",
".8h", 1,
false, 8 },
547 { AArch64::LD4Rv4s_POST,
"ld4r",
".4s", 1,
false, 16 },
548 { AArch64::LD4Rv2d_POST,
"ld4r",
".2d", 1,
false, 32 },
549 { AArch64::LD4Rv8b_POST,
"ld4r",
".8b", 1,
false, 4 },
550 { AArch64::LD4Rv4h_POST,
"ld4r",
".4h", 1,
false, 8 },
551 { AArch64::LD4Rv2s_POST,
"ld4r",
".2s", 1,
false, 16 },
552 { AArch64::LD4Rv1d_POST,
"ld4r",
".1d", 1,
false, 32 },
553 { AArch64::LD4Fourv16b,
"ld4",
".16b", 0,
false, 0 },
554 { AArch64::LD4Fourv8h,
"ld4",
".8h", 0,
false, 0 },
555 { AArch64::LD4Fourv4s,
"ld4",
".4s", 0,
false, 0 },
556 { AArch64::LD4Fourv2d,
"ld4",
".2d", 0,
false, 0 },
557 { AArch64::LD4Fourv8b,
"ld4",
".8b", 0,
false, 0 },
558 { AArch64::LD4Fourv4h,
"ld4",
".4h", 0,
false, 0 },
559 { AArch64::LD4Fourv2s,
"ld4",
".2s", 0,
false, 0 },
560 { AArch64::LD4Fourv16b_POST,
"ld4",
".16b", 1,
false, 64 },
561 { AArch64::LD4Fourv8h_POST,
"ld4",
".8h", 1,
false, 64 },
562 { AArch64::LD4Fourv4s_POST,
"ld4",
".4s", 1,
false, 64 },
563 { AArch64::LD4Fourv2d_POST,
"ld4",
".2d", 1,
false, 64 },
564 { AArch64::LD4Fourv8b_POST,
"ld4",
".8b", 1,
false, 32 },
565 { AArch64::LD4Fourv4h_POST,
"ld4",
".4h", 1,
false, 32 },
566 { AArch64::LD4Fourv2s_POST,
"ld4",
".2s", 1,
false, 32 },
567 { AArch64::ST1i8,
"st1",
".b", 0,
true, 0 },
568 { AArch64::ST1i16,
"st1",
".h", 0,
true, 0 },
569 { AArch64::ST1i32,
"st1",
".s", 0,
true, 0 },
570 { AArch64::ST1i64,
"st1",
".d", 0,
true, 0 },
571 { AArch64::ST1i8_POST,
"st1",
".b", 1,
true, 1 },
572 { AArch64::ST1i16_POST,
"st1",
".h", 1,
true, 2 },
573 { AArch64::ST1i32_POST,
"st1",
".s", 1,
true, 4 },
574 { AArch64::ST1i64_POST,
"st1",
".d", 1,
true, 8 },
575 { AArch64::ST1Onev16b,
"st1",
".16b", 0,
false, 0 },
576 { AArch64::ST1Onev8h,
"st1",
".8h", 0,
false, 0 },
577 { AArch64::ST1Onev4s,
"st1",
".4s", 0,
false, 0 },
578 { AArch64::ST1Onev2d,
"st1",
".2d", 0,
false, 0 },
579 { AArch64::ST1Onev8b,
"st1",
".8b", 0,
false, 0 },
580 { AArch64::ST1Onev4h,
"st1",
".4h", 0,
false, 0 },
581 { AArch64::ST1Onev2s,
"st1",
".2s", 0,
false, 0 },
582 { AArch64::ST1Onev1d,
"st1",
".1d", 0,
false, 0 },
583 { AArch64::ST1Onev16b_POST,
"st1",
".16b", 1,
false, 16 },
584 { AArch64::ST1Onev8h_POST,
"st1",
".8h", 1,
false, 16 },
585 { AArch64::ST1Onev4s_POST,
"st1",
".4s", 1,
false, 16 },
586 { AArch64::ST1Onev2d_POST,
"st1",
".2d", 1,
false, 16 },
587 { AArch64::ST1Onev8b_POST,
"st1",
".8b", 1,
false, 8 },
588 { AArch64::ST1Onev4h_POST,
"st1",
".4h", 1,
false, 8 },
589 { AArch64::ST1Onev2s_POST,
"st1",
".2s", 1,
false, 8 },
590 { AArch64::ST1Onev1d_POST,
"st1",
".1d", 1,
false, 8 },
591 { AArch64::ST1Twov16b,
"st1",
".16b", 0,
false, 0 },
592 { AArch64::ST1Twov8h,
"st1",
".8h", 0,
false, 0 },
593 { AArch64::ST1Twov4s,
"st1",
".4s", 0,
false, 0 },
594 { AArch64::ST1Twov2d,
"st1",
".2d", 0,
false, 0 },
595 { AArch64::ST1Twov8b,
"st1",
".8b", 0,
false, 0 },
596 { AArch64::ST1Twov4h,
"st1",
".4h", 0,
false, 0 },
597 { AArch64::ST1Twov2s,
"st1",
".2s", 0,
false, 0 },
598 { AArch64::ST1Twov1d,
"st1",
".1d", 0,
false, 0 },
599 { AArch64::ST1Twov16b_POST,
"st1",
".16b", 1,
false, 32 },
600 { AArch64::ST1Twov8h_POST,
"st1",
".8h", 1,
false, 32 },
601 { AArch64::ST1Twov4s_POST,
"st1",
".4s", 1,
false, 32 },
602 { AArch64::ST1Twov2d_POST,
"st1",
".2d", 1,
false, 32 },
603 { AArch64::ST1Twov8b_POST,
"st1",
".8b", 1,
false, 16 },
604 { AArch64::ST1Twov4h_POST,
"st1",
".4h", 1,
false, 16 },
605 { AArch64::ST1Twov2s_POST,
"st1",
".2s", 1,
false, 16 },
606 { AArch64::ST1Twov1d_POST,
"st1",
".1d", 1,
false, 16 },
607 { AArch64::ST1Threev16b,
"st1",
".16b", 0,
false, 0 },
608 { AArch64::ST1Threev8h,
"st1",
".8h", 0,
false, 0 },
609 { AArch64::ST1Threev4s,
"st1",
".4s", 0,
false, 0 },
610 { AArch64::ST1Threev2d,
"st1",
".2d", 0,
false, 0 },
611 { AArch64::ST1Threev8b,
"st1",
".8b", 0,
false, 0 },
612 { AArch64::ST1Threev4h,
"st1",
".4h", 0,
false, 0 },
613 { AArch64::ST1Threev2s,
"st1",
".2s", 0,
false, 0 },
614 { AArch64::ST1Threev1d,
"st1",
".1d", 0,
false, 0 },
615 { AArch64::ST1Threev16b_POST,
"st1",
".16b", 1,
false, 48 },
616 { AArch64::ST1Threev8h_POST,
"st1",
".8h", 1,
false, 48 },
617 { AArch64::ST1Threev4s_POST,
"st1",
".4s", 1,
false, 48 },
618 { AArch64::ST1Threev2d_POST,
"st1",
".2d", 1,
false, 48 },
619 { AArch64::ST1Threev8b_POST,
"st1",
".8b", 1,
false, 24 },
620 { AArch64::ST1Threev4h_POST,
"st1",
".4h", 1,
false, 24 },
621 { AArch64::ST1Threev2s_POST,
"st1",
".2s", 1,
false, 24 },
622 { AArch64::ST1Threev1d_POST,
"st1",
".1d", 1,
false, 24 },
623 { AArch64::ST1Fourv16b,
"st1",
".16b", 0,
false, 0 },
624 { AArch64::ST1Fourv8h,
"st1",
".8h", 0,
false, 0 },
625 { AArch64::ST1Fourv4s,
"st1",
".4s", 0,
false, 0 },
626 { AArch64::ST1Fourv2d,
"st1",
".2d", 0,
false, 0 },
627 { AArch64::ST1Fourv8b,
"st1",
".8b", 0,
false, 0 },
628 { AArch64::ST1Fourv4h,
"st1",
".4h", 0,
false, 0 },
629 { AArch64::ST1Fourv2s,
"st1",
".2s", 0,
false, 0 },
630 { AArch64::ST1Fourv1d,
"st1",
".1d", 0,
false, 0 },
631 { AArch64::ST1Fourv16b_POST,
"st1",
".16b", 1,
false, 64 },
632 { AArch64::ST1Fourv8h_POST,
"st1",
".8h", 1,
false, 64 },
633 { AArch64::ST1Fourv4s_POST,
"st1",
".4s", 1,
false, 64 },
634 { AArch64::ST1Fourv2d_POST,
"st1",
".2d", 1,
false, 64 },
635 { AArch64::ST1Fourv8b_POST,
"st1",
".8b", 1,
false, 32 },
636 { AArch64::ST1Fourv4h_POST,
"st1",
".4h", 1,
false, 32 },
637 { AArch64::ST1Fourv2s_POST,
"st1",
".2s", 1,
false, 32 },
638 { AArch64::ST1Fourv1d_POST,
"st1",
".1d", 1,
false, 32 },
639 { AArch64::ST2i8,
"st2",
".b", 0,
true, 0 },
640 { AArch64::ST2i16,
"st2",
".h", 0,
true, 0 },
641 { AArch64::ST2i32,
"st2",
".s", 0,
true, 0 },
642 { AArch64::ST2i64,
"st2",
".d", 0,
true, 0 },
643 { AArch64::ST2i8_POST,
"st2",
".b", 1,
true, 2 },
644 { AArch64::ST2i16_POST,
"st2",
".h", 1,
true, 4 },
645 { AArch64::ST2i32_POST,
"st2",
".s", 1,
true, 8 },
646 { AArch64::ST2i64_POST,
"st2",
".d", 1,
true, 16 },
647 { AArch64::ST2Twov16b,
"st2",
".16b", 0,
false, 0 },
648 { AArch64::ST2Twov8h,
"st2",
".8h", 0,
false, 0 },
649 { AArch64::ST2Twov4s,
"st2",
".4s", 0,
false, 0 },
650 { AArch64::ST2Twov2d,
"st2",
".2d", 0,
false, 0 },
651 { AArch64::ST2Twov8b,
"st2",
".8b", 0,
false, 0 },
652 { AArch64::ST2Twov4h,
"st2",
".4h", 0,
false, 0 },
653 { AArch64::ST2Twov2s,
"st2",
".2s", 0,
false, 0 },
654 { AArch64::ST2Twov16b_POST,
"st2",
".16b", 1,
false, 32 },
655 { AArch64::ST2Twov8h_POST,
"st2",
".8h", 1,
false, 32 },
656 { AArch64::ST2Twov4s_POST,
"st2",
".4s", 1,
false, 32 },
657 { AArch64::ST2Twov2d_POST,
"st2",
".2d", 1,
false, 32 },
658 { AArch64::ST2Twov8b_POST,
"st2",
".8b", 1,
false, 16 },
659 { AArch64::ST2Twov4h_POST,
"st2",
".4h", 1,
false, 16 },
660 { AArch64::ST2Twov2s_POST,
"st2",
".2s", 1,
false, 16 },
661 { AArch64::ST3i8,
"st3",
".b", 0,
true, 0 },
662 { AArch64::ST3i16,
"st3",
".h", 0,
true, 0 },
663 { AArch64::ST3i32,
"st3",
".s", 0,
true, 0 },
664 { AArch64::ST3i64,
"st3",
".d", 0,
true, 0 },
665 { AArch64::ST3i8_POST,
"st3",
".b", 1,
true, 3 },
666 { AArch64::ST3i16_POST,
"st3",
".h", 1,
true, 6 },
667 { AArch64::ST3i32_POST,
"st3",
".s", 1,
true, 12 },
668 { AArch64::ST3i64_POST,
"st3",
".d", 1,
true, 24 },
669 { AArch64::ST3Threev16b,
"st3",
".16b", 0,
false, 0 },
670 { AArch64::ST3Threev8h,
"st3",
".8h", 0,
false, 0 },
671 { AArch64::ST3Threev4s,
"st3",
".4s", 0,
false, 0 },
672 { AArch64::ST3Threev2d,
"st3",
".2d", 0,
false, 0 },
673 { AArch64::ST3Threev8b,
"st3",
".8b", 0,
false, 0 },
674 { AArch64::ST3Threev4h,
"st3",
".4h", 0,
false, 0 },
675 { AArch64::ST3Threev2s,
"st3",
".2s", 0,
false, 0 },
676 { AArch64::ST3Threev16b_POST,
"st3",
".16b", 1,
false, 48 },
677 { AArch64::ST3Threev8h_POST,
"st3",
".8h", 1,
false, 48 },
678 { AArch64::ST3Threev4s_POST,
"st3",
".4s", 1,
false, 48 },
679 { AArch64::ST3Threev2d_POST,
"st3",
".2d", 1,
false, 48 },
680 { AArch64::ST3Threev8b_POST,
"st3",
".8b", 1,
false, 24 },
681 { AArch64::ST3Threev4h_POST,
"st3",
".4h", 1,
false, 24 },
682 { AArch64::ST3Threev2s_POST,
"st3",
".2s", 1,
false, 24 },
683 { AArch64::ST4i8,
"st4",
".b", 0,
true, 0 },
684 { AArch64::ST4i16,
"st4",
".h", 0,
true, 0 },
685 { AArch64::ST4i32,
"st4",
".s", 0,
true, 0 },
686 { AArch64::ST4i64,
"st4",
".d", 0,
true, 0 },
687 { AArch64::ST4i8_POST,
"st4",
".b", 1,
true, 4 },
688 { AArch64::ST4i16_POST,
"st4",
".h", 1,
true, 8 },
689 { AArch64::ST4i32_POST,
"st4",
".s", 1,
true, 16 },
690 { AArch64::ST4i64_POST,
"st4",
".d", 1,
true, 32 },
691 { AArch64::ST4Fourv16b,
"st4",
".16b", 0,
false, 0 },
692 { AArch64::ST4Fourv8h,
"st4",
".8h", 0,
false, 0 },
693 { AArch64::ST4Fourv4s,
"st4",
".4s", 0,
false, 0 },
694 { AArch64::ST4Fourv2d,
"st4",
".2d", 0,
false, 0 },
695 { AArch64::ST4Fourv8b,
"st4",
".8b", 0,
false, 0 },
696 { AArch64::ST4Fourv4h,
"st4",
".4h", 0,
false, 0 },
697 { AArch64::ST4Fourv2s,
"st4",
".2s", 0,
false, 0 },
698 { AArch64::ST4Fourv16b_POST,
"st4",
".16b", 1,
false, 64 },
699 { AArch64::ST4Fourv8h_POST,
"st4",
".8h", 1,
false, 64 },
700 { AArch64::ST4Fourv4s_POST,
"st4",
".4s", 1,
false, 64 },
701 { AArch64::ST4Fourv2d_POST,
"st4",
".2d", 1,
false, 64 },
702 { AArch64::ST4Fourv8b_POST,
"st4",
".8b", 1,
false, 32 },
703 { AArch64::ST4Fourv4h_POST,
"st4",
".4h", 1,
false, 32 },
704 { AArch64::ST4Fourv2s_POST,
"st4",
".2s", 1,
false, 32 },
720 unsigned Opcode =
MI->getOpcode();
725 O <<
"\t" << (IsTbx ?
"tbx" :
"tbl") << Layout <<
'\t'
728 unsigned ListOpNum = IsTbx ? 2 : 1;
738 O <<
"\t" << LdStDesc->Mnemonic << LdStDesc->Layout <<
'\t';
742 int OpNum = LdStDesc->ListOperand;
745 if (LdStDesc->HasLane)
746 O <<
'[' <<
MI->getOperand(OpNum++).getImm() <<
']';
749 unsigned AddrReg =
MI->getOperand(OpNum++).getReg();
753 if (LdStDesc->NaturalOffset != 0) {
754 unsigned Reg =
MI->getOperand(OpNum++).getReg();
755 if (
Reg != AArch64::XZR)
758 assert(LdStDesc->NaturalOffset &&
"no offset on post-inc instruction?");
759 O <<
", #" << LdStDesc->NaturalOffset;
774 unsigned Opcode =
MI->getOpcode();
775 assert(Opcode == AArch64::SYSxt &&
"Invalid opcode for SYS alias!");
783 unsigned Op1Val = Op1.
getImm();
784 unsigned CnVal = Cn.
getImm();
785 unsigned CmVal = Cm.
getImm();
786 unsigned Op2Val = Op2.
getImm();
789 Encoding |= CmVal << 3;
790 Encoding |= CnVal << 7;
791 Encoding |= Op1Val << 11;
799 default:
return false;
803 default:
return false;
804 case 0:
goto Search_IC;
805 case 3:
goto Search_PRCTX;
816 default:
return false;
817 case 4:
Ins =
"cfp\t";
break;
818 case 5:
Ins =
"dvp\t";
break;
819 case 7:
Ins =
"cpp\t";
break;
827 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
837 case 4:
case 6:
case 10:
case 11:
case 12:
case 13:
case 14:
845 Name = std::string(
DC->Name);
850 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
860 }
else if (CnVal == 8 || CnVal == 9) {
883 template <
int EltSize>
888 assert(RegOp.
isReg() &&
"Unexpected operand type!");
914 template <
bool IsVertical>
919 assert(RegOp.
isReg() &&
"Unexpected operand type!");
925 O <<
Base << (IsVertical ?
"v" :
"h") <<
'.' << Suffix;
932 assert(RegOp.
isReg() &&
"Unexpected operand type!");
941 unsigned svcrop = MO.
getImm();
942 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
943 assert(SVCR &&
"Unexpected SVCR operand!");
952 unsigned Reg =
Op.getReg();
954 }
else if (
Op.isImm()) {
957 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
958 Op.getExpr()->print(
O, &
MAI);
993 unsigned Reg =
Op.getReg();
994 if (
Reg == AArch64::XZR)
1006 assert(
Op.isReg() &&
"Non-register vreg operand!");
1007 unsigned Reg =
Op.getReg();
1015 assert(
Op.isImm() &&
"System instruction C[nm] operands must be immediates!");
1016 O <<
"c" <<
Op.getImm();
1024 unsigned Val = (MO.
getImm() & 0xfff);
1025 assert(Val == MO.
getImm() &&
"Add/sub immediate out of range!");
1041 template <
typename T>
1045 uint64_t Val =
MI->getOperand(OpNum).getImm();
1053 unsigned Val =
MI->getOperand(OpNum).getImm();
1079 unsigned Val =
MI->getOperand(OpNum).getImm();
1087 unsigned Dest =
MI->getOperand(0).getReg();
1088 unsigned Src1 =
MI->getOperand(1).getReg();
1089 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1091 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1094 O <<
", lsl #" << ShiftVal;
1100 O <<
" #" << ShiftVal;
1104 unsigned Width,
char SrcRegKind,
1107 bool IsLSL = !SignExtend && SrcRegKind ==
'x';
1111 O << (SignExtend ?
's' :
'u') <<
"xt" << SrcRegKind;
1113 if (DoShift || IsLSL)
1120 bool SignExtend =
MI->getOperand(OpNum).getImm();
1121 bool DoShift =
MI->getOperand(OpNum + 1).getImm();
1125 template <
bool SignExtend,
int ExtW
idth,
char SrcRegKind,
char Suffix>
1131 if (Suffix ==
's' || Suffix ==
'd')
1134 assert(Suffix == 0 &&
"Unsupported suffix size");
1136 bool DoShift = ExtWidth != 8;
1137 if (SignExtend || DoShift || SrcRegKind ==
'w') {
1167 O <<
'#' <<
formatImm(Scale *
MI->getOperand(OpNum).getImm());
1195 template <
bool IsSVEPrefetch>
1199 unsigned prfop =
MI->getOperand(OpNum).getImm();
1200 if (IsSVEPrefetch) {
1201 if (
auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1205 }
else if (
auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
1216 unsigned psbhintop =
MI->getOperand(OpNum).getImm();
1217 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1227 unsigned btihintop =
MI->getOperand(OpNum).getImm() ^ 32;
1228 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1251 case AArch64::Q0:
Reg = AArch64::Q1;
break;
1252 case AArch64::Q1:
Reg = AArch64::Q2;
break;
1253 case AArch64::Q2:
Reg = AArch64::Q3;
break;
1254 case AArch64::Q3:
Reg = AArch64::Q4;
break;
1255 case AArch64::Q4:
Reg = AArch64::Q5;
break;
1256 case AArch64::Q5:
Reg = AArch64::Q6;
break;
1257 case AArch64::Q6:
Reg = AArch64::Q7;
break;
1258 case AArch64::Q7:
Reg = AArch64::Q8;
break;
1259 case AArch64::Q8:
Reg = AArch64::Q9;
break;
1260 case AArch64::Q9:
Reg = AArch64::Q10;
break;
1261 case AArch64::Q10:
Reg = AArch64::Q11;
break;
1262 case AArch64::Q11:
Reg = AArch64::Q12;
break;
1263 case AArch64::Q12:
Reg = AArch64::Q13;
break;
1264 case AArch64::Q13:
Reg = AArch64::Q14;
break;
1265 case AArch64::Q14:
Reg = AArch64::Q15;
break;
1266 case AArch64::Q15:
Reg = AArch64::Q16;
break;
1267 case AArch64::Q16:
Reg = AArch64::Q17;
break;
1268 case AArch64::Q17:
Reg = AArch64::Q18;
break;
1269 case AArch64::Q18:
Reg = AArch64::Q19;
break;
1270 case AArch64::Q19:
Reg = AArch64::Q20;
break;
1271 case AArch64::Q20:
Reg = AArch64::Q21;
break;
1272 case AArch64::Q21:
Reg = AArch64::Q22;
break;
1273 case AArch64::Q22:
Reg = AArch64::Q23;
break;
1274 case AArch64::Q23:
Reg = AArch64::Q24;
break;
1275 case AArch64::Q24:
Reg = AArch64::Q25;
break;
1276 case AArch64::Q25:
Reg = AArch64::Q26;
break;
1277 case AArch64::Q26:
Reg = AArch64::Q27;
break;
1278 case AArch64::Q27:
Reg = AArch64::Q28;
break;
1279 case AArch64::Q28:
Reg = AArch64::Q29;
break;
1280 case AArch64::Q29:
Reg = AArch64::Q30;
break;
1281 case AArch64::Q30:
Reg = AArch64::Q31;
break;
1286 case AArch64::Z0:
Reg = AArch64::Z1;
break;
1287 case AArch64::Z1:
Reg = AArch64::Z2;
break;
1288 case AArch64::Z2:
Reg = AArch64::Z3;
break;
1289 case AArch64::Z3:
Reg = AArch64::Z4;
break;
1290 case AArch64::Z4:
Reg = AArch64::Z5;
break;
1291 case AArch64::Z5:
Reg = AArch64::Z6;
break;
1292 case AArch64::Z6:
Reg = AArch64::Z7;
break;
1293 case AArch64::Z7:
Reg = AArch64::Z8;
break;
1294 case AArch64::Z8:
Reg = AArch64::Z9;
break;
1295 case AArch64::Z9:
Reg = AArch64::Z10;
break;
1296 case AArch64::Z10:
Reg = AArch64::Z11;
break;
1297 case AArch64::Z11:
Reg = AArch64::Z12;
break;
1298 case AArch64::Z12:
Reg = AArch64::Z13;
break;
1299 case AArch64::Z13:
Reg = AArch64::Z14;
break;
1300 case AArch64::Z14:
Reg = AArch64::Z15;
break;
1301 case AArch64::Z15:
Reg = AArch64::Z16;
break;
1302 case AArch64::Z16:
Reg = AArch64::Z17;
break;
1303 case AArch64::Z17:
Reg = AArch64::Z18;
break;
1304 case AArch64::Z18:
Reg = AArch64::Z19;
break;
1305 case AArch64::Z19:
Reg = AArch64::Z20;
break;
1306 case AArch64::Z20:
Reg = AArch64::Z21;
break;
1307 case AArch64::Z21:
Reg = AArch64::Z22;
break;
1308 case AArch64::Z22:
Reg = AArch64::Z23;
break;
1309 case AArch64::Z23:
Reg = AArch64::Z24;
break;
1310 case AArch64::Z24:
Reg = AArch64::Z25;
break;
1311 case AArch64::Z25:
Reg = AArch64::Z26;
break;
1312 case AArch64::Z26:
Reg = AArch64::Z27;
break;
1313 case AArch64::Z27:
Reg = AArch64::Z28;
break;
1314 case AArch64::Z28:
Reg = AArch64::Z29;
break;
1315 case AArch64::Z29:
Reg = AArch64::Z30;
break;
1316 case AArch64::Z30:
Reg = AArch64::Z31;
break;
1326 template<
unsigned size>
1331 static_assert(
size == 64 ||
size == 32,
1332 "Template parameter must be either 32 or 64");
1333 unsigned Reg =
MI->getOperand(OpNum).getReg();
1335 unsigned Sube = (
size == 32) ? AArch64::sube32 : AArch64::sube64;
1336 unsigned Subo = (
size == 32) ? AArch64::subo32 : AArch64::subo64;
1344 AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3,
1345 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7
1351 unsigned MaxRegs = 8;
1352 unsigned RegMask =
MI->getOperand(OpNum).getImm();
1354 unsigned NumRegs = 0;
1355 for (
unsigned I = 0;
I < MaxRegs; ++
I)
1356 if ((RegMask & (1 <<
I)) != 0)
1360 unsigned Printed = 0;
1361 for (
unsigned I = 0;
I < MaxRegs; ++
I) {
1362 unsigned Reg = RegMask & (1 <<
I);
1366 if (Printed + 1 != NumRegs)
1377 unsigned Reg =
MI->getOperand(OpNum).getReg();
1383 unsigned NumRegs = 1;
1419 if (
i + 1 != NumRegs)
1434 template <
unsigned NumLanes,
char LaneKind>
1438 std::string Suffix(
".");
1440 Suffix += itostr(NumLanes) + LaneKind;
1450 O <<
"[" <<
MI->getOperand(OpNum).getImm() <<
"]";
1456 O <<
MI->getOperand(OpNum).getImm();
1468 int64_t Offset =
Op.getImm() * 4;
1478 dyn_cast<MCConstantExpr>(
MI->getOperand(OpNum).getExpr());
1479 int64_t TargetAddress;
1497 const int64_t Offset =
Op.getImm() * 4096;
1512 unsigned Val =
MI->getOperand(OpNo).getImm();
1513 unsigned Opcode =
MI->getOpcode();
1516 if (Opcode == AArch64::ISB) {
1517 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1518 Name = ISB ? ISB->Name :
"";
1519 }
else if (Opcode == AArch64::TSB) {
1520 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1521 Name = TSB ? TSB->Name :
"";
1523 auto DB = AArch64DB::lookupDBByEncoding(Val);
1524 Name = DB ? DB->Name :
"";
1535 unsigned Val =
MI->getOperand(OpNo).getImm();
1536 assert(
MI->getOpcode() == AArch64::DSBnXS);
1539 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1540 Name = DB ? DB->Name :
"";
1550 return (
Reg && (Read ?
Reg->Readable :
Reg->Writeable) &&
1573 unsigned Val =
MI->getOperand(OpNo).getImm();
1578 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1579 O <<
"DBGDTRRX_EL0";
1584 if (Val == AArch64SysReg::TRCEXTINSELR) {
1585 O <<
"TRCEXTINSELR";
1600 unsigned Val =
MI->getOperand(OpNo).getImm();
1605 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1606 O <<
"DBGDTRTX_EL0";
1611 if (Val == AArch64SysReg::TRCEXTINSELR) {
1612 O <<
"TRCEXTINSELR";
1627 unsigned Val =
MI->getOperand(OpNo).getImm();
1629 auto PState = AArch64PState::lookupPStateByEncoding(Val);
1639 unsigned RawVal =
MI->getOperand(OpNo).getImm();
1641 O <<
format(
"#%#016llx", Val);
1644 template<
int64_t Angle,
int64_t Remainder>
1648 unsigned Val =
MI->getOperand(OpNo).getImm();
1649 O <<
"#" << (Val * Angle) + Remainder;
1655 unsigned Val =
MI->getOperand(OpNum).getImm();
1656 if (
auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1662 template <
char suffix>
1677 unsigned Reg =
MI->getOperand(OpNum).getReg();
1683 template <
typename T>
1685 std::make_unsigned_t<T> HexValue =
Value;
1701 template <
typename T>
1705 unsigned UnscaledVal =
MI->getOperand(OpNum).getImm();
1706 unsigned Shift =
MI->getOperand(OpNum + 1).getImm();
1708 "Unexepected shift type!");
1718 if (std::is_signed<T>())
1726 template <
typename T>
1730 typedef std::make_signed_t<T> SignedT;
1731 typedef std::make_unsigned_t<T> UnsignedT;
1733 uint64_t Val =
MI->getOperand(OpNum).getImm();
1737 if ((int16_t)PrintVal == (SignedT)PrintVal)
1739 else if ((
uint16_t)PrintVal == PrintVal)
1745 template <
int W
idth>
1751 case 8:
Base = AArch64::B0;
break;
1752 case 16:
Base = AArch64::H0;
break;
1753 case 32:
Base = AArch64::S0;
break;
1754 case 64:
Base = AArch64::D0;
break;
1755 case 128:
Base = AArch64::Q0;
break;
1759 unsigned Reg =
MI->getOperand(OpNum).getReg();
1763 template <
unsigned ImmIs0,
unsigned ImmIs1>
1767 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
1768 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
1769 unsigned Val =
MI->getOperand(OpNum).getImm();
1770 O <<
"#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
1776 unsigned Reg =
MI->getOperand(OpNum).getReg();
1783 unsigned Reg =
MI->getOperand(OpNum).getReg();