LLVM  16.0.0git
AArch64MCTargetDesc.h
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1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 
16 #include "llvm/MC/MCInstrDesc.h"
17 #include "llvm/Support/DataTypes.h"
18 
19 #include <memory>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInst;
27 class MCInstrInfo;
28 class MCInstPrinter;
29 class MCRegisterInfo;
30 class MCObjectTargetWriter;
31 class MCStreamer;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class MCTargetStreamer;
35 class Target;
36 class Triple;
37 
38 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
39  MCContext &Ctx);
40 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
41  const MCSubtargetInfo &STI,
42  const MCRegisterInfo &MRI,
43  const MCTargetOptions &Options);
44 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
45  const MCSubtargetInfo &STI,
46  const MCRegisterInfo &MRI,
47  const MCTargetOptions &Options);
48 
49 std::unique_ptr<MCObjectTargetWriter>
50 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
51 
52 std::unique_ptr<MCObjectTargetWriter>
54  bool IsILP32);
55 
56 std::unique_ptr<MCObjectTargetWriter>
57 createAArch64WinCOFFObjectWriter(const Triple &TheTriple);
58 
59 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
60  formatted_raw_ostream &OS,
61  MCInstPrinter *InstPrint,
62  bool isVerboseAsm);
63 
64 namespace AArch64_MC {
66 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
67 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
68 }
69 
70 namespace AArch64 {
73 };
74 } // namespace AArch64
75 
76 } // End llvm namespace
77 
78 // Defines symbolic names for AArch64 registers. This defines a mapping from
79 // register name to register number.
80 //
81 #define GET_REGINFO_ENUM
82 #include "AArch64GenRegisterInfo.inc"
83 
84 // Defines symbolic names for the AArch64 instructions.
85 //
86 #define GET_INSTRINFO_ENUM
87 #define GET_INSTRINFO_MC_HELPER_DECLS
88 #include "AArch64GenInstrInfo.inc"
89 
90 #define GET_SUBTARGETINFO_ENUM
91 #include "AArch64GenSubtargetInfo.inc"
92 
93 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCInstrDesc.h
llvm::AArch64_MC::isQForm
bool isQForm(const MCInst &MI, const MCInstrInfo *MCII)
Definition: AArch64MCTargetDesc.cpp:303
llvm::AArch64::OPERAND_IMPLICIT_IMM_0
@ OPERAND_IMPLICIT_IMM_0
Definition: AArch64MCTargetDesc.h:72
llvm::MachO::CPUType
CPUType
Definition: MachO.h:1560
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:858
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAArch64AsmTargetStreamer
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: AArch64ELFStreamer.cpp:262
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AArch64::OperandType
OperandType
Definition: AArch64MCTargetDesc.h:71
llvm::createAArch64ELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
Definition: AArch64ELFObjectWriter.cpp:457
llvm::createAArch64MachObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
Definition: AArch64MachObjectWriter.cpp:411
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createAArch64WinCOFFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)
Definition: AArch64WinCOFFObjectWriter.cpp:165
llvm::createAArch64beAsmBackend
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AArch64AsmBackend.cpp:773
llvm::AArch64_MC::isFpOrNEON
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII)
Definition: AArch64MCTargetDesc.cpp:310
uint32_t
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: AArch64MCTargetDesc.cpp:66
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
DataTypes.h
llvm::createAArch64leAsmBackend
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AArch64AsmBackend.cpp:753
llvm::createAArch64MCCodeEmitter
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: AArch64MCCodeEmitter.cpp:668