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13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
22 class formatted_raw_ostream;
30 class MCObjectTargetWriter;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class MCTargetStreamer;
41 const MCSubtargetInfo &STI,
42 const MCRegisterInfo &
MRI,
43 const MCTargetOptions &
Options);
45 const MCSubtargetInfo &STI,
46 const MCRegisterInfo &
MRI,
47 const MCTargetOptions &
Options);
49 std::unique_ptr<MCObjectTargetWriter>
52 std::unique_ptr<MCObjectTargetWriter>
56 std::unique_ptr<MCObjectTargetWriter>
60 formatted_raw_ostream &OS,
61 MCInstPrinter *InstPrint,
64 namespace AArch64_MC {
81 #define GET_REGINFO_ENUM
82 #include "AArch64GenRegisterInfo.inc"
86 #define GET_INSTRINFO_ENUM
87 #define GET_INSTRINFO_MC_HELPER_DECLS
88 #include "AArch64GenInstrInfo.inc"
90 #define GET_SUBTARGETINFO_ENUM
91 #include "AArch64GenSubtargetInfo.inc"
This is an optimization pass for GlobalISel generic memory operations.
bool isQForm(const MCInst &MI, const MCInstrInfo *MCII)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Instances of this class represent a single low-level machine instruction.
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII)
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Interface to description of machine instruction set.
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)