LLVM 17.0.0git
AArch64AsmBackend.cpp
Go to the documentation of this file.
1//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
13#include "llvm/ADT/Triple.h"
16#include "llvm/MC/MCAssembler.h"
17#include "llvm/MC/MCContext.h"
27#include "llvm/MC/MCValue.h"
30using namespace llvm;
31
32namespace {
33
34class AArch64AsmBackend : public MCAsmBackend {
35 static const unsigned PCRelFlagVal =
37protected:
38 Triple TheTriple;
39
40public:
41 AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
42 : MCAsmBackend(IsLittleEndian ? support::little : support::big),
43 TheTriple(TT) {}
44
45 unsigned getNumFixupKinds() const override {
47 }
48
49 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
50
51 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
52 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
53 // This table *must* be in the order that the fixup_* kinds are defined
54 // in AArch64FixupKinds.h.
55 //
56 // Name Offset (bits) Size (bits) Flags
57 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
58 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
59 {"fixup_aarch64_add_imm12", 10, 12, 0},
60 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
61 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
62 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
63 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
64 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
65 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
66 {"fixup_aarch64_movw", 5, 16, 0},
67 {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
68 {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
69 {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal},
70 {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal}};
71
72 // Fixup kinds from .reloc directive are like R_AARCH64_NONE. They do not
73 // require any extra processing.
76
77 if (Kind < FirstTargetFixupKind)
79
80 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
81 "Invalid kind!");
82 return Infos[Kind - FirstTargetFixupKind];
83 }
84
85 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
87 uint64_t Value, bool IsResolved,
88 const MCSubtargetInfo *STI) const override;
89
92 const MCAsmLayout &Layout) const override;
93 void relaxInstruction(MCInst &Inst,
94 const MCSubtargetInfo &STI) const override;
95 bool writeNopData(raw_ostream &OS, uint64_t Count,
96 const MCSubtargetInfo *STI) const override;
97
98 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
99
100 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
101 const MCValue &Target) override;
102};
103
104} // end anonymous namespace
105
106/// The number of bytes the fixup may change.
107static unsigned getFixupKindNumBytes(unsigned Kind) {
108 switch (Kind) {
109 default:
110 llvm_unreachable("Unknown fixup kind!");
111
112 case FK_Data_1:
113 return 1;
114
115 case FK_Data_2:
116 case FK_SecRel_2:
117 return 2;
118
129 return 3;
130
135 case FK_Data_4:
136 case FK_SecRel_4:
137 return 4;
138
139 case FK_Data_8:
140 return 8;
141 }
142}
143
144static unsigned AdrImmBits(unsigned Value) {
145 unsigned lo2 = Value & 0x3;
146 unsigned hi19 = (Value & 0x1ffffc) >> 2;
147 return (hi19 << 5) | (lo2 << 29);
148}
149
152 const Triple &TheTriple, bool IsResolved) {
153 int64_t SignedValue = static_cast<int64_t>(Value);
154 switch (Fixup.getTargetKind()) {
155 default:
156 llvm_unreachable("Unknown fixup kind!");
158 if (SignedValue > 2097151 || SignedValue < -2097152)
159 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
160 return AdrImmBits(Value & 0x1fffffULL);
162 assert(!IsResolved);
163 if (TheTriple.isOSBinFormatCOFF()) {
164 if (!isInt<21>(SignedValue))
165 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
166 return AdrImmBits(Value & 0x1fffffULL);
167 }
168 return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
171 // Signed 21-bit immediate
172 if (SignedValue > 2097151 || SignedValue < -2097152)
173 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
174 if (Value & 0x3)
175 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
176 // Low two bits are not encoded.
177 return (Value >> 2) & 0x7ffff;
180 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
181 Value &= 0xfff;
182 // Unsigned 12-bit immediate
183 if (Value >= 0x1000)
184 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
185 return Value;
187 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
188 Value &= 0xfff;
189 // Unsigned 12-bit immediate which gets multiplied by 2
190 if (Value >= 0x2000)
191 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
192 if (Value & 0x1)
193 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
194 return Value >> 1;
196 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
197 Value &= 0xfff;
198 // Unsigned 12-bit immediate which gets multiplied by 4
199 if (Value >= 0x4000)
200 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
201 if (Value & 0x3)
202 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
203 return Value >> 2;
205 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
206 Value &= 0xfff;
207 // Unsigned 12-bit immediate which gets multiplied by 8
208 if (Value >= 0x8000)
209 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
210 if (Value & 0x7)
211 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
212 return Value >> 3;
214 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
215 Value &= 0xfff;
216 // Unsigned 12-bit immediate which gets multiplied by 16
217 if (Value >= 0x10000)
218 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
219 if (Value & 0xf)
220 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");
221 return Value >> 4;
224 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
227 if (!RefKind) {
228 // The fixup is an expression
229 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
230 Ctx.reportError(Fixup.getLoc(),
231 "fixup value out of range [-0xFFFF, 0xFFFF]");
232
233 // Invert the negative immediate because it will feed into a MOVN.
234 if (SignedValue < 0)
235 SignedValue = ~SignedValue;
236 Value = static_cast<uint64_t>(SignedValue);
237 } else
238 // VK_GOTTPREL, VK_TPREL, VK_DTPREL are movw fixups, but they can't
239 // ever be resolved in the assembler.
240 Ctx.reportError(Fixup.getLoc(),
241 "relocation for a thread-local variable points to an "
242 "absolute symbol");
243 return Value;
244 }
245
246 if (!IsResolved) {
247 // FIXME: Figure out when this can actually happen, and verify our
248 // behavior.
249 Ctx.reportError(Fixup.getLoc(), "unresolved movw fixup not yet "
250 "implemented");
251 return Value;
252 }
253
255 switch (AArch64MCExpr::getAddressFrag(RefKind)) {
257 break;
259 SignedValue = SignedValue >> 16;
260 break;
262 SignedValue = SignedValue >> 32;
263 break;
265 SignedValue = SignedValue >> 48;
266 break;
267 default:
268 llvm_unreachable("Variant kind doesn't correspond to fixup");
269 }
270
271 } else {
272 switch (AArch64MCExpr::getAddressFrag(RefKind)) {
274 break;
276 Value = Value >> 16;
277 break;
279 Value = Value >> 32;
280 break;
282 Value = Value >> 48;
283 break;
284 default:
285 llvm_unreachable("Variant kind doesn't correspond to fixup");
286 }
287 }
288
289 if (RefKind & AArch64MCExpr::VK_NC) {
290 Value &= 0xFFFF;
291 }
293 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
294 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
295
296 // Invert the negative immediate because it will feed into a MOVN.
297 if (SignedValue < 0)
298 SignedValue = ~SignedValue;
299 Value = static_cast<uint64_t>(SignedValue);
300 }
301 else if (Value > 0xFFFF) {
302 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
303 }
304 return Value;
305 }
307 // Signed 16-bit immediate
308 if (SignedValue > 32767 || SignedValue < -32768)
309 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
310 // Low two bits are not encoded (4-byte alignment assumed).
311 if (Value & 0x3)
312 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
313 return (Value >> 2) & 0x3fff;
316 // Signed 28-bit immediate
317 if (SignedValue > 134217727 || SignedValue < -134217728)
318 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
319 // Low two bits are not encoded (4-byte alignment assumed).
320 if (Value & 0x3)
321 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
322 return (Value >> 2) & 0x3ffffff;
323 case FK_Data_1:
324 case FK_Data_2:
325 case FK_Data_4:
326 case FK_Data_8:
327 case FK_SecRel_2:
328 case FK_SecRel_4:
329 return Value;
330 }
331}
332
333std::optional<MCFixupKind>
334AArch64AsmBackend::getFixupKind(StringRef Name) const {
335 if (!TheTriple.isOSBinFormatELF())
336 return std::nullopt;
337
339#define ELF_RELOC(X, Y) .Case(#X, Y)
340#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
341#undef ELF_RELOC
342 .Case("BFD_RELOC_NONE", ELF::R_AARCH64_NONE)
343 .Case("BFD_RELOC_16", ELF::R_AARCH64_ABS16)
344 .Case("BFD_RELOC_32", ELF::R_AARCH64_ABS32)
345 .Case("BFD_RELOC_64", ELF::R_AARCH64_ABS64)
346 .Default(-1u);
347 if (Type == -1u)
348 return std::nullopt;
349 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
350}
351
352/// getFixupKindContainereSizeInBytes - The number of bytes of the
353/// container involved in big endian or 0 if the item is little endian
354unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
355 if (Endian == support::little)
356 return 0;
357
358 switch (Kind) {
359 default:
360 llvm_unreachable("Unknown fixup kind!");
361
362 case FK_Data_1:
363 return 1;
364 case FK_Data_2:
365 return 2;
366 case FK_Data_4:
367 return 4;
368 case FK_Data_8:
369 return 8;
370
385 // Instructions are always little endian
386 return 0;
387 }
388}
389
390void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
391 const MCValue &Target,
393 bool IsResolved,
394 const MCSubtargetInfo *STI) const {
395 if (!Value)
396 return; // Doesn't change encoding.
397 unsigned Kind = Fixup.getKind();
398 if (Kind >= FirstLiteralRelocationKind)
399 return;
400 unsigned NumBytes = getFixupKindNumBytes(Kind);
401 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
402 MCContext &Ctx = Asm.getContext();
403 int64_t SignedValue = static_cast<int64_t>(Value);
404 // Apply any target-specific value adjustments.
405 Value = adjustFixupValue(Fixup, Target, Value, Ctx, TheTriple, IsResolved);
406
407 // Shift the value into position.
408 Value <<= Info.TargetOffset;
409
410 unsigned Offset = Fixup.getOffset();
411 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
412
413 // Used to point to big endian bytes.
414 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());
415
416 // For each byte of the fragment that the fixup touches, mask in the
417 // bits from the fixup value.
418 if (FulleSizeInBytes == 0) {
419 // Handle as little-endian
420 for (unsigned i = 0; i != NumBytes; ++i) {
421 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
422 }
423 } else {
424 // Handle as big-endian
425 assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!");
426 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");
427 for (unsigned i = 0; i != NumBytes; ++i) {
428 unsigned Idx = FulleSizeInBytes - 1 - i;
429 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
430 }
431 }
432
433 // FIXME: getFixupKindInfo() and getFixupKindNumBytes() could be fixed to
434 // handle this more cleanly. This may affect the output of -show-mc-encoding.
436 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
438 (!RefKind && Fixup.getTargetKind() == AArch64::fixup_aarch64_movw)) {
439 // If the immediate is negative, generate MOVN else MOVZ.
440 // (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ.
441 if (SignedValue < 0)
442 Data[Offset + 3] &= ~(1 << 6);
443 else
444 Data[Offset + 3] |= (1 << 6);
445 }
446}
447
448bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
450 const MCRelaxableFragment *DF,
451 const MCAsmLayout &Layout) const {
452 // FIXME: This isn't correct for AArch64. Just moving the "generic" logic
453 // into the targets for now.
454 //
455 // Relax if the value is too big for a (signed) i8.
456 return int64_t(Value) != int64_t(int8_t(Value));
457}
458
459void AArch64AsmBackend::relaxInstruction(MCInst &Inst,
460 const MCSubtargetInfo &STI) const {
461 llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
462}
463
464bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
465 const MCSubtargetInfo *STI) const {
466 // If the count is not 4-byte aligned, we must be writing data into the text
467 // section (otherwise we have unaligned instructions, and thus have far
468 // bigger problems), so just write zeros instead.
469 OS.write_zeros(Count % 4);
470
471 // We are properly aligned, so write NOPs as requested.
472 Count /= 4;
473 for (uint64_t i = 0; i != Count; ++i)
474 OS.write("\x1f\x20\x03\xd5", 4);
475 return true;
476}
477
478bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
479 const MCFixup &Fixup,
480 const MCValue &Target) {
481 unsigned Kind = Fixup.getKind();
482 if (Kind >= FirstLiteralRelocationKind)
483 return true;
484
485 // The ADRP instruction adds some multiple of 0x1000 to the current PC &
486 // ~0xfff. This means that the required offset to reach a symbol can vary by
487 // up to one step depending on where the ADRP is in memory. For example:
488 //
489 // ADRP x0, there
490 // there:
491 //
492 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
493 // we'll need that as an offset. At any other address "there" will be in the
494 // same page as the ADRP and the instruction should encode 0x0. Assuming the
495 // section isn't 0x1000-aligned, we therefore need to delegate this decision
496 // to the linker -- a relocation!
498 return true;
499
500 return false;
501}
502
503namespace {
504
505namespace CU {
506
507/// Compact unwind encoding values.
509 /// A "frameless" leaf function, where no non-volatile registers are
510 /// saved. The return remains in LR throughout the function.
511 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
512
513 /// No compact unwind encoding available. Instead the low 23-bits of
514 /// the compact unwind encoding is the offset of the DWARF FDE in the
515 /// __eh_frame section. This mode is never used in object files. It is only
516 /// generated by the linker in final linked images, which have only DWARF info
517 /// for a function.
518 UNWIND_ARM64_MODE_DWARF = 0x03000000,
519
520 /// This is a standard arm64 prologue where FP/LR are immediately
521 /// pushed on the stack, then SP is copied to FP. If there are any
522 /// non-volatile register saved, they are copied into the stack fame in pairs
523 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
524 /// five X pairs and four D pairs can be saved, but the memory layout must be
525 /// in register number order.
526 UNWIND_ARM64_MODE_FRAME = 0x04000000,
527
528 /// Frame register pair encodings.
529 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
530 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
531 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
532 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
533 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
534 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
535 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
536 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
537 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
538};
539
540} // end CU namespace
541
542// FIXME: This should be in a separate file.
543class DarwinAArch64AsmBackend : public AArch64AsmBackend {
544 const MCRegisterInfo &MRI;
545
546 /// Encode compact unwind stack adjustment for frameless functions.
547 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
548 /// The stack size always needs to be 16 byte aligned.
549 uint32_t encodeStackAdjustment(uint32_t StackSize) const {
550 return (StackSize / 16) << 12;
551 }
552
553public:
554 DarwinAArch64AsmBackend(const Target &T, const Triple &TT,
555 const MCRegisterInfo &MRI)
556 : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {}
557
558 std::unique_ptr<MCObjectTargetWriter>
559 createObjectTargetWriter() const override {
561 uint32_t CPUSubType = cantFail(MachO::getCPUSubType(TheTriple));
562 return createAArch64MachObjectWriter(CPUType, CPUSubType,
563 TheTriple.isArch32Bit());
564 }
565
566 /// Generate the compact unwind encoding from the CFI directives.
567 uint32_t generateCompactUnwindEncoding(
568 ArrayRef<MCCFIInstruction> Instrs) const override {
569 if (Instrs.empty())
570 return CU::UNWIND_ARM64_MODE_FRAMELESS;
571
572 bool HasFP = false;
573 unsigned StackSize = 0;
574
575 uint32_t CompactUnwindEncoding = 0;
576 int CurOffset = 0;
577 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
578 const MCCFIInstruction &Inst = Instrs[i];
579
580 switch (Inst.getOperation()) {
581 default:
582 // Cannot handle this directive: bail out.
583 return CU::UNWIND_ARM64_MODE_DWARF;
585 // Defines a frame pointer.
586 unsigned XReg =
587 getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true));
588
589 // Other CFA registers than FP are not supported by compact unwind.
590 // Fallback on DWARF.
591 // FIXME: When opt-remarks are supported in MC, add a remark to notify
592 // the user.
593 if (XReg != AArch64::FP)
594 return CU::UNWIND_ARM64_MODE_DWARF;
595
596 if (i + 2 >= e)
597 return CU::UNWIND_ARM64_MODE_DWARF;
598
599 const MCCFIInstruction &LRPush = Instrs[++i];
601 return CU::UNWIND_ARM64_MODE_DWARF;
602 const MCCFIInstruction &FPPush = Instrs[++i];
604 return CU::UNWIND_ARM64_MODE_DWARF;
605
606 if (FPPush.getOffset() + 8 != LRPush.getOffset())
607 return CU::UNWIND_ARM64_MODE_DWARF;
608 CurOffset = FPPush.getOffset();
609
610 unsigned LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true);
611 unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true);
612
613 LRReg = getXRegFromWReg(LRReg);
614 FPReg = getXRegFromWReg(FPReg);
615
616 if (LRReg != AArch64::LR || FPReg != AArch64::FP)
617 return CU::UNWIND_ARM64_MODE_DWARF;
618
619 // Indicate that the function has a frame.
620 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
621 HasFP = true;
622 break;
623 }
625 if (StackSize != 0)
626 return CU::UNWIND_ARM64_MODE_DWARF;
627 StackSize = std::abs(Inst.getOffset());
628 break;
629 }
631 // Registers are saved in pairs. We expect there to be two consecutive
632 // `.cfi_offset' instructions with the appropriate registers specified.
633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true);
634 if (i + 1 == e)
635 return CU::UNWIND_ARM64_MODE_DWARF;
636
637 if (CurOffset != 0 && Inst.getOffset() != CurOffset - 8)
638 return CU::UNWIND_ARM64_MODE_DWARF;
639 CurOffset = Inst.getOffset();
640
641 const MCCFIInstruction &Inst2 = Instrs[++i];
643 return CU::UNWIND_ARM64_MODE_DWARF;
644 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true);
645
646 if (Inst2.getOffset() != CurOffset - 8)
647 return CU::UNWIND_ARM64_MODE_DWARF;
648 CurOffset = Inst2.getOffset();
649
650 // N.B. The encodings must be in register number order, and the X
651 // registers before the D registers.
652
653 // X19/X20 pair = 0x00000001,
654 // X21/X22 pair = 0x00000002,
655 // X23/X24 pair = 0x00000004,
656 // X25/X26 pair = 0x00000008,
657 // X27/X28 pair = 0x00000010
658 Reg1 = getXRegFromWReg(Reg1);
659 Reg2 = getXRegFromWReg(Reg2);
660
661 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
662 (CompactUnwindEncoding & 0xF1E) == 0)
663 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
664 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
665 (CompactUnwindEncoding & 0xF1C) == 0)
666 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
667 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
668 (CompactUnwindEncoding & 0xF18) == 0)
669 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
670 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
671 (CompactUnwindEncoding & 0xF10) == 0)
672 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
673 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
674 (CompactUnwindEncoding & 0xF00) == 0)
675 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
676 else {
677 Reg1 = getDRegFromBReg(Reg1);
678 Reg2 = getDRegFromBReg(Reg2);
679
680 // D8/D9 pair = 0x00000100,
681 // D10/D11 pair = 0x00000200,
682 // D12/D13 pair = 0x00000400,
683 // D14/D15 pair = 0x00000800
684 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
685 (CompactUnwindEncoding & 0xE00) == 0)
686 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
687 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
688 (CompactUnwindEncoding & 0xC00) == 0)
689 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
690 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
691 (CompactUnwindEncoding & 0x800) == 0)
692 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
693 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
694 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
695 else
696 // A pair was pushed which we cannot handle.
697 return CU::UNWIND_ARM64_MODE_DWARF;
698 }
699
700 break;
701 }
702 }
703 }
704
705 if (!HasFP) {
706 // With compact unwind info we can only represent stack adjustments of up
707 // to 65520 bytes.
708 if (StackSize > 65520)
709 return CU::UNWIND_ARM64_MODE_DWARF;
710
711 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
712 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
713 }
714
715 return CompactUnwindEncoding;
716 }
717};
718
719} // end anonymous namespace
720
721namespace {
722
723class ELFAArch64AsmBackend : public AArch64AsmBackend {
724public:
725 uint8_t OSABI;
726 bool IsILP32;
727
728 ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
729 bool IsLittleEndian, bool IsILP32)
730 : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI),
731 IsILP32(IsILP32) {}
732
733 std::unique_ptr<MCObjectTargetWriter>
734 createObjectTargetWriter() const override {
735 return createAArch64ELFObjectWriter(OSABI, IsILP32);
736 }
737};
738
739}
740
741namespace {
742class COFFAArch64AsmBackend : public AArch64AsmBackend {
743public:
744 COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple)
745 : AArch64AsmBackend(T, TheTriple, /*IsLittleEndian*/ true) {}
746
747 std::unique_ptr<MCObjectTargetWriter>
748 createObjectTargetWriter() const override {
749 return createAArch64WinCOFFObjectWriter(TheTriple);
750 }
751};
752}
753
755 const MCSubtargetInfo &STI,
756 const MCRegisterInfo &MRI,
757 const MCTargetOptions &Options) {
758 const Triple &TheTriple = STI.getTargetTriple();
759 if (TheTriple.isOSBinFormatMachO()) {
760 return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
761 }
762
763 if (TheTriple.isOSBinFormatCOFF())
764 return new COFFAArch64AsmBackend(T, TheTriple);
765
766 assert(TheTriple.isOSBinFormatELF() && "Invalid target");
767
768 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
769 bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;
770 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true,
771 IsILP32);
772}
773
775 const MCSubtargetInfo &STI,
776 const MCRegisterInfo &MRI,
777 const MCTargetOptions &Options) {
778 const Triple &TheTriple = STI.getTargetTriple();
779 assert(TheTriple.isOSBinFormatELF() &&
780 "Big endian is only supported for ELF targets!");
781 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
782 bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;
783 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false,
784 IsILP32);
785}
unsigned const MachineRegisterInfo * MRI
static unsigned AdrImmBits(unsigned Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
This header is deprecated in favour of llvm/TargetParser/Triple.h.
basic Basic Alias true
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
static LVOptions Options
Definition: LVOptions.cpp:25
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static VariantKind getSymbolLoc(VariantKind Kind)
static VariantKind getAddressFrag(VariantKind Kind)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:171
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:97
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
unsigned getRegister() const
Definition: MCDwarf.h:645
int getOffset() const
Definition: MCDwarf.h:664
OpType getOperation() const
Definition: MCDwarf.h:642
Context object for machine code objects.
Definition: MCContext.h:76
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1055
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:687
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:364
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:679
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:372
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1473
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:674
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
raw_ostream & write(unsigned char C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
@ fixup_aarch64_ldst_imm12_scale16
Expected< uint32_t > getCPUSubType(const Triple &T)
Definition: MachO.cpp:95
Expected< uint32_t > getCPUType(const Triple &T)
Definition: MachO.cpp:77
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)
static unsigned getXRegFromWReg(unsigned Reg)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static unsigned getDRegFromBReg(unsigned Reg)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:745
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...