LLVM  14.0.0git
AArch64MCTargetDesc.cpp
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1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64MCTargetDesc.h"
14 #include "AArch64ELFStreamer.h"
15 #include "AArch64MCAsmInfo.h"
16 #include "AArch64WinCOFFStreamer.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/Support/Endian.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #define GET_INSTRINFO_MC_HELPERS
37 #include "AArch64GenInstrInfo.inc"
38 
39 #define GET_SUBTARGETINFO_MC_DESC
40 #include "AArch64GenSubtargetInfo.inc"
41 
42 #define GET_REGINFO_MC_DESC
43 #include "AArch64GenRegisterInfo.inc"
44 
46  MCInstrInfo *X = new MCInstrInfo();
47  InitAArch64MCInstrInfo(X);
48  return X;
49 }
50 
51 static MCSubtargetInfo *
53  if (CPU.empty()) {
54  CPU = "generic";
55 
56  if (TT.isArm64e())
57  CPU = "apple-a12";
58  }
59 
60  // Most of the NEON instruction set isn't supported in streaming mode on SME
61  // targets, disable NEON unless explicitly requested.
62  bool RequestedNEON = FS.contains("neon");
63  bool RequestedStreamingSVE = FS.contains("streaming-sve");
64  MCSubtargetInfo *STI =
65  createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
66  if (RequestedStreamingSVE && !RequestedNEON &&
67  STI->hasFeature(AArch64::FeatureNEON))
68  STI->ToggleFeature(AArch64::FeatureNEON);
69  return STI;
70 }
71 
73  // Mapping from CodeView to MC register id.
74  static const struct {
76  MCPhysReg Reg;
77  } RegMap[] = {
78  {codeview::RegisterId::ARM64_W0, AArch64::W0},
79  {codeview::RegisterId::ARM64_W1, AArch64::W1},
80  {codeview::RegisterId::ARM64_W2, AArch64::W2},
81  {codeview::RegisterId::ARM64_W3, AArch64::W3},
82  {codeview::RegisterId::ARM64_W4, AArch64::W4},
83  {codeview::RegisterId::ARM64_W5, AArch64::W5},
84  {codeview::RegisterId::ARM64_W6, AArch64::W6},
85  {codeview::RegisterId::ARM64_W7, AArch64::W7},
86  {codeview::RegisterId::ARM64_W8, AArch64::W8},
87  {codeview::RegisterId::ARM64_W9, AArch64::W9},
88  {codeview::RegisterId::ARM64_W10, AArch64::W10},
89  {codeview::RegisterId::ARM64_W11, AArch64::W11},
90  {codeview::RegisterId::ARM64_W12, AArch64::W12},
91  {codeview::RegisterId::ARM64_W13, AArch64::W13},
92  {codeview::RegisterId::ARM64_W14, AArch64::W14},
93  {codeview::RegisterId::ARM64_W15, AArch64::W15},
94  {codeview::RegisterId::ARM64_W16, AArch64::W16},
95  {codeview::RegisterId::ARM64_W17, AArch64::W17},
96  {codeview::RegisterId::ARM64_W18, AArch64::W18},
97  {codeview::RegisterId::ARM64_W19, AArch64::W19},
98  {codeview::RegisterId::ARM64_W20, AArch64::W20},
99  {codeview::RegisterId::ARM64_W21, AArch64::W21},
100  {codeview::RegisterId::ARM64_W22, AArch64::W22},
101  {codeview::RegisterId::ARM64_W23, AArch64::W23},
102  {codeview::RegisterId::ARM64_W24, AArch64::W24},
103  {codeview::RegisterId::ARM64_W25, AArch64::W25},
104  {codeview::RegisterId::ARM64_W26, AArch64::W26},
105  {codeview::RegisterId::ARM64_W27, AArch64::W27},
106  {codeview::RegisterId::ARM64_W28, AArch64::W28},
107  {codeview::RegisterId::ARM64_W29, AArch64::W29},
108  {codeview::RegisterId::ARM64_W30, AArch64::W30},
109  {codeview::RegisterId::ARM64_WZR, AArch64::WZR},
110  {codeview::RegisterId::ARM64_X0, AArch64::X0},
111  {codeview::RegisterId::ARM64_X1, AArch64::X1},
112  {codeview::RegisterId::ARM64_X2, AArch64::X2},
113  {codeview::RegisterId::ARM64_X3, AArch64::X3},
114  {codeview::RegisterId::ARM64_X4, AArch64::X4},
115  {codeview::RegisterId::ARM64_X5, AArch64::X5},
116  {codeview::RegisterId::ARM64_X6, AArch64::X6},
117  {codeview::RegisterId::ARM64_X7, AArch64::X7},
118  {codeview::RegisterId::ARM64_X8, AArch64::X8},
119  {codeview::RegisterId::ARM64_X9, AArch64::X9},
120  {codeview::RegisterId::ARM64_X10, AArch64::X10},
121  {codeview::RegisterId::ARM64_X11, AArch64::X11},
122  {codeview::RegisterId::ARM64_X12, AArch64::X12},
123  {codeview::RegisterId::ARM64_X13, AArch64::X13},
124  {codeview::RegisterId::ARM64_X14, AArch64::X14},
125  {codeview::RegisterId::ARM64_X15, AArch64::X15},
126  {codeview::RegisterId::ARM64_X16, AArch64::X16},
127  {codeview::RegisterId::ARM64_X17, AArch64::X17},
128  {codeview::RegisterId::ARM64_X18, AArch64::X18},
129  {codeview::RegisterId::ARM64_X19, AArch64::X19},
130  {codeview::RegisterId::ARM64_X20, AArch64::X20},
131  {codeview::RegisterId::ARM64_X21, AArch64::X21},
132  {codeview::RegisterId::ARM64_X22, AArch64::X22},
133  {codeview::RegisterId::ARM64_X23, AArch64::X23},
134  {codeview::RegisterId::ARM64_X24, AArch64::X24},
135  {codeview::RegisterId::ARM64_X25, AArch64::X25},
136  {codeview::RegisterId::ARM64_X26, AArch64::X26},
137  {codeview::RegisterId::ARM64_X27, AArch64::X27},
138  {codeview::RegisterId::ARM64_X28, AArch64::X28},
139  {codeview::RegisterId::ARM64_FP, AArch64::FP},
140  {codeview::RegisterId::ARM64_LR, AArch64::LR},
141  {codeview::RegisterId::ARM64_SP, AArch64::SP},
142  {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
143  {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
144  {codeview::RegisterId::ARM64_S0, AArch64::S0},
145  {codeview::RegisterId::ARM64_S1, AArch64::S1},
146  {codeview::RegisterId::ARM64_S2, AArch64::S2},
147  {codeview::RegisterId::ARM64_S3, AArch64::S3},
148  {codeview::RegisterId::ARM64_S4, AArch64::S4},
149  {codeview::RegisterId::ARM64_S5, AArch64::S5},
150  {codeview::RegisterId::ARM64_S6, AArch64::S6},
151  {codeview::RegisterId::ARM64_S7, AArch64::S7},
152  {codeview::RegisterId::ARM64_S8, AArch64::S8},
153  {codeview::RegisterId::ARM64_S9, AArch64::S9},
154  {codeview::RegisterId::ARM64_S10, AArch64::S10},
155  {codeview::RegisterId::ARM64_S11, AArch64::S11},
156  {codeview::RegisterId::ARM64_S12, AArch64::S12},
157  {codeview::RegisterId::ARM64_S13, AArch64::S13},
158  {codeview::RegisterId::ARM64_S14, AArch64::S14},
159  {codeview::RegisterId::ARM64_S15, AArch64::S15},
160  {codeview::RegisterId::ARM64_S16, AArch64::S16},
161  {codeview::RegisterId::ARM64_S17, AArch64::S17},
162  {codeview::RegisterId::ARM64_S18, AArch64::S18},
163  {codeview::RegisterId::ARM64_S19, AArch64::S19},
164  {codeview::RegisterId::ARM64_S20, AArch64::S20},
165  {codeview::RegisterId::ARM64_S21, AArch64::S21},
166  {codeview::RegisterId::ARM64_S22, AArch64::S22},
167  {codeview::RegisterId::ARM64_S23, AArch64::S23},
168  {codeview::RegisterId::ARM64_S24, AArch64::S24},
169  {codeview::RegisterId::ARM64_S25, AArch64::S25},
170  {codeview::RegisterId::ARM64_S26, AArch64::S26},
171  {codeview::RegisterId::ARM64_S27, AArch64::S27},
172  {codeview::RegisterId::ARM64_S28, AArch64::S28},
173  {codeview::RegisterId::ARM64_S29, AArch64::S29},
174  {codeview::RegisterId::ARM64_S30, AArch64::S30},
175  {codeview::RegisterId::ARM64_S31, AArch64::S31},
176  {codeview::RegisterId::ARM64_D0, AArch64::D0},
177  {codeview::RegisterId::ARM64_D1, AArch64::D1},
178  {codeview::RegisterId::ARM64_D2, AArch64::D2},
179  {codeview::RegisterId::ARM64_D3, AArch64::D3},
180  {codeview::RegisterId::ARM64_D4, AArch64::D4},
181  {codeview::RegisterId::ARM64_D5, AArch64::D5},
182  {codeview::RegisterId::ARM64_D6, AArch64::D6},
183  {codeview::RegisterId::ARM64_D7, AArch64::D7},
184  {codeview::RegisterId::ARM64_D8, AArch64::D8},
185  {codeview::RegisterId::ARM64_D9, AArch64::D9},
186  {codeview::RegisterId::ARM64_D10, AArch64::D10},
187  {codeview::RegisterId::ARM64_D11, AArch64::D11},
188  {codeview::RegisterId::ARM64_D12, AArch64::D12},
189  {codeview::RegisterId::ARM64_D13, AArch64::D13},
190  {codeview::RegisterId::ARM64_D14, AArch64::D14},
191  {codeview::RegisterId::ARM64_D15, AArch64::D15},
192  {codeview::RegisterId::ARM64_D16, AArch64::D16},
193  {codeview::RegisterId::ARM64_D17, AArch64::D17},
194  {codeview::RegisterId::ARM64_D18, AArch64::D18},
195  {codeview::RegisterId::ARM64_D19, AArch64::D19},
196  {codeview::RegisterId::ARM64_D20, AArch64::D20},
197  {codeview::RegisterId::ARM64_D21, AArch64::D21},
198  {codeview::RegisterId::ARM64_D22, AArch64::D22},
199  {codeview::RegisterId::ARM64_D23, AArch64::D23},
200  {codeview::RegisterId::ARM64_D24, AArch64::D24},
201  {codeview::RegisterId::ARM64_D25, AArch64::D25},
202  {codeview::RegisterId::ARM64_D26, AArch64::D26},
203  {codeview::RegisterId::ARM64_D27, AArch64::D27},
204  {codeview::RegisterId::ARM64_D28, AArch64::D28},
205  {codeview::RegisterId::ARM64_D29, AArch64::D29},
206  {codeview::RegisterId::ARM64_D30, AArch64::D30},
207  {codeview::RegisterId::ARM64_D31, AArch64::D31},
208  {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
209  {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
210  {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
211  {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
212  {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
213  {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
214  {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
215  {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
216  {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
217  {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
218  {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
219  {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
220  {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
221  {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
222  {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
223  {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
224  {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
225  {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
226  {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
227  {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
228  {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
229  {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
230  {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
231  {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
232  {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
233  {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
234  {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
235  {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
236  {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
237  {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
238  {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
239  {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
240 
241  };
242  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
243  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
244 }
245 
248  InitAArch64MCRegisterInfo(X, AArch64::LR);
250  return X;
251 }
252 
254  const Triple &TheTriple,
255  const MCTargetOptions &Options) {
256  MCAsmInfo *MAI;
257  if (TheTriple.isOSBinFormatMachO())
258  MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);
259  else if (TheTriple.isWindowsMSVCEnvironment())
260  MAI = new AArch64MCAsmInfoMicrosoftCOFF();
261  else if (TheTriple.isOSBinFormatCOFF())
262  MAI = new AArch64MCAsmInfoGNUCOFF();
263  else {
264  assert(TheTriple.isOSBinFormatELF() && "Invalid target");
265  MAI = new AArch64MCAsmInfoELF(TheTriple);
266  }
267 
268  // Initial state of the frame pointer is SP.
269  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
271  MAI->addInitialFrameState(Inst);
272 
273  return MAI;
274 }
275 
277  unsigned SyntaxVariant,
278  const MCAsmInfo &MAI,
279  const MCInstrInfo &MII,
280  const MCRegisterInfo &MRI) {
281  if (SyntaxVariant == 0)
282  return new AArch64InstPrinter(MAI, MII, MRI);
283  if (SyntaxVariant == 1)
284  return new AArch64AppleInstPrinter(MAI, MII, MRI);
285 
286  return nullptr;
287 }
288 
290  std::unique_ptr<MCAsmBackend> &&TAB,
291  std::unique_ptr<MCObjectWriter> &&OW,
292  std::unique_ptr<MCCodeEmitter> &&Emitter,
293  bool RelaxAll) {
294  return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
295  std::move(Emitter), RelaxAll);
296 }
297 
299  std::unique_ptr<MCAsmBackend> &&TAB,
300  std::unique_ptr<MCObjectWriter> &&OW,
301  std::unique_ptr<MCCodeEmitter> &&Emitter,
302  bool RelaxAll,
303  bool DWARFMustBeAtTheEnd) {
304  return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
305  std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
306  /*LabelSections*/ true);
307 }
308 
309 static MCStreamer *
310 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
311  std::unique_ptr<MCObjectWriter> &&OW,
312  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
313  bool IncrementalLinkerCompatible) {
314  return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
315  std::move(Emitter), RelaxAll,
316  IncrementalLinkerCompatible);
317 }
318 
319 namespace {
320 
321 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
322 public:
323  AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
324 
325  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
326  uint64_t &Target) const override {
327  // Search for a PC-relative argument.
328  // This will handle instructions like bcc (where the first argument is the
329  // condition code) and cbz (where it is a register).
330  const auto &Desc = Info->get(Inst.getOpcode());
331  for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
332  if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
333  int64_t Imm = Inst.getOperand(i).getImm() * 4;
334  Target = Addr + Imm;
335  return true;
336  }
337  }
338  return false;
339  }
340 
341  std::vector<std::pair<uint64_t, uint64_t>>
342  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
343  uint64_t GotPltSectionVA,
344  const Triple &TargetTriple) const override {
345  // Do a lightweight parsing of PLT entries.
346  std::vector<std::pair<uint64_t, uint64_t>> Result;
347  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
348  Byte += 4) {
349  uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
350  uint64_t Off = 0;
351  // Check for optional bti c that prefixes adrp in BTI enabled entries
352  if (Insn == 0xd503245f) {
353  Off = 4;
354  Insn = support::endian::read32le(PltContents.data() + Byte + Off);
355  }
356  // Check for adrp.
357  if ((Insn & 0x9f000000) != 0x90000000)
358  continue;
359  Off += 4;
360  uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
361  (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
362  uint32_t Insn2 =
363  support::endian::read32le(PltContents.data() + Byte + Off);
364  // Check for: ldr Xt, [Xn, #pimm].
365  if (Insn2 >> 22 == 0x3e5) {
366  Imm += ((Insn2 >> 10) & 0xfff) << 3;
367  Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
368  Byte += 4;
369  }
370  }
371  return Result;
372  }
373 };
374 
375 } // end anonymous namespace
376 
378  return new AArch64MCInstrAnalysis(Info);
379 }
380 
381 // Force static initialization.
385  &getTheARM64_32Target()}) {
386  // Register the MC asm info.
388 
389  // Register the MC instruction info.
391 
392  // Register the MC register info.
394 
395  // Register the MC subtarget info.
397 
398  // Register the MC instruction analyzer.
400 
401  // Register the MC Code Emitter
403 
404  // Register the obj streamers.
408 
409  // Register the obj target streamer.
412 
413  // Register the asm streamer.
416  // Register the MCInstPrinter.
418  }
419 
420  // Register the asm backend.
426 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::codeview::SimpleTypeKind::Byte
@ Byte
i
i
Definition: README.txt:29
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:637
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
createAArch64MCInstPrinter
static MCInstPrinter * createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64MCTargetDesc.cpp:276
MCCodeEmitter.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
createAArch64MCAsmInfo
static MCAsmInfo * createAArch64MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: AArch64MCTargetDesc.cpp:253
ErrorHandling.h
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:972
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:823
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AArch64MCAsmInfoDarwin
Definition: AArch64MCAsmInfo.h:25
llvm::createMachOStreamer
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
Definition: MCMachOStreamer.cpp:509
llvm::AArch64MCAsmInfoELF
Definition: AArch64MCAsmInfo.h:32
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAArch64AsmTargetStreamer
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: AArch64ELFStreamer.cpp:261
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:54
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:930
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
createWinCOFFStreamer
static MCStreamer * createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: AArch64MCTargetDesc.cpp:310
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:947
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:162
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:557
llvm::createAArch64ObjectTargetStreamer
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: AArch64TargetStreamer.cpp:113
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
llvm::createAArch64MCCodeEmitter
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: AArch64MCCodeEmitter.cpp:679
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:632
llvm::AArch64MCAsmInfoGNUCOFF
Definition: AArch64MCAsmInfo.h:40
MCAsmBackend.h
AArch64ELFStreamer.h
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:118
createAArch64MCRegisterInfo
static MCRegisterInfo * createAArch64MCRegisterInfo(const Triple &Triple)
Definition: AArch64MCTargetDesc.cpp:246
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:645
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
AArch64MCAsmInfo.h
CodeView.h
llvm::Triple::getArch
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:307
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1097
llvm::MCCFIInstruction
Definition: MCDwarf.h:434
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::createAArch64WinCOFFStreamer
MCWinCOFFStreamer * createAArch64WinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: AArch64WinCOFFStreamer.cpp:223
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
AArch64AddressingModes.h
llvm::AArch64AppleInstPrinter
Definition: AArch64InstPrinter.h:219
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:877
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition: TargetRegistry.h:951
uint64_t
LLVMInitializeAArch64TargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC()
Definition: AArch64MCTargetDesc.cpp:382
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:978
MCRegisterInfo.h
llvm::AArch64MCAsmInfoMicrosoftCOFF
Definition: AArch64MCAsmInfo.h:36
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:517
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::createAArch64beAsmBackend
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AArch64AsmBackend.cpp:768
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:850
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::ArrayRef< uint8_t >
MCInstrAnalysis.h
AArch64InstPrinter.h
llvm::AArch64InstPrinter
Definition: AArch64InstPrinter.h:23
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: AArch64MCTargetDesc.cpp:72
llvm::createELFStreamer
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Definition: MCELFStreamer.cpp:888
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:817
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:943
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
uint16_t
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:837
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:955
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
AArch64MCTargetDesc.h
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
createAArch64InstrAnalysis
static MCInstrAnalysis * createAArch64InstrAnalysis(const MCInstrInfo *Info)
Definition: AArch64MCTargetDesc.cpp:377
createAArch64MCSubtargetInfo
static MCSubtargetInfo * createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition: AArch64MCTargetDesc.cpp:52
AArch64WinCOFFStreamer.h
createAArch64MCInstrInfo
static MCInstrInfo * createAArch64MCInstrInfo()
Definition: AArch64MCTargetDesc.cpp:45
Endian.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::createAArch64leAsmBackend
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AArch64AsmBackend.cpp:748
llvm::createAArch64ELFStreamer
MCELFStreamer * createAArch64ELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
Definition: AArch64ELFStreamer.cpp:267
AArch64TargetInfo.h