LLVM  16.0.0git
AArch64MCTargetDesc.cpp
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1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64MCTargetDesc.h"
14 #include "AArch64ELFStreamer.h"
15 #include "AArch64MCAsmInfo.h"
16 #include "AArch64WinCOFFStreamer.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/TargetRegistry.h"
30 #include "llvm/Support/Endian.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #define GET_INSTRINFO_MC_HELPERS
37 #define ENABLE_INSTR_PREDICATE_VERIFIER
38 #include "AArch64GenInstrInfo.inc"
39 
40 #define GET_SUBTARGETINFO_MC_DESC
41 #include "AArch64GenSubtargetInfo.inc"
42 
43 #define GET_REGINFO_MC_DESC
44 #include "AArch64GenRegisterInfo.inc"
45 
47  MCInstrInfo *X = new MCInstrInfo();
48  InitAArch64MCInstrInfo(X);
49  return X;
50 }
51 
52 static MCSubtargetInfo *
54  if (CPU.empty()) {
55  CPU = "generic";
56  if (FS.empty())
57  FS = "+v8a";
58 
59  if (TT.isArm64e())
60  CPU = "apple-a12";
61  }
62 
63  return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
64 }
65 
67  // Mapping from CodeView to MC register id.
68  static const struct {
70  MCPhysReg Reg;
71  } RegMap[] = {
72  {codeview::RegisterId::ARM64_W0, AArch64::W0},
73  {codeview::RegisterId::ARM64_W1, AArch64::W1},
74  {codeview::RegisterId::ARM64_W2, AArch64::W2},
75  {codeview::RegisterId::ARM64_W3, AArch64::W3},
76  {codeview::RegisterId::ARM64_W4, AArch64::W4},
77  {codeview::RegisterId::ARM64_W5, AArch64::W5},
78  {codeview::RegisterId::ARM64_W6, AArch64::W6},
79  {codeview::RegisterId::ARM64_W7, AArch64::W7},
80  {codeview::RegisterId::ARM64_W8, AArch64::W8},
81  {codeview::RegisterId::ARM64_W9, AArch64::W9},
82  {codeview::RegisterId::ARM64_W10, AArch64::W10},
83  {codeview::RegisterId::ARM64_W11, AArch64::W11},
84  {codeview::RegisterId::ARM64_W12, AArch64::W12},
85  {codeview::RegisterId::ARM64_W13, AArch64::W13},
86  {codeview::RegisterId::ARM64_W14, AArch64::W14},
87  {codeview::RegisterId::ARM64_W15, AArch64::W15},
88  {codeview::RegisterId::ARM64_W16, AArch64::W16},
89  {codeview::RegisterId::ARM64_W17, AArch64::W17},
90  {codeview::RegisterId::ARM64_W18, AArch64::W18},
91  {codeview::RegisterId::ARM64_W19, AArch64::W19},
92  {codeview::RegisterId::ARM64_W20, AArch64::W20},
93  {codeview::RegisterId::ARM64_W21, AArch64::W21},
94  {codeview::RegisterId::ARM64_W22, AArch64::W22},
95  {codeview::RegisterId::ARM64_W23, AArch64::W23},
96  {codeview::RegisterId::ARM64_W24, AArch64::W24},
97  {codeview::RegisterId::ARM64_W25, AArch64::W25},
98  {codeview::RegisterId::ARM64_W26, AArch64::W26},
99  {codeview::RegisterId::ARM64_W27, AArch64::W27},
100  {codeview::RegisterId::ARM64_W28, AArch64::W28},
101  {codeview::RegisterId::ARM64_W29, AArch64::W29},
102  {codeview::RegisterId::ARM64_W30, AArch64::W30},
103  {codeview::RegisterId::ARM64_WZR, AArch64::WZR},
104  {codeview::RegisterId::ARM64_X0, AArch64::X0},
105  {codeview::RegisterId::ARM64_X1, AArch64::X1},
106  {codeview::RegisterId::ARM64_X2, AArch64::X2},
107  {codeview::RegisterId::ARM64_X3, AArch64::X3},
108  {codeview::RegisterId::ARM64_X4, AArch64::X4},
109  {codeview::RegisterId::ARM64_X5, AArch64::X5},
110  {codeview::RegisterId::ARM64_X6, AArch64::X6},
111  {codeview::RegisterId::ARM64_X7, AArch64::X7},
112  {codeview::RegisterId::ARM64_X8, AArch64::X8},
113  {codeview::RegisterId::ARM64_X9, AArch64::X9},
114  {codeview::RegisterId::ARM64_X10, AArch64::X10},
115  {codeview::RegisterId::ARM64_X11, AArch64::X11},
116  {codeview::RegisterId::ARM64_X12, AArch64::X12},
117  {codeview::RegisterId::ARM64_X13, AArch64::X13},
118  {codeview::RegisterId::ARM64_X14, AArch64::X14},
119  {codeview::RegisterId::ARM64_X15, AArch64::X15},
120  {codeview::RegisterId::ARM64_X16, AArch64::X16},
121  {codeview::RegisterId::ARM64_X17, AArch64::X17},
122  {codeview::RegisterId::ARM64_X18, AArch64::X18},
123  {codeview::RegisterId::ARM64_X19, AArch64::X19},
124  {codeview::RegisterId::ARM64_X20, AArch64::X20},
125  {codeview::RegisterId::ARM64_X21, AArch64::X21},
126  {codeview::RegisterId::ARM64_X22, AArch64::X22},
127  {codeview::RegisterId::ARM64_X23, AArch64::X23},
128  {codeview::RegisterId::ARM64_X24, AArch64::X24},
129  {codeview::RegisterId::ARM64_X25, AArch64::X25},
130  {codeview::RegisterId::ARM64_X26, AArch64::X26},
131  {codeview::RegisterId::ARM64_X27, AArch64::X27},
132  {codeview::RegisterId::ARM64_X28, AArch64::X28},
133  {codeview::RegisterId::ARM64_FP, AArch64::FP},
134  {codeview::RegisterId::ARM64_LR, AArch64::LR},
135  {codeview::RegisterId::ARM64_SP, AArch64::SP},
136  {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
137  {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
138  {codeview::RegisterId::ARM64_S0, AArch64::S0},
139  {codeview::RegisterId::ARM64_S1, AArch64::S1},
140  {codeview::RegisterId::ARM64_S2, AArch64::S2},
141  {codeview::RegisterId::ARM64_S3, AArch64::S3},
142  {codeview::RegisterId::ARM64_S4, AArch64::S4},
143  {codeview::RegisterId::ARM64_S5, AArch64::S5},
144  {codeview::RegisterId::ARM64_S6, AArch64::S6},
145  {codeview::RegisterId::ARM64_S7, AArch64::S7},
146  {codeview::RegisterId::ARM64_S8, AArch64::S8},
147  {codeview::RegisterId::ARM64_S9, AArch64::S9},
148  {codeview::RegisterId::ARM64_S10, AArch64::S10},
149  {codeview::RegisterId::ARM64_S11, AArch64::S11},
150  {codeview::RegisterId::ARM64_S12, AArch64::S12},
151  {codeview::RegisterId::ARM64_S13, AArch64::S13},
152  {codeview::RegisterId::ARM64_S14, AArch64::S14},
153  {codeview::RegisterId::ARM64_S15, AArch64::S15},
154  {codeview::RegisterId::ARM64_S16, AArch64::S16},
155  {codeview::RegisterId::ARM64_S17, AArch64::S17},
156  {codeview::RegisterId::ARM64_S18, AArch64::S18},
157  {codeview::RegisterId::ARM64_S19, AArch64::S19},
158  {codeview::RegisterId::ARM64_S20, AArch64::S20},
159  {codeview::RegisterId::ARM64_S21, AArch64::S21},
160  {codeview::RegisterId::ARM64_S22, AArch64::S22},
161  {codeview::RegisterId::ARM64_S23, AArch64::S23},
162  {codeview::RegisterId::ARM64_S24, AArch64::S24},
163  {codeview::RegisterId::ARM64_S25, AArch64::S25},
164  {codeview::RegisterId::ARM64_S26, AArch64::S26},
165  {codeview::RegisterId::ARM64_S27, AArch64::S27},
166  {codeview::RegisterId::ARM64_S28, AArch64::S28},
167  {codeview::RegisterId::ARM64_S29, AArch64::S29},
168  {codeview::RegisterId::ARM64_S30, AArch64::S30},
169  {codeview::RegisterId::ARM64_S31, AArch64::S31},
170  {codeview::RegisterId::ARM64_D0, AArch64::D0},
171  {codeview::RegisterId::ARM64_D1, AArch64::D1},
172  {codeview::RegisterId::ARM64_D2, AArch64::D2},
173  {codeview::RegisterId::ARM64_D3, AArch64::D3},
174  {codeview::RegisterId::ARM64_D4, AArch64::D4},
175  {codeview::RegisterId::ARM64_D5, AArch64::D5},
176  {codeview::RegisterId::ARM64_D6, AArch64::D6},
177  {codeview::RegisterId::ARM64_D7, AArch64::D7},
178  {codeview::RegisterId::ARM64_D8, AArch64::D8},
179  {codeview::RegisterId::ARM64_D9, AArch64::D9},
180  {codeview::RegisterId::ARM64_D10, AArch64::D10},
181  {codeview::RegisterId::ARM64_D11, AArch64::D11},
182  {codeview::RegisterId::ARM64_D12, AArch64::D12},
183  {codeview::RegisterId::ARM64_D13, AArch64::D13},
184  {codeview::RegisterId::ARM64_D14, AArch64::D14},
185  {codeview::RegisterId::ARM64_D15, AArch64::D15},
186  {codeview::RegisterId::ARM64_D16, AArch64::D16},
187  {codeview::RegisterId::ARM64_D17, AArch64::D17},
188  {codeview::RegisterId::ARM64_D18, AArch64::D18},
189  {codeview::RegisterId::ARM64_D19, AArch64::D19},
190  {codeview::RegisterId::ARM64_D20, AArch64::D20},
191  {codeview::RegisterId::ARM64_D21, AArch64::D21},
192  {codeview::RegisterId::ARM64_D22, AArch64::D22},
193  {codeview::RegisterId::ARM64_D23, AArch64::D23},
194  {codeview::RegisterId::ARM64_D24, AArch64::D24},
195  {codeview::RegisterId::ARM64_D25, AArch64::D25},
196  {codeview::RegisterId::ARM64_D26, AArch64::D26},
197  {codeview::RegisterId::ARM64_D27, AArch64::D27},
198  {codeview::RegisterId::ARM64_D28, AArch64::D28},
199  {codeview::RegisterId::ARM64_D29, AArch64::D29},
200  {codeview::RegisterId::ARM64_D30, AArch64::D30},
201  {codeview::RegisterId::ARM64_D31, AArch64::D31},
202  {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
203  {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
204  {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
205  {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
206  {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
207  {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
208  {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
209  {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
210  {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
211  {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
212  {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
213  {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
214  {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
215  {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
216  {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
217  {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
218  {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
219  {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
220  {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
221  {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
222  {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
223  {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
224  {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
225  {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
226  {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
227  {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
228  {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
229  {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
230  {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
231  {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
232  {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
233  {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
234  {codeview::RegisterId::ARM64_B0, AArch64::B0},
235  {codeview::RegisterId::ARM64_B1, AArch64::B1},
236  {codeview::RegisterId::ARM64_B2, AArch64::B2},
237  {codeview::RegisterId::ARM64_B3, AArch64::B3},
238  {codeview::RegisterId::ARM64_B4, AArch64::B4},
239  {codeview::RegisterId::ARM64_B5, AArch64::B5},
240  {codeview::RegisterId::ARM64_B6, AArch64::B6},
241  {codeview::RegisterId::ARM64_B7, AArch64::B7},
242  {codeview::RegisterId::ARM64_B8, AArch64::B8},
243  {codeview::RegisterId::ARM64_B9, AArch64::B9},
244  {codeview::RegisterId::ARM64_B10, AArch64::B10},
245  {codeview::RegisterId::ARM64_B11, AArch64::B11},
246  {codeview::RegisterId::ARM64_B12, AArch64::B12},
247  {codeview::RegisterId::ARM64_B13, AArch64::B13},
248  {codeview::RegisterId::ARM64_B14, AArch64::B14},
249  {codeview::RegisterId::ARM64_B15, AArch64::B15},
250  {codeview::RegisterId::ARM64_B16, AArch64::B16},
251  {codeview::RegisterId::ARM64_B17, AArch64::B17},
252  {codeview::RegisterId::ARM64_B18, AArch64::B18},
253  {codeview::RegisterId::ARM64_B19, AArch64::B19},
254  {codeview::RegisterId::ARM64_B20, AArch64::B20},
255  {codeview::RegisterId::ARM64_B21, AArch64::B21},
256  {codeview::RegisterId::ARM64_B22, AArch64::B22},
257  {codeview::RegisterId::ARM64_B23, AArch64::B23},
258  {codeview::RegisterId::ARM64_B24, AArch64::B24},
259  {codeview::RegisterId::ARM64_B25, AArch64::B25},
260  {codeview::RegisterId::ARM64_B26, AArch64::B26},
261  {codeview::RegisterId::ARM64_B27, AArch64::B27},
262  {codeview::RegisterId::ARM64_B28, AArch64::B28},
263  {codeview::RegisterId::ARM64_B29, AArch64::B29},
264  {codeview::RegisterId::ARM64_B30, AArch64::B30},
265  {codeview::RegisterId::ARM64_B31, AArch64::B31},
266  {codeview::RegisterId::ARM64_H0, AArch64::H0},
267  {codeview::RegisterId::ARM64_H1, AArch64::H1},
268  {codeview::RegisterId::ARM64_H2, AArch64::H2},
269  {codeview::RegisterId::ARM64_H3, AArch64::H3},
270  {codeview::RegisterId::ARM64_H4, AArch64::H4},
271  {codeview::RegisterId::ARM64_H5, AArch64::H5},
272  {codeview::RegisterId::ARM64_H6, AArch64::H6},
273  {codeview::RegisterId::ARM64_H7, AArch64::H7},
274  {codeview::RegisterId::ARM64_H8, AArch64::H8},
275  {codeview::RegisterId::ARM64_H9, AArch64::H9},
276  {codeview::RegisterId::ARM64_H10, AArch64::H10},
277  {codeview::RegisterId::ARM64_H11, AArch64::H11},
278  {codeview::RegisterId::ARM64_H12, AArch64::H12},
279  {codeview::RegisterId::ARM64_H13, AArch64::H13},
280  {codeview::RegisterId::ARM64_H14, AArch64::H14},
281  {codeview::RegisterId::ARM64_H15, AArch64::H15},
282  {codeview::RegisterId::ARM64_H16, AArch64::H16},
283  {codeview::RegisterId::ARM64_H17, AArch64::H17},
284  {codeview::RegisterId::ARM64_H18, AArch64::H18},
285  {codeview::RegisterId::ARM64_H19, AArch64::H19},
286  {codeview::RegisterId::ARM64_H20, AArch64::H20},
287  {codeview::RegisterId::ARM64_H21, AArch64::H21},
288  {codeview::RegisterId::ARM64_H22, AArch64::H22},
289  {codeview::RegisterId::ARM64_H23, AArch64::H23},
290  {codeview::RegisterId::ARM64_H24, AArch64::H24},
291  {codeview::RegisterId::ARM64_H25, AArch64::H25},
292  {codeview::RegisterId::ARM64_H26, AArch64::H26},
293  {codeview::RegisterId::ARM64_H27, AArch64::H27},
294  {codeview::RegisterId::ARM64_H28, AArch64::H28},
295  {codeview::RegisterId::ARM64_H29, AArch64::H29},
296  {codeview::RegisterId::ARM64_H30, AArch64::H30},
297  {codeview::RegisterId::ARM64_H31, AArch64::H31},
298  };
299  for (const auto &I : RegMap)
300  MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
301 }
302 
303 bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
304  const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
305  return llvm::any_of(MI, [&](const MCOperand &Op) {
306  return Op.isReg() && FPR128.contains(Op.getReg());
307  });
308 }
309 
310 bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {
311  const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
312  const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID];
313  const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID];
314  const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
315  const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID];
316 
317  auto IsFPR = [&](const MCOperand &Op) {
318  if (!Op.isReg())
319  return false;
320  auto Reg = Op.getReg();
321  return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||
322  FPR16.contains(Reg) || FPR8.contains(Reg);
323  };
324 
325  return llvm::any_of(MI, IsFPR);
326 }
327 
330  InitAArch64MCRegisterInfo(X, AArch64::LR);
332  return X;
333 }
334 
336  const Triple &TheTriple,
337  const MCTargetOptions &Options) {
338  MCAsmInfo *MAI;
339  if (TheTriple.isOSBinFormatMachO())
340  MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);
341  else if (TheTriple.isWindowsMSVCEnvironment())
342  MAI = new AArch64MCAsmInfoMicrosoftCOFF();
343  else if (TheTriple.isOSBinFormatCOFF())
344  MAI = new AArch64MCAsmInfoGNUCOFF();
345  else {
346  assert(TheTriple.isOSBinFormatELF() && "Invalid target");
347  MAI = new AArch64MCAsmInfoELF(TheTriple);
348  }
349 
350  // Initial state of the frame pointer is SP.
351  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
353  MAI->addInitialFrameState(Inst);
354 
355  return MAI;
356 }
357 
359  unsigned SyntaxVariant,
360  const MCAsmInfo &MAI,
361  const MCInstrInfo &MII,
362  const MCRegisterInfo &MRI) {
363  if (SyntaxVariant == 0)
364  return new AArch64InstPrinter(MAI, MII, MRI);
365  if (SyntaxVariant == 1)
366  return new AArch64AppleInstPrinter(MAI, MII, MRI);
367 
368  return nullptr;
369 }
370 
372  std::unique_ptr<MCAsmBackend> &&TAB,
373  std::unique_ptr<MCObjectWriter> &&OW,
374  std::unique_ptr<MCCodeEmitter> &&Emitter,
375  bool RelaxAll) {
376  return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
377  std::move(Emitter), RelaxAll);
378 }
379 
381  std::unique_ptr<MCAsmBackend> &&TAB,
382  std::unique_ptr<MCObjectWriter> &&OW,
383  std::unique_ptr<MCCodeEmitter> &&Emitter,
384  bool RelaxAll,
385  bool DWARFMustBeAtTheEnd) {
386  return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
387  std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
388  /*LabelSections*/ true);
389 }
390 
391 static MCStreamer *
392 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
393  std::unique_ptr<MCObjectWriter> &&OW,
394  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
395  bool IncrementalLinkerCompatible) {
396  return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
397  std::move(Emitter), RelaxAll,
398  IncrementalLinkerCompatible);
399 }
400 
401 namespace {
402 
403 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
404 public:
405  AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
406 
407  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
408  uint64_t &Target) const override {
409  // Search for a PC-relative argument.
410  // This will handle instructions like bcc (where the first argument is the
411  // condition code) and cbz (where it is a register).
412  const auto &Desc = Info->get(Inst.getOpcode());
413  for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
414  if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
415  int64_t Imm = Inst.getOperand(i).getImm() * 4;
416  Target = Addr + Imm;
417  return true;
418  }
419  }
420  return false;
421  }
422 
423  std::vector<std::pair<uint64_t, uint64_t>>
424  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
425  uint64_t GotPltSectionVA,
426  const Triple &TargetTriple) const override {
427  // Do a lightweight parsing of PLT entries.
428  std::vector<std::pair<uint64_t, uint64_t>> Result;
429  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
430  Byte += 4) {
431  uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
432  uint64_t Off = 0;
433  // Check for optional bti c that prefixes adrp in BTI enabled entries
434  if (Insn == 0xd503245f) {
435  Off = 4;
436  Insn = support::endian::read32le(PltContents.data() + Byte + Off);
437  }
438  // Check for adrp.
439  if ((Insn & 0x9f000000) != 0x90000000)
440  continue;
441  Off += 4;
442  uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
443  (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
444  uint32_t Insn2 =
445  support::endian::read32le(PltContents.data() + Byte + Off);
446  // Check for: ldr Xt, [Xn, #pimm].
447  if (Insn2 >> 22 == 0x3e5) {
448  Imm += ((Insn2 >> 10) & 0xfff) << 3;
449  Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
450  Byte += 4;
451  }
452  }
453  return Result;
454  }
455 };
456 
457 } // end anonymous namespace
458 
460  return new AArch64MCInstrAnalysis(Info);
461 }
462 
463 // Force static initialization.
467  &getTheARM64_32Target()}) {
468  // Register the MC asm info.
470 
471  // Register the MC instruction info.
473 
474  // Register the MC register info.
476 
477  // Register the MC subtarget info.
479 
480  // Register the MC instruction analyzer.
482 
483  // Register the MC Code Emitter
485 
486  // Register the obj streamers.
490 
491  // Register the obj target streamer.
494 
495  // Register the asm streamer.
498  // Register the null streamer.
501 
502  // Register the MCInstPrinter.
504  }
505 
506  // Register the asm backend.
512 }
llvm::codeview::SimpleTypeKind::Byte
@ Byte
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:678
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::AArch64_MC::isQForm
bool isQForm(const MCInst &MI, const MCInstrInfo *MCII)
Definition: AArch64MCTargetDesc.cpp:303
createAArch64MCInstPrinter
static MCInstPrinter * createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64MCTargetDesc.cpp:358
MCCodeEmitter.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
createAArch64MCAsmInfo
static MCAsmInfo * createAArch64MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: AArch64MCTargetDesc.cpp:335
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1038
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:881
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AArch64MCAsmInfoDarwin
Definition: AArch64MCAsmInfo.h:24
llvm::createMachOStreamer
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
Definition: MCMachOStreamer.cpp:565
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::AArch64MCAsmInfoELF
Definition: AArch64MCAsmInfo.h:31
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAArch64AsmTargetStreamer
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: AArch64ELFStreamer.cpp:302
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:988
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
createWinCOFFStreamer
static MCStreamer * createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: AArch64MCTargetDesc.cpp:392
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1005
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:161
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:592
llvm::createAArch64ObjectTargetStreamer
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: AArch64TargetStreamer.cpp:113
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Emitter
dxil DXContainer Global Emitter
Definition: DXContainerGlobals.cpp:67
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:673
llvm::AArch64MCAsmInfoGNUCOFF
Definition: AArch64MCAsmInfo.h:39
MCAsmBackend.h
AArch64ELFStreamer.h
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
createAArch64MCRegisterInfo
static MCRegisterInfo * createAArch64MCRegisterInfo(const Triple &Triple)
Definition: AArch64MCTargetDesc.cpp:328
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:686
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
AArch64MCAsmInfo.h
CodeView.h
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:354
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1178
llvm::MCCFIInstruction
Definition: MCDwarf.h:478
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::createAArch64WinCOFFStreamer
MCWinCOFFStreamer * createAArch64WinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: AArch64WinCOFFStreamer.cpp:290
AArch64AddressingModes.h
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::createAArch64NullTargetStreamer
MCTargetStreamer * createAArch64NullTargetStreamer(MCStreamer &S)
Definition: AArch64TargetStreamer.cpp:123
llvm::AArch64AppleInstPrinter
Definition: AArch64InstPrinter.h:238
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:935
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition: TargetRegistry.h:1009
uint64_t
LLVMInitializeAArch64TargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC()
Definition: AArch64MCTargetDesc.cpp:464
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1044
MCRegisterInfo.h
llvm::AArch64MCAsmInfoMicrosoftCOFF
Definition: AArch64MCAsmInfo.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:519
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
llvm::createAArch64beAsmBackend
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AArch64AsmBackend.cpp:773
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:908
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::AArch64_MC::isFpOrNEON
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII)
Definition: AArch64MCTargetDesc.cpp:310
llvm::ArrayRef< uint8_t >
MCInstrAnalysis.h
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1716
AArch64InstPrinter.h
llvm::AArch64InstPrinter
Definition: AArch64InstPrinter.h:23
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: AArch64MCTargetDesc.cpp:66
llvm::createELFStreamer
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Definition: MCELFStreamer.cpp:887
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:875
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:1001
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:130
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:895
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1013
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
AArch64MCTargetDesc.h
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1033
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
createAArch64InstrAnalysis
static MCInstrAnalysis * createAArch64InstrAnalysis(const MCInstrInfo *Info)
Definition: AArch64MCTargetDesc.cpp:459
createAArch64MCSubtargetInfo
static MCSubtargetInfo * createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition: AArch64MCTargetDesc.cpp:53
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
AArch64WinCOFFStreamer.h
createAArch64MCInstrInfo
static MCInstrInfo * createAArch64MCInstrInfo()
Definition: AArch64MCTargetDesc.cpp:46
Endian.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::createAArch64leAsmBackend
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AArch64AsmBackend.cpp:753
llvm::createAArch64MCCodeEmitter
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: AArch64MCCodeEmitter.cpp:722
llvm::createAArch64ELFStreamer
MCELFStreamer * createAArch64ELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
Definition: AArch64ELFStreamer.cpp:308
AArch64TargetInfo.h