9#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
10#define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
18class MachineRegisterInfo;
26std::pair<Register, unsigned>
28 GISelKnownBits *KnownBits =
nullptr,
29 bool CheckNUW =
false);
unsigned const MachineRegisterInfo * MRI
bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty)
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr, bool CheckNUW=false)
Returns base register and constant offset.
This is an optimization pass for GlobalISel generic memory operations.