LLVM  13.0.0git
AMDGPUGlobalISelUtils.h
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1 //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
11 
12 #include "llvm/ADT/ArrayRef.h"
13 #include "llvm/CodeGen/Register.h"
14 #include <utility>
15 
16 namespace llvm {
17 
18 class MachineRegisterInfo;
19 
20 namespace AMDGPU {
21 
22 /// Returns base register and constant offset.
23 std::pair<Register, unsigned>
24 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg);
25 
26 bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask);
27 
28 }
29 }
30 
31 #endif
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AMDGPU::getBaseWithConstantOffset
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
Returns base register and constant offset.
Definition: AMDGPUGlobalISelUtils.cpp:17
ArrayRef.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::isLegalVOP3PShuffleMask
bool isLegalVOP3PShuffleMask(ArrayRef< int > Mask)
Definition: AMDGPUGlobalISelUtils.cpp:61
Register.h