LLVM  13.0.0git
AccelTable.h
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1 //==- include/llvm/CodeGen/AccelTable.h - Accelerator Tables -----*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file contains support for writing accelerator tables.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_ACCELTABLE_H
14 #define LLVM_CODEGEN_ACCELTABLE_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringMap.h"
19 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/DIE.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/Allocator.h"
25 #include "llvm/Support/DJB.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Format.h"
29 #include <cstddef>
30 #include <cstdint>
31 #include <vector>
32 
33 /// \file
34 /// The DWARF and Apple accelerator tables are an indirect hash table optimized
35 /// for null lookup rather than access to known data. The Apple accelerator
36 /// tables are a precursor of the newer DWARF v5 accelerator tables. Both
37 /// formats share common design ideas.
38 ///
39 /// The Apple accelerator table are output into an on-disk format that looks
40 /// like this:
41 ///
42 /// .------------------.
43 /// | HEADER |
44 /// |------------------|
45 /// | BUCKETS |
46 /// |------------------|
47 /// | HASHES |
48 /// |------------------|
49 /// | OFFSETS |
50 /// |------------------|
51 /// | DATA |
52 /// `------------------'
53 ///
54 /// The header contains a magic number, version, type of hash function,
55 /// the number of buckets, total number of hashes, and room for a special struct
56 /// of data and the length of that struct.
57 ///
58 /// The buckets contain an index (e.g. 6) into the hashes array. The hashes
59 /// section contains all of the 32-bit hash values in contiguous memory, and the
60 /// offsets contain the offset into the data area for the particular hash.
61 ///
62 /// For a lookup example, we could hash a function name and take it modulo the
63 /// number of buckets giving us our bucket. From there we take the bucket value
64 /// as an index into the hashes table and look at each successive hash as long
65 /// as the hash value is still the same modulo result (bucket value) as earlier.
66 /// If we have a match we look at that same entry in the offsets table and grab
67 /// the offset in the data for our final match.
68 ///
69 /// The DWARF v5 accelerator table consists of zero or more name indices that
70 /// are output into an on-disk format that looks like this:
71 ///
72 /// .------------------.
73 /// | HEADER |
74 /// |------------------|
75 /// | CU LIST |
76 /// |------------------|
77 /// | LOCAL TU LIST |
78 /// |------------------|
79 /// | FOREIGN TU LIST |
80 /// |------------------|
81 /// | HASH TABLE |
82 /// |------------------|
83 /// | NAME TABLE |
84 /// |------------------|
85 /// | ABBREV TABLE |
86 /// |------------------|
87 /// | ENTRY POOL |
88 /// `------------------'
89 ///
90 /// For the full documentation please refer to the DWARF 5 standard.
91 ///
92 ///
93 /// This file defines the class template AccelTable, which is represents an
94 /// abstract view of an Accelerator table, without any notion of an on-disk
95 /// layout. This class is parameterized by an entry type, which should derive
96 /// from AccelTableData. This is the type of individual entries in the table,
97 /// and it should store the data necessary to emit them. AppleAccelTableData is
98 /// the base class for Apple Accelerator Table entries, which have a uniform
99 /// structure based on a sequence of Atoms. There are different sub-classes
100 /// derived from AppleAccelTable, which differ in the set of Atoms and how they
101 /// obtain their values.
102 ///
103 /// An Apple Accelerator Table can be serialized by calling emitAppleAccelTable
104 /// function.
105 
106 namespace llvm {
107 
108 class AsmPrinter;
109 class DwarfCompileUnit;
110 class DwarfDebug;
111 
112 /// Interface which the different types of accelerator table data have to
113 /// conform. It serves as a base class for different values of the template
114 /// argument of the AccelTable class template.
116 public:
117  virtual ~AccelTableData() = default;
118 
119  bool operator<(const AccelTableData &Other) const {
120  return order() < Other.order();
121  }
122 
123  // Subclasses should implement:
124  // static uint32_t hash(StringRef Name);
125 
126 #ifndef NDEBUG
127  virtual void print(raw_ostream &OS) const = 0;
128 #endif
129 protected:
130  virtual uint64_t order() const = 0;
131 };
132 
133 /// A base class holding non-template-dependant functionality of the AccelTable
134 /// class. Clients should not use this class directly but rather instantiate
135 /// AccelTable with a type derived from AccelTableData.
137 public:
139 
140  /// Represents a group of entries with identical name (and hence, hash value).
141  struct HashData {
144  std::vector<AccelTableData *> Values;
146 
148  : Name(Name), HashValue(Hash(Name.getString())) {}
149 
150 #ifndef NDEBUG
151  void print(raw_ostream &OS) const;
152  void dump() const { print(dbgs()); }
153 #endif
154  };
155  using HashList = std::vector<HashData *>;
156  using BucketList = std::vector<HashList>;
157 
158 protected:
159  /// Allocator for HashData and Values.
161 
164 
168 
171 
172  void computeBucketCount();
173 
175 
176 public:
179  uint32_t getBucketCount() const { return BucketCount; }
181  uint32_t getUniqueNameCount() const { return Entries.size(); }
182 
183 #ifndef NDEBUG
184  void print(raw_ostream &OS) const;
185  void dump() const { print(dbgs()); }
186 #endif
187 
188  AccelTableBase(const AccelTableBase &) = delete;
189  void operator=(const AccelTableBase &) = delete;
190 };
191 
192 /// This class holds an abstract representation of an Accelerator Table,
193 /// consisting of a sequence of buckets, each bucket containint a sequence of
194 /// HashData entries. The class is parameterized by the type of entries it
195 /// holds. The type template parameter also defines the hash function to use for
196 /// hashing names.
197 template <typename DataT> class AccelTable : public AccelTableBase {
198 public:
199  AccelTable() : AccelTableBase(DataT::hash) {}
200 
201  template <typename... Types>
202  void addName(DwarfStringPoolEntryRef Name, Types &&... Args);
203 };
204 
205 template <typename AccelTableDataT>
206 template <typename... Types>
208  Types &&... Args) {
209  assert(Buckets.empty() && "Already finalized!");
210  // If the string is in the list already then add this die to the list
211  // otherwise add a new one.
212  auto Iter = Entries.try_emplace(Name.getString(), Name, Hash).first;
213  assert(Iter->second.Name == Name);
214  Iter->second.Values.push_back(
215  new (Allocator) AccelTableDataT(std::forward<Types>(Args)...));
216 }
217 
218 /// A base class for different implementations of Data classes for Apple
219 /// Accelerator Tables. The columns in the table are defined by the static Atoms
220 /// variable defined on the subclasses.
222 public:
223  /// An Atom defines the form of the data in an Apple accelerator table.
224  /// Conceptually it is a column in the accelerator consisting of a type and a
225  /// specification of the form of its data.
226  struct Atom {
227  /// Atom Type.
228  const uint16_t Type;
229  /// DWARF Form.
230  const uint16_t Form;
231 
233 
234 #ifndef NDEBUG
235  void print(raw_ostream &OS) const;
236  void dump() const { print(dbgs()); }
237 #endif
238  };
239  // Subclasses should define:
240  // static constexpr Atom Atoms[];
241 
242  virtual void emit(AsmPrinter *Asm) const = 0;
243 
244  static uint32_t hash(StringRef Buffer) { return djbHash(Buffer); }
245 };
246 
247 /// The Data class implementation for DWARF v5 accelerator table. Unlike the
248 /// Apple Data classes, this class is just a DIE wrapper, and does not know to
249 /// serialize itself. The complete serialization logic is in the
250 /// emitDWARF5AccelTable function.
252 public:
254 
256 
257 #ifndef NDEBUG
258  void print(raw_ostream &OS) const override;
259 #endif
260 
261  const DIE &getDie() const { return Die; }
262  uint64_t getDieOffset() const { return Die.getOffset(); }
263  unsigned getDieTag() const { return Die.getTag(); }
264 
265 protected:
266  const DIE &Die;
267 
268  uint64_t order() const override { return Die.getOffset(); }
269 };
270 
272 public:
274 
276  unsigned CUIndex)
278 
279 #ifndef NDEBUG
280  void print(raw_ostream &OS) const override;
281 #endif
282 
283  uint64_t getDieOffset() const { return DieOffset; }
284  unsigned getDieTag() const { return DieTag; }
285  unsigned getCUIndex() const { return CUIndex; }
286 
287 protected:
288  uint64_t DieOffset;
289  unsigned DieTag;
290  unsigned CUIndex;
291 
292  uint64_t order() const override { return DieOffset; }
293 };
294 
295 void emitAppleAccelTableImpl(AsmPrinter *Asm, AccelTableBase &Contents,
296  StringRef Prefix, const MCSymbol *SecBegin,
297  ArrayRef<AppleAccelTableData::Atom> Atoms);
298 
299 /// Emit an Apple Accelerator Table consisting of entries in the specified
300 /// AccelTable. The DataT template parameter should be derived from
301 /// AppleAccelTableData.
302 template <typename DataT>
304  StringRef Prefix, const MCSymbol *SecBegin) {
305  static_assert(std::is_convertible<DataT *, AppleAccelTableData *>::value, "");
306  emitAppleAccelTableImpl(Asm, Contents, Prefix, SecBegin, DataT::Atoms);
307 }
308 
309 void emitDWARF5AccelTable(AsmPrinter *Asm,
310  AccelTable<DWARF5AccelTableData> &Contents,
311  const DwarfDebug &DD,
312  ArrayRef<std::unique_ptr<DwarfCompileUnit>> CUs);
313 
315  AsmPrinter *Asm, AccelTable<DWARF5AccelTableStaticData> &Contents,
316  ArrayRef<MCSymbol *> CUs,
317  llvm::function_ref<unsigned(const DWARF5AccelTableStaticData &)>
318  getCUIndexForEntry);
319 
320 /// Accelerator table data implementation for simple Apple accelerator tables
321 /// with just a DIE reference.
323 public:
325 
326  void emit(AsmPrinter *Asm) const override;
327 
328  static constexpr Atom Atoms[] = {
329  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4)};
330 
331 #ifndef NDEBUG
332  void print(raw_ostream &OS) const override;
333 #endif
334 protected:
335  uint64_t order() const override { return Die.getOffset(); }
336 
337  const DIE &Die;
338 };
339 
340 /// Accelerator table data implementation for Apple type accelerator tables.
342 public:
344 
345  void emit(AsmPrinter *Asm) const override;
346 
347  static constexpr Atom Atoms[] = {
348  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4),
349  Atom(dwarf::DW_ATOM_die_tag, dwarf::DW_FORM_data2),
350  Atom(dwarf::DW_ATOM_type_flags, dwarf::DW_FORM_data1)};
351 
352 #ifndef NDEBUG
353  void print(raw_ostream &OS) const override;
354 #endif
355 };
356 
357 /// Accelerator table data implementation for simple Apple accelerator tables
358 /// with a DIE offset but no actual DIE pointer.
360 public:
362 
363  void emit(AsmPrinter *Asm) const override;
364 
365  static constexpr Atom Atoms[] = {
366  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4)};
367 
368 #ifndef NDEBUG
369  void print(raw_ostream &OS) const override;
370 #endif
371 protected:
372  uint64_t order() const override { return Offset; }
373 
375 };
376 
377 /// Accelerator table data implementation for type accelerator tables with
378 /// a DIE offset but no actual DIE pointer.
380 public:
387 
388  void emit(AsmPrinter *Asm) const override;
389 
390  static constexpr Atom Atoms[] = {
391  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4),
392  Atom(dwarf::DW_ATOM_die_tag, dwarf::DW_FORM_data2),
393  Atom(5, dwarf::DW_FORM_data1), Atom(6, dwarf::DW_FORM_data4)};
394 
395 #ifndef NDEBUG
396  void print(raw_ostream &OS) const override;
397 #endif
398 protected:
399  uint64_t order() const override { return Offset; }
400 
404 };
405 
406 } // end namespace llvm
407 
408 #endif // LLVM_CODEGEN_ACCELTABLE_H
MipsGenSubtargetInfo
Signposts
static ManagedStatic< SignpostEmitter > Signposts
Allows llvm::Timer to emit signposts when supported.
Definition: Timer.cpp:53
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:490
block
we get the following basic block
Definition: README_ALTIVEC.txt:95
llvm::objcarc::ARCInstKind::User
@ User
could "use" a pointer
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should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
llvm::DWARF5AccelTableStaticData::order
uint64_t order() const override
Definition: AccelTable.h:292
ARCGenRegisterInfo
llvm::AccelTableBase::HashData::dump
void dump() const
Definition: AccelTable.h:152
llvm::DWARF5AccelTableStaticData::DieTag
unsigned DieTag
Definition: AccelTable.h:289
llvm
Definition: AllocatorList.h:23
llvm::AccelTableBase::getBucketCount
uint32_t getBucketCount() const
Definition: AccelTable.h:179
llvm::dwarf::Constants
Constants
Definition: Dwarf.h:427
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
LiveDebugValues
Generic LiveDebugValues pass.
Definition: LiveDebugValues.cpp:39
Pass
print lazy value Lazy Value Info Printer Pass
Definition: LazyValueInfo.cpp:1947
llvm::lltok::Error
@ Error
Definition: LLToken.h:21
LanaiGenSubtargetInfo
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:623
DJB.h
llvm::object::RelocationResolver
uint64_t(*)(uint64_t Type, uint64_t Offset, uint64_t S, uint64_t LocData, int64_t Addend) RelocationResolver
Definition: RelocationResolver.h:37
ARMGenSubtargetInfo
llvm::AccelTableKind::Dwarf
@ Dwarf
DWARF v5 .debug_names.
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:164
llvm::AccelTableBase::UniqueHashCount
uint32_t UniqueHashCount
Definition: AccelTable.h:167
MSP430GenInstrInfo
cpp
test_demangle cpp
Definition: README.txt:46
llvm::AppleAccelTableStaticOffsetData::Offset
uint32_t Offset
Definition: AccelTable.h:374
LanaiGenInstrInfo
StringRef.h
llvm::AppleAccelTableData::Atom::Form
const uint16_t Form
DWARF Form.
Definition: AccelTable.h:230
llvm::dwarf::DW_ATOM_die_offset
@ DW_ATOM_die_offset
Marker as the end of a list of atoms.
Definition: Dwarf.h:504
XCoreGenRegisterInfo
it
Reference model for inliner Oz decision policy Note this model is also referenced by test Transforms Inline ML tests if replacing it
Definition: README.txt:3
llvm::DWARF5AccelTableStaticData::DieOffset
uint64_t DieOffset
Definition: AccelTable.h:288
llvm::Statistic
TrackingStatistic Statistic
Definition: Statistic.h:159
llvm::AliasAnalysis
AAResults AliasAnalysis
Temporary typedef for legacy code that uses a generic AliasAnalysis pointer or reference.
Definition: AliasAnalysis.h:944
SparcGenSubtargetInfo
AArch64GenRegisterInfo
tools
The object format emitted by the WebAssembly backed is documented see the home tools
Definition: README.txt:16
td
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo td
Definition: README_P9.txt:166
MSP430GenSubtargetInfo
llvm::AccelTableBase::Hash
HashFn * Hash
Definition: AccelTable.h:165
llvm::AccelTable::addName
void addName(DwarfStringPoolEntryRef Name, Types &&... Args)
Definition: AccelTable.h:207
Allocator.h
MSP430GenRegisterInfo
llvm::CGSCCPassManager
PassManager< LazyCallGraph::SCC, CGSCCAnalysisManager, LazyCallGraph &, CGSCCUpdateResult & > CGSCCPassManager
The CGSCC pass manager.
Definition: CGSCCPassManager.h:150
llvm::lltok::APSInt
@ APSInt
Definition: LLToken.h:491
Passes
const char * Passes
Definition: PassBuilderBindings.cpp:46
to
Should compile to
Definition: README.txt:449
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
Instructions
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions
Definition: MSA.txt:11
llvm::AppleAccelTableStaticTypeData::ObjCClassIsImplementation
bool ObjCClassIsImplementation
Definition: AccelTable.h:403
Analysis
block Block Frequency Analysis
Definition: BlockFrequencyInfo.cpp:302
AMDGPUSubtarget
#define AMDGPUSubtarget
Definition: AMDGPUInstructionSelector.cpp:40
llvm::AccelTableBase::Hashes
HashList Hashes
Definition: AccelTable.h:169
llvm::AppleAccelTableData::Atom::dump
void dump() const
Definition: AccelTable.h:236
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
SystemZGenInstrInfo
LanaiGenRegisterInfo
impl
place backedge safepoints impl
Definition: PlaceSafepoints.cpp:612
llvm::AccelTableBase::Entries
StringEntries Entries
Definition: AccelTable.h:163
llvm::DIE
A structured debug information entry.
Definition: DIE.h:739
llvm::AppleAccelTableTypeData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:694
llvm::AccelTable
This class holds an abstract representation of an Accelerator Table, consisting of a sequence of buck...
Definition: AccelTable.h:197
patch
this could be done in SelectionDAGISel along with other special bytes It would be nice to revert this patch
Definition: README.txt:104
llvm::DIE::getTag
dwarf::Tag getTag() const
Definition: DIE.h:775
llvm::DWARF5AccelTableStaticData::CUIndex
unsigned CUIndex
Definition: AccelTable.h:290
llvm::msgpack::Type::Binary
@ Binary
intrinsic
QP Compare Ordered outs ins xscmpudp No intrinsic
Definition: README_P9.txt:303
llvm::AppleAccelTableOffsetData::AppleAccelTableOffsetData
AppleAccelTableOffsetData(const DIE &D)
Definition: AccelTable.h:324
Format.h
and
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 and
Definition: README.txt:1271
x86
Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On x86
Definition: README.txt:318
SpecialSubKind::allocator
@ allocator
llvm::AppleAccelTableData::Atom::Atom
constexpr Atom(uint16_t Type, uint16_t Form)
Definition: AccelTable.h:232
llvm::WinEH::EncodingType::ARM
@ ARM
Windows AXP64.
llvm::AccelTableData::order
virtual uint64_t order() const =0
llvm::AccelTableData
Interface which the different types of accelerator table data have to conform.
Definition: AccelTable.h:115
RISCVGenInstrInfo
endif
__FakeVCSRevision h endif() endif() set(generated_files "$
Definition: CMakeLists.txt:16
llvm::AppleAccelTableStaticTypeData::order
uint64_t order() const override
Definition: AccelTable.h:399
llvm::DwarfStringPoolEntryRef
String pool entry reference.
Definition: DwarfStringPoolEntry.h:31
R600GenInstrInfo
Interval
std::pair< uint32_t, uint32_t > Interval
Definition: MappedBlockStream.cpp:38
AVRGenSubtargetInfo
attrs
function attrs
Definition: FunctionAttrs.cpp:1679
llvm::AccelTableBase::operator=
void operator=(const AccelTableBase &)=delete
HexagonGenInstrInfo
XCoreGenSubtargetInfo
llvm::AppleAccelTableStaticOffsetData::order
uint64_t order() const override
Definition: AccelTable.h:372
llvm::AccelTableData::operator<
bool operator<(const AccelTableData &Other) const
Definition: AccelTable.h:119
llvm::AccelTableBase::computeBucketCount
void computeBucketCount()
Definition: AccelTable.cpp:34
X86GenRegisterInfo
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::DWARF5AccelTableData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:680
VEGenSubtargetInfo
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::emitAppleAccelTable
void emitAppleAccelTable(AsmPrinter *Asm, AccelTable< DataT > &Contents, StringRef Prefix, const MCSymbol *SecBegin)
Emit an Apple Accelerator Table consisting of entries in the specified AccelTable.
Definition: AccelTable.h:303
BranchRelaxation
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
AArch64GenInstrInfo
MipsGenRegisterInfo
llvm::MODULE
@ MODULE
Definition: Attributor.h:3861
llvm::orc::tpctypes::LookupResult
std::vector< JITTargetAddress > LookupResult
Definition: TargetProcessControlTypes.h:62
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1094
llvm::AppleAccelTableStaticTypeData::Tag
uint16_t Tag
Definition: AccelTable.h:402
llvm::cl::apply
void apply(Opt *O, const Mod &M, const Mods &... Ms)
Definition: CommandLine.h:1308
llvm::AppleAccelTableStaticTypeData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:608
AVRGenInstrInfo
llvm::AppleAccelTableData::emit
virtual void emit(AsmPrinter *Asm) const =0
llvm::AccelTableBase::AccelTableBase
AccelTableBase(HashFn *Hash)
Definition: AccelTable.h:174
llvm::dwarf::DW_ATOM_die_tag
@ DW_ATOM_die_tag
Definition: Dwarf.h:507
llvm::AppleAccelTableData::Atom
An Atom defines the form of the data in an Apple accelerator table.
Definition: AccelTable.h:226
LoopPredication
static cl::opt< bool > LoopPredication("indvars-predicate-loops", cl::Hidden, cl::init(true), cl::desc("Predicate conditions in read only loops"))
BPFGenSubtargetInfo
llvm::AccelTableBase::HashData
Represents a group of entries with identical name (and hence, hash value).
Definition: AccelTable.h:141
llvm::AppleAccelTableData::hash
static uint32_t hash(StringRef Buffer)
Definition: AccelTable.h:244
X86GenInstrInfo
MCSymbol.h
t
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
Definition: README-SSE.txt:788
llvm::AccelTableBase::Allocator
BumpPtrAllocator Allocator
Allocator for HashData and Values.
Definition: AccelTable.h:160
llvm::AppleAccelTableStaticOffsetData
Accelerator table data implementation for simple Apple accelerator tables with a DIE offset but no ac...
Definition: AccelTable.h:359
M68kGenInstrInfo
group
bb420 i The CBE manages to mtctr r0 r11 stbx r9 addi bdz later b loop This could be much the loop would be a single dispatch group
Definition: README.txt:61
NVPTXGenInstrInfo
opt
arm prera ldst opt
Definition: ARMLoadStoreOptimizer.cpp:2191
llvm::AppleAccelTableStaticOffsetData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:604
ARMGenRegisterInfo
be
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can be
Definition: README.txt:14
AArch64GenSubtargetInfo
llvm::AccelTable::AccelTable
AccelTable()
Definition: AccelTable.h:199
InlineInfo
@ InlineInfo
Definition: FunctionInfo.cpp:24
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
HexagonGenSubtargetInfo
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
Threading
jump Jump Threading
Definition: JumpThreading.cpp:175
llvm::zlib::compress
Error compress(StringRef InputBuffer, SmallVectorImpl< char > &CompressedBuffer, int Level=DefaultCompression)
Definition: Compression.cpp:49
llvm::AppleAccelTableStaticOffsetData::AppleAccelTableStaticOffsetData
AppleAccelTableStaticOffsetData(uint32_t Offset)
Definition: AccelTable.h:361
Annotation2Metadata
Annotation2Metadata
Definition: Annotation2Metadata.cpp:96
Bitcode
write Write Bitcode
Definition: BitcodeWriterPass.cpp:74
llvm::AccelTableBase::HashData::HashValue
uint32_t HashValue
Definition: AccelTable.h:143
DwarfStringPoolEntry.h
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:744
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:622
StringMap.h
llvm::AccelTableBase::HashData::Sym
MCSymbol * Sym
Definition: AccelTable.h:145
BPFGenRegisterInfo
llvm::AccelTableBase
A base class holding non-template-dependant functionality of the AccelTable class.
Definition: AccelTable.h:136
list
serve action InlinerSizeModel llvm::InlinerSizeModel list(APPEND GeneratedMLSources ${GENERATED_HEADERS}) endif() if(DEFINED LLVM_HAVE_TF_API) endif() endif() add_llvm_component_library(LLVMAnalysis AliasAnalysis.cpp AliasAnalysisEvaluator.cpp AliasAnalysisSummary.cpp AliasSetTracker.cpp Analysis.cpp AssumeBundleQueries.cpp AssumptionCache.cpp BasicAliasAnalysis.cpp BlockFrequencyInfo.cpp BlockFrequencyInfoImpl.cpp BranchProbabilityInfo.cpp CFG.cpp CFGPrinter.cpp CFLAndersAliasAnalysis.cpp CFLSteensAliasAnalysis.cpp CGSCCPassManager.cpp CallGraph.cpp CallGraphSCCPass.cpp CallPrinter.cpp CaptureTracking.cpp CmpInstAnalysis.cpp CostModel.cpp CodeMetrics.cpp ConstantFolding.cpp DDG.cpp DDGPrinter.cpp ConstraintSystem.cpp Delinearization.cpp DemandedBits.cpp DependenceAnalysis.cpp DependenceGraphBuilder.cpp DevelopmentModeInlineAdvisor.cpp DivergenceAnalysis.cpp DomPrinter.cpp DomTreeUpdater.cpp DominanceFrontier.cpp EHPersonalities.cpp FunctionPropertiesAnalysis.cpp GlobalsModRef.cpp GuardUtils.cpp HeatUtils.cpp IRSimilarityIdentifier.cpp IVDescriptors.cpp IVUsers.cpp ImportedFunctionsInliningStatistics.cpp IndirectCallPromotionAnalysis.cpp InlineCost.cpp InlineAdvisor.cpp InlineSizeEstimatorAnalysis.cpp InstCount.cpp InstructionPrecedenceTracking.cpp InstructionSimplify.cpp Interval.cpp IntervalPartition.cpp LazyBranchProbabilityInfo.cpp LazyBlockFrequencyInfo.cpp LazyCallGraph.cpp LazyValueInfo.cpp LegacyDivergenceAnalysis.cpp Lint.cpp Loads.cpp LoopAccessAnalysis.cpp LoopAnalysisManager.cpp LoopCacheAnalysis.cpp LoopNestAnalysis.cpp LoopUnrollAnalyzer.cpp LoopInfo.cpp LoopPass.cpp MLInlineAdvisor.cpp MemDepPrinter.cpp MemDerefPrinter.cpp MemoryBuiltins.cpp MemoryDependenceAnalysis.cpp MemoryLocation.cpp MemorySSA.cpp MemorySSAUpdater.cpp ModuleDebugInfoPrinter.cpp ModuleSummaryAnalysis.cpp MustExecute.cpp ObjCARCAliasAnalysis.cpp ObjCARCAnalysisUtils.cpp ObjCARCInstKind.cpp OptimizationRemarkEmitter.cpp OverflowInstAnalysis.cpp PHITransAddr.cpp PhiValues.cpp PostDominators.cpp ProfileSummaryInfo.cpp PtrUseVisitor.cpp RegionInfo.cpp RegionPass.cpp RegionPrinter.cpp ReleaseModeModelRunner.cpp ReplayInlineAdvisor.cpp ScalarEvolution.cpp ScalarEvolutionAliasAnalysis.cpp ScalarEvolutionDivision.cpp ScalarEvolutionNormalization.cpp StackLifetime.cpp StackSafetyAnalysis.cpp SyncDependenceAnalysis.cpp SyntheticCountsUtils.cpp TFUtils.cpp TargetLibraryInfo.cpp TargetTransformInfo.cpp Trace.cpp TypeBasedAliasAnalysis.cpp TypeMetadataUtils.cpp ScopedNoAliasAA.cpp ValueLattice.cpp ValueLatticeUtils.cpp ValueTracking.cpp VectorUtils.cpp VFABIDemangling.cpp $
Definition: CMakeLists.txt:8
llvm::NVPTX::PTXLdStInstCode::Scalar
@ Scalar
Definition: NVPTX.h:122
c
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
Definition: README.txt:418
llvm::emitAppleAccelTableImpl
void emitAppleAccelTableImpl(AsmPrinter *Asm, AccelTableBase &Contents, StringRef Prefix, const MCSymbol *SecBegin, ArrayRef< AppleAccelTableData::Atom > Atoms)
Definition: AccelTable.cpp:539
only
dot regions only
Definition: RegionPrinter.cpp:205
add_subdirectory
add_subdirectory(IR) add_subdirectory(Support) add_subdirectory(Frontend) if(NOT "$
Definition: CMakeLists.txt:1
add_pdb_impl_folder
diaguids lib LIBPDB_ADDITIONAL_LIBRARIES add_pdb_impl_folder(DIA DIA/DIADataStream.cpp DIA/DIAEnumDebugStreams.cpp DIA/DIAEnumFrameData.cpp DIA/DIAEnumInjectedSources.cpp DIA/DIAEnumLineNumbers.cpp DIA/DIAEnumSectionContribs.cpp DIA/DIAEnumSourceFiles.cpp DIA/DIAEnumSymbols.cpp DIA/DIAEnumTables.cpp DIA/DIAError.cpp DIA/DIAFrameData.cpp DIA/DIAInjectedSource.cpp DIA/DIALineNumber.cpp DIA/DIARawSymbol.cpp DIA/DIASectionContrib.cpp DIA/DIASession.cpp DIA/DIASourceFile.cpp DIA/DIATable.cpp) set(LIBPDB_ADDITIONAL_HEADER_DIRS "$
Definition: CMakeLists.txt:19
llvm::LoopPassManager
PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager
The Loop pass manager.
Definition: LoopPassManager.h:201
NVPTXGenSubtargetInfo
include
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(DebugInfo) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
Definition: CMakeLists.txt:1
llvm::StringMap< HashData, BumpPtrAllocator & >
DIE.h
llvm::AppleAccelTableTypeData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:596
ARCGenInstrInfo
X86GenSubtargetInfo
llvm::AppleAccelTableTypeData::AppleAccelTableTypeData
AppleAccelTableTypeData(const DIE &D)
Definition: AccelTable.h:343
llvm::OutputFileType::Object
@ Object
PPCGenSubtargetInfo
WebAssemblyGenInstrInfo
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:168
llvm::DWARF5AccelTableStaticData::hash
static uint32_t hash(StringRef Name)
Definition: AccelTable.h:273
AMDGPURegBankCombinerHelper
Definition: AMDGPURegBankCombiner.cpp:32
llvm::AccelTableBase::print
void print(raw_ostream &OS) const
Definition: AccelTable.cpp:661
ARMGenInstrInfo
llvm::HighlightColor::Remark
@ Remark
Verifier
verify safepoint Safepoint IR Verifier
Definition: SafepointIRVerifier.cpp:253
llvm::DWARF5AccelTableData::getDieOffset
uint64_t getDieOffset() const
Definition: AccelTable.h:262
needed
We should do a little better with eliminating dead stores The stores to the stack are dead since a and b are not needed
Definition: README_ALTIVEC.txt:212
llvm::AccelTableBase::getUniqueNameCount
uint32_t getUniqueNameCount() const
Definition: AccelTable.h:181
AVRGenRegisterInfo
HexagonGenRegisterInfo
inc
Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these it can use inc
Definition: README.txt:1367
llvm::MachO::Architecture
Architecture
Defines the architecture slices that are supported by Text-based Stub files.
Definition: Architecture.h:27
llvm::remarks::Format::YAML
@ YAML
LICM
loop versioning Loop Versioning For LICM
Definition: LoopVersioningLICM.cpp:658
llvm::DWARF5AccelTableData::Die
const DIE & Die
Definition: AccelTable.h:266
llvm::AccelTableBase::BucketList
std::vector< HashList > BucketList
Definition: AccelTable.h:156
llvm::DWARF5AccelTableStaticData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:685
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1502
llvm::caseFoldingDjbHash
uint32_t caseFoldingDjbHash(StringRef Buffer, uint32_t H=5381)
Computes the Bernstein hash after folding the input according to the Dwarf 5 standard case folding ru...
Definition: DJB.cpp:71
llvm::AccelTableBase::HashData::Values
std::vector< AccelTableData * > Values
Definition: AccelTable.h:144
llvm::DWARF5AccelTableStaticData
Definition: AccelTable.h:271
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:67
llvm::DWARF5AccelTableData::getDie
const DIE & getDie() const
Definition: AccelTable.h:261
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::AppleAccelTableStaticTypeData::QualifiedNameHash
uint32_t QualifiedNameHash
Definition: AccelTable.h:401
Remarks
annotation Annotation Remarks
Definition: AnnotationRemarks.cpp:118
SystemZGenSubtargetInfo
R600GenRegisterInfo
I
#define I(x, y, z)
Definition: MD5.cpp:59
Debug
bool Debug
Definition: PassBuilderBindings.cpp:51
llvm::AppleAccelTableStaticOffsetData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:365
Magic
const char Magic[]
Definition: Archive.cpp:41
llvm::AccelTableBase::getUniqueHashCount
uint32_t getUniqueHashCount() const
Definition: AccelTable.h:180
ArrayRef.h
llvm::pdb::PDB_ReaderType::Native
@ Native
message
message(STATUS "Targeting ${t}") add_subdirectory($
Definition: CMakeLists.txt:31
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AppleAccelTableStaticTypeData::AppleAccelTableStaticTypeData
AppleAccelTableStaticTypeData(uint32_t Offset, uint16_t Tag, bool ObjCClassIsImplementation, uint32_t QualifiedNameHash)
Definition: AccelTable.h:381
MergedLoadStoreMotion
mldst MergedLoadStoreMotion
Definition: MergedLoadStoreMotion.cpp:409
llvm::AppleAccelTableStaticTypeData
Accelerator table data implementation for type accelerator tables with a DIE offset but no actual DIE...
Definition: AccelTable.h:379
removed
currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be removed
Definition: README.txt:1552
PreferPredicateTy::Option
Option
Definition: LoopVectorize.cpp:213
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:64
BPFGenInstrInfo
llvm::codeview::CodeViewContainer::ObjectFile
@ ObjectFile
VEGenRegisterInfo
register
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That when the encoding does not require two syntactical operands to refer to the same register
Definition: README.txt:726
llvm::StringMapImpl::size
unsigned size() const
Definition: StringMap.h:93
isel
amdgpu isel
Definition: AMDGPUISelDAGToDAG.cpp:375
add_llvm_component_library
add_llvm_component_library(LLVMAArch64Desc AArch64AsmBackend.cpp AArch64ELFObjectWriter.cpp AArch64ELFStreamer.cpp AArch64InstPrinter.cpp AArch64MCAsmInfo.cpp AArch64MCCodeEmitter.cpp AArch64MCExpr.cpp AArch64MCTargetDesc.cpp AArch64MachObjectWriter.cpp AArch64TargetStreamer.cpp AArch64WinCOFFObjectWriter.cpp AArch64WinCOFFStreamer.cpp LINK_COMPONENTS AArch64Info AArch64Utils MC BinaryFormat Support ADD_TO_COMPONENT AArch64) add_dependencies(LLVMAArch64Desc AArch64CommonTableGen) include_directories($
Definition: CMakeLists.txt:1
llvm::DWARF5AccelTableStaticData::getCUIndex
unsigned getCUIndex() const
Definition: AccelTable.h:285
llvm::AppleAccelTableData::Atom::Type
const uint16_t Type
Atom Type.
Definition: AccelTable.h:228
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::AppleAccelTableOffsetData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:690
llvm::AccelTableBase::Buckets
BucketList Buckets
Definition: AccelTable.h:170
Scheduler
Machine Instruction Scheduler
Definition: MachineScheduler.cpp:220
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Mips16HardFloat
static cl::opt< bool > Mips16HardFloat("mips16-hard-float", cl::NotHidden, cl::desc("Enable mips16 hard float."), cl::init(false))
RegUsageInfoCollector
RegUsageInfoCollector
Definition: RegUsageInfoCollector.cpp:73
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
Dwarf.h
llvm::AppleAccelTableStaticTypeData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:703
llvm::AppleAccelTableOffsetData::order
uint64_t order() const override
Definition: AccelTable.h:335
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::cl::Sink
@ Sink
Definition: CommandLine.h:171
llvm::FlattenCFG
bool FlattenCFG(BasicBlock *BB, AAResults *AA=nullptr)
This function is used to flatten a CFG.
Definition: FlattenCFG.cpp:543
VEGenInstrInfo
library
Itanium Name Demangler i e convert the string _Z1fv into but neither can depend on each other libcxxabi needs the demangler to implement which is part of the itanium ABI spec LLVM needs a copy for a bunch of but doesn t want to use the system s __cxa_demangle because it a might not be and b probably isn t that up to date on the latest language features The copy of the demangler in LLVM has some extra stuff that aren t needed in which depend on the shared generic components Despite these we want to keep the core generic demangling library identical between both copies to simplify development and testing If you re working on the generic library
Definition: README.txt:30
uint32_t
SparcGenRegisterInfo
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
llvm::DemoteRegToStack
AllocaInst * DemoteRegToStack(Instruction &X, bool VolatileLoads=false, Instruction *AllocaPoint=nullptr)
This function takes a virtual register computed by an Instruction and replaces it with a slot in the ...
Definition: DemoteRegToStack.cpp:23
AMDGPUGenInstrInfo
llvm::CloneFunction
Function * CloneFunction(Function *F, ValueToValueMapTy &VMap, ClonedCodeInfo *CodeInfo=nullptr)
Return a copy of the specified function and add it to that function's module.
Definition: CloneFunction.cpp:283
macro
macro(add_pdb_impl_folder group) list(APPEND PDB_IMPL_SOURCES $
Definition: CMakeLists.txt:1
ARCGenSubtargetInfo
llvm::AccelTableBase::dump
void dump() const
Definition: AccelTable.h:185
llvm::DWARF5AccelTableData
The Data class implementation for DWARF v5 accelerator table.
Definition: AccelTable.h:251
writer
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local $pop6 WebAssembly registers are implicitly initialized to zero Explicit zeroing is therefore often redundant and could be optimized away Small indices may use smaller encodings than large indices WebAssemblyRegColoring and or WebAssemblyRegRenumbering should sort registers according to their usage frequency to maximize the usage of smaller encodings Many cases of irreducible control flow could be transformed more optimally than via the transform in WebAssemblyFixIrreducibleControlFlow cpp It may also be worthwhile to do transforms before register particularly when duplicating to allow register coloring to be aware of the duplication WebAssemblyRegStackify could use AliasAnalysis to reorder loads and stores more aggressively WebAssemblyRegStackify is currently a greedy algorithm This means for a binary however wasm doesn t actually require this WebAssemblyRegStackify could be or possibly to take full advantage of what WebAssembly permits Add support for mergeable sections in the Wasm writer
Definition: README.txt:154
llvm::BuryPointer
void BuryPointer(const void *Ptr)
Definition: BuryPointer.cpp:15
WebAssemblyGenSubtargetInfo
llvm::DWARF5AccelTableData::getDieTag
unsigned getDieTag() const
Definition: AccelTable.h:263
llvm::cl::Optional
@ Optional
Definition: CommandLine.h:119
SparcGenInstrInfo
ConstantFold
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
Definition: SimplifyCFG.cpp:5206
llvm::pdb::PDB_DataKind::Local
@ Local
CFG
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to CFG
Definition: README.txt:39
Signals
static const int Signals[]
Definition: CrashRecoveryContext.cpp:345
llvm::DWARF5AccelTableStaticData::DWARF5AccelTableStaticData
DWARF5AccelTableStaticData(uint64_t DieOffset, unsigned DieTag, unsigned CUIndex)
Definition: AccelTable.h:275
PPCGenInstrInfo
AMDGPUGenSubtargetInfo
add_llvm_component_group
tools llvm config LibraryDependencies inc add_llvm_component_group(all-targets LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD}) add_llvm_component_group(Engine) if(TARGET $
Definition: CMakeLists.txt:47
llvm::AppleAccelTableData
A base class for different implementations of Data classes for Apple Accelerator Tables.
Definition: AccelTable.h:221
tables
we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this whole function isel would also handle this Investigate lowering of sparse switch statements into perfect hash tables
Definition: README.txt:439
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::AccelTableBase::getBuckets
ArrayRef< HashList > getBuckets() const
Definition: AccelTable.h:178
uint16_t
code
*Add support for compiling functions in both ARM and Thumb then taking the smallest *Add support for compiling individual basic blocks in thumb when in a larger ARM function This can be used for presumed cold code
Definition: README-Thumb.txt:9
can
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill can
Definition: README-SSE.txt:269
or
compiles or
Definition: README.txt:606
llvm::DWARF5AccelTableStaticData::getDieOffset
uint64_t getDieOffset() const
Definition: AccelTable.h:283
llvm::pdb::PDB_ReaderType::DIA
@ DIA
AMDGPUGenRegisterInfo
RISCVGenRegisterInfo
llvm::AppleAccelTableTypeData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:347
llvm::LoopRotation
bool LoopRotation(Loop *L, LoopInfo *LI, const TargetTransformInfo *TTI, AssumptionCache *AC, DominatorTree *DT, ScalarEvolution *SE, MemorySSAUpdater *MSSAU, const SimplifyQuery &SQ, bool RotationOnly, unsigned Threshold, bool IsUtilMode, bool PrepareForLTO=false)
Convert a loop into a loop with bottom test.
Definition: LoopRotationUtils.cpp:830
llvm::AppleAccelTableOffsetData
Accelerator table data implementation for simple Apple accelerator tables with just a DIE reference.
Definition: AccelTable.h:322
find_first_existing_vc_file
find_first_existing_vc_file("${LLVM_MAIN_SRC_DIR}" llvm_vc) set(version_inc "$
Definition: CMakeLists.txt:1
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
ppc
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including ppc
Definition: README.txt:567
PPCGenRegisterInfo
SystemZGenRegisterInfo
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
v3
we get the following basic r4 lvx v3
Definition: README_ALTIVEC.txt:95
Inliner
partial Partial Inliner
Definition: PartialInlining.cpp:1522
AMDGPUPostLegalizerCombinerHelper
Definition: AMDGPUPostLegalizerCombiner.cpp:32
llvm::DWARF5AccelTableData::hash
static uint32_t hash(StringRef Name)
Definition: AccelTable.h:253
R600GenSubtargetInfo
R600ExpandSpecialInstrs
R600ExpandSpecialInstrs
Definition: R600ExpandSpecialInstrs.cpp:51
llvm::AppleAccelTableOffsetData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:328
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::NVPTX::PTXLdStInstCode::GLOBAL
@ GLOBAL
Definition: NVPTX.h:109
llvm::sys::RWMutex
SmartRWMutex< false > RWMutex
Definition: RWMutex.h:162
llvm::AccelTableBase::HashData::HashData
HashData(DwarfStringPoolEntryRef Name, HashFn *Hash)
Definition: AccelTable.h:147
This
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical This
Definition: README.txt:418
set
VCSRevision h set(generate_vcs_version_script "${LLVM_CMAKE_PATH}/GenerateVersionFromVCS.cmake") if(LLVM_APPEND_VC_REV) set(llvm_source_dir $
Definition: CMakeLists.txt:6
WebAssemblyGenRegisterInfo
llvm::DWARF5AccelTableData::order
uint64_t order() const override
Definition: AccelTable.h:268
Evaluator
aa Exhaustive Alias Analysis Precision Evaluator
Definition: AliasAnalysisEvaluator.cpp:433
llvm::AppleAccelTableStaticTypeData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:390
llvm::DWARF5AccelTableStaticData::getDieTag
unsigned getDieTag() const
Definition: AccelTable.h:284
SmallVector.h
Currently
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C Currently
Definition: README-SSE.txt:89
AddressSanitizer
INITIALIZE_PASS(ASanGlobalsMetadataWrapperPass, "asan-globals-md", "Read metadata to mark which globals should be instrumented " "when running ASan.", false, true) char AddressSanitizerLegacyPass AddressSanitizer
Definition: AddressSanitizer.cpp:1283
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:146
llvm::LoopAnalysisManager
AnalysisManager< Loop, LoopStandardAnalysisResults & > LoopAnalysisManager
The loop analysis manager.
Definition: LoopAnalysisManager.h:75
llvm::CloneModule
std::unique_ptr< Module > CloneModule(const Module &M)
Return an exact copy of the specified module.
Definition: CloneModule.cpp:34
llvm::AccelTableData::~AccelTableData
virtual ~AccelTableData()=default
LineType::Metadata
@ Metadata
llvm::AccelTableBase::HashData::print
void print(raw_ostream &OS) const
Definition: AccelTable.cpp:648
llvm::AccelTableBase::BucketCount
uint32_t BucketCount
Definition: AccelTable.h:166
RISCVGenSubtargetInfo
LLVM
MIPS Relocation Principles In LLVM
Definition: Relocation.txt:3
llvm::AccelTableBase::HashFn
uint32_t(StringRef) HashFn
Definition: AccelTable.h:138
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::AppleAccelTableTypeData
Accelerator table data implementation for Apple type accelerator tables.
Definition: AccelTable.h:341
llvm::AccelTableBase::HashList
std::vector< HashData * > HashList
Definition: AccelTable.h:155
llvm::InlineFunction
InlineResult InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, AAResults *CalleeAAR=nullptr, bool InsertLifetime=true, Function *ForwardVarArgsTo=nullptr)
This function inlines the called function into the basic block of the caller.
Definition: InlineFunction.cpp:1757
lowering
amdgpu printf runtime AMDGPU Printf lowering
Definition: AMDGPUPrintfRuntimeBinding.cpp:87
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:49
source_group
source_group(${group} FILES ${ARGN}) endmacro() if(LLVM_ENABLE_DIA_SDK) include_directories($
Definition: CMakeLists.txt:3
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::AccelTableData::print
virtual void print(raw_ostream &OS) const =0
llvm::InliningAdvisorMode::Release
@ Release
llvm::AppleAccelTableStaticOffsetData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:699
XCoreGenInstrInfo
llvm::dwarf::DW_ATOM_type_flags
@ DW_ATOM_type_flags
Definition: Dwarf.h:508
llvm::djbHash
uint32_t djbHash(StringRef Buffer, uint32_t H=5381)
The Bernstein hash function used by the DWARF accelerator tables.
Definition: DJB.h:21
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::EngineKind::Interpreter
@ Interpreter
Definition: ExecutionEngine.h:526
matcher
Code Generation Notes for reduce the size of the ISel matcher
Definition: MSA.txt:5
llvm::AppleAccelTableOffsetData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:590
raw_ostream.h
llvm::DIE::getOffset
unsigned getOffset() const
Get the compile/type unit relative offset of this DIE.
Definition: DIE.h:777
llvm::AppleAccelTableData::Atom::print
void print(raw_ostream &OS) const
Definition: AccelTable.cpp:630
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::SplitModule
void SplitModule(Module &M, unsigned N, function_ref< void(std::unique_ptr< Module > MPart)> ModuleCallback, bool PreserveLocals=false)
Splits the module M into N linkable partitions.
Definition: SplitModule.cpp:248
MemorySSA
early cse Early CSE w MemorySSA
Definition: EarlyCSE.cpp:1735
packetizer
hexagon packetizer
Definition: HexagonVLIWPacketizer.cpp:130
llvm::DWARF5AccelTableData::DWARF5AccelTableData
DWARF5AccelTableData(const DIE &Die)
Definition: AccelTable.h:255
Debug.h
MipsGenInstrInfo
M68kGenSubtargetInfo
llvm::AccelTableBase::finalize
void finalize(AsmPrinter *Asm, StringRef Prefix)
Definition: AccelTable.cpp:54
gen
pgo instr gen
Definition: PGOInstrumentation.cpp:480
NVPTXGenRegisterInfo
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:165
SpecialSubKind::string
@ string
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1169
M68kGenRegisterInfo
llvm::irsymtab::build
Error build(ArrayRef< Module * > Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)
Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.
Definition: IRSymtab.cpp:351
llvm::AppleAccelTableOffsetData::Die
const DIE & Die
Definition: AccelTable.h:337
llvm::AccelTableBase::HashData::Name
DwarfStringPoolEntryRef Name
Definition: AccelTable.h:142
llvm::emitDWARF5AccelTable
void emitDWARF5AccelTable(AsmPrinter *Asm, AccelTable< DWARF5AccelTableData > &Contents, const DwarfDebug &DD, ArrayRef< std::unique_ptr< DwarfCompileUnit >> CUs)
Definition: AccelTable.cpp:546