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13 #ifndef LLVM_CODEGEN_ACCELTABLE_H
14 #define LLVM_CODEGEN_ACCELTABLE_H
105 class DwarfCompileUnit;
199 template <
typename... Types>
203 template <
typename AccelTableDataT>
204 template <
typename... Types>
207 assert(Buckets.empty() &&
"Already finalized!");
210 auto Iter = Entries.try_emplace(Name.getString(), Name, Hash).first;
211 assert(Iter->second.Name == Name);
212 Iter->second.Values.push_back(
213 new (
Allocator) AccelTableDataT(std::forward<Types>(
Args)...));
295 ArrayRef<AppleAccelTableData::Atom> Atoms);
300 template <
typename DataT>
303 static_assert(std::is_convertible<DataT *, AppleAccelTableData *>::value);
308 AccelTable<DWARF5AccelTableData> &Contents,
309 const DwarfDebug &DD,
310 ArrayRef<std::unique_ptr<DwarfCompileUnit>> CUs);
313 AsmPrinter *
Asm, AccelTable<DWARF5AccelTableStaticData> &Contents,
314 ArrayRef<MCSymbol *> CUs,
391 Atom(5, dwarf::DW_FORM_data1),
Atom(6, dwarf::DW_FORM_data4)};
406 #endif // LLVM_CODEGEN_ACCELTABLE_H
static ManagedStatic< SignpostEmitter > Signposts
Allows llvm::Timer to emit signposts when supported.
we get the following basic block
@ User
could "use" a pointer
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
uint64_t order() const override
This is an optimization pass for GlobalISel generic memory operations.
QP Compare Ordered outs ins xscmpudp No intrinsic
uint32_t getBucketCount() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
print lazy value Lazy Value Info Printer Pass
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
#define SET(ID, TYPE, VAL)
uint64_t(*)(uint64_t Type, uint64_t Offset, uint64_t S, uint64_t LocData, int64_t Addend) RelocationResolver
@ Dwarf
DWARF v5 .debug_names.
GenericSSAContext< Function > SSAContext
source_group(${group} FILES ${ARGN}) endmacro() add_lv_impl_folder(Core Core/LVCompare.cpp Core/LVElement.cpp Core/LVLine.cpp Core/LVLocation.cpp Core/LVObject.cpp Core/LVOptions.cpp Core/LVRange.cpp Core/LVReader.cpp Core/LVScope.cpp Core/LVSort.cpp Core/LVSupport.cpp Core/LVSymbol.cpp Core/LVType.cpp) add_lv_impl_folder(Readers LVReaderHandler.cpp Readers/LVBinaryReader.cpp Readers/LVELFReader.cpp) list(APPEND LIBLV_ADDITIONAL_HEADER_DIRS "$
A disassembler class for M68k.
add_subdirectory(IR) add_subdirectory(Support) add_subdirectory(Frontend) add_subdirectory(TargetParser) if(NOT "$
const uint16_t Form
DWARF Form.
@ DW_ATOM_die_offset
Marker as the end of a list of atoms.
TrackingStatistic Statistic
AAResults AliasAnalysis
Temporary typedef for legacy code that uses a generic AliasAnalysis pointer or reference.
InlineResult InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, bool MergeAttributes=false, AAResults *CalleeAAR=nullptr, bool InsertLifetime=true, Function *ForwardVarArgsTo=nullptr)
This function inlines the called function into the basic block of the caller.
The object format emitted by the WebAssembly backed is documented see the home tools
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo td
void addName(DwarfStringPoolEntryRef Name, Types &&... Args)
PassManager< LazyCallGraph::SCC, CGSCCAnalysisManager, LazyCallGraph &, CGSCCUpdateResult & > CGSCCPassManager
The CGSCC pass manager.
The instances of the Type class are immutable: once they are created, they are never changed.
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions
bool ObjCClassIsImplementation
constexpr ExtensionInfo Extensions[]
llvm Testing Support LINK_COMPONENTS Support target_link_libraries(LLVMTestingSupport PRIVATE llvm_gtest) if(HOST_WINNT AND "$
place backedge safepoints impl
A structured debug information entry.
void print(raw_ostream &OS) const override
This class holds an abstract representation of an Accelerator Table, consisting of a sequence of buck...
this could be done in SelectionDAGISel along with other special bytes It would be nice to revert this patch
dwarf::Tag getTag() const
AppleAccelTableOffsetData(const DIE &D)
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 and
Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On x86
constexpr Atom(uint16_t Type, uint16_t Form)
virtual uint64_t order() const =0
Interface which the different types of accelerator table data have to conform.
riscv prera expand pseudo
__FakeVCSRevision h endif() endif() set(generated_files "$
uint64_t order() const override
DwarfStringPoolEntryRef: Dwarf string pool entry reference.
Itanium Name Demangler i e convert the string _Z1fv into and both[sub] projects need to demangle but neither can depend on each other *libcxxabi needs the demangler to implement which is part of the itanium ABI spec *LLVM needs a copy for a bunch of and cannot rely on the system s __cxa_demangle because it a might not be and b may not be up to date on the latest language features The copy of the demangler in LLVM has some extra stuff that aren t needed in which depend on the shared generic components Despite these we want to keep the core generic demangling library identical between both copies to simplify development and testing If you re working on the generic library
CodeGen else() add_llvm_component_group(Native) add_llvm_component_group(NativeCodeGen) endif() LLVMBuildResolveComponentsLink() LLVMBuildGenerateCFragment(OUTPUT $
void operator=(const AccelTableBase &)=delete
SmallVector< uint8_t, 10 > BuildID
A build ID in binary form.
rpmalloc rpmalloc c elseif(LLVM_INTEGRATED_CRT_ALLOC MATCHES "snmalloc$") set(ALLOCATOR_FILES "$
uint64_t order() const override
bool operator<(const AccelTableData &Other) const
void computeBucketCount()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void print(raw_ostream &OS) const override
add_llvm_component_library(LLVMFuzzerCLI FuzzerCLI.cpp PARTIAL_SOURCES_INTENDED ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/FuzzMutate LINK_COMPONENTS Support TargetParser) add_llvm_component_library(LLVMFuzzMutate IRMutator.cpp OpDescriptor.cpp Operations.cpp RandomIRBuilder.cpp PARTIAL_SOURCES_INTENDED ADDITIONAL_HEADER_DIRS $
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void emitAppleAccelTable(AsmPrinter *Asm, AccelTable< DataT > &Contents, StringRef Prefix, const MCSymbol *SecBegin)
Emit an Apple Accelerator Table consisting of entries in the specified AccelTable.
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
void apply(Opt *O, const Mod &M, const Mods &... Ms)
void emit(AsmPrinter *Asm) const override
virtual void emit(AsmPrinter *Asm) const =0
AccelTableBase(HashFn *Hash)
An Atom defines the form of the data in an Apple accelerator table.
static cl::opt< bool > LoopPredication("indvars-predicate-loops", cl::Hidden, cl::init(true), cl::desc("Predicate conditions in read only loops"))
Represents a group of entries with identical name (and hence, hash value).
static uint32_t hash(StringRef Buffer)
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
block Block Frequency Analysis
std::optional< T > Optional
BumpPtrAllocator Allocator
Allocator for HashData and Values.
Accelerator table data implementation for simple Apple accelerator tables with a DIE offset but no ac...
bb420 i The CBE manages to mtctr r0 r11 stbx r9 addi bdz later b loop This could be much the loop would be a single dispatch group
void emit(AsmPrinter *Asm) const override
llvm DebugInfo PDB Native list(APPEND LIBPDB_ADDITIONAL_HEADER_DIRS "${LLVM_MAIN_INCLUDE_DIR}/llvm/DebugInfo/PDB") add_llvm_component_library(LLVMDebugInfoPDB GenericError.cpp IPDBSourceFile.cpp PDB.cpp PDBContext.cpp PDBExtras.cpp PDBInterfaceAnchors.cpp PDBSymbol.cpp PDBSymbolAnnotation.cpp PDBSymbolBlock.cpp PDBSymbolCompiland.cpp PDBSymbolCompilandDetails.cpp PDBSymbolCompilandEnv.cpp PDBSymbolCustom.cpp PDBSymbolData.cpp PDBSymbolExe.cpp PDBSymbolFunc.cpp PDBSymbolFuncDebugEnd.cpp PDBSymbolFuncDebugStart.cpp PDBSymbolLabel.cpp PDBSymbolPublicSymbol.cpp PDBSymbolThunk.cpp PDBSymbolTypeArray.cpp PDBSymbolTypeBaseClass.cpp PDBSymbolTypeBuiltin.cpp PDBSymbolTypeCustom.cpp PDBSymbolTypeDimension.cpp PDBSymbolTypeEnum.cpp PDBSymbolTypeFriend.cpp PDBSymbolTypeFunctionArg.cpp PDBSymbolTypeFunctionSig.cpp PDBSymbolTypeManaged.cpp PDBSymbolTypePointer.cpp PDBSymbolTypeTypedef.cpp PDBSymbolTypeUDT.cpp PDBSymbolTypeVTable.cpp PDBSymbolTypeVTableShape.cpp PDBSymbolUnknown.cpp PDBSymbolUsingNamespace.cpp PDBSymDumper.cpp UDTLayout.cpp $
macro(add_lv_impl_folder group) list(APPEND LV_IMPL_SOURCES $
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can be
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRPrinter) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(DWARFLinkerParallel) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TargetParser) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
@ Wasm
WebAssembly Exception Handling.
This class implements an extremely fast bulk output stream that can only output to a stream.
AppleAccelTableStaticOffsetData(uint32_t Offset)
Statically lint checks LLVM IR
@ AND
Bitwise operators - logical and, logical or, logical xor.
A base class holding non-template-dependant functionality of the AccelTable class.
std::vector< ExecutorAddr > LookupResult
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
void emitAppleAccelTableImpl(AsmPrinter *Asm, AccelTableBase &Contents, StringRef Prefix, const MCSymbol *SecBegin, ArrayRef< AppleAccelTableData::Atom > Atoms)
diaguids lib LIBPDB_ADDITIONAL_LIBRARIES add_pdb_impl_folder(DIA DIA/DIADataStream.cpp DIA/DIAEnumDebugStreams.cpp DIA/DIAEnumFrameData.cpp DIA/DIAEnumInjectedSources.cpp DIA/DIAEnumLineNumbers.cpp DIA/DIAEnumSectionContribs.cpp DIA/DIAEnumSourceFiles.cpp DIA/DIAEnumSymbols.cpp DIA/DIAEnumTables.cpp DIA/DIAError.cpp DIA/DIAFrameData.cpp DIA/DIAInjectedSource.cpp DIA/DIALineNumber.cpp DIA/DIARawSymbol.cpp DIA/DIASectionContrib.cpp DIA/DIASession.cpp DIA/DIASourceFile.cpp DIA/DIATable.cpp) set(LIBPDB_ADDITIONAL_HEADER_DIRS "$
PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager
The Loop pass manager.
void emit(AsmPrinter *Asm) const override
AppleAccelTableTypeData(const DIE &D)
An efficient, type-erasing, non-owning reference to a callable.
static uint32_t hash(StringRef Name)
LLVM_HAS_NOGLOBAL_CTOR_MUTEX rpmalloc
void print(raw_ostream &OS) const
verify safepoint Safepoint IR Verifier
#define PROPERTY(ENUM, FIELD)
uint64_t getDieOffset() const
We should do a little better with eliminating dead stores The stores to the stack are dead since a and b are not needed
uint32_t getUniqueNameCount() const
Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these it can use inc
static Expected< BitVector > expand(StringRef S, StringRef Original)
Architecture
Defines the architecture slices that are supported by Text-based Stub files.
loop versioning Loop Versioning For LICM
std::vector< HashList > BucketList
void print(raw_ostream &OS) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
uint32_t caseFoldingDjbHash(StringRef Buffer, uint32_t H=5381)
Computes the Bernstein hash after folding the input according to the Dwarf 5 standard case folding ru...
std::vector< AccelTableData * > Values
Allocate memory in an ever growing pool, as if by bump-pointer.
const DIE & getDie() const
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
uint32_t QualifiedNameHash
IRBuilder(LLVMContext &, FolderTy, InserterTy, MDNode *, ArrayRef< OperandBundleDef >) -> IRBuilder< FolderTy, InserterTy >
static constexpr Atom Atoms[]
uint32_t getUniqueHashCount() const
message(STATUS "Targeting ${t}") add_subdirectory($
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
AppleAccelTableStaticTypeData(uint32_t Offset, uint16_t Tag, bool ObjCClassIsImplementation, uint32_t QualifiedNameHash)
mldst MergedLoadStoreMotion
Accelerator table data implementation for type accelerator tables with a DIE offset but no actual DIE...
currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be removed
@ BasicBlock
Various leaf nodes.
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That when the encoding does not require two syntactical operands to refer to the same register
unsigned getCUIndex() const
const uint16_t Type
Atom Type.
void print(raw_ostream &OS) const override
Machine Instruction Scheduler
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static cl::opt< bool > Mips16HardFloat("mips16-hard-float", cl::NotHidden, cl::desc("Enable mips16 hard float."), cl::init(false))
StringRef - Represent a constant reference to a string, i.e.
static const char Magic[]
void print(raw_ostream &OS) const override
uint64_t order() const override
if(llvm_vc STREQUAL "") set(fake_version_inc "$
bool FlattenCFG(BasicBlock *BB, AAResults *AA=nullptr)
This function is used to flatten a CFG.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Machine Check Debug Module
AllocaInst * DemoteRegToStack(Instruction &X, bool VolatileLoads=false, Instruction *AllocaPoint=nullptr)
This function takes a virtual register computed by an Instruction and replaces it with a slot in the ...
Function * CloneFunction(Function *F, ValueToValueMapTy &VMap, ClonedCodeInfo *CodeInfo=nullptr)
Return a copy of the specified function and add it to that function's module.
The Data class implementation for DWARF v5 accelerator table.
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local $pop6 WebAssembly registers are implicitly initialized to zero Explicit zeroing is therefore often redundant and could be optimized away Small indices may use smaller encodings than large indices WebAssemblyRegColoring and or WebAssemblyRegRenumbering should sort registers according to their usage frequency to maximize the usage of smaller encodings Many cases of irreducible control flow could be transformed more optimally than via the transform in WebAssemblyFixIrreducibleControlFlow cpp It may also be worthwhile to do transforms before register particularly when duplicating to allow register coloring to be aware of the duplication WebAssemblyRegStackify could use AliasAnalysis to reorder loads and stores more aggressively WebAssemblyRegStackify is currently a greedy algorithm This means for a binary however wasm doesn t actually require this WebAssemblyRegStackify could be or possibly to take full advantage of what WebAssembly permits Add support for mergeable sections in the Wasm writer
void BuryPointer(const void *Ptr)
unsigned getDieTag() const
dfa jump DFA Jump Threading
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to CFG
static const int Signals[]
DWARF5AccelTableStaticData(uint64_t DieOffset, unsigned DieTag, unsigned CUIndex)
tools llvm config LibraryDependencies inc add_llvm_component_group(all-targets LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD}) add_llvm_component_group(Engine) if(TARGET $
A base class for different implementations of Data classes for Apple Accelerator Tables.
we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this whole function isel would also handle this Investigate lowering of sparse switch statements into perfect hash tables
ArrayRef< HashList > getBuckets() const
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill can
uint64_t getDieOffset() const
void compress(ArrayRef< uint8_t > Input, SmallVectorImpl< uint8_t > &CompressedBuffer, int Level=DefaultCompression)
static constexpr Atom Atoms[]
bool LoopRotation(Loop *L, LoopInfo *LI, const TargetTransformInfo *TTI, AssumptionCache *AC, DominatorTree *DT, ScalarEvolution *SE, MemorySSAUpdater *MSSAU, const SimplifyQuery &SQ, bool RotationOnly, unsigned Threshold, bool IsUtilMode, bool PrepareForLTO=false)
Convert a loop into a loop with bottom test.
Accelerator table data implementation for simple Apple accelerator tables with just a DIE reference.
find_first_existing_vc_file("${LLVM_MAIN_SRC_DIR}" llvm_vc) set(version_inc "$
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including ppc
This class is intended to be used as a driving class for all asm writers.
we get the following basic r4 lvx v3
static uint32_t hash(StringRef Name)
static constexpr Atom Atoms[]
SmartRWMutex< false > RWMutex
HashData(DwarfStringPoolEntryRef Name, HashFn *Hash)
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical This
uint64_t order() const override
std::optional< std::vector< StOtherPiece > > Other
aa Exhaustive Alias Analysis Precision Evaluator
static constexpr Atom Atoms[]
VCSRevision h set(generate_vcs_version_script "${LLVM_CMAKE_DIR}/GenerateVersionFromVCS.cmake") if(LLVM_APPEND_VC_REV) set(llvm_source_dir $
unsigned getDieTag() const
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C Currently
AnalysisManager< Loop, LoopStandardAnalysisResults & > LoopAnalysisManager
The loop analysis manager.
std::unique_ptr< Module > CloneModule(const Module &M)
Return an exact copy of the specified module.
virtual ~AccelTableData()=default
void print(raw_ostream &OS) const
MIPS Relocation Principles In LLVM
uint32_t(StringRef) HashFn
should just be implemented with a CLZ instruction Since there are other e PPC
Accelerator table data implementation for Apple type accelerator tables.
std::vector< HashData * > HashList
amdgpu printf runtime AMDGPU Printf lowering
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin h
ArrayRef(const T &OneElt) -> ArrayRef< T >
virtual void print(raw_ostream &OS) const =0
void print(raw_ostream &OS) const override
uint32_t djbHash(StringRef Buffer, uint32_t H=5381)
The Bernstein hash function used by the DWARF accelerator tables.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
GenericSSAContext< MachineFunction > MachineSSAContext
Code Generation Notes for reduce the size of the ISel matcher
void emit(AsmPrinter *Asm) const override
unsigned getOffset() const
Get the compile/type unit relative offset of this DIE.
void print(raw_ostream &OS) const
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
void SplitModule(Module &M, unsigned N, function_ref< void(std::unique_ptr< Module > MPart)> ModuleCallback, bool PreserveLocals=false)
Splits the module M into N linkable partitions.
early cse Early CSE w MemorySSA
std::pair< uint64_t, uint64_t > Interval
DWARF5AccelTableData(const DIE &Die)
void finalize(AsmPrinter *Asm, StringRef Prefix)
Error build(ArrayRef< Module * > Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)
Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.
DwarfStringPoolEntryRef Name
void emitDWARF5AccelTable(AsmPrinter *Asm, AccelTable< DWARF5AccelTableData > &Contents, const DwarfDebug &DD, ArrayRef< std::unique_ptr< DwarfCompileUnit >> CUs)