LLVM  13.0.0git
RegAllocBasic.cpp
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1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the RABasic function pass, which provides a minimal
10 // implementation of the basic register allocator.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AllocationOrder.h"
15 #include "LiveDebugVariables.h"
16 #include "RegAllocBase.h"
28 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/Spiller.h"
33 #include "llvm/Pass.h"
34 #include "llvm/Support/Debug.h"
36 #include <cstdlib>
37 #include <queue>
38 
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "regalloc"
42 
43 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
45 
46 namespace {
47  struct CompSpillWeight {
48  bool operator()(LiveInterval *A, LiveInterval *B) const {
49  return A->weight() < B->weight();
50  }
51  };
52 }
53 
54 namespace {
55 /// RABasic provides a minimal implementation of the basic register allocation
56 /// algorithm. It prioritizes live virtual registers by spill weight and spills
57 /// whenever a register is unavailable. This is not practical in production but
58 /// provides a useful baseline both for measuring other allocators and comparing
59 /// the speed of the basic algorithm against other styles of allocators.
60 class RABasic : public MachineFunctionPass,
61  public RegAllocBase,
62  private LiveRangeEdit::Delegate {
63  // context
64  MachineFunction *MF;
65 
66  // state
67  std::unique_ptr<Spiller> SpillerInstance;
68  std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
69  CompSpillWeight> Queue;
70 
71  // Scratch space. Allocated here to avoid repeated malloc calls in
72  // selectOrSplit().
73  BitVector UsableRegs;
74 
75  bool LRE_CanEraseVirtReg(Register) override;
76  void LRE_WillShrinkVirtReg(Register) override;
77 
78 public:
79  RABasic();
80 
81  /// Return the pass name.
82  StringRef getPassName() const override { return "Basic Register Allocator"; }
83 
84  /// RABasic analysis usage.
85  void getAnalysisUsage(AnalysisUsage &AU) const override;
86 
87  void releaseMemory() override;
88 
89  Spiller &spiller() override { return *SpillerInstance; }
90 
91  void enqueue(LiveInterval *LI) override {
92  Queue.push(LI);
93  }
94 
95  LiveInterval *dequeue() override {
96  if (Queue.empty())
97  return nullptr;
98  LiveInterval *LI = Queue.top();
99  Queue.pop();
100  return LI;
101  }
102 
103  MCRegister selectOrSplit(LiveInterval &VirtReg,
104  SmallVectorImpl<Register> &SplitVRegs) override;
105 
106  /// Perform register allocation.
107  bool runOnMachineFunction(MachineFunction &mf) override;
108 
109  MachineFunctionProperties getRequiredProperties() const override {
112  }
113 
114  MachineFunctionProperties getClearedProperties() const override {
117  }
118 
119  // Helper for spilling all live virtual registers currently unified under preg
120  // that interfere with the most recently queried lvr. Return true if spilling
121  // was successful, and append any new spilled/split intervals to splitLVRs.
122  bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
123  SmallVectorImpl<Register> &SplitVRegs);
124 
125  static char ID;
126 };
127 
128 char RABasic::ID = 0;
129 
130 } // end anonymous namespace
131 
133 
134 INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
135  false, false)
139 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
140 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
147  false)
148 
149 bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) {
150  LiveInterval &LI = LIS->getInterval(VirtReg);
151  if (VRM->hasPhys(VirtReg)) {
152  Matrix->unassign(LI);
153  aboutToRemoveInterval(LI);
154  return true;
155  }
156  // Unassigned virtreg is probably in the priority queue.
157  // RegAllocBase will erase it after dequeueing.
158  // Nonetheless, clear the live-range so that the debug
159  // dump will show the right state for that VirtReg.
160  LI.clear();
161  return false;
162 }
163 
164 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) {
165  if (!VRM->hasPhys(VirtReg))
166  return;
167 
168  // Register is assigned, put it back on the queue for reassignment.
169  LiveInterval &LI = LIS->getInterval(VirtReg);
170  Matrix->unassign(LI);
171  enqueue(&LI);
172 }
173 
174 RABasic::RABasic(): MachineFunctionPass(ID) {
175 }
176 
177 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
178  AU.setPreservesCFG();
186  AU.addRequired<LiveStacks>();
187  AU.addPreserved<LiveStacks>();
194  AU.addRequired<VirtRegMap>();
195  AU.addPreserved<VirtRegMap>();
198  MachineFunctionPass::getAnalysisUsage(AU);
199 }
200 
201 void RABasic::releaseMemory() {
202  SpillerInstance.reset();
203 }
204 
205 
206 // Spill or split all live virtual registers currently unified under PhysReg
207 // that interfere with VirtReg. The newly spilled or split live intervals are
208 // returned by appending them to SplitVRegs.
209 bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
210  SmallVectorImpl<Register> &SplitVRegs) {
211  // Record each interference and determine if all are spillable before mutating
212  // either the union or live intervals.
214 
215  // Collect interferences assigned to any alias of the physical register.
216  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
217  LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
219  for (unsigned i = Q.interferingVRegs().size(); i; --i) {
220  LiveInterval *Intf = Q.interferingVRegs()[i - 1];
221  if (!Intf->isSpillable() || Intf->weight() > VirtReg.weight())
222  return false;
223  Intfs.push_back(Intf);
224  }
225  }
226  LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
227  << " interferences with " << VirtReg << "\n");
228  assert(!Intfs.empty() && "expected interference");
229 
230  // Spill each interfering vreg allocated to PhysReg or an alias.
231  for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
232  LiveInterval &Spill = *Intfs[i];
233 
234  // Skip duplicates.
235  if (!VRM->hasPhys(Spill.reg()))
236  continue;
237 
238  // Deallocate the interfering vreg by removing it from the union.
239  // A LiveInterval instance may not be in a union during modification!
240  Matrix->unassign(Spill);
241 
242  // Spill the extracted interval.
243  LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
244  spiller().spill(LRE);
245  }
246  return true;
247 }
248 
249 // Driver for the register assignment and splitting heuristics.
250 // Manages iteration over the LiveIntervalUnions.
251 //
252 // This is a minimal implementation of register assignment and splitting that
253 // spills whenever we run out of registers.
254 //
255 // selectOrSplit can only be called once per live virtual register. We then do a
256 // single interference test for each register the correct class until we find an
257 // available register. So, the number of interference tests in the worst case is
258 // |vregs| * |machineregs|. And since the number of interference tests is
259 // minimal, there is no value in caching them outside the scope of
260 // selectOrSplit().
261 MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg,
262  SmallVectorImpl<Register> &SplitVRegs) {
263  // Populate a list of physical register spill candidates.
264  SmallVector<MCRegister, 8> PhysRegSpillCands;
265 
266  // Check for an available register in this class.
267  auto Order =
268  AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
269  for (MCRegister PhysReg : Order) {
270  assert(PhysReg.isValid());
271  // Check for interference in PhysReg
272  switch (Matrix->checkInterference(VirtReg, PhysReg)) {
273  case LiveRegMatrix::IK_Free:
274  // PhysReg is available, allocate it.
275  return PhysReg;
276 
277  case LiveRegMatrix::IK_VirtReg:
278  // Only virtual registers in the way, we may be able to spill them.
279  PhysRegSpillCands.push_back(PhysReg);
280  continue;
281 
282  default:
283  // RegMask or RegUnit interference.
284  continue;
285  }
286  }
287 
288  // Try to spill another interfering reg with less spill weight.
289  for (MCRegister &PhysReg : PhysRegSpillCands) {
290  if (!spillInterferences(VirtReg, PhysReg, SplitVRegs))
291  continue;
292 
293  assert(!Matrix->checkInterference(VirtReg, PhysReg) &&
294  "Interference after spill.");
295  // Tell the caller to allocate to this newly freed physical register.
296  return PhysReg;
297  }
298 
299  // No other spill candidates were found, so spill the current VirtReg.
300  LLVM_DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
301  if (!VirtReg.isSpillable())
302  return ~0u;
303  LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
304  spiller().spill(LRE);
305 
306  // The live virtual register requesting allocation was spilled, so tell
307  // the caller not to allocate anything during this round.
308  return 0;
309 }
310 
311 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
312  LLVM_DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
313  << "********** Function: " << mf.getName() << '\n');
314 
315  MF = &mf;
316  RegAllocBase::init(getAnalysis<VirtRegMap>(),
317  getAnalysis<LiveIntervals>(),
318  getAnalysis<LiveRegMatrix>());
319  VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, getAnalysis<MachineLoopInfo>(),
320  getAnalysis<MachineBlockFrequencyInfo>());
321  VRAI.calculateSpillWeightsAndHints();
322 
323  SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, VRAI));
324 
325  allocatePhysRegs();
326  postOptimization();
327 
328  // Diagnostic output before rewriting
329  LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
330 
331  releaseMemory();
332  return true;
333 }
334 
336 {
337  return new RABasic();
338 }
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Definition: README.txt:29
llvm::Spiller
Spiller interface.
Definition: Spiller.h:24
LiveRegMatrix.h
MachineInstr.h
llvm
Definition: AllocatorList.h:23
llvm::RABasicID
char & RABasicID
Basic register allocator.
Definition: RegAllocBasic.cpp:132
AllocationOrder.h
Pass.h
llvm::LiveInterval::isSpillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:813
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
LiveDebugVariables.h
llvm::VirtRegAuxInfo
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.
Definition: CalcSpillWeights.h:46
llvm::LiveInterval::weight
float weight() const
Definition: LiveInterval.h:712
llvm::MCRegister::isValid
bool isValid() const
Definition: MCRegister.h:74
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
Spiller.h
llvm::MachineFunctionProperties::Property::IsSSA
@ IsSSA
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RegisterRegAlloc
Definition: RegAllocRegistry.h:60
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::AMDGPU::HSAMD::ValueKind::Queue
@ Queue
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
MachineRegisterInfo.h
AliasAnalysis.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::createInlineSpiller
Spiller * createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
Create and return a spiller that will insert spill code directly instead of deferring though VirtRegM...
Definition: InlineSpiller.cpp:246
MachineLoopInfo.h
llvm::MachineBlockFrequencyInfo
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
Definition: MachineBlockFrequencyInfo.h:33
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::LiveRangeEdit
Definition: LiveRangeEdit.h:46
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:169
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator", false, false) INITIALIZE_PASS_END(RABasic
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
llvm::BitVector
Definition: BitVector.h:74
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
Passes.h
LiveIntervals.h
VirtRegMap.h
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:522
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LiveDebugVariables
Definition: LiveDebugVariables.h:32
llvm::MachineFunction
Definition: MachineFunction.h:230
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
llvm::LiveIntervalUnion::Query::interferingVRegs
const SmallVectorImpl< LiveInterval * > & interferingVRegs() const
Definition: LiveIntervalUnion.h:166
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
LiveRangeEdit.h
RegAllocBase.h
llvm::MachineFunctionProperties::Property::NoPHIs
@ NoPHIs
llvm::RegAllocBase
RegAllocBase provides the register allocation driver and interface that can be extended to add intere...
Definition: RegAllocBase.h:60
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::LiveIntervalUnion::Query::collectInterferingVRegs
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
Definition: LiveIntervalUnion.cpp:128
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::LiveIntervalUnion::Query
Query interferences between a single live virtual register and a live interval union.
Definition: LiveIntervalUnion.h:112
LiveStacks.h
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:146
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::AAResultsWrapperPass
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Definition: AliasAnalysis.h:1269
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::LiveRange::clear
void clear()
Definition: LiveInterval.h:292
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::createBasicRegisterAllocator
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
Definition: RegAllocBasic.cpp:335
llvm::AnalysisUsage::addRequiredID
AnalysisUsage & addRequiredID(const void *ID)
Definition: Pass.cpp:267
llvm::LiveRangeEdit::Delegate
Callback methods for LiveRangeEdit owners.
Definition: LiveRangeEdit.h:49
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
CalcSpillWeights.h
regallocbasic
regallocbasic
Definition: RegAllocBasic.cpp:146
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::LiveStacks
Definition: LiveStacks.h:31
MachineBlockFrequencyInfo.h
basicRegAlloc
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator)
TargetRegisterInfo.h
Debug.h
RegAllocRegistry.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40