LLVM  14.0.0git
BPFISelLowering.h
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1 //===-- BPFISelLowering.h - BPF DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that BPF uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
15 #define LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
16 
17 #include "BPF.h"
20 
21 namespace llvm {
22 class BPFSubtarget;
23 namespace BPFISD {
24 enum NodeType : unsigned {
32 };
33 }
34 
36 public:
37  explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
38 
39  // Provide custom lowering hooks for some operations.
40  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
41 
42  // This method returns the name of a target specific DAG node.
43  const char *getTargetNodeName(unsigned Opcode) const override;
44 
45  // This method decides whether folding a constant offset
46  // with the given GlobalAddress is legal.
47  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
48 
50  getConstraintType(StringRef Constraint) const override;
51 
52  std::pair<unsigned, const TargetRegisterClass *>
54  StringRef Constraint, MVT VT) const override;
55 
58  MachineBasicBlock *BB) const override;
59 
60  bool getHasAlu32() const { return HasAlu32; }
61  bool getHasJmp32() const { return HasJmp32; }
62  bool getHasJmpExt() const { return HasJmpExt; }
63 
65  EVT VT) const override;
66 
67  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
68 
69 private:
70  // Control Instruction Selection Features
71  bool HasAlu32;
72  bool HasJmp32;
73  bool HasJmpExt;
74 
75  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
76  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
77  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
78 
79  // Lower the result values of a call, copying them out of physregs into vregs
80  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
81  CallingConv::ID CallConv, bool IsVarArg,
83  const SDLoc &DL, SelectionDAG &DAG,
84  SmallVectorImpl<SDValue> &InVals) const;
85 
86  // Maximum number of arguments to a call
87  static const unsigned MaxArgs;
88 
89  // Lower a call into CALLSEQ_START - BPFISD:CALL - CALLSEQ_END chain
91  SmallVectorImpl<SDValue> &InVals) const override;
92 
93  // Lower incoming arguments, copy physregs into vregs
94  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
95  bool IsVarArg,
97  const SDLoc &DL, SelectionDAG &DAG,
98  SmallVectorImpl<SDValue> &InVals) const override;
99 
100  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
102  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
103  SelectionDAG &DAG) const override;
104 
105  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
106  SelectionDAG &DAG) const override;
107 
108  EVT getOptimalMemOpType(const MemOp &Op,
109  const AttributeList &FuncAttributes) const override {
110  return Op.size() >= 8 ? MVT::i64 : MVT::i32;
111  }
112 
113  bool isIntDivCheap(EVT VT, AttributeList Attr) const override { return true; }
114 
115  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
116  Type *Ty) const override {
117  return true;
118  }
119 
120  // Prevent reducing load width during SelectionDag phase.
121  // Otherwise, we may transform the following
122  // ctx = ctx + reloc_offset
123  // ... (*(u32 *)ctx) & 0x8000...
124  // to
125  // ctx = ctx + reloc_offset
126  // ... (*(u8 *)(ctx + 1)) & 0x80 ...
127  // which will be rejected by the verifier.
128  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
129  EVT NewVT) const override {
130  return false;
131  }
132 
133  // isTruncateFree - Return true if it's free to truncate a value of
134  // type Ty1 to type Ty2. e.g. On BPF at alu32 mode, it's free to truncate
135  // a i64 value in register R1 to i32 by referencing its sub-register W1.
136  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
137  bool isTruncateFree(EVT VT1, EVT VT2) const override;
138 
139  // For 32bit ALU result zext to 64bit is free.
140  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
141  bool isZExtFree(EVT VT1, EVT VT2) const override;
142 
143  unsigned EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, unsigned Reg,
144  bool isSigned) const;
145 
146  MachineBasicBlock * EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
147  MachineBasicBlock *BB)
148  const;
149 
150 };
151 }
152 
153 #endif
llvm::BPFTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: BPFISelLowering.cpp:624
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4133
llvm::BPFISD::MEMCPY
@ MEMCPY
Definition: BPFISelLowering.h:31
llvm::BPFTargetLowering::getConstraintType
BPFTargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: BPFISelLowering.cpp:224
llvm::BPFTargetLowering::getHasJmpExt
bool getHasJmpExt() const
Definition: BPFISelLowering.h:62
llvm::BPFTargetLowering::getHasAlu32
bool getHasAlu32() const
Definition: BPFISelLowering.h:60
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::MemOp
Definition: TargetLowering.h:111
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::AttributeList
Definition: Attributes.h:398
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
BPF.h
llvm::BPFISD::NodeType
NodeType
Definition: BPFISelLowering.h:24
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::BPFTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: BPFISelLowering.cpp:238
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::BPFISD::BR_CC
@ BR_CC
Definition: BPFISelLowering.h:29
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1335
llvm::BPFISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: BPFISelLowering.h:25
TargetLowering.h
llvm::BPFTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: BPFISelLowering.cpp:853
llvm::BPFISD::SELECT_CC
@ SELECT_CC
Definition: BPFISelLowering.h:28
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3165
llvm::BPFTargetLowering::BPFTargetLowering
BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI)
Definition: BPFISelLowering.cpp:56
llvm::BPFTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: BPFISelLowering.cpp:716
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::BPFTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: BPFISelLowering.cpp:281
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3723
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::BPFISD::CALL
@ CALL
Definition: BPFISelLowering.h:27
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::BPFTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: BPFISelLowering.cpp:858
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1700
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::BPFTargetLowering
Definition: BPFISelLowering.h:35
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::BPFTargetLowering::getHasJmp32
bool getHasJmp32() const
Definition: BPFISelLowering.h:61
llvm::BPFISD::Wrapper
@ Wrapper
Definition: BPFISelLowering.h:30
llvm::BPFTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: BPFISelLowering.cpp:187
N
#define N
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::BPFISD::RET_FLAG
@ RET_FLAG
Definition: BPFISelLowering.h:26
llvm::BPFSubtarget
Definition: BPFSubtarget.h:31