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14 #ifndef LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
15 #define LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
52 std::pair<unsigned, const TargetRegisterClass *>
65 EVT VT)
const override;
87 static const unsigned MaxArgs;
113 bool isIntDivCheap(EVT VT, AttributeList Attr)
const override {
return true; }
115 bool shouldConvertConstantLoadToIntImm(
const APInt &
Imm,
116 Type *Ty)
const override {
129 EVT NewVT)
const override {
133 bool isLegalAddressingMode(
const DataLayout &
DL,
const AddrMode &AM,
134 Type *Ty,
unsigned AS,
135 Instruction *
I =
nullptr)
const override;
140 bool isTruncateFree(Type *Ty1, Type *Ty2)
const override;
141 bool isTruncateFree(EVT VT1, EVT VT2)
const override;
144 bool isZExtFree(Type *Ty1, Type *Ty2)
const override;
145 bool isZExtFree(EVT VT1, EVT VT2)
const override;
147 unsigned EmitSubregExt(MachineInstr &
MI, MachineBasicBlock *
BB,
unsigned Reg,
148 bool isSigned)
const;
150 MachineBasicBlock * EmitInstrWithCustomInserterMemcpy(MachineInstr &
MI,
151 MachineBasicBlock *
BB)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
BPFTargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool getHasJmpExt() const
Reg
All possible values of the reg field in the ModR/M byte.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Representation of each machine instruction.
This is an important class for using LLVM in a threaded context.
This structure contains all information that is necessary for lowering calls.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB