28 #define DEBUG_TYPE "delay-slot-filler"
30 STATISTIC(FilledSlots,
"Number of delay slots filled");
33 "disable-sparc-delay-filler",
35 cl::desc(
"Disable the Sparc delay slot filler."),
45 StringRef getPassName()
const override {
return "SPARC Delay Slot Filler"; }
54 F.getRegInfo().invalidateLiveness();
57 Changed |= runOnMachineBasicBlock(
MBB);
78 bool &sawLoad,
bool &sawStore,
106 bool Changed =
false;
116 (
MI->getOpcode() == SP::RESTORErr
117 ||
MI->getOpcode() == SP::RESTOREri)) {
118 Changed |= tryCombineRestoreWithPrevInst(
MBB,
MI);
124 if (!Subtarget->
isV9() &&
125 (
MI->getOpcode() == SP::FCMPS ||
MI->getOpcode() == SP::FCMPD
126 ||
MI->getOpcode() == SP::FCMPQ)) {
133 if (!
MI->hasDelaySlot())
139 D = findDelayInstr(
MBB,
MI);
149 unsigned structSize = 0;
150 if (needsUnimp(
MI, structSize)) {
153 assert (J !=
MBB.
end() &&
"MI needs a delay instruction.");
171 bool sawLoad =
false;
172 bool sawStore =
false;
177 unsigned Opc =
slot->getOpcode();
182 if (Opc == SP::RETL || Opc ==
SP::TAIL_CALL || Opc == SP::TAIL_CALLri) {
186 if (J->getOpcode() == SP::RESTORErr
187 || J->getOpcode() == SP::RESTOREri) {
197 insertCallDefsUses(
slot, RegDefs, RegUses);
199 insertDefsUses(
slot, RegDefs, RegUses);
212 if (
I->isDebugInstr())
215 if (
I->hasUnmodeledSideEffects() ||
I->isInlineAsm() ||
I->isPosition() ||
216 I->hasDelaySlot() ||
I->isBundledWithSucc())
219 if (delayHasHazard(
I, sawLoad, sawStore, RegDefs, RegUses)) {
220 insertDefsUses(
I, RegDefs, RegUses);
236 if (candidate->isImplicitDef() || candidate->isKill())
239 if (candidate->mayLoad()) {
245 if (candidate->mayStore()) {
253 for (
unsigned i = 0,
e = candidate->getNumOperands();
i!=
e; ++
i) {
262 if (IsRegInSet(RegDefs,
Reg) || IsRegInSet(RegUses,
Reg))
267 if (IsRegInSet(RegDefs,
Reg))
272 unsigned Opcode = candidate->getOpcode();
277 Opcode >= SP::LDDArr && Opcode <= SP::LDrr)
283 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD)
298 switch(
MI->getOpcode()) {
305 assert(
Reg.isReg() &&
"CALL first operand is not a register.");
306 assert(
Reg.isUse() &&
"CALL first operand is not a use.");
312 assert(Operand1.
isReg() &&
"CALLrr second operand is not a register.");
313 assert(Operand1.
isUse() &&
"CALLrr second operand is not a use.");
349 if (RegSet.
count(*AI))
359 unsigned structSizeOpNum = 0;
360 switch (
I->getOpcode()) {
362 case SP::CALL: structSizeOpNum = 1;
break;
364 case SP::CALLri: structSizeOpNum = 2;
break;
366 case SP::TAIL_CALLri:
386 Register reg = AddMI->getOperand(0).getReg();
387 if (reg < SP::I0 || reg > SP::I7)
391 RestoreMI->eraseFromParent();
394 AddMI->setDesc(
TII->get((AddMI->getOpcode() == SP::ADDrr)
399 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
414 Register reg = OrMI->getOperand(0).getReg();
415 if (reg < SP::I0 || reg > SP::I7)
419 if (OrMI->getOpcode() == SP::ORrr
420 && OrMI->getOperand(1).getReg() != SP::G0
421 && OrMI->getOperand(2).getReg() != SP::G0)
424 if (OrMI->getOpcode() == SP::ORri
425 && OrMI->getOperand(1).getReg() != SP::G0
426 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
430 RestoreMI->eraseFromParent();
433 OrMI->setDesc(
TII->get((OrMI->getOpcode() == SP::ORrr)
438 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
452 Register reg = SetHiMI->getOperand(0).getReg();
453 if (reg < SP::I0 || reg > SP::I7)
456 if (!SetHiMI->getOperand(1).isImm())
459 int64_t imm = SetHiMI->getOperand(1).getImm();
466 imm = (imm << 10) & 0x1FFF;
468 assert(RestoreMI->getOpcode() == SP::RESTORErr);
470 RestoreMI->setDesc(
TII->get(SP::RESTOREri));
472 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
473 RestoreMI->getOperand(1).setReg(SP::G0);
474 RestoreMI->getOperand(2).ChangeToImmediate(imm);
478 SetHiMI->eraseFromParent();
492 &&
MBBI->getOperand(0).getReg() == SP::G0
493 &&
MBBI->getOperand(1).getReg() == SP::G0
494 &&
MBBI->getOperand(2).getReg() == SP::G0);
499 if (PrevInst->isBundledWithSucc())
504 switch (PrevInst->getOpcode()) {