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13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
22 class MachineBasicBlock;
25 class MipsTargetMachine;
27 class TargetRegisterClass;
46 bool *Fast =
nullptr)
const override;
63 bool isEligibleForTailCallOptimization(
64 const CCState &CCInfo,
unsigned NextStackOffset,
69 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
70 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
71 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
95 unsigned BranchOp)
const;
111 unsigned EltSizeInBytes,
143 #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
This is an optimization pass for GlobalISel generic memory operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CCState - This class holds information needed while lowering arguments and return values.
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Represents one node in the SelectionDAG.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Representation of each machine instruction.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
Flags
Flags values. These may be or'd together.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB