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MipsSEISelLowering.h
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1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15 
16 #include "MipsISelLowering.h"
19 
20 namespace llvm {
21 
22 class MachineBasicBlock;
23 class MachineInstr;
24 class MipsSubtarget;
25 class MipsTargetMachine;
26 class SelectionDAG;
27 class TargetRegisterClass;
28 
30  public:
32  const MipsSubtarget &STI);
33 
34  /// Enable MSA support for the given integer type and Register
35  /// class.
37 
38  /// Enable MSA support for the given floating-point type and
39  /// Register class.
41  const TargetRegisterClass *RC);
42 
44  EVT VT, unsigned AS = 0, Align Alignment = Align(1),
46  bool *Fast = nullptr) const override;
47 
48  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
49 
50  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
51 
54  MachineBasicBlock *MBB) const override;
55 
56  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
57  return false;
58  }
59 
60  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
61 
62  private:
63  bool isEligibleForTailCallOptimization(
64  const CCState &CCInfo, unsigned NextStackOffset,
65  const MipsFunctionInfo &FI) const override;
66 
67  void
68  getOpndList(SmallVectorImpl<SDValue> &Ops,
69  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
70  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
71  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
72  SDValue Chain) const override;
73 
74  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
75  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
76  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
77 
78  SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
79  SelectionDAG &DAG) const;
80 
81  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
82  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
83  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
84  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
85  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
86  /// Lower VECTOR_SHUFFLE into one of a number of instructions
87  /// depending on the indices in the shuffle.
88  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
89  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
90 
91  MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
92  MachineBasicBlock *BB) const;
93  MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
95  unsigned BranchOp) const;
96  /// Emit the COPY_FW pseudo instruction
97  MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
98  MachineBasicBlock *BB) const;
99  /// Emit the COPY_FD pseudo instruction
100  MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
101  MachineBasicBlock *BB) const;
102  /// Emit the INSERT_FW pseudo instruction
103  MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
104  MachineBasicBlock *BB) const;
105  /// Emit the INSERT_FD pseudo instruction
106  MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
107  MachineBasicBlock *BB) const;
108  /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
109  MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
111  unsigned EltSizeInBytes,
112  bool IsFP) const;
113  /// Emit the FILL_FW pseudo instruction
114  MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
115  MachineBasicBlock *BB) const;
116  /// Emit the FILL_FD pseudo instruction
117  MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
118  MachineBasicBlock *BB) const;
119  /// Emit the FEXP2_W_1 pseudo instructions.
120  MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
121  MachineBasicBlock *BB) const;
122  /// Emit the FEXP2_D_1 pseudo instructions.
123  MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
124  MachineBasicBlock *BB) const;
125  /// Emit the FILL_FW pseudo instruction
126  MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
127  MachineBasicBlock *BB) const;
128  /// Emit the FILL_FD pseudo instruction
129  MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
130  MachineBasicBlock *BB) const;
131  /// Emit the FEXP2_W_1 pseudo instructions.
132  MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
134  bool IsFGR64) const;
135  /// Emit the FEXP2_D_1 pseudo instructions.
136  MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
137  MachineBasicBlock *BBi,
138  bool IsFGR64) const;
139  };
140 
141 } // end namespace llvm
142 
143 #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
llvm::MipsSETargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: MipsSEISelLowering.cpp:1026
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MipsSETargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: MipsSEISelLowering.cpp:449
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::MipsSETargetLowering::addMSAFloatType
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
Definition: MipsSEISelLowering.cpp:372
llvm::MipsSETargetLowering::MipsSETargetLowering
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsSEISelLowering.cpp:64
llvm::MipsSETargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MipsSEISelLowering.cpp:1067
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3525
llvm::MipsSETargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: MipsSEISelLowering.h:56
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
Definition: MipsSEISelLowering.cpp:424
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ArrayRef< int >
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:261
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MipsSETargetLowering
Definition: MipsSEISelLowering.h:29
MipsISelLowering.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::MipsSETargetLowering::addMSAIntType
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
Definition: MipsSEISelLowering.cpp:318
N
#define N
llvm::MipsSETargetLowering::getRepRegClassFor
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
Definition: MipsSEISelLowering.cpp:309
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133