LLVM  14.0.0git
MipsSEISelLowering.cpp
Go to the documentation of this file.
1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelLowering.h"
14 #include "MipsMachineFunction.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Triple.h"
35 #include "llvm/IR/DebugLoc.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/IR/IntrinsicsMips.h"
38 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/Debug.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <iterator>
49 #include <utility>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "mips-isel"
54 
55 static cl::opt<bool>
56 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
57  cl::desc("MIPS: permit tail calls."), cl::init(false));
58 
59 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
60  cl::desc("Expand double precision loads and "
61  "stores to their single precision "
62  "counterparts"));
63 
65  const MipsSubtarget &STI)
66  : MipsTargetLowering(TM, STI) {
67  // Set up the register classes
68  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
69 
70  if (Subtarget.isGP64bit())
71  addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
72 
73  if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
74  // Expand all truncating stores and extending loads.
75  for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) {
76  for (MVT VT1 : MVT::fixedlen_vector_valuetypes()) {
77  setTruncStoreAction(VT0, VT1, Expand);
81  }
82  }
83  }
84 
85  if (Subtarget.hasDSP()) {
87 
88  for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
89  addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
90 
91  // Expand all builtin opcodes.
92  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
93  setOperationAction(Opc, VecTys[i], Expand);
94 
100  }
101 
107 
108  if (Subtarget.hasMips32r2()) {
111  }
112  }
113 
114  if (Subtarget.hasDSPR2())
116 
117  if (Subtarget.hasMSA()) {
118  addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
119  addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
120  addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
121  addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
122  addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
123  addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
124  addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
125 
126  // f16 is a storage-only type, always promote it to f32.
127  addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
163 
169  }
170 
171  if (!Subtarget.useSoftFloat()) {
172  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
173 
174  // When dealing with single precision only, use libcalls
175  if (!Subtarget.isSingleFloat()) {
176  if (Subtarget.isFP64bit())
177  addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
178  else
179  addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
180  }
181  }
182 
187 
188  if (Subtarget.hasCnMips())
190  else if (Subtarget.isGP64bit())
192 
193  if (Subtarget.isGP64bit()) {
200  }
201 
204 
210 
212 
216 
218  !Subtarget.hasMips64()) {
220  }
221 
222  if (NoDPLoadStore) {
225  }
226 
227  if (Subtarget.hasMips32r6()) {
228  // MIPS32r6 replaces the accumulator-based multiplies with a three register
229  // instruction
235 
236  // MIPS32r6 replaces the accumulator-based division/remainder with separate
237  // three register division and remainder instructions.
244 
245  // MIPS32r6 replaces conditional moves with an equivalent that removes the
246  // need for three GPR read ports.
250 
254 
255  assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
259 
261 
262  // Floating point > and >= are supported via < and <=
267 
272  }
273 
274  if (Subtarget.hasMips64r6()) {
275  // MIPS64r6 replaces the accumulator-based multiplies with a three register
276  // instruction
282 
283  // MIPS32r6 replaces the accumulator-based division/remainder with separate
284  // three register division and remainder instructions.
291 
292  // MIPS64r6 replaces conditional moves with an equivalent that removes the
293  // need for three GPR read ports.
297  }
298 
300 }
301 
302 const MipsTargetLowering *
304  const MipsSubtarget &STI) {
305  return new MipsSETargetLowering(TM, STI);
306 }
307 
308 const TargetRegisterClass *
310  if (VT == MVT::Untyped)
311  return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
312 
314 }
315 
316 // Enable MSA support for the given integer type and Register class.
319  addRegisterClass(Ty, RC);
320 
321  // Expand all builtin opcodes.
322  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
323  setOperationAction(Opc, Ty, Expand);
324 
332 
354 
355  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
360  }
361 
368 }
369 
370 // Enable MSA support for the given floating-point type and Register class.
373  addRegisterClass(Ty, RC);
374 
375  // Expand all builtin opcodes.
376  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
377  setOperationAction(Opc, Ty, Expand);
378 
385 
386  if (Ty != MVT::v8f16) {
398 
406  }
407 }
408 
409 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
410  if(!Subtarget.hasMips32r6())
412 
413  EVT ResTy = Op->getValueType(0);
414  SDLoc DL(Op);
415 
416  // Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
417  // floating point register are undefined. Not really an issue as sel.d, which
418  // is produced from an FSELECT node, only looks at bit 0.
419  SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
420  return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
421  Op->getOperand(2));
422 }
423 
425  EVT VT, unsigned, Align, MachineMemOperand::Flags, bool *Fast) const {
427 
429  // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
430  // implementation defined whether this is handled by hardware, software, or
431  // a hybrid of the two but it's expected that most implementations will
432  // handle the majority of cases in hardware.
433  if (Fast)
434  *Fast = true;
435  return true;
436  }
437 
438  switch (SVT) {
439  case MVT::i64:
440  case MVT::i32:
441  if (Fast)
442  *Fast = true;
443  return true;
444  default:
445  return false;
446  }
447 }
448 
450  SelectionDAG &DAG) const {
451  switch(Op.getOpcode()) {
452  case ISD::LOAD: return lowerLOAD(Op, DAG);
453  case ISD::STORE: return lowerSTORE(Op, DAG);
454  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
455  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
456  case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
457  case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
458  case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
459  case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
460  case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
461  DAG);
462  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
463  case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
464  case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
465  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
466  case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
467  case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
468  case ISD::SELECT: return lowerSELECT(Op, DAG);
469  case ISD::BITCAST: return lowerBITCAST(Op, DAG);
470  }
471 
473 }
474 
475 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
476 //
477 // Performs the following transformations:
478 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
479 // sign/zero-extension is completely overwritten by the new one performed by
480 // the ISD::AND.
481 // - Removes redundant zero extensions performed by an ISD::AND.
484  const MipsSubtarget &Subtarget) {
485  if (!Subtarget.hasMSA())
486  return SDValue();
487 
488  SDValue Op0 = N->getOperand(0);
489  SDValue Op1 = N->getOperand(1);
490  unsigned Op0Opcode = Op0->getOpcode();
491 
492  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
493  // where $d + 1 == 2^n and n == 32
494  // or $d + 1 == 2^n and n <= 32 and ZExt
495  // -> (MipsVExtractZExt $a, $b, $c)
496  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
497  Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
498  ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
499 
500  if (!Mask)
501  return SDValue();
502 
503  int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
504 
505  if (Log2IfPositive <= 0)
506  return SDValue(); // Mask+1 is not a power of 2
507 
508  SDValue Op0Op2 = Op0->getOperand(2);
509  EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
510  unsigned ExtendTySize = ExtendTy.getSizeInBits();
511  unsigned Log2 = Log2IfPositive;
512 
513  if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
514  Log2 == ExtendTySize) {
515  SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
516  return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
517  Op0->getVTList(),
518  makeArrayRef(Ops, Op0->getNumOperands()));
519  }
520  }
521 
522  return SDValue();
523 }
524 
525 // Determine if the specified node is a constant vector splat.
526 //
527 // Returns true and sets Imm if:
528 // * N is a ISD::BUILD_VECTOR representing a constant splat
529 //
530 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
531 // differences are that it assumes the MSA has already been checked and the
532 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
533 // must not be in order for binsri.d to be selectable).
534 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
535  BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
536 
537  if (!Node)
538  return false;
539 
540  APInt SplatValue, SplatUndef;
541  unsigned SplatBitSize;
542  bool HasAnyUndefs;
543 
544  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
545  8, !IsLittleEndian))
546  return false;
547 
548  Imm = SplatValue;
549 
550  return true;
551 }
552 
553 // Test whether the given node is an all-ones build_vector.
554 static bool isVectorAllOnes(SDValue N) {
555  // Look through bitcasts. Endianness doesn't matter because we are looking
556  // for an all-ones value.
557  if (N->getOpcode() == ISD::BITCAST)
558  N = N->getOperand(0);
559 
560  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
561 
562  if (!BVN)
563  return false;
564 
565  APInt SplatValue, SplatUndef;
566  unsigned SplatBitSize;
567  bool HasAnyUndefs;
568 
569  // Endianness doesn't matter in this context because we are looking for
570  // an all-ones value.
571  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
572  return SplatValue.isAllOnesValue();
573 
574  return false;
575 }
576 
577 // Test whether N is the bitwise inverse of OfNode.
578 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
579  if (N->getOpcode() != ISD::XOR)
580  return false;
581 
582  if (isVectorAllOnes(N->getOperand(0)))
583  return N->getOperand(1) == OfNode;
584 
585  if (isVectorAllOnes(N->getOperand(1)))
586  return N->getOperand(0) == OfNode;
587 
588  return false;
589 }
590 
591 // Perform combines where ISD::OR is the root node.
592 //
593 // Performs the following transformations:
594 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
595 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
596 // vector type.
599  const MipsSubtarget &Subtarget) {
600  if (!Subtarget.hasMSA())
601  return SDValue();
602 
603  EVT Ty = N->getValueType(0);
604 
605  if (!Ty.is128BitVector())
606  return SDValue();
607 
608  SDValue Op0 = N->getOperand(0);
609  SDValue Op1 = N->getOperand(1);
610 
611  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
612  SDValue Op0Op0 = Op0->getOperand(0);
613  SDValue Op0Op1 = Op0->getOperand(1);
614  SDValue Op1Op0 = Op1->getOperand(0);
615  SDValue Op1Op1 = Op1->getOperand(1);
616  bool IsLittleEndian = !Subtarget.isLittle();
617 
618  SDValue IfSet, IfClr, Cond;
619  bool IsConstantMask = false;
620  APInt Mask, InvMask;
621 
622  // If Op0Op0 is an appropriate mask, try to find it's inverse in either
623  // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
624  // looking.
625  // IfClr will be set if we find a valid match.
626  if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
627  Cond = Op0Op0;
628  IfSet = Op0Op1;
629 
630  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
631  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
632  IfClr = Op1Op1;
633  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
634  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
635  IfClr = Op1Op0;
636 
637  IsConstantMask = true;
638  }
639 
640  // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
641  // thing again using this mask.
642  // IfClr will be set if we find a valid match.
643  if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
644  Cond = Op0Op1;
645  IfSet = Op0Op0;
646 
647  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
648  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
649  IfClr = Op1Op1;
650  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
651  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
652  IfClr = Op1Op0;
653 
654  IsConstantMask = true;
655  }
656 
657  // If IfClr is not yet set, try looking for a non-constant match.
658  // IfClr will be set if we find a valid match amongst the eight
659  // possibilities.
660  if (!IfClr.getNode()) {
661  if (isBitwiseInverse(Op0Op0, Op1Op0)) {
662  Cond = Op1Op0;
663  IfSet = Op1Op1;
664  IfClr = Op0Op1;
665  } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
666  Cond = Op1Op0;
667  IfSet = Op1Op1;
668  IfClr = Op0Op0;
669  } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
670  Cond = Op1Op1;
671  IfSet = Op1Op0;
672  IfClr = Op0Op1;
673  } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
674  Cond = Op1Op1;
675  IfSet = Op1Op0;
676  IfClr = Op0Op0;
677  } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
678  Cond = Op0Op0;
679  IfSet = Op0Op1;
680  IfClr = Op1Op1;
681  } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
682  Cond = Op0Op0;
683  IfSet = Op0Op1;
684  IfClr = Op1Op0;
685  } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
686  Cond = Op0Op1;
687  IfSet = Op0Op0;
688  IfClr = Op1Op1;
689  } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
690  Cond = Op0Op1;
691  IfSet = Op0Op0;
692  IfClr = Op1Op0;
693  }
694  }
695 
696  // At this point, IfClr will be set if we have a valid match.
697  if (!IfClr.getNode())
698  return SDValue();
699 
700  assert(Cond.getNode() && IfSet.getNode());
701 
702  // Fold degenerate cases.
703  if (IsConstantMask) {
704  if (Mask.isAllOnesValue())
705  return IfSet;
706  else if (Mask == 0)
707  return IfClr;
708  }
709 
710  // Transform the DAG into an equivalent VSELECT.
711  return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
712  }
713 
714  return SDValue();
715 }
716 
718  SelectionDAG &DAG,
719  const MipsSubtarget &Subtarget) {
720  // Estimate the number of operations the below transform will turn a
721  // constant multiply into. The number is approximately equal to the minimal
722  // number of powers of two that constant can be broken down to by adding
723  // or subtracting them.
724  //
725  // If we have taken more than 12[1] / 8[2] steps to attempt the
726  // optimization for a native sized value, it is more than likely that this
727  // optimization will make things worse.
728  //
729  // [1] MIPS64 requires 6 instructions at most to materialize any constant,
730  // multiplication requires at least 4 cycles, but another cycle (or two)
731  // to retrieve the result from the HI/LO registers.
732  //
733  // [2] For MIPS32, more than 8 steps is expensive as the constant could be
734  // materialized in 2 instructions, multiplication requires at least 4
735  // cycles, but another cycle (or two) to retrieve the result from the
736  // HI/LO registers.
737  //
738  // TODO:
739  // - MaxSteps needs to consider the `VT` of the constant for the current
740  // target.
741  // - Consider to perform this optimization after type legalization.
742  // That allows to remove a workaround for types not supported natively.
743  // - Take in account `-Os, -Oz` flags because this optimization
744  // increases code size.
745  unsigned MaxSteps = Subtarget.isABI_O32() ? 8 : 12;
746 
747  SmallVector<APInt, 16> WorkStack(1, C);
748  unsigned Steps = 0;
749  unsigned BitWidth = C.getBitWidth();
750 
751  while (!WorkStack.empty()) {
752  APInt Val = WorkStack.pop_back_val();
753 
754  if (Val == 0 || Val == 1)
755  continue;
756 
757  if (Steps >= MaxSteps)
758  return false;
759 
760  if (Val.isPowerOf2()) {
761  ++Steps;
762  continue;
763  }
764 
765  APInt Floor = APInt(BitWidth, 1) << Val.logBase2();
766  APInt Ceil = Val.isNegative() ? APInt(BitWidth, 0)
767  : APInt(BitWidth, 1) << C.ceilLogBase2();
768  if ((Val - Floor).ule(Ceil - Val)) {
769  WorkStack.push_back(Floor);
770  WorkStack.push_back(Val - Floor);
771  } else {
772  WorkStack.push_back(Ceil);
773  WorkStack.push_back(Ceil - Val);
774  }
775 
776  ++Steps;
777  }
778 
779  // If the value being multiplied is not supported natively, we have to pay
780  // an additional legalization cost, conservatively assume an increase in the
781  // cost of 3 instructions per step. This values for this heuristic were
782  // determined experimentally.
783  unsigned RegisterSize = DAG.getTargetLoweringInfo()
784  .getRegisterType(*DAG.getContext(), VT)
785  .getSizeInBits();
786  Steps *= (VT.getSizeInBits() != RegisterSize) * 3;
787  if (Steps > 27)
788  return false;
789 
790  return true;
791 }
792 
794  EVT ShiftTy, SelectionDAG &DAG) {
795  // Return 0.
796  if (C == 0)
797  return DAG.getConstant(0, DL, VT);
798 
799  // Return x.
800  if (C == 1)
801  return X;
802 
803  // If c is power of 2, return (shl x, log2(c)).
804  if (C.isPowerOf2())
805  return DAG.getNode(ISD::SHL, DL, VT, X,
806  DAG.getConstant(C.logBase2(), DL, ShiftTy));
807 
808  unsigned BitWidth = C.getBitWidth();
809  APInt Floor = APInt(BitWidth, 1) << C.logBase2();
810  APInt Ceil = C.isNegative() ? APInt(BitWidth, 0) :
811  APInt(BitWidth, 1) << C.ceilLogBase2();
812 
813  // If |c - floor_c| <= |c - ceil_c|,
814  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
815  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
816  if ((C - Floor).ule(Ceil - C)) {
817  SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
818  SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
819  return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
820  }
821 
822  // If |c - floor_c| > |c - ceil_c|,
823  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
824  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
825  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
826  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
827 }
828 
831  const MipsSETargetLowering *TL,
832  const MipsSubtarget &Subtarget) {
833  EVT VT = N->getValueType(0);
834 
835  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
837  C->getAPIntValue(), VT, DAG, Subtarget))
838  return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
839  TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
840  DAG);
841 
842  return SDValue(N, 0);
843 }
844 
845 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
846  SelectionDAG &DAG,
847  const MipsSubtarget &Subtarget) {
848  // See if this is a vector splat immediate node.
849  APInt SplatValue, SplatUndef;
850  unsigned SplatBitSize;
851  bool HasAnyUndefs;
852  unsigned EltSize = Ty.getScalarSizeInBits();
853  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
854 
855  if (!Subtarget.hasDSP())
856  return SDValue();
857 
858  if (!BV ||
859  !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
860  EltSize, !Subtarget.isLittle()) ||
861  (SplatBitSize != EltSize) ||
862  (SplatValue.getZExtValue() >= EltSize))
863  return SDValue();
864 
865  SDLoc DL(N);
866  return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
867  DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
868 }
869 
872  const MipsSubtarget &Subtarget) {
873  EVT Ty = N->getValueType(0);
874 
875  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
876  return SDValue();
877 
878  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
879 }
880 
881 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
882 // constant splats into MipsISD::SHRA_DSP for DSPr2.
883 //
884 // Performs the following transformations:
885 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
886 // sign/zero-extension is completely overwritten by the new one performed by
887 // the ISD::SRA and ISD::SHL nodes.
888 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
889 // sequence.
890 //
891 // See performDSPShiftCombine for more information about the transformation
892 // used for DSPr2.
895  const MipsSubtarget &Subtarget) {
896  EVT Ty = N->getValueType(0);
897 
898  if (Subtarget.hasMSA()) {
899  SDValue Op0 = N->getOperand(0);
900  SDValue Op1 = N->getOperand(1);
901 
902  // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
903  // where $d + sizeof($c) == 32
904  // or $d + sizeof($c) <= 32 and SExt
905  // -> (MipsVExtractSExt $a, $b, $c)
906  if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
907  SDValue Op0Op0 = Op0->getOperand(0);
908  ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
909 
910  if (!ShAmount)
911  return SDValue();
912 
913  if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
915  return SDValue();
916 
917  EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
918  unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
919 
920  if (TotalBits == 32 ||
921  (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
922  TotalBits <= 32)) {
923  SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
924  Op0Op0->getOperand(2) };
925  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
926  Op0Op0->getVTList(),
927  makeArrayRef(Ops, Op0Op0->getNumOperands()));
928  }
929  }
930  }
931 
932  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
933  return SDValue();
934 
935  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
936 }
937 
938 
941  const MipsSubtarget &Subtarget) {
942  EVT Ty = N->getValueType(0);
943 
944  if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
945  return SDValue();
946 
947  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
948 }
949 
950 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
951  bool IsV216 = (Ty == MVT::v2i16);
952 
953  switch (CC) {
954  case ISD::SETEQ:
955  case ISD::SETNE: return true;
956  case ISD::SETLT:
957  case ISD::SETLE:
958  case ISD::SETGT:
959  case ISD::SETGE: return IsV216;
960  case ISD::SETULT:
961  case ISD::SETULE:
962  case ISD::SETUGT:
963  case ISD::SETUGE: return !IsV216;
964  default: return false;
965  }
966 }
967 
969  EVT Ty = N->getValueType(0);
970 
971  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
972  return SDValue();
973 
974  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
975  return SDValue();
976 
977  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
978  N->getOperand(1), N->getOperand(2));
979 }
980 
982  EVT Ty = N->getValueType(0);
983 
984  if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
985  SDValue SetCC = N->getOperand(0);
986 
987  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
988  return SDValue();
989 
990  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
991  SetCC.getOperand(0), SetCC.getOperand(1),
992  N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
993  }
994 
995  return SDValue();
996 }
997 
999  const MipsSubtarget &Subtarget) {
1000  EVT Ty = N->getValueType(0);
1001 
1002  if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
1003  // Try the following combines:
1004  // (xor (or $a, $b), (build_vector allones))
1005  // (xor (or $a, $b), (bitcast (build_vector allones)))
1006  SDValue Op0 = N->getOperand(0);
1007  SDValue Op1 = N->getOperand(1);
1008  SDValue NotOp;
1009 
1011  NotOp = Op1;
1012  else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1013  NotOp = Op0;
1014  else
1015  return SDValue();
1016 
1017  if (NotOp->getOpcode() == ISD::OR)
1018  return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1019  NotOp->getOperand(1));
1020  }
1021 
1022  return SDValue();
1023 }
1024 
1025 SDValue
1027  SelectionDAG &DAG = DCI.DAG;
1028  SDValue Val;
1029 
1030  switch (N->getOpcode()) {
1031  case ISD::AND:
1032  Val = performANDCombine(N, DAG, DCI, Subtarget);
1033  break;
1034  case ISD::OR:
1035  Val = performORCombine(N, DAG, DCI, Subtarget);
1036  break;
1037  case ISD::MUL:
1038  return performMULCombine(N, DAG, DCI, this, Subtarget);
1039  case ISD::SHL:
1040  Val = performSHLCombine(N, DAG, DCI, Subtarget);
1041  break;
1042  case ISD::SRA:
1043  return performSRACombine(N, DAG, DCI, Subtarget);
1044  case ISD::SRL:
1045  return performSRLCombine(N, DAG, DCI, Subtarget);
1046  case ISD::VSELECT:
1047  return performVSELECTCombine(N, DAG);
1048  case ISD::XOR:
1049  Val = performXORCombine(N, DAG, Subtarget);
1050  break;
1051  case ISD::SETCC:
1052  Val = performSETCCCombine(N, DAG);
1053  break;
1054  }
1055 
1056  if (Val.getNode()) {
1057  LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1058  N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n";
1059  Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n");
1060  return Val;
1061  }
1062 
1064 }
1065 
1068  MachineBasicBlock *BB) const {
1069  switch (MI.getOpcode()) {
1070  default:
1072  case Mips::BPOSGE32_PSEUDO:
1073  return emitBPOSGE32(MI, BB);
1074  case Mips::SNZ_B_PSEUDO:
1075  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1076  case Mips::SNZ_H_PSEUDO:
1077  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1078  case Mips::SNZ_W_PSEUDO:
1079  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1080  case Mips::SNZ_D_PSEUDO:
1081  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1082  case Mips::SNZ_V_PSEUDO:
1083  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1084  case Mips::SZ_B_PSEUDO:
1085  return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1086  case Mips::SZ_H_PSEUDO:
1087  return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1088  case Mips::SZ_W_PSEUDO:
1089  return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1090  case Mips::SZ_D_PSEUDO:
1091  return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1092  case Mips::SZ_V_PSEUDO:
1093  return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1094  case Mips::COPY_FW_PSEUDO:
1095  return emitCOPY_FW(MI, BB);
1096  case Mips::COPY_FD_PSEUDO:
1097  return emitCOPY_FD(MI, BB);
1098  case Mips::INSERT_FW_PSEUDO:
1099  return emitINSERT_FW(MI, BB);
1100  case Mips::INSERT_FD_PSEUDO:
1101  return emitINSERT_FD(MI, BB);
1102  case Mips::INSERT_B_VIDX_PSEUDO:
1103  case Mips::INSERT_B_VIDX64_PSEUDO:
1104  return emitINSERT_DF_VIDX(MI, BB, 1, false);
1105  case Mips::INSERT_H_VIDX_PSEUDO:
1106  case Mips::INSERT_H_VIDX64_PSEUDO:
1107  return emitINSERT_DF_VIDX(MI, BB, 2, false);
1108  case Mips::INSERT_W_VIDX_PSEUDO:
1109  case Mips::INSERT_W_VIDX64_PSEUDO:
1110  return emitINSERT_DF_VIDX(MI, BB, 4, false);
1111  case Mips::INSERT_D_VIDX_PSEUDO:
1112  case Mips::INSERT_D_VIDX64_PSEUDO:
1113  return emitINSERT_DF_VIDX(MI, BB, 8, false);
1114  case Mips::INSERT_FW_VIDX_PSEUDO:
1115  case Mips::INSERT_FW_VIDX64_PSEUDO:
1116  return emitINSERT_DF_VIDX(MI, BB, 4, true);
1117  case Mips::INSERT_FD_VIDX_PSEUDO:
1118  case Mips::INSERT_FD_VIDX64_PSEUDO:
1119  return emitINSERT_DF_VIDX(MI, BB, 8, true);
1120  case Mips::FILL_FW_PSEUDO:
1121  return emitFILL_FW(MI, BB);
1122  case Mips::FILL_FD_PSEUDO:
1123  return emitFILL_FD(MI, BB);
1124  case Mips::FEXP2_W_1_PSEUDO:
1125  return emitFEXP2_W_1(MI, BB);
1126  case Mips::FEXP2_D_1_PSEUDO:
1127  return emitFEXP2_D_1(MI, BB);
1128  case Mips::ST_F16:
1129  return emitST_F16_PSEUDO(MI, BB);
1130  case Mips::LD_F16:
1131  return emitLD_F16_PSEUDO(MI, BB);
1132  case Mips::MSA_FP_EXTEND_W_PSEUDO:
1133  return emitFPEXTEND_PSEUDO(MI, BB, false);
1134  case Mips::MSA_FP_ROUND_W_PSEUDO:
1135  return emitFPROUND_PSEUDO(MI, BB, false);
1136  case Mips::MSA_FP_EXTEND_D_PSEUDO:
1137  return emitFPEXTEND_PSEUDO(MI, BB, true);
1138  case Mips::MSA_FP_ROUND_D_PSEUDO:
1139  return emitFPROUND_PSEUDO(MI, BB, true);
1140  }
1141 }
1142 
1143 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1144  const CCState &CCInfo, unsigned NextStackOffset,
1145  const MipsFunctionInfo &FI) const {
1146  if (!UseMipsTailCalls)
1147  return false;
1148 
1149  // Exception has to be cleared with eret.
1150  if (FI.isISR())
1151  return false;
1152 
1153  // Return false if either the callee or caller has a byval argument.
1154  if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1155  return false;
1156 
1157  // Return true if the callee's argument area is no larger than the
1158  // caller's.
1159  return NextStackOffset <= FI.getIncomingArgSize();
1160 }
1161 
1162 void MipsSETargetLowering::
1163 getOpndList(SmallVectorImpl<SDValue> &Ops,
1164  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1165  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1166  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1167  SDValue Chain) const {
1168  Ops.push_back(Callee);
1169  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1170  InternalLinkage, IsCallReloc, CLI, Callee,
1171  Chain);
1172 }
1173 
1174 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1175  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1176 
1177  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1178  return MipsTargetLowering::lowerLOAD(Op, DAG);
1179 
1180  // Replace a double precision load with two i32 loads and a buildpair64.
1181  SDLoc DL(Op);
1182  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1183  EVT PtrVT = Ptr.getValueType();
1184 
1185  // i32 load from lower address.
1186  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1187  Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1188 
1189  // i32 load from higher address.
1190  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1191  SDValue Hi = DAG.getLoad(
1192  MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1193  std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1194 
1195  if (!Subtarget.isLittle())
1196  std::swap(Lo, Hi);
1197 
1199  SDValue Ops[2] = {BP, Hi.getValue(1)};
1200  return DAG.getMergeValues(Ops, DL);
1201 }
1202 
1203 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1204  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1205 
1206  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1207  return MipsTargetLowering::lowerSTORE(Op, DAG);
1208 
1209  // Replace a double precision store with two extractelement64s and i32 stores.
1210  SDLoc DL(Op);
1211  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1212  EVT PtrVT = Ptr.getValueType();
1214  Val, DAG.getConstant(0, DL, MVT::i32));
1216  Val, DAG.getConstant(1, DL, MVT::i32));
1217 
1218  if (!Subtarget.isLittle())
1219  std::swap(Lo, Hi);
1220 
1221  // i32 store to lower address.
1222  Chain =
1223  DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1224  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1225 
1226  // i32 store to higher address.
1227  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1228  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1229  std::min(Nd.getAlignment(), 4U),
1230  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1231 }
1232 
1233 SDValue MipsSETargetLowering::lowerBITCAST(SDValue Op,
1234  SelectionDAG &DAG) const {
1235  SDLoc DL(Op);
1236  MVT Src = Op.getOperand(0).getValueType().getSimpleVT();
1237  MVT Dest = Op.getValueType().getSimpleVT();
1238 
1239  // Bitcast i64 to double.
1240  if (Src == MVT::i64 && Dest == MVT::f64) {
1242  Op.getOperand(0), DAG.getIntPtrConstant(0, DL));
1244  Op.getOperand(0), DAG.getIntPtrConstant(1, DL));
1245  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1246  }
1247 
1248  // Bitcast double to i64.
1249  if (Src == MVT::f64 && Dest == MVT::i64) {
1250  SDValue Lo =
1251  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1252  DAG.getConstant(0, DL, MVT::i32));
1253  SDValue Hi =
1254  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1255  DAG.getConstant(1, DL, MVT::i32));
1256  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1257  }
1258 
1259  // Skip other cases of bitcast and use default lowering.
1260  return SDValue();
1261 }
1262 
1263 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1264  bool HasLo, bool HasHi,
1265  SelectionDAG &DAG) const {
1266  // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1268 
1269  EVT Ty = Op.getOperand(0).getValueType();
1270  SDLoc DL(Op);
1271  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1272  Op.getOperand(0), Op.getOperand(1));
1273  SDValue Lo, Hi;
1274 
1275  if (HasLo)
1276  Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1277  if (HasHi)
1278  Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1279 
1280  if (!HasLo || !HasHi)
1281  return HasLo ? Lo : Hi;
1282 
1283  SDValue Vals[] = { Lo, Hi };
1284  return DAG.getMergeValues(Vals, DL);
1285 }
1286 
1289  DAG.getConstant(0, DL, MVT::i32));
1291  DAG.getConstant(1, DL, MVT::i32));
1292  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1293 }
1294 
1298  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1299 }
1300 
1301 // This function expands mips intrinsic nodes which have 64-bit input operands
1302 // or output values.
1303 //
1304 // out64 = intrinsic-node in64
1305 // =>
1306 // lo = copy (extract-element (in64, 0))
1307 // hi = copy (extract-element (in64, 1))
1308 // mips-specific-node
1309 // v0 = copy lo
1310 // v1 = copy hi
1311 // out64 = merge-values (v0, v1)
1312 //
1313 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1314  SDLoc DL(Op);
1315  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1317  unsigned OpNo = 0;
1318 
1319  // See if Op has a chain input.
1320  if (HasChainIn)
1321  Ops.push_back(Op->getOperand(OpNo++));
1322 
1323  // The next operand is the intrinsic opcode.
1324  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1325 
1326  // See if the next operand has type i64.
1327  SDValue Opnd = Op->getOperand(++OpNo), In64;
1328 
1329  if (Opnd.getValueType() == MVT::i64)
1330  In64 = initAccumulator(Opnd, DL, DAG);
1331  else
1332  Ops.push_back(Opnd);
1333 
1334  // Push the remaining operands.
1335  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1336  Ops.push_back(Op->getOperand(OpNo));
1337 
1338  // Add In64 to the end of the list.
1339  if (In64.getNode())
1340  Ops.push_back(In64);
1341 
1342  // Scan output.
1343  SmallVector<EVT, 2> ResTys;
1344 
1345  for (EVT Ty : Op->values())
1346  ResTys.push_back((Ty == MVT::i64) ? MVT::Untyped : Ty);
1347 
1348  // Create node.
1349  SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1350  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1351 
1352  if (!HasChainIn)
1353  return Out;
1354 
1355  assert(Val->getValueType(1) == MVT::Other);
1356  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1357  return DAG.getMergeValues(Vals, DL);
1358 }
1359 
1360 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1361 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1362  SDLoc DL(Op);
1363  SDValue Vec = Op->getOperand(1);
1364  SDValue Idx = Op->getOperand(2);
1365  EVT ResTy = Op->getValueType(0);
1366  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1367 
1368  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1369  DAG.getValueType(EltTy));
1370 
1371  return Result;
1372 }
1373 
1374 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1375  EVT ResVecTy = Op->getValueType(0);
1376  EVT ViaVecTy = ResVecTy;
1377  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1378  SDLoc DL(Op);
1379 
1380  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1381  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1382  // lanes.
1383  SDValue LaneA = Op->getOperand(OpNr);
1384  SDValue LaneB;
1385 
1386  if (ResVecTy == MVT::v2i64) {
1387  // In case of the index being passed as an immediate value, set the upper
1388  // lane to 0 so that the splati.d instruction can be matched.
1389  if (isa<ConstantSDNode>(LaneA))
1390  LaneB = DAG.getConstant(0, DL, MVT::i32);
1391  // Having the index passed in a register, set the upper lane to the same
1392  // value as the lower - this results in the BUILD_VECTOR node not being
1393  // expanded through stack. This way we are able to pattern match the set of
1394  // nodes created here to splat.d.
1395  else
1396  LaneB = LaneA;
1397  ViaVecTy = MVT::v4i32;
1398  if(BigEndian)
1399  std::swap(LaneA, LaneB);
1400  } else
1401  LaneB = LaneA;
1402 
1403  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1404  LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1405 
1406  SDValue Result = DAG.getBuildVector(
1407  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1408 
1409  if (ViaVecTy != ResVecTy) {
1410  SDValue One = DAG.getConstant(1, DL, ViaVecTy);
1411  Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1412  DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1413  }
1414 
1415  return Result;
1416 }
1417 
1418 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1419  bool IsSigned = false) {
1420  auto *CImm = cast<ConstantSDNode>(Op->getOperand(ImmOp));
1421  return DAG.getConstant(
1422  APInt(Op->getValueType(0).getScalarType().getSizeInBits(),
1423  IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
1424  SDLoc(Op), Op->getValueType(0));
1425 }
1426 
1427 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1428  bool BigEndian, SelectionDAG &DAG) {
1429  EVT ViaVecTy = VecTy;
1430  SDValue SplatValueA = SplatValue;
1431  SDValue SplatValueB = SplatValue;
1432  SDLoc DL(SplatValue);
1433 
1434  if (VecTy == MVT::v2i64) {
1435  // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1436  ViaVecTy = MVT::v4i32;
1437 
1438  SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1439  SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1440  DAG.getConstant(32, DL, MVT::i32));
1441  SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1442  }
1443 
1444  // We currently hold the parts in little endian order. Swap them if
1445  // necessary.
1446  if (BigEndian)
1447  std::swap(SplatValueA, SplatValueB);
1448 
1449  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1450  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1451  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1452  SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1453 
1454  SDValue Result = DAG.getBuildVector(
1455  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1456 
1457  if (VecTy != ViaVecTy)
1458  Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1459 
1460  return Result;
1461 }
1462 
1464  unsigned Opc, SDValue Imm,
1465  bool BigEndian) {
1466  EVT VecTy = Op->getValueType(0);
1467  SDValue Exp2Imm;
1468  SDLoc DL(Op);
1469 
1470  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1471  // here for now.
1472  if (VecTy == MVT::v2i64) {
1473  if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1474  APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1475 
1476  SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1477  MVT::i32);
1478  SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1479 
1480  if (BigEndian)
1481  std::swap(BitImmLoOp, BitImmHiOp);
1482 
1483  Exp2Imm = DAG.getNode(
1486  {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1487  }
1488  }
1489 
1490  if (!Exp2Imm.getNode()) {
1491  // We couldnt constant fold, do a vector shift instead
1492 
1493  // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1494  // only values 0-63 are valid.
1495  if (VecTy == MVT::v2i64)
1496  Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1497 
1498  Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1499 
1500  Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1501  Exp2Imm);
1502  }
1503 
1504  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1505 }
1506 
1508  SDLoc DL(Op);
1509  EVT ResTy = Op->getValueType(0);
1510  SDValue Vec = Op->getOperand(2);
1511  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1512  MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1513  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1514  DL, ResEltTy);
1515  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1516 
1517  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1518 }
1519 
1521  EVT ResTy = Op->getValueType(0);
1522  SDLoc DL(Op);
1523  SDValue One = DAG.getConstant(1, DL, ResTy);
1524  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1525 
1526  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1527  DAG.getNOT(DL, Bit, ResTy));
1528 }
1529 
1531  SDLoc DL(Op);
1532  EVT ResTy = Op->getValueType(0);
1533  APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1534  << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1535  SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1536 
1537  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1538 }
1539 
1540 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1541  SelectionDAG &DAG) const {
1542  SDLoc DL(Op);
1543  unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1544  switch (Intrinsic) {
1545  default:
1546  return SDValue();
1547  case Intrinsic::mips_shilo:
1548  return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1549  case Intrinsic::mips_dpau_h_qbl:
1550  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1551  case Intrinsic::mips_dpau_h_qbr:
1552  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1553  case Intrinsic::mips_dpsu_h_qbl:
1554  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1555  case Intrinsic::mips_dpsu_h_qbr:
1556  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1557  case Intrinsic::mips_dpa_w_ph:
1558  return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1559  case Intrinsic::mips_dps_w_ph:
1560  return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1561  case Intrinsic::mips_dpax_w_ph:
1562  return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1563  case Intrinsic::mips_dpsx_w_ph:
1564  return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1565  case Intrinsic::mips_mulsa_w_ph:
1566  return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1567  case Intrinsic::mips_mult:
1568  return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1569  case Intrinsic::mips_multu:
1570  return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1571  case Intrinsic::mips_madd:
1572  return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1573  case Intrinsic::mips_maddu:
1574  return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1575  case Intrinsic::mips_msub:
1576  return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1577  case Intrinsic::mips_msubu:
1578  return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1579  case Intrinsic::mips_addv_b:
1580  case Intrinsic::mips_addv_h:
1581  case Intrinsic::mips_addv_w:
1582  case Intrinsic::mips_addv_d:
1583  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1584  Op->getOperand(2));
1585  case Intrinsic::mips_addvi_b:
1586  case Intrinsic::mips_addvi_h:
1587  case Intrinsic::mips_addvi_w:
1588  case Intrinsic::mips_addvi_d:
1589  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1590  lowerMSASplatImm(Op, 2, DAG));
1591  case Intrinsic::mips_and_v:
1592  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1593  Op->getOperand(2));
1594  case Intrinsic::mips_andi_b:
1595  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1596  lowerMSASplatImm(Op, 2, DAG));
1597  case Intrinsic::mips_bclr_b:
1598  case Intrinsic::mips_bclr_h:
1599  case Intrinsic::mips_bclr_w:
1600  case Intrinsic::mips_bclr_d:
1601  return lowerMSABitClear(Op, DAG);
1602  case Intrinsic::mips_bclri_b:
1603  case Intrinsic::mips_bclri_h:
1604  case Intrinsic::mips_bclri_w:
1605  case Intrinsic::mips_bclri_d:
1606  return lowerMSABitClearImm(Op, DAG);
1607  case Intrinsic::mips_binsli_b:
1608  case Intrinsic::mips_binsli_h:
1609  case Intrinsic::mips_binsli_w:
1610  case Intrinsic::mips_binsli_d: {
1611  // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1612  EVT VecTy = Op->getValueType(0);
1613  EVT EltTy = VecTy.getVectorElementType();
1614  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1615  report_fatal_error("Immediate out of range");
1617  Op->getConstantOperandVal(3) + 1);
1618  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1619  DAG.getConstant(Mask, DL, VecTy, true),
1620  Op->getOperand(2), Op->getOperand(1));
1621  }
1622  case Intrinsic::mips_binsri_b:
1623  case Intrinsic::mips_binsri_h:
1624  case Intrinsic::mips_binsri_w:
1625  case Intrinsic::mips_binsri_d: {
1626  // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1627  EVT VecTy = Op->getValueType(0);
1628  EVT EltTy = VecTy.getVectorElementType();
1629  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1630  report_fatal_error("Immediate out of range");
1632  Op->getConstantOperandVal(3) + 1);
1633  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1634  DAG.getConstant(Mask, DL, VecTy, true),
1635  Op->getOperand(2), Op->getOperand(1));
1636  }
1637  case Intrinsic::mips_bmnz_v:
1638  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1639  Op->getOperand(2), Op->getOperand(1));
1640  case Intrinsic::mips_bmnzi_b:
1641  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1642  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1643  Op->getOperand(1));
1644  case Intrinsic::mips_bmz_v:
1645  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1646  Op->getOperand(1), Op->getOperand(2));
1647  case Intrinsic::mips_bmzi_b:
1648  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1649  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1650  Op->getOperand(2));
1651  case Intrinsic::mips_bneg_b:
1652  case Intrinsic::mips_bneg_h:
1653  case Intrinsic::mips_bneg_w:
1654  case Intrinsic::mips_bneg_d: {
1655  EVT VecTy = Op->getValueType(0);
1656  SDValue One = DAG.getConstant(1, DL, VecTy);
1657 
1658  return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1659  DAG.getNode(ISD::SHL, DL, VecTy, One,
1660  truncateVecElts(Op, DAG)));
1661  }
1662  case Intrinsic::mips_bnegi_b:
1663  case Intrinsic::mips_bnegi_h:
1664  case Intrinsic::mips_bnegi_w:
1665  case Intrinsic::mips_bnegi_d:
1666  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1667  !Subtarget.isLittle());
1668  case Intrinsic::mips_bnz_b:
1669  case Intrinsic::mips_bnz_h:
1670  case Intrinsic::mips_bnz_w:
1671  case Intrinsic::mips_bnz_d:
1672  return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1673  Op->getOperand(1));
1674  case Intrinsic::mips_bnz_v:
1675  return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1676  Op->getOperand(1));
1677  case Intrinsic::mips_bsel_v:
1678  // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1679  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1680  Op->getOperand(1), Op->getOperand(3),
1681  Op->getOperand(2));
1682  case Intrinsic::mips_bseli_b:
1683  // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1684  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1685  Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1686  Op->getOperand(2));
1687  case Intrinsic::mips_bset_b:
1688  case Intrinsic::mips_bset_h:
1689  case Intrinsic::mips_bset_w:
1690  case Intrinsic::mips_bset_d: {
1691  EVT VecTy = Op->getValueType(0);
1692  SDValue One = DAG.getConstant(1, DL, VecTy);
1693 
1694  return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1695  DAG.getNode(ISD::SHL, DL, VecTy, One,
1696  truncateVecElts(Op, DAG)));
1697  }
1698  case Intrinsic::mips_bseti_b:
1699  case Intrinsic::mips_bseti_h:
1700  case Intrinsic::mips_bseti_w:
1701  case Intrinsic::mips_bseti_d:
1702  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1703  !Subtarget.isLittle());
1704  case Intrinsic::mips_bz_b:
1705  case Intrinsic::mips_bz_h:
1706  case Intrinsic::mips_bz_w:
1707  case Intrinsic::mips_bz_d:
1708  return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1709  Op->getOperand(1));
1710  case Intrinsic::mips_bz_v:
1711  return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1712  Op->getOperand(1));
1713  case Intrinsic::mips_ceq_b:
1714  case Intrinsic::mips_ceq_h:
1715  case Intrinsic::mips_ceq_w:
1716  case Intrinsic::mips_ceq_d:
1717  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1718  Op->getOperand(2), ISD::SETEQ);
1719  case Intrinsic::mips_ceqi_b:
1720  case Intrinsic::mips_ceqi_h:
1721  case Intrinsic::mips_ceqi_w:
1722  case Intrinsic::mips_ceqi_d:
1723  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1724  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1725  case Intrinsic::mips_cle_s_b:
1726  case Intrinsic::mips_cle_s_h:
1727  case Intrinsic::mips_cle_s_w:
1728  case Intrinsic::mips_cle_s_d:
1729  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1730  Op->getOperand(2), ISD::SETLE);
1731  case Intrinsic::mips_clei_s_b:
1732  case Intrinsic::mips_clei_s_h:
1733  case Intrinsic::mips_clei_s_w:
1734  case Intrinsic::mips_clei_s_d:
1735  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1736  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1737  case Intrinsic::mips_cle_u_b:
1738  case Intrinsic::mips_cle_u_h:
1739  case Intrinsic::mips_cle_u_w:
1740  case Intrinsic::mips_cle_u_d:
1741  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1742  Op->getOperand(2), ISD::SETULE);
1743  case Intrinsic::mips_clei_u_b:
1744  case Intrinsic::mips_clei_u_h:
1745  case Intrinsic::mips_clei_u_w:
1746  case Intrinsic::mips_clei_u_d:
1747  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1748  lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1749  case Intrinsic::mips_clt_s_b:
1750  case Intrinsic::mips_clt_s_h:
1751  case Intrinsic::mips_clt_s_w:
1752  case Intrinsic::mips_clt_s_d:
1753  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1754  Op->getOperand(2), ISD::SETLT);
1755  case Intrinsic::mips_clti_s_b:
1756  case Intrinsic::mips_clti_s_h:
1757  case Intrinsic::mips_clti_s_w:
1758  case Intrinsic::mips_clti_s_d:
1759  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1760  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1761  case Intrinsic::mips_clt_u_b:
1762  case Intrinsic::mips_clt_u_h:
1763  case Intrinsic::mips_clt_u_w:
1764  case Intrinsic::mips_clt_u_d:
1765  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1766  Op->getOperand(2), ISD::SETULT);
1767  case Intrinsic::mips_clti_u_b:
1768  case Intrinsic::mips_clti_u_h:
1769  case Intrinsic::mips_clti_u_w:
1770  case Intrinsic::mips_clti_u_d:
1771  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1772  lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1773  case Intrinsic::mips_copy_s_b:
1774  case Intrinsic::mips_copy_s_h:
1775  case Intrinsic::mips_copy_s_w:
1777  case Intrinsic::mips_copy_s_d:
1778  if (Subtarget.hasMips64())
1779  // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1781  else {
1782  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1783  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1784  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1785  Op->getValueType(0), Op->getOperand(1),
1786  Op->getOperand(2));
1787  }
1788  case Intrinsic::mips_copy_u_b:
1789  case Intrinsic::mips_copy_u_h:
1790  case Intrinsic::mips_copy_u_w:
1792  case Intrinsic::mips_copy_u_d:
1793  if (Subtarget.hasMips64())
1794  // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1796  else {
1797  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1798  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1799  // Note: When i64 is illegal, this results in copy_s.w instructions
1800  // instead of copy_u.w instructions. This makes no difference to the
1801  // behaviour since i64 is only illegal when the register file is 32-bit.
1802  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1803  Op->getValueType(0), Op->getOperand(1),
1804  Op->getOperand(2));
1805  }
1806  case Intrinsic::mips_div_s_b:
1807  case Intrinsic::mips_div_s_h:
1808  case Intrinsic::mips_div_s_w:
1809  case Intrinsic::mips_div_s_d:
1810  return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1811  Op->getOperand(2));
1812  case Intrinsic::mips_div_u_b:
1813  case Intrinsic::mips_div_u_h:
1814  case Intrinsic::mips_div_u_w:
1815  case Intrinsic::mips_div_u_d:
1816  return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1817  Op->getOperand(2));
1818  case Intrinsic::mips_fadd_w:
1819  case Intrinsic::mips_fadd_d:
1820  // TODO: If intrinsics have fast-math-flags, propagate them.
1821  return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1822  Op->getOperand(2));
1823  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1824  case Intrinsic::mips_fceq_w:
1825  case Intrinsic::mips_fceq_d:
1826  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1827  Op->getOperand(2), ISD::SETOEQ);
1828  case Intrinsic::mips_fcle_w:
1829  case Intrinsic::mips_fcle_d:
1830  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1831  Op->getOperand(2), ISD::SETOLE);
1832  case Intrinsic::mips_fclt_w:
1833  case Intrinsic::mips_fclt_d:
1834  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1835  Op->getOperand(2), ISD::SETOLT);
1836  case Intrinsic::mips_fcne_w:
1837  case Intrinsic::mips_fcne_d:
1838  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1839  Op->getOperand(2), ISD::SETONE);
1840  case Intrinsic::mips_fcor_w:
1841  case Intrinsic::mips_fcor_d:
1842  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1843  Op->getOperand(2), ISD::SETO);
1844  case Intrinsic::mips_fcueq_w:
1845  case Intrinsic::mips_fcueq_d:
1846  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1847  Op->getOperand(2), ISD::SETUEQ);
1848  case Intrinsic::mips_fcule_w:
1849  case Intrinsic::mips_fcule_d:
1850  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1851  Op->getOperand(2), ISD::SETULE);
1852  case Intrinsic::mips_fcult_w:
1853  case Intrinsic::mips_fcult_d:
1854  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1855  Op->getOperand(2), ISD::SETULT);
1856  case Intrinsic::mips_fcun_w:
1857  case Intrinsic::mips_fcun_d:
1858  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1859  Op->getOperand(2), ISD::SETUO);
1860  case Intrinsic::mips_fcune_w:
1861  case Intrinsic::mips_fcune_d:
1862  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1863  Op->getOperand(2), ISD::SETUNE);
1864  case Intrinsic::mips_fdiv_w:
1865  case Intrinsic::mips_fdiv_d:
1866  // TODO: If intrinsics have fast-math-flags, propagate them.
1867  return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1868  Op->getOperand(2));
1869  case Intrinsic::mips_ffint_u_w:
1870  case Intrinsic::mips_ffint_u_d:
1871  return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1872  Op->getOperand(1));
1873  case Intrinsic::mips_ffint_s_w:
1874  case Intrinsic::mips_ffint_s_d:
1875  return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1876  Op->getOperand(1));
1877  case Intrinsic::mips_fill_b:
1878  case Intrinsic::mips_fill_h:
1879  case Intrinsic::mips_fill_w:
1880  case Intrinsic::mips_fill_d: {
1881  EVT ResTy = Op->getValueType(0);
1883  Op->getOperand(1));
1884 
1885  // If ResTy is v2i64 then the type legalizer will break this node down into
1886  // an equivalent v4i32.
1887  return DAG.getBuildVector(ResTy, DL, Ops);
1888  }
1889  case Intrinsic::mips_fexp2_w:
1890  case Intrinsic::mips_fexp2_d: {
1891  // TODO: If intrinsics have fast-math-flags, propagate them.
1892  EVT ResTy = Op->getValueType(0);
1893  return DAG.getNode(
1894  ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1895  DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1896  }
1897  case Intrinsic::mips_flog2_w:
1898  case Intrinsic::mips_flog2_d:
1899  return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1900  case Intrinsic::mips_fmadd_w:
1901  case Intrinsic::mips_fmadd_d:
1902  return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1903  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1904  case Intrinsic::mips_fmul_w:
1905  case Intrinsic::mips_fmul_d:
1906  // TODO: If intrinsics have fast-math-flags, propagate them.
1907  return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1908  Op->getOperand(2));
1909  case Intrinsic::mips_fmsub_w:
1910  case Intrinsic::mips_fmsub_d: {
1911  // TODO: If intrinsics have fast-math-flags, propagate them.
1912  return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
1913  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1914  }
1915  case Intrinsic::mips_frint_w:
1916  case Intrinsic::mips_frint_d:
1917  return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1918  case Intrinsic::mips_fsqrt_w:
1919  case Intrinsic::mips_fsqrt_d:
1920  return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1921  case Intrinsic::mips_fsub_w:
1922  case Intrinsic::mips_fsub_d:
1923  // TODO: If intrinsics have fast-math-flags, propagate them.
1924  return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1925  Op->getOperand(2));
1926  case Intrinsic::mips_ftrunc_u_w:
1927  case Intrinsic::mips_ftrunc_u_d:
1928  return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1929  Op->getOperand(1));
1930  case Intrinsic::mips_ftrunc_s_w:
1931  case Intrinsic::mips_ftrunc_s_d:
1932  return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1933  Op->getOperand(1));
1934  case Intrinsic::mips_ilvev_b:
1935  case Intrinsic::mips_ilvev_h:
1936  case Intrinsic::mips_ilvev_w:
1937  case Intrinsic::mips_ilvev_d:
1938  return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1939  Op->getOperand(1), Op->getOperand(2));
1940  case Intrinsic::mips_ilvl_b:
1941  case Intrinsic::mips_ilvl_h:
1942  case Intrinsic::mips_ilvl_w:
1943  case Intrinsic::mips_ilvl_d:
1944  return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1945  Op->getOperand(1), Op->getOperand(2));
1946  case Intrinsic::mips_ilvod_b:
1947  case Intrinsic::mips_ilvod_h:
1948  case Intrinsic::mips_ilvod_w:
1949  case Intrinsic::mips_ilvod_d:
1950  return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1951  Op->getOperand(1), Op->getOperand(2));
1952  case Intrinsic::mips_ilvr_b:
1953  case Intrinsic::mips_ilvr_h:
1954  case Intrinsic::mips_ilvr_w:
1955  case Intrinsic::mips_ilvr_d:
1956  return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1957  Op->getOperand(1), Op->getOperand(2));
1958  case Intrinsic::mips_insert_b:
1959  case Intrinsic::mips_insert_h:
1960  case Intrinsic::mips_insert_w:
1961  case Intrinsic::mips_insert_d:
1962  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1963  Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1964  case Intrinsic::mips_insve_b:
1965  case Intrinsic::mips_insve_h:
1966  case Intrinsic::mips_insve_w:
1967  case Intrinsic::mips_insve_d: {
1968  // Report an error for out of range values.
1969  int64_t Max;
1970  switch (Intrinsic) {
1971  case Intrinsic::mips_insve_b: Max = 15; break;
1972  case Intrinsic::mips_insve_h: Max = 7; break;
1973  case Intrinsic::mips_insve_w: Max = 3; break;
1974  case Intrinsic::mips_insve_d: Max = 1; break;
1975  default: llvm_unreachable("Unmatched intrinsic");
1976  }
1977  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1978  if (Value < 0 || Value > Max)
1979  report_fatal_error("Immediate out of range");
1980  return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1981  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1982  DAG.getConstant(0, DL, MVT::i32));
1983  }
1984  case Intrinsic::mips_ldi_b:
1985  case Intrinsic::mips_ldi_h:
1986  case Intrinsic::mips_ldi_w:
1987  case Intrinsic::mips_ldi_d:
1988  return lowerMSASplatImm(Op, 1, DAG, true);
1989  case Intrinsic::mips_lsa:
1990  case Intrinsic::mips_dlsa: {
1991  EVT ResTy = Op->getValueType(0);
1992  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1993  DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1994  Op->getOperand(2), Op->getOperand(3)));
1995  }
1996  case Intrinsic::mips_maddv_b:
1997  case Intrinsic::mips_maddv_h:
1998  case Intrinsic::mips_maddv_w:
1999  case Intrinsic::mips_maddv_d: {
2000  EVT ResTy = Op->getValueType(0);
2001  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2002  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2003  Op->getOperand(2), Op->getOperand(3)));
2004  }
2005  case Intrinsic::mips_max_s_b:
2006  case Intrinsic::mips_max_s_h:
2007  case Intrinsic::mips_max_s_w:
2008  case Intrinsic::mips_max_s_d:
2009  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2010  Op->getOperand(1), Op->getOperand(2));
2011  case Intrinsic::mips_max_u_b:
2012  case Intrinsic::mips_max_u_h:
2013  case Intrinsic::mips_max_u_w:
2014  case Intrinsic::mips_max_u_d:
2015  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2016  Op->getOperand(1), Op->getOperand(2));
2017  case Intrinsic::mips_maxi_s_b:
2018  case Intrinsic::mips_maxi_s_h:
2019  case Intrinsic::mips_maxi_s_w:
2020  case Intrinsic::mips_maxi_s_d:
2021  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2022  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2023  case Intrinsic::mips_maxi_u_b:
2024  case Intrinsic::mips_maxi_u_h:
2025  case Intrinsic::mips_maxi_u_w:
2026  case Intrinsic::mips_maxi_u_d:
2027  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2028  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2029  case Intrinsic::mips_min_s_b:
2030  case Intrinsic::mips_min_s_h:
2031  case Intrinsic::mips_min_s_w:
2032  case Intrinsic::mips_min_s_d:
2033  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2034  Op->getOperand(1), Op->getOperand(2));
2035  case Intrinsic::mips_min_u_b:
2036  case Intrinsic::mips_min_u_h:
2037  case Intrinsic::mips_min_u_w:
2038  case Intrinsic::mips_min_u_d:
2039  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2040  Op->getOperand(1), Op->getOperand(2));
2041  case Intrinsic::mips_mini_s_b:
2042  case Intrinsic::mips_mini_s_h:
2043  case Intrinsic::mips_mini_s_w:
2044  case Intrinsic::mips_mini_s_d:
2045  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2046  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2047  case Intrinsic::mips_mini_u_b:
2048  case Intrinsic::mips_mini_u_h:
2049  case Intrinsic::mips_mini_u_w:
2050  case Intrinsic::mips_mini_u_d:
2051  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2052  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2053  case Intrinsic::mips_mod_s_b:
2054  case Intrinsic::mips_mod_s_h:
2055  case Intrinsic::mips_mod_s_w:
2056  case Intrinsic::mips_mod_s_d:
2057  return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2058  Op->getOperand(2));
2059  case Intrinsic::mips_mod_u_b:
2060  case Intrinsic::mips_mod_u_h:
2061  case Intrinsic::mips_mod_u_w:
2062  case Intrinsic::mips_mod_u_d:
2063  return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2064  Op->getOperand(2));
2065  case Intrinsic::mips_mulv_b:
2066  case Intrinsic::mips_mulv_h:
2067  case Intrinsic::mips_mulv_w:
2068  case Intrinsic::mips_mulv_d:
2069  return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2070  Op->getOperand(2));
2071  case Intrinsic::mips_msubv_b:
2072  case Intrinsic::mips_msubv_h:
2073  case Intrinsic::mips_msubv_w:
2074  case Intrinsic::mips_msubv_d: {
2075  EVT ResTy = Op->getValueType(0);
2076  return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2077  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2078  Op->getOperand(2), Op->getOperand(3)));
2079  }
2080  case Intrinsic::mips_nlzc_b:
2081  case Intrinsic::mips_nlzc_h:
2082  case Intrinsic::mips_nlzc_w:
2083  case Intrinsic::mips_nlzc_d:
2084  return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2085  case Intrinsic::mips_nor_v: {
2086  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2087  Op->getOperand(1), Op->getOperand(2));
2088  return DAG.getNOT(DL, Res, Res->getValueType(0));
2089  }
2090  case Intrinsic::mips_nori_b: {
2091  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2092  Op->getOperand(1),
2093  lowerMSASplatImm(Op, 2, DAG));
2094  return DAG.getNOT(DL, Res, Res->getValueType(0));
2095  }
2096  case Intrinsic::mips_or_v:
2097  return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2098  Op->getOperand(2));
2099  case Intrinsic::mips_ori_b:
2100  return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2101  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2102  case Intrinsic::mips_pckev_b:
2103  case Intrinsic::mips_pckev_h:
2104  case Intrinsic::mips_pckev_w:
2105  case Intrinsic::mips_pckev_d:
2106  return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2107  Op->getOperand(1), Op->getOperand(2));
2108  case Intrinsic::mips_pckod_b:
2109  case Intrinsic::mips_pckod_h:
2110  case Intrinsic::mips_pckod_w:
2111  case Intrinsic::mips_pckod_d:
2112  return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2113  Op->getOperand(1), Op->getOperand(2));
2114  case Intrinsic::mips_pcnt_b:
2115  case Intrinsic::mips_pcnt_h:
2116  case Intrinsic::mips_pcnt_w:
2117  case Intrinsic::mips_pcnt_d:
2118  return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2119  case Intrinsic::mips_sat_s_b:
2120  case Intrinsic::mips_sat_s_h:
2121  case Intrinsic::mips_sat_s_w:
2122  case Intrinsic::mips_sat_s_d:
2123  case Intrinsic::mips_sat_u_b:
2124  case Intrinsic::mips_sat_u_h:
2125  case Intrinsic::mips_sat_u_w:
2126  case Intrinsic::mips_sat_u_d: {
2127  // Report an error for out of range values.
2128  int64_t Max;
2129  switch (Intrinsic) {
2130  case Intrinsic::mips_sat_s_b:
2131  case Intrinsic::mips_sat_u_b: Max = 7; break;
2132  case Intrinsic::mips_sat_s_h:
2133  case Intrinsic::mips_sat_u_h: Max = 15; break;
2134  case Intrinsic::mips_sat_s_w:
2135  case Intrinsic::mips_sat_u_w: Max = 31; break;
2136  case Intrinsic::mips_sat_s_d:
2137  case Intrinsic::mips_sat_u_d: Max = 63; break;
2138  default: llvm_unreachable("Unmatched intrinsic");
2139  }
2140  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2141  if (Value < 0 || Value > Max)
2142  report_fatal_error("Immediate out of range");
2143  return SDValue();
2144  }
2145  case Intrinsic::mips_shf_b:
2146  case Intrinsic::mips_shf_h:
2147  case Intrinsic::mips_shf_w: {
2148  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2149  if (Value < 0 || Value > 255)
2150  report_fatal_error("Immediate out of range");
2151  return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2152  Op->getOperand(2), Op->getOperand(1));
2153  }
2154  case Intrinsic::mips_sldi_b:
2155  case Intrinsic::mips_sldi_h:
2156  case Intrinsic::mips_sldi_w:
2157  case Intrinsic::mips_sldi_d: {
2158  // Report an error for out of range values.
2159  int64_t Max;
2160  switch (Intrinsic) {
2161  case Intrinsic::mips_sldi_b: Max = 15; break;
2162  case Intrinsic::mips_sldi_h: Max = 7; break;
2163  case Intrinsic::mips_sldi_w: Max = 3; break;
2164  case Intrinsic::mips_sldi_d: Max = 1; break;
2165  default: llvm_unreachable("Unmatched intrinsic");
2166  }
2167  int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2168  if (Value < 0 || Value > Max)
2169  report_fatal_error("Immediate out of range");
2170  return SDValue();
2171  }
2172  case Intrinsic::mips_sll_b:
2173  case Intrinsic::mips_sll_h:
2174  case Intrinsic::mips_sll_w:
2175  case Intrinsic::mips_sll_d:
2176  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2177  truncateVecElts(Op, DAG));
2178  case Intrinsic::mips_slli_b:
2179  case Intrinsic::mips_slli_h:
2180  case Intrinsic::mips_slli_w:
2181  case Intrinsic::mips_slli_d:
2182  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2183  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2184  case Intrinsic::mips_splat_b:
2185  case Intrinsic::mips_splat_h:
2186  case Intrinsic::mips_splat_w:
2187  case Intrinsic::mips_splat_d:
2188  // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2189  // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2190  // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2191  // Instead we lower to MipsISD::VSHF and match from there.
2192  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2193  lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2194  Op->getOperand(1));
2195  case Intrinsic::mips_splati_b:
2196  case Intrinsic::mips_splati_h:
2197  case Intrinsic::mips_splati_w:
2198  case Intrinsic::mips_splati_d:
2199  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2200  lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2201  Op->getOperand(1));
2202  case Intrinsic::mips_sra_b:
2203  case Intrinsic::mips_sra_h:
2204  case Intrinsic::mips_sra_w:
2205  case Intrinsic::mips_sra_d:
2206  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2207  truncateVecElts(Op, DAG));
2208  case Intrinsic::mips_srai_b:
2209  case Intrinsic::mips_srai_h:
2210  case Intrinsic::mips_srai_w:
2211  case Intrinsic::mips_srai_d:
2212  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2213  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2214  case Intrinsic::mips_srari_b:
2215  case Intrinsic::mips_srari_h:
2216  case Intrinsic::mips_srari_w:
2217  case Intrinsic::mips_srari_d: {
2218  // Report an error for out of range values.
2219  int64_t Max;
2220  switch (Intrinsic) {
2221  case Intrinsic::mips_srari_b: Max = 7; break;
2222  case Intrinsic::mips_srari_h: Max = 15; break;
2223  case Intrinsic::mips_srari_w: Max = 31; break;
2224  case Intrinsic::mips_srari_d: Max = 63; break;
2225  default: llvm_unreachable("Unmatched intrinsic");
2226  }
2227  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2228  if (Value < 0 || Value > Max)
2229  report_fatal_error("Immediate out of range");
2230  return SDValue();
2231  }
2232  case Intrinsic::mips_srl_b:
2233  case Intrinsic::mips_srl_h:
2234  case Intrinsic::mips_srl_w:
2235  case Intrinsic::mips_srl_d:
2236  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2237  truncateVecElts(Op, DAG));
2238  case Intrinsic::mips_srli_b:
2239  case Intrinsic::mips_srli_h:
2240  case Intrinsic::mips_srli_w:
2241  case Intrinsic::mips_srli_d:
2242  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2243  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2244  case Intrinsic::mips_srlri_b:
2245  case Intrinsic::mips_srlri_h:
2246  case Intrinsic::mips_srlri_w:
2247  case Intrinsic::mips_srlri_d: {
2248  // Report an error for out of range values.
2249  int64_t Max;
2250  switch (Intrinsic) {
2251  case Intrinsic::mips_srlri_b: Max = 7; break;
2252  case Intrinsic::mips_srlri_h: Max = 15; break;
2253  case Intrinsic::mips_srlri_w: Max = 31; break;
2254  case Intrinsic::mips_srlri_d: Max = 63; break;
2255  default: llvm_unreachable("Unmatched intrinsic");
2256  }
2257  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2258  if (Value < 0 || Value > Max)
2259  report_fatal_error("Immediate out of range");
2260  return SDValue();
2261  }
2262  case Intrinsic::mips_subv_b:
2263  case Intrinsic::mips_subv_h:
2264  case Intrinsic::mips_subv_w:
2265  case Intrinsic::mips_subv_d:
2266  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2267  Op->getOperand(2));
2268  case Intrinsic::mips_subvi_b:
2269  case Intrinsic::mips_subvi_h:
2270  case Intrinsic::mips_subvi_w:
2271  case Intrinsic::mips_subvi_d:
2272  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2273  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2274  case Intrinsic::mips_vshf_b:
2275  case Intrinsic::mips_vshf_h:
2276  case Intrinsic::mips_vshf_w:
2277  case Intrinsic::mips_vshf_d:
2278  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2279  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2280  case Intrinsic::mips_xor_v:
2281  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2282  Op->getOperand(2));
2283  case Intrinsic::mips_xori_b:
2284  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2285  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2286  case Intrinsic::thread_pointer: {
2287  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2288  return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2289  }
2290  }
2291 }
2292 
2294  const MipsSubtarget &Subtarget) {
2295  SDLoc DL(Op);
2296  SDValue ChainIn = Op->getOperand(0);
2297  SDValue Address = Op->getOperand(2);
2298  SDValue Offset = Op->getOperand(3);
2299  EVT ResTy = Op->getValueType(0);
2300  EVT PtrTy = Address->getValueType(0);
2301 
2302  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2303  // however takes an i32 signed constant offset. The actual type of the
2304  // intrinsic is a scaled signed i10.
2305  if (Subtarget.isABI_N64())
2306  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2307 
2308  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2309  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2310  Align(16));
2311 }
2312 
2313 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2314  SelectionDAG &DAG) const {
2315  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2316  switch (Intr) {
2317  default:
2318  return SDValue();
2319  case Intrinsic::mips_extp:
2320  return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2321  case Intrinsic::mips_extpdp:
2322  return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2323  case Intrinsic::mips_extr_w:
2324  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2325  case Intrinsic::mips_extr_r_w:
2326  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2327  case Intrinsic::mips_extr_rs_w:
2328  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2329  case Intrinsic::mips_extr_s_h:
2330  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2331  case Intrinsic::mips_mthlip:
2332  return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2333  case Intrinsic::mips_mulsaq_s_w_ph:
2334  return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2335  case Intrinsic::mips_maq_s_w_phl:
2336  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2337  case Intrinsic::mips_maq_s_w_phr:
2338  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2339  case Intrinsic::mips_maq_sa_w_phl:
2340  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2341  case Intrinsic::mips_maq_sa_w_phr:
2342  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2343  case Intrinsic::mips_dpaq_s_w_ph:
2344  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2345  case Intrinsic::mips_dpsq_s_w_ph:
2346  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2347  case Intrinsic::mips_dpaq_sa_l_w:
2348  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2349  case Intrinsic::mips_dpsq_sa_l_w:
2350  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2351  case Intrinsic::mips_dpaqx_s_w_ph:
2352  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2353  case Intrinsic::mips_dpaqx_sa_w_ph:
2354  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2355  case Intrinsic::mips_dpsqx_s_w_ph:
2356  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2357  case Intrinsic::mips_dpsqx_sa_w_ph:
2358  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2359  case Intrinsic::mips_ld_b:
2360  case Intrinsic::mips_ld_h:
2361  case Intrinsic::mips_ld_w:
2362  case Intrinsic::mips_ld_d:
2363  return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2364  }
2365 }
2366 
2368  const MipsSubtarget &Subtarget) {
2369  SDLoc DL(Op);
2370  SDValue ChainIn = Op->getOperand(0);
2371  SDValue Value = Op->getOperand(2);
2372  SDValue Address = Op->getOperand(3);
2373  SDValue Offset = Op->getOperand(4);
2374  EVT PtrTy = Address->getValueType(0);
2375 
2376  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2377  // however takes an i32 signed constant offset. The actual type of the
2378  // intrinsic is a scaled signed i10.
2379  if (Subtarget.isABI_N64())
2380  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2381 
2382  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2383 
2384  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2385  Align(16));
2386 }
2387 
2388 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2389  SelectionDAG &DAG) const {
2390  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2391  switch (Intr) {
2392  default:
2393  return SDValue();
2394  case Intrinsic::mips_st_b:
2395  case Intrinsic::mips_st_h:
2396  case Intrinsic::mips_st_w:
2397  case Intrinsic::mips_st_d:
2398  return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2399  }
2400 }
2401 
2402 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2403 //
2404 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2405 // choose to sign-extend but we could have equally chosen zero-extend. The
2406 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2407 // result into this node later (possibly changing it to a zero-extend in the
2408 // process).
2409 SDValue MipsSETargetLowering::
2410 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2411  SDLoc DL(Op);
2412  EVT ResTy = Op->getValueType(0);
2413  SDValue Op0 = Op->getOperand(0);
2414  EVT VecTy = Op0->getValueType(0);
2415 
2416  if (!VecTy.is128BitVector())
2417  return SDValue();
2418 
2419  if (ResTy.isInteger()) {
2420  SDValue Op1 = Op->getOperand(1);
2421  EVT EltTy = VecTy.getVectorElementType();
2422  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2423  DAG.getValueType(EltTy));
2424  }
2425 
2426  return Op;
2427 }
2428 
2429 static bool isConstantOrUndef(const SDValue Op) {
2430  if (Op->isUndef())
2431  return true;
2432  if (isa<ConstantSDNode>(Op))
2433  return true;
2434  if (isa<ConstantFPSDNode>(Op))
2435  return true;
2436  return false;
2437 }
2438 
2440  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2441  if (isConstantOrUndef(Op->getOperand(i)))
2442  return true;
2443  return false;
2444 }
2445 
2446 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2447 // backend.
2448 //
2449 // Lowers according to the following rules:
2450 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2451 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2452 // immediate
2453 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2454 // is a power of 2 less than or equal to 64 and the value does not fit into a
2455 // signed 10-bit immediate
2456 // - Non-constant splats are legal as-is.
2457 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2458 // - All others are illegal and must be expanded.
2459 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2460  SelectionDAG &DAG) const {
2461  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2462  EVT ResTy = Op->getValueType(0);
2463  SDLoc DL(Op);
2464  APInt SplatValue, SplatUndef;
2465  unsigned SplatBitSize;
2466  bool HasAnyUndefs;
2467 
2468  if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2469  return SDValue();
2470 
2471  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2472  HasAnyUndefs, 8,
2473  !Subtarget.isLittle()) && SplatBitSize <= 64) {
2474  // We can only cope with 8, 16, 32, or 64-bit elements
2475  if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2476  SplatBitSize != 64)
2477  return SDValue();
2478 
2479  // If the value isn't an integer type we will have to bitcast
2480  // from an integer type first. Also, if there are any undefs, we must
2481  // lower them to defined values first.
2482  if (ResTy.isInteger() && !HasAnyUndefs)
2483  return Op;
2484 
2485  EVT ViaVecTy;
2486 
2487  switch (SplatBitSize) {
2488  default:
2489  return SDValue();
2490  case 8:
2491  ViaVecTy = MVT::v16i8;
2492  break;
2493  case 16:
2494  ViaVecTy = MVT::v8i16;
2495  break;
2496  case 32:
2497  ViaVecTy = MVT::v4i32;
2498  break;
2499  case 64:
2500  // There's no fill.d to fall back on for 64-bit values
2501  return SDValue();
2502  }
2503 
2504  // SelectionDAG::getConstant will promote SplatValue appropriately.
2505  SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2506 
2507  // Bitcast to the type we originally wanted
2508  if (ViaVecTy != ResTy)
2509  Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2510 
2511  return Result;
2512  } else if (DAG.isSplatValue(Op, /* AllowUndefs */ false))
2513  return Op;
2514  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2515  // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2516  // The resulting code is the same length as the expansion, but it doesn't
2517  // use memory operations
2518  EVT ResTy = Node->getValueType(0);
2519 
2520  assert(ResTy.isVector());
2521 
2522  unsigned NumElts = ResTy.getVectorNumElements();
2523  SDValue Vector = DAG.getUNDEF(ResTy);
2524  for (unsigned i = 0; i < NumElts; ++i) {
2525  Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2526  Node->getOperand(i),
2527  DAG.getConstant(i, DL, MVT::i32));
2528  }
2529  return Vector;
2530  }
2531 
2532  return SDValue();
2533 }
2534 
2535 // Lower VECTOR_SHUFFLE into SHF (if possible).
2536 //
2537 // SHF splits the vector into blocks of four elements, then shuffles these
2538 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2539 //
2540 // It is therefore possible to lower into SHF when the mask takes the form:
2541 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2542 // When undef's appear they are treated as if they were whatever value is
2543 // necessary in order to fit the above forms.
2544 //
2545 // For example:
2546 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2547 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2548 // i32 7, i32 6, i32 5, i32 4>
2549 // is lowered to:
2550 // (SHF_H $w0, $w1, 27)
2551 // where the 27 comes from:
2552 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2554  SmallVector<int, 16> Indices,
2555  SelectionDAG &DAG) {
2556  int SHFIndices[4] = { -1, -1, -1, -1 };
2557 
2558  if (Indices.size() < 4)
2559  return SDValue();
2560 
2561  for (unsigned i = 0; i < 4; ++i) {
2562  for (unsigned j = i; j < Indices.size(); j += 4) {
2563  int Idx = Indices[j];
2564 
2565  // Convert from vector index to 4-element subvector index
2566  // If an index refers to an element outside of the subvector then give up
2567  if (Idx != -1) {
2568  Idx -= 4 * (j / 4);
2569  if (Idx < 0 || Idx >= 4)
2570  return SDValue();
2571  }
2572 
2573  // If the mask has an undef, replace it with the current index.
2574  // Note that it might still be undef if the current index is also undef
2575  if (SHFIndices[i] == -1)
2576  SHFIndices[i] = Idx;
2577 
2578  // Check that non-undef values are the same as in the mask. If they
2579  // aren't then give up
2580  if (!(Idx == -1 || Idx == SHFIndices[i]))
2581  return SDValue();
2582  }
2583  }
2584 
2585  // Calculate the immediate. Replace any remaining undefs with zero
2586  APInt Imm(32, 0);
2587  for (int i = 3; i >= 0; --i) {
2588  int Idx = SHFIndices[i];
2589 
2590  if (Idx == -1)
2591  Idx = 0;
2592 
2593  Imm <<= 2;
2594  Imm |= Idx & 0x3;
2595  }
2596 
2597  SDLoc DL(Op);
2598  return DAG.getNode(MipsISD::SHF, DL, ResTy,
2599  DAG.getTargetConstant(Imm, DL, MVT::i32),
2600  Op->getOperand(0));
2601 }
2602 
2603 /// Determine whether a range fits a regular pattern of values.
2604 /// This function accounts for the possibility of jumping over the End iterator.
2605 template <typename ValType>
2606 static bool
2608  unsigned CheckStride,
2610  ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2611  auto &I = Begin;
2612 
2613  while (I != End) {
2614  if (*I != -1 && *I != ExpectedIndex)
2615  return false;
2616  ExpectedIndex += ExpectedIndexStride;
2617 
2618  // Incrementing past End is undefined behaviour so we must increment one
2619  // step at a time and check for End at each step.
2620  for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2621  ; // Empty loop body.
2622  }
2623  return true;
2624 }
2625 
2626 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2627 //
2628 // It is a SPLATI when the mask is:
2629 // <x, x, x, ...>
2630 // where x is any valid index.
2631 //
2632 // When undef's appear in the mask they are treated as if they were whatever
2633 // value is necessary in order to fit the above form.
2635  SmallVector<int, 16> Indices,
2636  SelectionDAG &DAG) {
2637  assert((Indices.size() % 2) == 0);
2638 
2639  int SplatIndex = -1;
2640  for (const auto &V : Indices) {
2641  if (V != -1) {
2642  SplatIndex = V;
2643  break;
2644  }
2645  }
2646 
2647  return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2648  0);
2649 }
2650 
2651 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2652 //
2653 // ILVEV interleaves the even elements from each vector.
2654 //
2655 // It is possible to lower into ILVEV when the mask consists of two of the
2656 // following forms interleaved:
2657 // <0, 2, 4, ...>
2658 // <n, n+2, n+4, ...>
2659 // where n is the number of elements in the vector.
2660 // For example:
2661 // <0, 0, 2, 2, 4, 4, ...>
2662 // <0, n, 2, n+2, 4, n+4, ...>
2663 //
2664 // When undef's appear in the mask they are treated as if they were whatever
2665 // value is necessary in order to fit the above forms.
2667  SmallVector<int, 16> Indices,
2668  SelectionDAG &DAG) {
2669  assert((Indices.size() % 2) == 0);
2670 
2671  SDValue Wt;
2672  SDValue Ws;
2673  const auto &Begin = Indices.begin();
2674  const auto &End = Indices.end();
2675 
2676  // Check even elements are taken from the even elements of one half or the
2677  // other and pick an operand accordingly.
2678  if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2679  Wt = Op->getOperand(0);
2680  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2681  Wt = Op->getOperand(1);
2682  else
2683  return SDValue();
2684 
2685  // Check odd elements are taken from the even elements of one half or the
2686  // other and pick an operand accordingly.
2687  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2688  Ws = Op->getOperand(0);
2689  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2690  Ws = Op->getOperand(1);
2691  else
2692  return SDValue();
2693 
2694  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2695 }
2696 
2697 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2698 //
2699 // ILVOD interleaves the odd elements from each vector.
2700 //
2701 // It is possible to lower into ILVOD when the mask consists of two of the
2702 // following forms interleaved:
2703 // <1, 3, 5, ...>
2704 // <n+1, n+3, n+5, ...>
2705 // where n is the number of elements in the vector.
2706 // For example:
2707 // <1, 1, 3, 3, 5, 5, ...>
2708 // <1, n+1, 3, n+3, 5, n+5, ...>
2709 //
2710 // When undef's appear in the mask they are treated as if they were whatever
2711 // value is necessary in order to fit the above forms.
2713  SmallVector<int, 16> Indices,
2714  SelectionDAG &DAG) {
2715  assert((Indices.size() % 2) == 0);
2716 
2717  SDValue Wt;
2718  SDValue Ws;
2719  const auto &Begin = Indices.begin();
2720  const auto &End = Indices.end();
2721 
2722  // Check even elements are taken from the odd elements of one half or the
2723  // other and pick an operand accordingly.
2724  if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2725  Wt = Op->getOperand(0);
2726  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2727  Wt = Op->getOperand(1);
2728  else
2729  return SDValue();
2730 
2731  // Check odd elements are taken from the odd elements of one half or the
2732  // other and pick an operand accordingly.
2733  if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2734  Ws = Op->getOperand(0);
2735  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2736  Ws = Op->getOperand(1);
2737  else
2738  return SDValue();
2739 
2740  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2741 }
2742 
2743 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2744 //
2745 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2746 // each vector.
2747 //
2748 // It is possible to lower into ILVR when the mask consists of two of the
2749 // following forms interleaved:
2750 // <0, 1, 2, ...>
2751 // <n, n+1, n+2, ...>
2752 // where n is the number of elements in the vector.
2753 // For example:
2754 // <0, 0, 1, 1, 2, 2, ...>
2755 // <0, n, 1, n+1, 2, n+2, ...>
2756 //
2757 // When undef's appear in the mask they are treated as if they were whatever
2758 // value is necessary in order to fit the above forms.
2760  SmallVector<int, 16> Indices,
2761  SelectionDAG &DAG) {
2762  assert((Indices.size() % 2) == 0);
2763 
2764  SDValue Wt;
2765  SDValue Ws;
2766  const auto &Begin = Indices.begin();
2767  const auto &End = Indices.end();
2768 
2769  // Check even elements are taken from the right (lowest-indexed) elements of
2770  // one half or the other and pick an operand accordingly.
2771  if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2772  Wt = Op->getOperand(0);
2773  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2774  Wt = Op->getOperand(1);
2775  else
2776  return SDValue();
2777 
2778  // Check odd elements are taken from the right (lowest-indexed) elements of
2779  // one half or the other and pick an operand accordingly.
2780  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2781  Ws = Op->getOperand(0);
2782  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2783  Ws = Op->getOperand(1);
2784  else
2785  return SDValue();
2786 
2787  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2788 }
2789 
2790 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2791 //
2792 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2793 // of each vector.
2794 //
2795 // It is possible to lower into ILVL when the mask consists of two of the
2796 // following forms interleaved:
2797 // <x, x+1, x+2, ...>
2798 // <n+x, n+x+1, n+x+2, ...>
2799 // where n is the number of elements in the vector and x is half n.
2800 // For example:
2801 // <x, x, x+1, x+1, x+2, x+2, ...>
2802 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2803 //
2804 // When undef's appear in the mask they are treated as if they were whatever
2805 // value is necessary in order to fit the above forms.
2807  SmallVector<int, 16> Indices,
2808  SelectionDAG &DAG) {
2809  assert((Indices.size() % 2) == 0);
2810 
2811  unsigned HalfSize = Indices.size() / 2;
2812  SDValue Wt;
2813  SDValue Ws;
2814  const auto &Begin = Indices.begin();
2815  const auto &End = Indices.end();
2816 
2817  // Check even elements are taken from the left (highest-indexed) elements of
2818  // one half or the other and pick an operand accordingly.
2819  if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2820  Wt = Op->getOperand(0);
2821  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2822  Wt = Op->getOperand(1);
2823  else
2824  return SDValue();
2825 
2826  // Check odd elements are taken from the left (highest-indexed) elements of
2827  // one half or the other and pick an operand accordingly.
2828  if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2829  Ws = Op->getOperand(0);
2830  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2831  1))
2832  Ws = Op->getOperand(1);
2833  else
2834  return SDValue();
2835 
2836  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2837 }
2838 
2839 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2840 //
2841 // PCKEV copies the even elements of each vector into the result vector.
2842 //
2843 // It is possible to lower into PCKEV when the mask consists of two of the
2844 // following forms concatenated:
2845 // <0, 2, 4, ...>
2846 // <n, n+2, n+4, ...>
2847 // where n is the number of elements in the vector.
2848 // For example:
2849 // <0, 2, 4, ..., 0, 2, 4, ...>
2850 // <0, 2, 4, ..., n, n+2, n+4, ...>
2851 //
2852 // When undef's appear in the mask they are treated as if they were whatever
2853 // value is necessary in order to fit the above forms.
2855  SmallVector<int, 16> Indices,
2856  SelectionDAG &DAG) {
2857  assert((Indices.size() % 2) == 0);
2858 
2859  SDValue Wt;
2860  SDValue Ws;
2861  const auto &Begin = Indices.begin();
2862  const auto &Mid = Indices.begin() + Indices.size() / 2;
2863  const auto &End = Indices.end();
2864 
2865  if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2866  Wt = Op->getOperand(0);
2867  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2868  Wt = Op->getOperand(1);
2869  else
2870  return SDValue();
2871 
2872  if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2873  Ws = Op->getOperand(0);
2874  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2875  Ws = Op->getOperand(1);
2876  else
2877  return SDValue();
2878 
2879  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2880 }
2881 
2882 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2883 //
2884 // PCKOD copies the odd elements of each vector into the result vector.
2885 //
2886 // It is possible to lower into PCKOD when the mask consists of two of the
2887 // following forms concatenated:
2888 // <1, 3, 5, ...>
2889 // <n+1, n+3, n+5, ...>
2890 // where n is the number of elements in the vector.
2891 // For example:
2892 // <1, 3, 5, ..., 1, 3, 5, ...>
2893 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2894 //
2895 // When undef's appear in the mask they are treated as if they were whatever
2896 // value is necessary in order to fit the above forms.
2898  SmallVector<int, 16> Indices,
2899  SelectionDAG &DAG) {
2900  assert((Indices.size() % 2) == 0);
2901 
2902  SDValue Wt;
2903  SDValue Ws;
2904  const auto &Begin = Indices.begin();
2905  const auto &Mid = Indices.begin() + Indices.size() / 2;
2906  const auto &End = Indices.end();
2907 
2908  if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2909  Wt = Op->getOperand(0);
2910  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2911  Wt = Op->getOperand(1);
2912  else
2913  return SDValue();
2914 
2915  if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2916  Ws = Op->getOperand(0);
2917  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2918  Ws = Op->getOperand(1);
2919  else
2920  return SDValue();
2921 
2922  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2923 }
2924 
2925 // Lower VECTOR_SHUFFLE into VSHF.
2926 //
2927 // This mostly consists of converting the shuffle indices in Indices into a
2928 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2929 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2930 // if the type is v8i16 and all the indices are less than 8 then the second
2931 // operand is unused and can be replaced with anything. We choose to replace it
2932 // with the used operand since this reduces the number of instructions overall.
2934  SmallVector<int, 16> Indices,
2935  SelectionDAG &DAG) {
2937  SDValue Op0;
2938  SDValue Op1;
2939  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2940  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2941  bool Using1stVec = false;
2942  bool Using2ndVec = false;
2943  SDLoc DL(Op);
2944  int ResTyNumElts = ResTy.getVectorNumElements();
2945 
2946  for (int i = 0; i < ResTyNumElts; ++i) {
2947  // Idx == -1 means UNDEF
2948  int Idx = Indices[i];
2949 
2950  if (0 <= Idx && Idx < ResTyNumElts)
2951  Using1stVec = true;
2952  if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2953  Using2ndVec = true;
2954  }
2955 
2956  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2957  ++I)
2958  Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2959 
2960  SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
2961 
2962  if (Using1stVec && Using2ndVec) {
2963  Op0 = Op->getOperand(0);
2964  Op1 = Op->getOperand(1);
2965  } else if (Using1stVec)
2966  Op0 = Op1 = Op->getOperand(0);
2967  else if (Using2ndVec)
2968  Op0 = Op1 = Op->getOperand(1);
2969  else
2970  llvm_unreachable("shuffle vector mask references neither vector operand?");
2971 
2972  // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2973  // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2974  // VSHF concatenates the vectors in a bitwise fashion:
2975  // <0b00, 0b01> + <0b10, 0b11> ->
2976  // 0b0100 + 0b1110 -> 0b01001110
2977  // <0b10, 0b11, 0b00, 0b01>
2978  // We must therefore swap the operands to get the correct result.
2979  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2980 }
2981 
2982 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2983 // indices in the shuffle.
2984 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2985  SelectionDAG &DAG) const {
2986  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2987  EVT ResTy = Op->getValueType(0);
2988 
2989  if (!ResTy.is128BitVector())
2990  return SDValue();
2991 
2992  int ResTyNumElts = ResTy.getVectorNumElements();
2993  SmallVector<int, 16> Indices;
2994 
2995  for (int i = 0; i < ResTyNumElts; ++i)
2996  Indices.push_back(Node->getMaskElt(i));
2997 
2998  // splati.[bhwd] is preferable to the others but is matched from
2999  // MipsISD::VSHF.
3000  if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
3001  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3002  SDValue Result;
3003  if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
3004  return Result;
3005  if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
3006  return Result;
3007  if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
3008  return Result;
3009  if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
3010  return Result;
3011  if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
3012  return Result;
3013  if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
3014  return Result;
3015  if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
3016  return Result;
3017  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3018 }
3019 
3021 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
3022  MachineBasicBlock *BB) const {
3023  // $bb:
3024  // bposge32_pseudo $vr0
3025  // =>
3026  // $bb:
3027  // bposge32 $tbb
3028  // $fbb:
3029  // li $vr2, 0
3030  // b $sink
3031  // $tbb:
3032  // li $vr1, 1
3033  // $sink:
3034  // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
3035 
3036  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3038  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3039  DebugLoc DL = MI.getDebugLoc();
3040  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3042  MachineFunction *F = BB->getParent();
3043  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3044  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3045  MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3046  F->insert(It, FBB);
3047  F->insert(It, TBB);
3048  F->insert(It, Sink);
3049 
3050  // Transfer the remainder of BB and its successor edges to Sink.
3051  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3052  BB->end());
3053  Sink->transferSuccessorsAndUpdatePHIs(BB);
3054 
3055  // Add successors.
3056  BB->addSuccessor(FBB);
3057  BB->addSuccessor(TBB);
3058  FBB->addSuccessor(Sink);
3059  TBB->addSuccessor(Sink);
3060 
3061  // Insert the real bposge32 instruction to $BB.
3062  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3063  // Insert the real bposge32c instruction to $BB.
3064  BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3065 
3066  // Fill $FBB.
3067  Register VR2 = RegInfo.createVirtualRegister(RC);
3068  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3069  .addReg(Mips::ZERO).addImm(0);
3070  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3071 
3072  // Fill $TBB.
3073  Register VR1 = RegInfo.createVirtualRegister(RC);
3074  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3075  .addReg(Mips::ZERO).addImm(1);
3076 
3077  // Insert phi function to $Sink.
3078  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3079  MI.getOperand(0).getReg())
3080  .addReg(VR2)
3081  .addMBB(FBB)
3082  .addReg(VR1)
3083  .addMBB(TBB);
3084 
3085  MI.eraseFromParent(); // The pseudo instruction is gone now.
3086  return Sink;
3087 }
3088 
3089 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3090  MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
3091  // $bb:
3092  // vany_nonzero $rd, $ws
3093  // =>
3094  // $bb:
3095  // bnz.b $ws, $tbb
3096  // b $fbb
3097  // $fbb:
3098  // li $rd1, 0
3099  // b $sink
3100  // $tbb:
3101  // li $rd2, 1
3102  // $sink:
3103  // $rd = phi($rd1, $fbb, $rd2, $tbb)
3104 
3105  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3107  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3108  DebugLoc DL = MI.getDebugLoc();
3109  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3111  MachineFunction *F = BB->getParent();
3112  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3113  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3114  MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3115  F->insert(It, FBB);
3116  F->insert(It, TBB);
3117  F->insert(It, Sink);
3118 
3119  // Transfer the remainder of BB and its successor edges to Sink.
3120  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3121  BB->end());
3122  Sink->transferSuccessorsAndUpdatePHIs(BB);
3123 
3124  // Add successors.
3125  BB->addSuccessor(FBB);
3126  BB->addSuccessor(TBB);
3127  FBB->addSuccessor(Sink);
3128  TBB->addSuccessor(Sink);
3129 
3130  // Insert the real bnz.b instruction to $BB.
3131  BuildMI(BB, DL, TII->get(BranchOp))
3132  .addReg(MI.getOperand(1).getReg())
3133  .addMBB(TBB);
3134 
3135  // Fill $FBB.
3136  Register RD1 = RegInfo.createVirtualRegister(RC);
3137  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3138  .addReg(Mips::ZERO).addImm(0);
3139  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3140 
3141  // Fill $TBB.
3142  Register RD2 = RegInfo.createVirtualRegister(RC);
3143  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3144  .addReg(Mips::ZERO).addImm(1);
3145 
3146  // Insert phi function to $Sink.
3147  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3148  MI.getOperand(0).getReg())
3149  .addReg(RD1)
3150  .addMBB(FBB)
3151  .addReg(RD2)
3152  .addMBB(TBB);
3153 
3154  MI.eraseFromParent(); // The pseudo instruction is gone now.
3155  return Sink;
3156 }
3157 
3158 // Emit the COPY_FW pseudo instruction.
3159 //
3160 // copy_fw_pseudo $fd, $ws, n
3161 // =>
3162 // copy_u_w $rt, $ws, $n
3163 // mtc1 $rt, $fd
3164 //
3165 // When n is zero, the equivalent operation can be performed with (potentially)
3166 // zero instructions due to register overlaps. This optimization is never valid
3167 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3169 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3170  MachineBasicBlock *BB) const {
3172  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3173  DebugLoc DL = MI.getDebugLoc();
3174  Register Fd = MI.getOperand(0).getReg();
3175  Register Ws = MI.getOperand(1).getReg();
3176  unsigned Lane = MI.getOperand(2).getImm();
3177 
3178  if (Lane == 0) {
3179  unsigned Wt = Ws;
3180  if (!Subtarget.useOddSPReg()) {
3181  // We must copy to an even-numbered MSA register so that the
3182  // single-precision sub-register is also guaranteed to be even-numbered.
3183  Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3184 
3185  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3186  }
3187 
3188  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3189  } else {
3190  Register Wt = RegInfo.createVirtualRegister(
3191  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3192  : &Mips::MSA128WEvensRegClass);
3193 
3194  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3195  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3196  }
3197 
3198  MI.eraseFromParent(); // The pseudo instruction is gone now.
3199  return BB;
3200 }
3201 
3202 // Emit the COPY_FD pseudo instruction.
3203 //
3204 // copy_fd_pseudo $fd, $ws, n
3205 // =>
3206 // splati.d $wt, $ws, $n
3207 // copy $fd, $wt:sub_64
3208 //
3209 // When n is zero, the equivalent operation can be performed with (potentially)
3210 // zero instructions due to register overlaps. This optimization is always
3211 // valid because FR=1 mode which is the only supported mode in MSA.
3213 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3214  MachineBasicBlock *BB) const {
3216 
3218  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3219  Register Fd = MI.getOperand(0).getReg();
3220  Register Ws = MI.getOperand(1).getReg();
3221  unsigned Lane = MI.getOperand(2).getImm() * 2;
3222  DebugLoc DL = MI.getDebugLoc();
3223 
3224  if (Lane == 0)
3225  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3226  else {
3227  Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3228 
3229  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3230  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3231  }
3232 
3233  MI.eraseFromParent(); // The pseudo instruction is gone now.
3234  return BB;
3235 }
3236 
3237 // Emit the INSERT_FW pseudo instruction.
3238 //
3239 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3240 // =>
3241 // subreg_to_reg $wt:sub_lo, $fs
3242 // insve_w $wd[$n], $wd_in, $wt[0]
3244 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3245  MachineBasicBlock *BB) const {
3247  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3248  DebugLoc DL = MI.getDebugLoc();
3249  Register Wd = MI.getOperand(0).getReg();
3250  Register Wd_in = MI.getOperand(1).getReg();
3251  unsigned Lane = MI.getOperand(2).getImm();
3252  Register Fs = MI.getOperand(3).getReg();
3253  Register Wt = RegInfo.createVirtualRegister(
3254  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3255  : &Mips::MSA128WEvensRegClass);
3256 
3257  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3258  .addImm(0)
3259  .addReg(Fs)
3260  .addImm(Mips::sub_lo);
3261  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3262  .addReg(Wd_in)
3263  .addImm(Lane)
3264  .addReg(Wt)
3265  .addImm(0);
3266 
3267  MI.eraseFromParent(); // The pseudo instruction is gone now.
3268  return BB;
3269 }
3270 
3271 // Emit the INSERT_FD pseudo instruction.
3272 //
3273 // insert_fd_pseudo $wd, $fs, n
3274 // =>
3275 // subreg_to_reg $wt:sub_64, $fs
3276 // insve_d $wd[$n], $wd_in, $wt[0]
3278 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3279  MachineBasicBlock *BB) const {
3281 
3283  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3284  DebugLoc DL = MI.getDebugLoc();
3285  Register Wd = MI.getOperand(0).getReg();
3286  Register Wd_in = MI.getOperand(1).getReg();
3287  unsigned Lane = MI.getOperand(2).getImm();
3288  Register Fs = MI.getOperand(3).getReg();
3289  Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3290 
3291  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3292  .addImm(0)
3293  .addReg(Fs)
3294  .addImm(Mips::sub_64);
3295  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3296  .addReg(Wd_in)
3297  .addImm(Lane)
3298  .addReg(Wt)
3299  .addImm(0);
3300 
3301  MI.eraseFromParent(); // The pseudo instruction is gone now.
3302  return BB;
3303 }
3304 
3305 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3306 //
3307 // For integer:
3308 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3309 // =>
3310 // (SLL $lanetmp1, $lane, <log2size)
3311 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3312 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3313 // (NEG $lanetmp2, $lanetmp1)
3314 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3315 //
3316 // For floating point:
3317 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3318 // =>
3319 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3320 // (SLL $lanetmp1, $lane, <log2size)
3321 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3322 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3323 // (NEG $lanetmp2, $lanetmp1)
3324 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3325 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3326  MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3327  bool IsFP) const {
3329  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3330  DebugLoc DL = MI.getDebugLoc();
3331  Register Wd = MI.getOperand(0).getReg();
3332  Register SrcVecReg = MI.getOperand(1).getReg();
3333  Register LaneReg = MI.getOperand(2).getReg();
3334  Register SrcValReg = MI.getOperand(3).getReg();
3335 
3336  const TargetRegisterClass *VecRC = nullptr;
3337  // FIXME: This should be true for N32 too.
3338  const TargetRegisterClass *GPRRC =
3339  Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3340  unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3341  unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3342  unsigned EltLog2Size;
3343  unsigned InsertOp = 0;
3344  unsigned InsveOp = 0;
3345  switch (EltSizeInBytes) {
3346  default:
3347  llvm_unreachable("Unexpected size");
3348  case 1:
3349  EltLog2Size = 0;
3350  InsertOp = Mips::INSERT_B;
3351  InsveOp = Mips::INSVE_B;
3352  VecRC = &Mips::MSA128BRegClass;
3353  break;
3354  case 2:
3355  EltLog2Size = 1;
3356  InsertOp = Mips::INSERT_H;
3357  InsveOp = Mips::INSVE_H;
3358  VecRC = &Mips::MSA128HRegClass;
3359  break;
3360  case 4:
3361  EltLog2Size = 2;
3362  InsertOp = Mips::INSERT_W;
3363  InsveOp = Mips::INSVE_W;
3364  VecRC = &Mips::MSA128WRegClass;
3365  break;
3366  case 8:
3367  EltLog2Size = 3;
3368  InsertOp = Mips::INSERT_D;
3369  InsveOp = Mips::INSVE_D;
3370  VecRC = &Mips::MSA128DRegClass;
3371  break;
3372  }
3373 
3374  if (IsFP) {
3375  Register Wt = RegInfo.createVirtualRegister(VecRC);
3376  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3377  .addImm(0)
3378  .addReg(SrcValReg)
3379  .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3380  SrcValReg = Wt;
3381  }
3382 
3383  // Convert the lane index into a byte index
3384  if (EltSizeInBytes != 1) {
3385  Register LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3386  BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3387  .addReg(LaneReg)
3388  .addImm(EltLog2Size);
3389  LaneReg = LaneTmp1;
3390  }
3391 
3392  // Rotate bytes around so that the desired lane is element zero
3393  Register WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3394  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3395  .addReg(SrcVecReg)
3396  .addReg(SrcVecReg)
3397  .addReg(LaneReg, 0, SubRegIdx);
3398 
3399  Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3400  if (IsFP) {
3401  // Use insve.df to insert to element zero
3402  BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3403  .addReg(WdTmp1)
3404  .addImm(0)
3405  .addReg(SrcValReg)
3406  .addImm(0);
3407  } else {
3408  // Use insert.df to insert to element zero
3409  BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3410  .addReg(WdTmp1)
3411  .addReg(SrcValReg)
3412  .addImm(0);
3413  }
3414 
3415  // Rotate elements the rest of the way for a full rotation.
3416  // sld.df inteprets $rt modulo the number of columns so we only need to negate
3417  // the lane index to do this.
3418  Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3419  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3420  LaneTmp2)
3421  .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3422  .addReg(LaneReg);
3423  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3424  .addReg(WdTmp2)
3425  .addReg(WdTmp2)
3426  .addReg(LaneTmp2, 0, SubRegIdx);
3427 
3428  MI.eraseFromParent(); // The pseudo instruction is gone now.
3429  return BB;
3430 }
3431 
3432 // Emit the FILL_FW pseudo instruction.
3433 //
3434 // fill_fw_pseudo $wd, $fs
3435 // =>
3436 // implicit_def $wt1
3437 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3438 // splati.w $wd, $wt2[0]
3440 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3441  MachineBasicBlock *BB) const {
3443  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3444  DebugLoc DL = MI.getDebugLoc();
3445  Register Wd = MI.getOperand(0).getReg();
3446  Register Fs = MI.getOperand(1).getReg();
3447  Register Wt1 = RegInfo.createVirtualRegister(
3448  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3449  : &Mips::MSA128WEvensRegClass);
3450  Register Wt2 = RegInfo.createVirtualRegister(
3451  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3452  : &Mips::MSA128WEvensRegClass);
3453 
3454  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3455  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3456  .addReg(Wt1)
3457  .addReg(Fs)
3458  .addImm(Mips::sub_lo);
3459  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3460 
3461  MI.eraseFromParent(); // The pseudo instruction is gone now.
3462  return BB;
3463 }
3464 
3465 // Emit the FILL_FD pseudo instruction.
3466 //
3467 // fill_fd_pseudo $wd, $fs
3468 // =>
3469 // implicit_def $wt1
3470 // insert_subreg $wt2:subreg_64, $wt1, $fs
3471 // splati.d $wd, $wt2[0]
3473 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3474  MachineBasicBlock *BB) const {
3476 
3478  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3479  DebugLoc DL = MI.getDebugLoc();
3480  Register Wd = MI.getOperand(0).getReg();
3481  Register Fs = MI.getOperand(1).getReg();
3482  Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3483  Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3484 
3485  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3486  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3487  .addReg(Wt1)
3488  .addReg(Fs)
3489  .addImm(Mips::sub_64);
3490  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3491 
3492  MI.eraseFromParent(); // The pseudo instruction is gone now.
3493  return BB;
3494 }
3495 
3496 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3497 // register.
3498 //
3499 // STF16 MSA128F16:$wd, mem_simm10:$addr
3500 // =>
3501 // copy_u.h $rtemp,$wd[0]
3502 // sh $rtemp, $addr
3503 //
3504 // Safety: We can't use st.h & co as they would over write the memory after
3505 // the destination. It would require half floats be allocated 16 bytes(!) of
3506 // space.
3508 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3509  MachineBasicBlock *BB) const {
3510 
3512  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3513  DebugLoc DL = MI.getDebugLoc();
3514  Register Ws = MI.getOperand(0).getReg();
3515  Register Rt = MI.getOperand(1).getReg();
3516  const MachineMemOperand &MMO = **MI.memoperands_begin();
3517  unsigned Imm = MMO.getOffset();
3518 
3519  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3520  // spill and reload can expand as a GPR64 operand. Examine the
3521  // operand in detail and default to ABI.
3522  const TargetRegisterClass *RC =
3523  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3524  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3525  : &Mips::GPR64RegClass);
3526  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3527  Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3528 
3529  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3530  if(!UsingMips32) {
3531  Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3532  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3533  .addImm(0)
3534  .addReg(Rs)
3535  .addImm(Mips::sub_32);
3536  Rs = Tmp;
3537  }
3538  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3539  .addReg(Rs)
3540  .addReg(Rt)
3541  .addImm(Imm)
3542  .addMemOperand(BB->getParent()->getMachineMemOperand(
3543  &MMO, MMO.getOffset(), MMO.getSize()));
3544 
3545  MI.eraseFromParent();
3546  return BB;
3547 }
3548 
3549 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3550 //
3551 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3552 // =>
3553 // lh $rtemp, $addr
3554 // fill.h $wd, $rtemp
3555 //
3556 // Safety: We can't use ld.h & co as they over-read from the source.
3557 // Additionally, if the address is not modulo 16, 2 cases can occur:
3558 // a) Segmentation fault as the load instruction reads from a memory page
3559 // memory it's not supposed to.
3560 // b) The load crosses an implementation specific boundary, requiring OS
3561 // intervention.
3563 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3564  MachineBasicBlock *BB) const {
3565 
3567  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3568  DebugLoc DL = MI.getDebugLoc();
3569  Register Wd = MI.getOperand(0).getReg();
3570 
3571  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3572  // spill and reload can expand as a GPR64 operand. Examine the
3573  // operand in detail and default to ABI.
3574  const TargetRegisterClass *RC =
3575  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3576  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3577  : &Mips::GPR64RegClass);
3578 
3579  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3580  Register Rt = RegInfo.createVirtualRegister(RC);
3581 
3582  MachineInstrBuilder MIB =
3583  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3584  for (unsigned i = 1; i < MI.getNumOperands(); i++)
3585  MIB.add(MI.getOperand(i));
3586 
3587  if(!UsingMips32) {
3588  Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3589  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3590  Rt = Tmp;
3591  }
3592 
3593  BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3594 
3595  MI.eraseFromParent();
3596  return BB;
3597 }
3598 
3599 // Emit the FPROUND_PSEUDO instruction.
3600 //
3601 // Round an FGR64Opnd, FGR32Opnd to an f16.
3602 //
3603 // Safety: Cycle the operand through the GPRs so the result always ends up
3604 // the correct MSA register.
3605 //
3606 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3607 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3608 // (which they can be, as the MSA registers are defined to alias the
3609 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3610 // the correct register class. That requires operands be tie-able across
3611 // register classes which have a sub/super register class relationship.
3612 //
3613 // For FPG32Opnd:
3614 //
3615 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3616 // =>
3617 // mfc1 $rtemp, $fs
3618 // fill.w $rtemp, $wtemp
3619 // fexdo.w $wd, $wtemp, $wtemp
3620 //
3621 // For FPG64Opnd on mips32r2+:
3622 //
3623 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3624 // =>
3625 // mfc1 $rtemp, $fs
3626 // fill.w $rtemp, $wtemp
3627 // mfhc1 $rtemp2, $fs
3628 // insert.w $wtemp[1], $rtemp2
3629 // insert.w $wtemp[3], $rtemp2
3630 // fexdo.w $wtemp2, $wtemp, $wtemp
3631 // fexdo.h $wd, $temp2, $temp2
3632 //
3633 // For FGR64Opnd on mips64r2+:
3634 //
3635 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3636 // =>
3637 // dmfc1 $rtemp, $fs
3638 // fill.d $rtemp, $wtemp
3639 // fexdo.w $wtemp2, $wtemp, $wtemp
3640 // fexdo.h $wd, $wtemp2, $wtemp2
3641 //
3642 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3643 // undef bits are "just right" and the exception enable bits are
3644 // set. By using fill.w to replicate $fs into all elements over
3645 // insert.w for one element, we avoid that potiential case. If
3646 // fexdo.[hw] causes an exception in, the exception is valid and it
3647 // occurs for all elements.
3649 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3651  bool IsFGR64) const {
3652 
3653  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3654  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3655  // it.
3657 
3658  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3659  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3660 
3662  DebugLoc DL = MI.getDebugLoc();
3663  Register Wd = MI.getOperand(0).getReg();
3664  Register Fs = MI.getOperand(1).getReg();
3665 
3666  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3667  Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3668  const TargetRegisterClass *GPRRC =
3669  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3670  unsigned MFC1Opc = IsFGR64onMips64
3671  ? Mips::DMFC1
3672  : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3673  unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3674 
3675  // Perform the register class copy as mentioned above.
3676  Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3677  BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3678  BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3679  unsigned WPHI = Wtemp;
3680 
3681  if (IsFGR64onMips32) {
3682  Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3683  BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3684  Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3685  Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3686  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3687  .addReg(Wtemp)
3688  .addReg(Rtemp2)
3689  .addImm(1);
3690  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3691  .addReg(Wtemp2)
3692  .addReg(Rtemp2)
3693  .addImm(3);
3694  WPHI = Wtemp3;
3695  }
3696 
3697  if (IsFGR64) {
3698  Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3699  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3700  .addReg(WPHI)
3701  .addReg(WPHI);
3702  WPHI = Wtemp2;
3703  }
3704 
3705  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3706 
3707  MI.eraseFromParent();
3708  return BB;
3709 }
3710 
3711 // Emit the FPEXTEND_PSEUDO instruction.
3712 //
3713 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3714 //
3715 // Safety: Cycle the result through the GPRs so the result always ends up
3716 // the correct floating point register.
3717 //
3718 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3719 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3720 // (which they can be, as the MSA registers are defined to alias the
3721 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3722 // the correct register class. That requires operands be tie-able across
3723 // register classes which have a sub/super register class relationship. I
3724 // haven't checked.
3725 //
3726 // For FGR32Opnd:
3727 //
3728 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3729 // =>
3730 // fexupr.w $wtemp, $ws
3731 // copy_s.w $rtemp, $ws[0]
3732 // mtc1 $rtemp, $fd
3733 //
3734 // For FGR64Opnd on Mips64:
3735 //
3736 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3737 // =>
3738 // fexupr.w $wtemp, $ws
3739 // fexupr.d $wtemp2, $wtemp
3740 // copy_s.d $rtemp, $wtemp2s[0]
3741 // dmtc1 $rtemp, $fd
3742 //
3743 // For FGR64Opnd on Mips32:
3744 //
3745 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3746 // =>
3747 // fexupr.w $wtemp, $ws
3748 // fexupr.d $wtemp2, $wtemp
3749 // copy_s.w $rtemp, $wtemp2[0]
3750 // mtc1 $rtemp, $ftemp
3751 // copy_s.w $rtemp2, $wtemp2[1]
3752 // $fd = mthc1 $rtemp2, $ftemp
3754 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3756  bool IsFGR64) const {
3757 
3758  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3759  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3760  // it.
3762 
3763  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3764  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3765 
3767  DebugLoc DL = MI.getDebugLoc();
3768  Register Fd = MI.getOperand(0).getReg();
3769  Register Ws = MI.getOperand(1).getReg();
3770 
3771  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3772  const TargetRegisterClass *GPRRC =
3773  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3774  unsigned MTC1Opc = IsFGR64onMips64
3775  ? Mips::DMTC1
3776  : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3777  Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3778 
3779  Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3780  Register WPHI = Wtemp;
3781 
3782  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3783  if (IsFGR64) {
3784  WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3785  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3786  }
3787 
3788  // Perform the safety regclass copy mentioned above.
3789  Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3790  Register FPRPHI = IsFGR64onMips32
3791  ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3792  : Fd;
3793  BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3794  BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3795 
3796  if (IsFGR64onMips32) {
3797  Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3798  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3799  .addReg(WPHI)
3800  .addImm(1);
3801  BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3802  .addReg(FPRPHI)
3803  .addReg(Rtemp2);
3804  }
3805 
3806  MI.eraseFromParent();
3807  return BB;
3808 }
3809 
3810 // Emit the FEXP2_W_1 pseudo instructions.
3811 //
3812 // fexp2_w_1_pseudo $wd, $wt
3813 // =>
3814 // ldi.w $ws, 1
3815 // fexp2.w $wd, $ws, $wt
3817 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3818  MachineBasicBlock *BB) const {
3820  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3821  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3822  Register Ws1 = RegInfo.createVirtualRegister(RC);
3823  Register Ws2 = RegInfo.createVirtualRegister(RC);
3824  DebugLoc DL = MI.getDebugLoc();
3825 
3826  // Splat 1.0 into a vector
3827  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3828  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3829 
3830  // Emit 1.0 * fexp2(Wt)
3831  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3832  .addReg(Ws2)
3833  .addReg(MI.getOperand(1).getReg());
3834 
3835  MI.eraseFromParent(); // The pseudo instruction is gone now.
3836  return BB;
3837 }
3838 
3839 // Emit the FEXP2_D_1 pseudo instructions.
3840 //
3841 // fexp2_d_1_pseudo $wd, $wt
3842 // =>
3843 // ldi.d $ws, 1
3844 // fexp2.d $wd, $ws, $wt
3846 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3847  MachineBasicBlock *BB) const {
3849  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3850  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3851  Register Ws1 = RegInfo.createVirtualRegister(RC);
3852  Register Ws2 = RegInfo.createVirtualRegister(RC);
3853  DebugLoc DL = MI.getDebugLoc();
3854 
3855  // Splat 1.0 into a vector
3856  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3857  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3858 
3859  // Emit 1.0 * fexp2(Wt)
3860  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3861  .addReg(Ws2)
3862  .addReg(MI.getOperand(1).getReg());
3863 
3864  MI.eraseFromParent(); // The pseudo instruction is gone now.
3865  return BB;
3866 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:872
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1368
llvm::MipsSETargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: MipsSEISelLowering.cpp:1026
ValueTypes.h
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1542
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm::StoreSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2313
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:563
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1379
llvm::ISD::INTRINSIC_VOID
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:199
llvm::ISD::SETO
@ SETO
Definition: ISDOpcodes.h:1364
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MipsISD::VEXTRACT_SEXT_ELT
@ VEXTRACT_SEXT_ELT
Definition: MipsISelLowering.h:241
llvm::MipsISD::DPSU_H_QBL
@ DPSU_H_QBL
Definition: MipsISelLowering.h:178
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Definition: SelectionDAGNodes.h:958
llvm::MipsISD::VALL_ZERO
@ VALL_ZERO
Definition: MipsISelLowering.h:212
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::MipsSubtarget::hasMips32r2
bool hasMips32r2() const
Definition: MipsSubtarget.h:256
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1376
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:848
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1380
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
truncateVecElts
static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:1507
llvm::MipsSETargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: MipsSEISelLowering.cpp:449
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:898
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MipsSETargetLowering::addMSAFloatType
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
Definition: MipsSEISelLowering.cpp:372
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:152
llvm::MipsSETargetLowering::MipsSETargetLowering
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsSEISelLowering.cpp:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1697
llvm::APInt::isPowerOf2
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:469
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1375
llvm::MipsSubtarget::systemSupportsUnalignedAccess
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
Definition: MipsSubtarget.h:373
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:227
performSHLCombine
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
Definition: MipsSEISelLowering.cpp:870
llvm::MipsISD::PCKEV
@ PCKEV
Definition: MipsISelLowering.h:231
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
ErrorHandling.h
genConstMult
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:793
llvm::MipsSETargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MipsSEISelLowering.cpp:1067
lowerMSASplatImm
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
Definition: MipsSEISelLowering.cpp:1418
lowerMSABitClearImm
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:1530
llvm::MipsISD::VANY_NONZERO
@ VANY_NONZERO
Definition: MipsISelLowering.h:215
isConstantOrUndefBUILD_VECTOR
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
Definition: MipsSEISelLowering.cpp:2439
llvm::MipsSubtarget::hasMips64r6
bool hasMips64r6() const
Definition: MipsSubtarget.h:276
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1328
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:875
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1351
llvm::MipsISD::ILVR
@ ILVR
Definition: MipsISelLowering.h:230
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
MachineBasicBlock.h
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:466
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:785
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3531
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2263
APInt.h
llvm::MipsSubtarget::hasMips64
bool hasMips64() const
Definition: MipsSubtarget.h:272
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1370
llvm::MipsISD::ExtractElementF64
@ ExtractElementF64
Definition: MipsISelLowering.h:148
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1581
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MipsTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: MipsISelLowering.cpp:1153
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7486
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
llvm::MipsSubtarget::getInstrInfo
const MipsInstrInfo * getInstrInfo() const override
Definition: MipsSubtarget.h:382
llvm::SelectionDAG::isSplatValue
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0)
Test whether V has a splatted value for all the demanded elements.
Definition: SelectionDAG.cpp:2462
isVECTOR_SHUFFLE_SPLATI
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:2634
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MipsSubtarget::useOddSPReg
bool useOddSPReg() const
Definition: MipsSubtarget.h:285
lowerMSACopyIntr
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Definition: MipsSEISelLowering.cpp:1361
llvm::MipsISD::Multu
@ Multu
Definition: MipsISelLowering.h:133
NoDPLoadStore
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
UseMipsTailCalls
static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
STLExtras.h
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1335
llvm::APInt::lshr
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:987
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1358
llvm::MVT::v2f64
@ v2f64
Definition: MachineValueType.h:172
llvm::MipsISD::MFHI
@ MFHI
Definition: MipsISelLowering.h:125
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SelectionDAG::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:442
llvm::MipsISD::MAQ_SA_W_PHL
@ MAQ_SA_W_PHL
Definition: MipsISelLowering.h:174
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1366
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:627
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:867
llvm::MipsISD::MFLO
@ MFLO
Definition: MipsISelLowering.h:126
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
lowerDSPIntr
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Definition: MipsSEISelLowering.cpp:1313
lowerMSALoadIntr
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
Definition: MipsSEISelLowering.cpp:2293
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MipsTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MipsISelLowering.cpp:1283
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:956
llvm::SDNode::getVTList
SDVTList getVTList() const
Definition: SelectionDAGNodes.h:924
performANDCombine
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
Definition: MipsSEISelLowering.cpp:482
MachineRegisterInfo.h
llvm::ShuffleVectorSDNode
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
Definition: SelectionDAGNodes.h:1484
llvm::MipsISD::MAdd
@ MAdd
Definition: MipsISelLowering.h:136
shouldTransformMulToShiftsAddsSubs
static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
Definition: MipsSEISelLowering.cpp:717
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
performORCombine
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
Definition: MipsSEISelLowering.cpp:597
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
lowerVECTOR_SHUFFLE_ILVR
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:2759
llvm::MipsSubtarget::getRegisterInfo
const MipsRegisterInfo * getRegisterInfo() const override
Definition: MipsSubtarget.h:386
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:746
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:885
CommandLine.h
llvm::Triple::isLittleEndian
bool isLittleEndian() const
Tests whether the target triple is little endian.
Definition: Triple.cpp:1574
llvm::MipsTargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: MipsISelLowering.cpp:2791
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:963
llvm::MipsISD::EXTR_RS_W
@ EXTR_RS_W
Definition: MipsISelLowering.h:166
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7436
llvm::MipsFunctionInfo::getIncomingArgSize
unsigned getIncomingArgSize() const
Definition: MipsMachineFunction.h:51
llvm::SDNode::getOpcode
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Definition: SelectionDAGNodes.h:621
isConstantOrUndef
static bool isConstantOrUndef(const SDValue Op)
Definition: MipsSEISelLowering.cpp:2429
llvm::MVT::v8f16
@ v8f16
Definition: MachineValueType.h:137
llvm::APInt::isNegative
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:364
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:694
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1113
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:668
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MipsISD::DPSU_H_QBR
@ DPSU_H_QBR
Definition: MipsISelLowering.h:179
llvm::MipsISD::MTHLIP
@ MTHLIP
Definition: MipsISelLowering.h:168
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:679
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1377
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:951
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1987
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:443
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MipsISD::VEXTRACT_ZEXT_ELT
@ VEXTRACT_ZEXT_ELT
Definition: MipsISelLowering.h:242
Intrinsics.h
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
lowerVECTOR_SHUFFLE_ILVEV
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:2666
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1348
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:207
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:309
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
llvm::MipsTargetLowering::getOpndList
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
Definition: MipsISelLowering.cpp:3024
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:883
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3525
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:658
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2168
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MipsISD::DPAU_H_QBR
@ DPAU_H_QBR
Definition: MipsISelLowering.h:177
MipsRegisterInfo.h
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:145
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:739
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1631
llvm::MipsISD::DPAX_W_PH
@ DPAX_W_PH
Definition: MipsISelLowering.h:188
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:655
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:882
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:881
extractLOHI
static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:1295
llvm::wasm::ValType
ValType
Definition: Wasm.h:392
DebugLoc.h
llvm::MipsISD::DivRem
@ DivRem
Definition: MipsISelLowering.h:142
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1361
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::ISD::FSINCOS
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:915
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MipsISD::ThreadPointer
@ ThreadPointer
Definition: MipsISelLowering.h:91
llvm::MipsISD::MTLOHI
@ MTLOHI
Definition: MipsISelLowering.h:129
llvm::EVT::changeVectorElementTypeToInteger
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:94
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1390
lowerVECTOR_SHUFFLE_ILVOD
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Definition: MipsSEISelLowering.cpp:2712
llvm::MVT::v4i8
@ v4i8
Definition: MachineValueType.h:78
llvm::MipsISD::FSELECT
@ FSELECT
Definition: MipsISelLowering.h:103
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1362
llvm::APInt::isAllOnesValue
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:401
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::codeview::ClassOptions::Intrinsic
@ Intrinsic
<