37#include "llvm/IR/IntrinsicsMips.h"
53#define DEBUG_TYPE "mips-isel"
60 cl::desc(
"Expand double precision loads and "
61 "stores to their single precision "
88 for (
const auto &VecTy : VecTys) {
303 if (VT == MVT::Untyped)
304 return Subtarget.
hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
348 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
379 if (Ty != MVT::v8f16) {
406 EVT ResTy =
Op->getValueType(0);
444 switch(
Op.getOpcode()) {
496 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
498 if (Log2IfPositive <= 0)
502 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
504 unsigned Log2 = Log2IfPositive;
507 Log2 == ExtendTySize) {
533 APInt SplatValue, SplatUndef;
534 unsigned SplatBitSize;
537 if (!
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
551 N =
N->getOperand(0);
558 APInt SplatValue, SplatUndef;
559 unsigned SplatBitSize;
564 if (BVN->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
576 return N->getOperand(1) == OfNode;
579 return N->getOperand(0) == OfNode;
596 EVT Ty =
N->getValueType(0);
609 bool IsLittleEndian = !Subtarget.
isLittle();
612 bool IsConstantMask =
false;
619 if (
isVSplat(Op0Op0, Mask, IsLittleEndian)) {
623 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
624 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
626 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
627 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
630 IsConstantMask =
true;
640 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
641 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
643 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
644 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
647 IsConstantMask =
true;
696 if (IsConstantMask) {
697 if (Mask.isAllOnes())
738 unsigned MaxSteps = Subtarget.
isABI_O32() ? 8 : 12;
744 while (!WorkStack.
empty()) {
747 if (Val == 0 || Val == 1)
750 if (Steps >= MaxSteps)
761 if ((Val - Floor).ule(Ceil - Val)) {
809 if ((
C - Floor).ule(Ceil -
C)) {
826 EVT VT =
N->getValueType(0);
830 C->getAPIntValue(), VT, DAG, Subtarget))
842 APInt SplatValue, SplatUndef;
843 unsigned SplatBitSize;
852 !BV->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
854 (SplatBitSize != EltSize) ||
859 return DAG.
getNode(Opc,
DL, Ty,
N->getOperand(0),
866 EVT Ty =
N->getValueType(0);
868 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
889 EVT Ty =
N->getValueType(0);
910 EVT ExtendTy = cast<VTSDNode>(Op0Op0->
getOperand(2))->getVT();
913 if (TotalBits == 32 ||
925 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.
hasDSPR2()))
935 EVT Ty =
N->getValueType(0);
937 if (((Ty != MVT::v2i16) || !Subtarget.
hasDSPR2()) && (Ty != MVT::v4i8))
944 bool IsV216 = (Ty == MVT::v2i16);
957 default:
return false;
962 EVT Ty =
N->getValueType(0);
964 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
971 N->getOperand(1),
N->getOperand(2));
975 EVT Ty =
N->getValueType(0);
977 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
985 N->getOperand(1),
N->getOperand(2), SetCC.
getOperand(2));
993 EVT Ty =
N->getValueType(0);
1023 switch (
N->getOpcode()) {
1051 N->printrWithDepth(
dbgs(), &DAG);
dbgs() <<
"\n=> \n";
1062 switch (
MI.getOpcode()) {
1065 case Mips::BPOSGE32_PSEUDO:
1066 return emitBPOSGE32(
MI, BB);
1067 case Mips::SNZ_B_PSEUDO:
1068 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_B);
1069 case Mips::SNZ_H_PSEUDO:
1070 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_H);
1071 case Mips::SNZ_W_PSEUDO:
1072 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_W);
1073 case Mips::SNZ_D_PSEUDO:
1074 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_D);
1075 case Mips::SNZ_V_PSEUDO:
1076 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_V);
1077 case Mips::SZ_B_PSEUDO:
1078 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_B);
1079 case Mips::SZ_H_PSEUDO:
1080 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_H);
1081 case Mips::SZ_W_PSEUDO:
1082 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_W);
1083 case Mips::SZ_D_PSEUDO:
1084 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_D);
1085 case Mips::SZ_V_PSEUDO:
1086 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_V);
1087 case Mips::COPY_FW_PSEUDO:
1088 return emitCOPY_FW(
MI, BB);
1089 case Mips::COPY_FD_PSEUDO:
1090 return emitCOPY_FD(
MI, BB);
1091 case Mips::INSERT_FW_PSEUDO:
1092 return emitINSERT_FW(
MI, BB);
1093 case Mips::INSERT_FD_PSEUDO:
1094 return emitINSERT_FD(
MI, BB);
1095 case Mips::INSERT_B_VIDX_PSEUDO:
1096 case Mips::INSERT_B_VIDX64_PSEUDO:
1097 return emitINSERT_DF_VIDX(
MI, BB, 1,
false);
1098 case Mips::INSERT_H_VIDX_PSEUDO:
1099 case Mips::INSERT_H_VIDX64_PSEUDO:
1100 return emitINSERT_DF_VIDX(
MI, BB, 2,
false);
1101 case Mips::INSERT_W_VIDX_PSEUDO:
1102 case Mips::INSERT_W_VIDX64_PSEUDO:
1103 return emitINSERT_DF_VIDX(
MI, BB, 4,
false);
1104 case Mips::INSERT_D_VIDX_PSEUDO:
1105 case Mips::INSERT_D_VIDX64_PSEUDO:
1106 return emitINSERT_DF_VIDX(
MI, BB, 8,
false);
1107 case Mips::INSERT_FW_VIDX_PSEUDO:
1108 case Mips::INSERT_FW_VIDX64_PSEUDO:
1109 return emitINSERT_DF_VIDX(
MI, BB, 4,
true);
1110 case Mips::INSERT_FD_VIDX_PSEUDO:
1111 case Mips::INSERT_FD_VIDX64_PSEUDO:
1112 return emitINSERT_DF_VIDX(
MI, BB, 8,
true);
1113 case Mips::FILL_FW_PSEUDO:
1114 return emitFILL_FW(
MI, BB);
1115 case Mips::FILL_FD_PSEUDO:
1116 return emitFILL_FD(
MI, BB);
1117 case Mips::FEXP2_W_1_PSEUDO:
1118 return emitFEXP2_W_1(
MI, BB);
1119 case Mips::FEXP2_D_1_PSEUDO:
1120 return emitFEXP2_D_1(
MI, BB);
1122 return emitST_F16_PSEUDO(
MI, BB);
1124 return emitLD_F16_PSEUDO(
MI, BB);
1125 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1126 return emitFPEXTEND_PSEUDO(
MI, BB,
false);
1127 case Mips::MSA_FP_ROUND_W_PSEUDO:
1128 return emitFPROUND_PSEUDO(
MI, BB,
false);
1129 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1130 return emitFPEXTEND_PSEUDO(
MI, BB,
true);
1131 case Mips::MSA_FP_ROUND_D_PSEUDO:
1132 return emitFPROUND_PSEUDO(
MI, BB,
true);
1136bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1137 const CCState &CCInfo,
unsigned NextStackOffset,
1155void MipsSETargetLowering::
1157 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1158 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
1159 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
1163 InternalLinkage, IsCallReloc, CLI, Callee,
1176 EVT PtrVT =
Ptr.getValueType();
1205 EVT PtrVT =
Ptr.getValueType();
1228 MVT Src =
Op.getOperand(0).getValueType().getSimpleVT();
1229 MVT Dest =
Op.getValueType().getSimpleVT();
1232 if (Src == MVT::i64 && Dest == MVT::f64) {
1240 if (Src == MVT::f64 && Dest == MVT::i64) {
1255 bool HasLo,
bool HasHi,
1260 EVT Ty =
Op.getOperand(0).getValueType();
1263 Op.getOperand(0),
Op.getOperand(1));
1271 if (!HasLo || !HasHi)
1272 return HasLo ?
Lo :
Hi;
1280 std::tie(InLo, InHi) = DAG.
SplitScalar(In,
DL, MVT::i32, MVT::i32);
1304 bool HasChainIn =
Op->getOperand(0).getValueType() == MVT::Other;
1316 SDValue Opnd =
Op->getOperand(++OpNo), In64;
1334 for (
EVT Ty :
Op->values())
1335 ResTys.
push_back((Ty == MVT::i64) ? MVT::Untyped : Ty);
1354 EVT ResTy =
Op->getValueType(0);
1364 EVT ResVecTy =
Op->getValueType(0);
1365 EVT ViaVecTy = ResVecTy;
1375 if (ResVecTy == MVT::v2i64) {
1378 if (isa<ConstantSDNode>(LaneA))
1386 ViaVecTy = MVT::v4i32;
1392 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1393 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1398 if (ViaVecTy != ResVecTy) {
1408 bool IsSigned =
false) {
1409 auto *CImm = cast<ConstantSDNode>(
Op->getOperand(ImmOp));
1411 APInt(
Op->getValueType(0).getScalarType().getSizeInBits(),
1412 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
1418 EVT ViaVecTy = VecTy;
1419 SDValue SplatValueA = SplatValue;
1420 SDValue SplatValueB = SplatValue;
1423 if (VecTy == MVT::v2i64) {
1425 ViaVecTy = MVT::v4i32;
1438 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1439 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1440 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1441 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1446 if (VecTy != ViaVecTy)
1455 EVT VecTy =
Op->getValueType(0);
1461 if (VecTy == MVT::v2i64) {
1463 APInt BitImm =
APInt(64, 1) << CImm->getAPIntValue();
1475 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1484 if (VecTy == MVT::v2i64)
1493 return DAG.
getNode(Opc,
DL, VecTy,
Op->getOperand(1), Exp2Imm);
1498 EVT ResTy =
Op->getValueType(0);
1501 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1510 EVT ResTy =
Op->getValueType(0);
1521 EVT ResTy =
Op->getValueType(0);
1523 << cast<ConstantSDNode>(
Op->getOperand(2))->getAPIntValue();
1532 unsigned Intrinsic = cast<ConstantSDNode>(
Op->getOperand(0))->getZExtValue();
1533 switch (Intrinsic) {
1536 case Intrinsic::mips_shilo:
1538 case Intrinsic::mips_dpau_h_qbl:
1540 case Intrinsic::mips_dpau_h_qbr:
1542 case Intrinsic::mips_dpsu_h_qbl:
1544 case Intrinsic::mips_dpsu_h_qbr:
1546 case Intrinsic::mips_dpa_w_ph:
1548 case Intrinsic::mips_dps_w_ph:
1550 case Intrinsic::mips_dpax_w_ph:
1552 case Intrinsic::mips_dpsx_w_ph:
1554 case Intrinsic::mips_mulsa_w_ph:
1556 case Intrinsic::mips_mult:
1558 case Intrinsic::mips_multu:
1560 case Intrinsic::mips_madd:
1562 case Intrinsic::mips_maddu:
1564 case Intrinsic::mips_msub:
1566 case Intrinsic::mips_msubu:
1568 case Intrinsic::mips_addv_b:
1569 case Intrinsic::mips_addv_h:
1570 case Intrinsic::mips_addv_w:
1571 case Intrinsic::mips_addv_d:
1574 case Intrinsic::mips_addvi_b:
1575 case Intrinsic::mips_addvi_h:
1576 case Intrinsic::mips_addvi_w:
1577 case Intrinsic::mips_addvi_d:
1580 case Intrinsic::mips_and_v:
1583 case Intrinsic::mips_andi_b:
1586 case Intrinsic::mips_bclr_b:
1587 case Intrinsic::mips_bclr_h:
1588 case Intrinsic::mips_bclr_w:
1589 case Intrinsic::mips_bclr_d:
1591 case Intrinsic::mips_bclri_b:
1592 case Intrinsic::mips_bclri_h:
1593 case Intrinsic::mips_bclri_w:
1594 case Intrinsic::mips_bclri_d:
1596 case Intrinsic::mips_binsli_b:
1597 case Intrinsic::mips_binsli_h:
1598 case Intrinsic::mips_binsli_w:
1599 case Intrinsic::mips_binsli_d: {
1601 EVT VecTy =
Op->getValueType(0);
1606 Op->getConstantOperandVal(3) + 1);
1609 Op->getOperand(2),
Op->getOperand(1));
1611 case Intrinsic::mips_binsri_b:
1612 case Intrinsic::mips_binsri_h:
1613 case Intrinsic::mips_binsri_w:
1614 case Intrinsic::mips_binsri_d: {
1616 EVT VecTy =
Op->getValueType(0);
1621 Op->getConstantOperandVal(3) + 1);
1624 Op->getOperand(2),
Op->getOperand(1));
1626 case Intrinsic::mips_bmnz_v:
1628 Op->getOperand(2),
Op->getOperand(1));
1629 case Intrinsic::mips_bmnzi_b:
1633 case Intrinsic::mips_bmz_v:
1635 Op->getOperand(1),
Op->getOperand(2));
1636 case Intrinsic::mips_bmzi_b:
1640 case Intrinsic::mips_bneg_b:
1641 case Intrinsic::mips_bneg_h:
1642 case Intrinsic::mips_bneg_w:
1643 case Intrinsic::mips_bneg_d: {
1644 EVT VecTy =
Op->getValueType(0);
1651 case Intrinsic::mips_bnegi_b:
1652 case Intrinsic::mips_bnegi_h:
1653 case Intrinsic::mips_bnegi_w:
1654 case Intrinsic::mips_bnegi_d:
1657 case Intrinsic::mips_bnz_b:
1658 case Intrinsic::mips_bnz_h:
1659 case Intrinsic::mips_bnz_w:
1660 case Intrinsic::mips_bnz_d:
1663 case Intrinsic::mips_bnz_v:
1666 case Intrinsic::mips_bsel_v:
1669 Op->getOperand(1),
Op->getOperand(3),
1671 case Intrinsic::mips_bseli_b:
1676 case Intrinsic::mips_bset_b:
1677 case Intrinsic::mips_bset_h:
1678 case Intrinsic::mips_bset_w:
1679 case Intrinsic::mips_bset_d: {
1680 EVT VecTy =
Op->getValueType(0);
1687 case Intrinsic::mips_bseti_b:
1688 case Intrinsic::mips_bseti_h:
1689 case Intrinsic::mips_bseti_w:
1690 case Intrinsic::mips_bseti_d:
1693 case Intrinsic::mips_bz_b:
1694 case Intrinsic::mips_bz_h:
1695 case Intrinsic::mips_bz_w:
1696 case Intrinsic::mips_bz_d:
1699 case Intrinsic::mips_bz_v:
1702 case Intrinsic::mips_ceq_b:
1703 case Intrinsic::mips_ceq_h:
1704 case Intrinsic::mips_ceq_w:
1705 case Intrinsic::mips_ceq_d:
1708 case Intrinsic::mips_ceqi_b:
1709 case Intrinsic::mips_ceqi_h:
1710 case Intrinsic::mips_ceqi_w:
1711 case Intrinsic::mips_ceqi_d:
1714 case Intrinsic::mips_cle_s_b:
1715 case Intrinsic::mips_cle_s_h:
1716 case Intrinsic::mips_cle_s_w:
1717 case Intrinsic::mips_cle_s_d:
1720 case Intrinsic::mips_clei_s_b:
1721 case Intrinsic::mips_clei_s_h:
1722 case Intrinsic::mips_clei_s_w:
1723 case Intrinsic::mips_clei_s_d:
1726 case Intrinsic::mips_cle_u_b:
1727 case Intrinsic::mips_cle_u_h:
1728 case Intrinsic::mips_cle_u_w:
1729 case Intrinsic::mips_cle_u_d:
1732 case Intrinsic::mips_clei_u_b:
1733 case Intrinsic::mips_clei_u_h:
1734 case Intrinsic::mips_clei_u_w:
1735 case Intrinsic::mips_clei_u_d:
1738 case Intrinsic::mips_clt_s_b:
1739 case Intrinsic::mips_clt_s_h:
1740 case Intrinsic::mips_clt_s_w:
1741 case Intrinsic::mips_clt_s_d:
1744 case Intrinsic::mips_clti_s_b:
1745 case Intrinsic::mips_clti_s_h:
1746 case Intrinsic::mips_clti_s_w:
1747 case Intrinsic::mips_clti_s_d:
1750 case Intrinsic::mips_clt_u_b:
1751 case Intrinsic::mips_clt_u_h:
1752 case Intrinsic::mips_clt_u_w:
1753 case Intrinsic::mips_clt_u_d:
1756 case Intrinsic::mips_clti_u_b:
1757 case Intrinsic::mips_clti_u_h:
1758 case Intrinsic::mips_clti_u_w:
1759 case Intrinsic::mips_clti_u_d:
1762 case Intrinsic::mips_copy_s_b:
1763 case Intrinsic::mips_copy_s_h:
1764 case Intrinsic::mips_copy_s_w:
1766 case Intrinsic::mips_copy_s_d:
1774 Op->getValueType(0),
Op->getOperand(1),
1777 case Intrinsic::mips_copy_u_b:
1778 case Intrinsic::mips_copy_u_h:
1779 case Intrinsic::mips_copy_u_w:
1781 case Intrinsic::mips_copy_u_d:
1792 Op->getValueType(0),
Op->getOperand(1),
1795 case Intrinsic::mips_div_s_b:
1796 case Intrinsic::mips_div_s_h:
1797 case Intrinsic::mips_div_s_w:
1798 case Intrinsic::mips_div_s_d:
1801 case Intrinsic::mips_div_u_b:
1802 case Intrinsic::mips_div_u_h:
1803 case Intrinsic::mips_div_u_w:
1804 case Intrinsic::mips_div_u_d:
1807 case Intrinsic::mips_fadd_w:
1808 case Intrinsic::mips_fadd_d:
1813 case Intrinsic::mips_fceq_w:
1814 case Intrinsic::mips_fceq_d:
1817 case Intrinsic::mips_fcle_w:
1818 case Intrinsic::mips_fcle_d:
1821 case Intrinsic::mips_fclt_w:
1822 case Intrinsic::mips_fclt_d:
1825 case Intrinsic::mips_fcne_w:
1826 case Intrinsic::mips_fcne_d:
1829 case Intrinsic::mips_fcor_w:
1830 case Intrinsic::mips_fcor_d:
1833 case Intrinsic::mips_fcueq_w:
1834 case Intrinsic::mips_fcueq_d:
1837 case Intrinsic::mips_fcule_w:
1838 case Intrinsic::mips_fcule_d:
1841 case Intrinsic::mips_fcult_w:
1842 case Intrinsic::mips_fcult_d:
1845 case Intrinsic::mips_fcun_w:
1846 case Intrinsic::mips_fcun_d:
1849 case Intrinsic::mips_fcune_w:
1850 case Intrinsic::mips_fcune_d:
1853 case Intrinsic::mips_fdiv_w:
1854 case Intrinsic::mips_fdiv_d:
1858 case Intrinsic::mips_ffint_u_w:
1859 case Intrinsic::mips_ffint_u_d:
1862 case Intrinsic::mips_ffint_s_w:
1863 case Intrinsic::mips_ffint_s_d:
1866 case Intrinsic::mips_fill_b:
1867 case Intrinsic::mips_fill_h:
1868 case Intrinsic::mips_fill_w:
1869 case Intrinsic::mips_fill_d: {
1870 EVT ResTy =
Op->getValueType(0);
1878 case Intrinsic::mips_fexp2_w:
1879 case Intrinsic::mips_fexp2_d: {
1881 EVT ResTy =
Op->getValueType(0);
1886 case Intrinsic::mips_flog2_w:
1887 case Intrinsic::mips_flog2_d:
1889 case Intrinsic::mips_fmadd_w:
1890 case Intrinsic::mips_fmadd_d:
1892 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
1893 case Intrinsic::mips_fmul_w:
1894 case Intrinsic::mips_fmul_d:
1898 case Intrinsic::mips_fmsub_w:
1899 case Intrinsic::mips_fmsub_d: {
1902 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
1904 case Intrinsic::mips_frint_w:
1905 case Intrinsic::mips_frint_d:
1907 case Intrinsic::mips_fsqrt_w:
1908 case Intrinsic::mips_fsqrt_d:
1910 case Intrinsic::mips_fsub_w:
1911 case Intrinsic::mips_fsub_d:
1915 case Intrinsic::mips_ftrunc_u_w:
1916 case Intrinsic::mips_ftrunc_u_d:
1919 case Intrinsic::mips_ftrunc_s_w:
1920 case Intrinsic::mips_ftrunc_s_d:
1923 case Intrinsic::mips_ilvev_b:
1924 case Intrinsic::mips_ilvev_h:
1925 case Intrinsic::mips_ilvev_w:
1926 case Intrinsic::mips_ilvev_d:
1928 Op->getOperand(1),
Op->getOperand(2));
1929 case Intrinsic::mips_ilvl_b:
1930 case Intrinsic::mips_ilvl_h:
1931 case Intrinsic::mips_ilvl_w:
1932 case Intrinsic::mips_ilvl_d:
1934 Op->getOperand(1),
Op->getOperand(2));
1935 case Intrinsic::mips_ilvod_b:
1936 case Intrinsic::mips_ilvod_h:
1937 case Intrinsic::mips_ilvod_w:
1938 case Intrinsic::mips_ilvod_d:
1940 Op->getOperand(1),
Op->getOperand(2));
1941 case Intrinsic::mips_ilvr_b:
1942 case Intrinsic::mips_ilvr_h:
1943 case Intrinsic::mips_ilvr_w:
1944 case Intrinsic::mips_ilvr_d:
1946 Op->getOperand(1),
Op->getOperand(2));
1947 case Intrinsic::mips_insert_b:
1948 case Intrinsic::mips_insert_h:
1949 case Intrinsic::mips_insert_w:
1950 case Intrinsic::mips_insert_d:
1952 Op->getOperand(1),
Op->getOperand(3),
Op->getOperand(2));
1953 case Intrinsic::mips_insve_b:
1954 case Intrinsic::mips_insve_h:
1955 case Intrinsic::mips_insve_w:
1956 case Intrinsic::mips_insve_d: {
1959 switch (Intrinsic) {
1960 case Intrinsic::mips_insve_b:
Max = 15;
break;
1961 case Intrinsic::mips_insve_h:
Max = 7;
break;
1962 case Intrinsic::mips_insve_w:
Max = 3;
break;
1963 case Intrinsic::mips_insve_d:
Max = 1;
break;
1966 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
1967 if (Value < 0 || Value > Max)
1970 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3),
1973 case Intrinsic::mips_ldi_b:
1974 case Intrinsic::mips_ldi_h:
1975 case Intrinsic::mips_ldi_w:
1976 case Intrinsic::mips_ldi_d:
1978 case Intrinsic::mips_lsa:
1979 case Intrinsic::mips_dlsa: {
1980 EVT ResTy =
Op->getValueType(0);
1983 Op->getOperand(2),
Op->getOperand(3)));
1985 case Intrinsic::mips_maddv_b:
1986 case Intrinsic::mips_maddv_h:
1987 case Intrinsic::mips_maddv_w:
1988 case Intrinsic::mips_maddv_d: {
1989 EVT ResTy =
Op->getValueType(0);
1992 Op->getOperand(2),
Op->getOperand(3)));
1994 case Intrinsic::mips_max_s_b:
1995 case Intrinsic::mips_max_s_h:
1996 case Intrinsic::mips_max_s_w:
1997 case Intrinsic::mips_max_s_d:
1999 Op->getOperand(1),
Op->getOperand(2));
2000 case Intrinsic::mips_max_u_b:
2001 case Intrinsic::mips_max_u_h:
2002 case Intrinsic::mips_max_u_w:
2003 case Intrinsic::mips_max_u_d:
2005 Op->getOperand(1),
Op->getOperand(2));
2006 case Intrinsic::mips_maxi_s_b:
2007 case Intrinsic::mips_maxi_s_h:
2008 case Intrinsic::mips_maxi_s_w:
2009 case Intrinsic::mips_maxi_s_d:
2012 case Intrinsic::mips_maxi_u_b:
2013 case Intrinsic::mips_maxi_u_h:
2014 case Intrinsic::mips_maxi_u_w:
2015 case Intrinsic::mips_maxi_u_d:
2018 case Intrinsic::mips_min_s_b:
2019 case Intrinsic::mips_min_s_h:
2020 case Intrinsic::mips_min_s_w:
2021 case Intrinsic::mips_min_s_d:
2023 Op->getOperand(1),
Op->getOperand(2));
2024 case Intrinsic::mips_min_u_b:
2025 case Intrinsic::mips_min_u_h:
2026 case Intrinsic::mips_min_u_w:
2027 case Intrinsic::mips_min_u_d:
2029 Op->getOperand(1),
Op->getOperand(2));
2030 case Intrinsic::mips_mini_s_b:
2031 case Intrinsic::mips_mini_s_h:
2032 case Intrinsic::mips_mini_s_w:
2033 case Intrinsic::mips_mini_s_d:
2036 case Intrinsic::mips_mini_u_b:
2037 case Intrinsic::mips_mini_u_h:
2038 case Intrinsic::mips_mini_u_w:
2039 case Intrinsic::mips_mini_u_d:
2042 case Intrinsic::mips_mod_s_b:
2043 case Intrinsic::mips_mod_s_h:
2044 case Intrinsic::mips_mod_s_w:
2045 case Intrinsic::mips_mod_s_d:
2048 case Intrinsic::mips_mod_u_b:
2049 case Intrinsic::mips_mod_u_h:
2050 case Intrinsic::mips_mod_u_w:
2051 case Intrinsic::mips_mod_u_d:
2054 case Intrinsic::mips_mulv_b:
2055 case Intrinsic::mips_mulv_h:
2056 case Intrinsic::mips_mulv_w:
2057 case Intrinsic::mips_mulv_d:
2060 case Intrinsic::mips_msubv_b:
2061 case Intrinsic::mips_msubv_h:
2062 case Intrinsic::mips_msubv_w:
2063 case Intrinsic::mips_msubv_d: {
2064 EVT ResTy =
Op->getValueType(0);
2067 Op->getOperand(2),
Op->getOperand(3)));
2069 case Intrinsic::mips_nlzc_b:
2070 case Intrinsic::mips_nlzc_h:
2071 case Intrinsic::mips_nlzc_w:
2072 case Intrinsic::mips_nlzc_d:
2074 case Intrinsic::mips_nor_v: {
2076 Op->getOperand(1),
Op->getOperand(2));
2079 case Intrinsic::mips_nori_b: {
2085 case Intrinsic::mips_or_v:
2088 case Intrinsic::mips_ori_b:
2091 case Intrinsic::mips_pckev_b:
2092 case Intrinsic::mips_pckev_h:
2093 case Intrinsic::mips_pckev_w:
2094 case Intrinsic::mips_pckev_d:
2096 Op->getOperand(1),
Op->getOperand(2));
2097 case Intrinsic::mips_pckod_b:
2098 case Intrinsic::mips_pckod_h:
2099 case Intrinsic::mips_pckod_w:
2100 case Intrinsic::mips_pckod_d:
2102 Op->getOperand(1),
Op->getOperand(2));
2103 case Intrinsic::mips_pcnt_b:
2104 case Intrinsic::mips_pcnt_h:
2105 case Intrinsic::mips_pcnt_w:
2106 case Intrinsic::mips_pcnt_d:
2108 case Intrinsic::mips_sat_s_b:
2109 case Intrinsic::mips_sat_s_h:
2110 case Intrinsic::mips_sat_s_w:
2111 case Intrinsic::mips_sat_s_d:
2112 case Intrinsic::mips_sat_u_b:
2113 case Intrinsic::mips_sat_u_h:
2114 case Intrinsic::mips_sat_u_w:
2115 case Intrinsic::mips_sat_u_d: {
2118 switch (Intrinsic) {
2119 case Intrinsic::mips_sat_s_b:
2120 case Intrinsic::mips_sat_u_b:
Max = 7;
break;
2121 case Intrinsic::mips_sat_s_h:
2122 case Intrinsic::mips_sat_u_h:
Max = 15;
break;
2123 case Intrinsic::mips_sat_s_w:
2124 case Intrinsic::mips_sat_u_w:
Max = 31;
break;
2125 case Intrinsic::mips_sat_s_d:
2126 case Intrinsic::mips_sat_u_d:
Max = 63;
break;
2129 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2130 if (Value < 0 || Value > Max)
2134 case Intrinsic::mips_shf_b:
2135 case Intrinsic::mips_shf_h:
2136 case Intrinsic::mips_shf_w: {
2137 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2138 if (Value < 0 || Value > 255)
2141 Op->getOperand(2),
Op->getOperand(1));
2143 case Intrinsic::mips_sldi_b:
2144 case Intrinsic::mips_sldi_h:
2145 case Intrinsic::mips_sldi_w:
2146 case Intrinsic::mips_sldi_d: {
2149 switch (Intrinsic) {
2150 case Intrinsic::mips_sldi_b:
Max = 15;
break;
2151 case Intrinsic::mips_sldi_h:
Max = 7;
break;
2152 case Intrinsic::mips_sldi_w:
Max = 3;
break;
2153 case Intrinsic::mips_sldi_d:
Max = 1;
break;
2156 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(3))->getSExtValue();
2157 if (Value < 0 || Value > Max)
2161 case Intrinsic::mips_sll_b:
2162 case Intrinsic::mips_sll_h:
2163 case Intrinsic::mips_sll_w:
2164 case Intrinsic::mips_sll_d:
2167 case Intrinsic::mips_slli_b:
2168 case Intrinsic::mips_slli_h:
2169 case Intrinsic::mips_slli_w:
2170 case Intrinsic::mips_slli_d:
2173 case Intrinsic::mips_splat_b:
2174 case Intrinsic::mips_splat_h:
2175 case Intrinsic::mips_splat_w:
2176 case Intrinsic::mips_splat_d:
2184 case Intrinsic::mips_splati_b:
2185 case Intrinsic::mips_splati_h:
2186 case Intrinsic::mips_splati_w:
2187 case Intrinsic::mips_splati_d:
2191 case Intrinsic::mips_sra_b:
2192 case Intrinsic::mips_sra_h:
2193 case Intrinsic::mips_sra_w:
2194 case Intrinsic::mips_sra_d:
2197 case Intrinsic::mips_srai_b:
2198 case Intrinsic::mips_srai_h:
2199 case Intrinsic::mips_srai_w:
2200 case Intrinsic::mips_srai_d:
2203 case Intrinsic::mips_srari_b:
2204 case Intrinsic::mips_srari_h:
2205 case Intrinsic::mips_srari_w:
2206 case Intrinsic::mips_srari_d: {
2209 switch (Intrinsic) {
2210 case Intrinsic::mips_srari_b:
Max = 7;
break;
2211 case Intrinsic::mips_srari_h:
Max = 15;
break;
2212 case Intrinsic::mips_srari_w:
Max = 31;
break;
2213 case Intrinsic::mips_srari_d:
Max = 63;
break;
2216 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2217 if (Value < 0 || Value > Max)
2221 case Intrinsic::mips_srl_b:
2222 case Intrinsic::mips_srl_h:
2223 case Intrinsic::mips_srl_w:
2224 case Intrinsic::mips_srl_d:
2227 case Intrinsic::mips_srli_b:
2228 case Intrinsic::mips_srli_h:
2229 case Intrinsic::mips_srli_w:
2230 case Intrinsic::mips_srli_d:
2233 case Intrinsic::mips_srlri_b:
2234 case Intrinsic::mips_srlri_h:
2235 case Intrinsic::mips_srlri_w:
2236 case Intrinsic::mips_srlri_d: {
2239 switch (Intrinsic) {
2240 case Intrinsic::mips_srlri_b:
Max = 7;
break;
2241 case Intrinsic::mips_srlri_h:
Max = 15;
break;
2242 case Intrinsic::mips_srlri_w:
Max = 31;
break;
2243 case Intrinsic::mips_srlri_d:
Max = 63;
break;
2246 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2247 if (Value < 0 || Value > Max)
2251 case Intrinsic::mips_subv_b:
2252 case Intrinsic::mips_subv_h:
2253 case Intrinsic::mips_subv_w:
2254 case Intrinsic::mips_subv_d:
2257 case Intrinsic::mips_subvi_b:
2258 case Intrinsic::mips_subvi_h:
2259 case Intrinsic::mips_subvi_w:
2260 case Intrinsic::mips_subvi_d:
2263 case Intrinsic::mips_vshf_b:
2264 case Intrinsic::mips_vshf_h:
2265 case Intrinsic::mips_vshf_w:
2266 case Intrinsic::mips_vshf_d:
2268 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
2269 case Intrinsic::mips_xor_v:
2272 case Intrinsic::mips_xori_b:
2275 case Intrinsic::thread_pointer: {
2288 EVT ResTy =
Op->getValueType(0);
2304 unsigned Intr = cast<ConstantSDNode>(
Op->getOperand(1))->getZExtValue();
2308 case Intrinsic::mips_extp:
2310 case Intrinsic::mips_extpdp:
2312 case Intrinsic::mips_extr_w:
2314 case Intrinsic::mips_extr_r_w:
2316 case Intrinsic::mips_extr_rs_w:
2318 case Intrinsic::mips_extr_s_h:
2320 case Intrinsic::mips_mthlip:
2322 case Intrinsic::mips_mulsaq_s_w_ph:
2324 case Intrinsic::mips_maq_s_w_phl:
2326 case Intrinsic::mips_maq_s_w_phr:
2328 case Intrinsic::mips_maq_sa_w_phl:
2330 case Intrinsic::mips_maq_sa_w_phr:
2332 case Intrinsic::mips_dpaq_s_w_ph:
2334 case Intrinsic::mips_dpsq_s_w_ph:
2336 case Intrinsic::mips_dpaq_sa_l_w:
2338 case Intrinsic::mips_dpsq_sa_l_w:
2340 case Intrinsic::mips_dpaqx_s_w_ph:
2342 case Intrinsic::mips_dpaqx_sa_w_ph:
2344 case Intrinsic::mips_dpsqx_s_w_ph:
2346 case Intrinsic::mips_dpsqx_sa_w_ph:
2348 case Intrinsic::mips_ld_b:
2349 case Intrinsic::mips_ld_h:
2350 case Intrinsic::mips_ld_w:
2351 case Intrinsic::mips_ld_d:
2379 unsigned Intr = cast<ConstantSDNode>(
Op->getOperand(1))->getZExtValue();
2383 case Intrinsic::mips_st_b:
2384 case Intrinsic::mips_st_h:
2385 case Intrinsic::mips_st_w:
2386 case Intrinsic::mips_st_d:
2401 EVT ResTy =
Op->getValueType(0);
2421 if (isa<ConstantSDNode>(
Op))
2423 if (isa<ConstantFPSDNode>(
Op))
2451 EVT ResTy =
Op->getValueType(0);
2453 APInt SplatValue, SplatUndef;
2454 unsigned SplatBitSize;
2460 if (
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2464 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2476 switch (SplatBitSize) {
2480 ViaVecTy = MVT::v16i8;
2483 ViaVecTy = MVT::v8i16;
2486 ViaVecTy = MVT::v4i32;
2497 if (ViaVecTy != ResTy)
2507 EVT ResTy =
Node->getValueType(0);
2513 for (
unsigned i = 0; i < NumElts; ++i) {
2515 Node->getOperand(i),
2545 int SHFIndices[4] = { -1, -1, -1, -1 };
2547 if (Indices.
size() < 4)
2550 for (
unsigned i = 0; i < 4; ++i) {
2551 for (
unsigned j = i; j < Indices.
size(); j += 4) {
2552 int Idx = Indices[j];
2558 if (Idx < 0 || Idx >= 4)
2564 if (SHFIndices[i] == -1)
2565 SHFIndices[i] =
Idx;
2569 if (!(
Idx == -1 ||
Idx == SHFIndices[i]))
2576 for (
int i = 3; i >= 0; --i) {
2577 int Idx = SHFIndices[i];
2594template <
typename ValType>
2597 unsigned CheckStride,
2599 ValType ExpectedIndex,
unsigned ExpectedIndexStride) {
2603 if (*
I != -1 && *
I != ExpectedIndex)
2605 ExpectedIndex += ExpectedIndexStride;
2609 for (
unsigned n = 0; n < CheckStride &&
I !=
End; ++n, ++
I)
2628 int SplatIndex = -1;
2629 for (
const auto &V : Indices) {
2636 return fitsRegularPattern<int>(Indices.
begin(), 1, Indices.
end(), SplatIndex,
2662 const auto &Begin = Indices.
begin();
2663 const auto &
End = Indices.
end();
2667 if (fitsRegularPattern<int>(Begin, 2,
End, 0, 2))
2668 Wt =
Op->getOperand(0);
2669 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size(), 2))
2670 Wt =
Op->getOperand(1);
2676 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 0, 2))
2677 Ws =
Op->getOperand(0);
2678 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size(), 2))
2679 Ws =
Op->getOperand(1);
2708 const auto &Begin = Indices.
begin();
2709 const auto &
End = Indices.
end();
2713 if (fitsRegularPattern<int>(Begin, 2,
End, 1, 2))
2714 Wt =
Op->getOperand(0);
2715 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size() + 1, 2))
2716 Wt =
Op->getOperand(1);
2722 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 1, 2))
2723 Ws =
Op->getOperand(0);
2724 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size() + 1, 2))
2725 Ws =
Op->getOperand(1);
2755 const auto &Begin = Indices.
begin();
2756 const auto &
End = Indices.
end();
2760 if (fitsRegularPattern<int>(Begin, 2,
End, 0, 1))
2761 Wt =
Op->getOperand(0);
2762 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size(), 1))
2763 Wt =
Op->getOperand(1);
2769 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 0, 1))
2770 Ws =
Op->getOperand(0);
2771 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size(), 1))
2772 Ws =
Op->getOperand(1);
2800 unsigned HalfSize = Indices.
size() / 2;
2803 const auto &Begin = Indices.
begin();
2804 const auto &
End = Indices.
end();
2808 if (fitsRegularPattern<int>(Begin, 2,
End, HalfSize, 1))
2809 Wt =
Op->getOperand(0);
2810 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size() + HalfSize, 1))
2811 Wt =
Op->getOperand(1);
2817 if (fitsRegularPattern<int>(Begin + 1, 2,
End, HalfSize, 1))
2818 Ws =
Op->getOperand(0);
2819 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size() + HalfSize,
2821 Ws =
Op->getOperand(1);
2850 const auto &Begin = Indices.
begin();
2851 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2852 const auto &
End = Indices.
end();
2854 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2855 Wt =
Op->getOperand(0);
2856 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size(), 2))
2857 Wt =
Op->getOperand(1);
2861 if (fitsRegularPattern<int>(Mid, 1,
End, 0, 2))
2862 Ws =
Op->getOperand(0);
2863 else if (fitsRegularPattern<int>(Mid, 1,
End, Indices.
size(), 2))
2864 Ws =
Op->getOperand(1);
2893 const auto &Begin = Indices.
begin();
2894 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2895 const auto &
End = Indices.
end();
2897 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2898 Wt =
Op->getOperand(0);
2899 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size() + 1, 2))
2900 Wt =
Op->getOperand(1);
2904 if (fitsRegularPattern<int>(Mid, 1,
End, 1, 2))
2905 Ws =
Op->getOperand(0);
2906 else if (fitsRegularPattern<int>(Mid, 1,
End, Indices.
size() + 1, 2))
2907 Ws =
Op->getOperand(1);
2930 bool Using1stVec =
false;
2931 bool Using2ndVec =
false;
2935 for (
int i = 0; i < ResTyNumElts; ++i) {
2937 int Idx = Indices[i];
2939 if (0 <=
Idx &&
Idx < ResTyNumElts)
2941 if (ResTyNumElts <=
Idx &&
Idx < ResTyNumElts * 2)
2945 for (
int Idx : Indices)
2950 if (Using1stVec && Using2ndVec) {
2951 Op0 =
Op->getOperand(0);
2952 Op1 =
Op->getOperand(1);
2953 }
else if (Using1stVec)
2954 Op0 = Op1 =
Op->getOperand(0);
2955 else if (Using2ndVec)
2956 Op0 = Op1 =
Op->getOperand(1);
2958 llvm_unreachable(
"shuffle vector mask references neither vector operand?");
2975 EVT ResTy =
Op->getValueType(0);
2983 for (
int i = 0; i < ResTyNumElts; ++i)
3036 F->insert(It, Sink);
3041 Sink->transferSuccessorsAndUpdatePHIs(BB);
3067 MI.getOperand(0).getReg())
3073 MI.eraseFromParent();
3105 F->insert(It, Sink);
3110 Sink->transferSuccessorsAndUpdatePHIs(BB);
3136 MI.getOperand(0).getReg())
3142 MI.eraseFromParent();
3164 unsigned Lane =
MI.getOperand(2).getImm();
3171 Wt =
RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3180 : &Mips::MSA128WEvensRegClass);
3186 MI.eraseFromParent();
3209 unsigned Lane =
MI.getOperand(2).getImm() * 2;
3221 MI.eraseFromParent();
3239 unsigned Lane =
MI.getOperand(2).getImm();
3243 : &Mips::MSA128WEvensRegClass);
3255 MI.eraseFromParent();
3275 unsigned Lane =
MI.getOperand(2).getImm();
3289 MI.eraseFromParent();
3320 Register SrcVecReg =
MI.getOperand(1).getReg();
3321 Register LaneReg =
MI.getOperand(2).getReg();
3322 Register SrcValReg =
MI.getOperand(3).getReg();
3330 unsigned EltLog2Size;
3331 unsigned InsertOp = 0;
3332 unsigned InsveOp = 0;
3333 switch (EltSizeInBytes) {
3338 InsertOp = Mips::INSERT_B;
3339 InsveOp = Mips::INSVE_B;
3340 VecRC = &Mips::MSA128BRegClass;
3344 InsertOp = Mips::INSERT_H;
3345 InsveOp = Mips::INSVE_H;
3346 VecRC = &Mips::MSA128HRegClass;
3350 InsertOp = Mips::INSERT_W;
3351 InsveOp = Mips::INSVE_W;
3352 VecRC = &Mips::MSA128WRegClass;
3356 InsertOp = Mips::INSERT_D;
3357 InsveOp = Mips::INSVE_D;
3358 VecRC = &Mips::MSA128DRegClass;
3367 .
addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3372 if (EltSizeInBytes != 1) {
3385 .
addReg(LaneReg, 0, SubRegIdx);
3414 .
addReg(LaneTmp2, 0, SubRegIdx);
3416 MI.eraseFromParent();
3437 : &Mips::MSA128WEvensRegClass);
3440 : &Mips::MSA128WEvensRegClass);
3449 MI.eraseFromParent();
3480 MI.eraseFromParent();
3511 MI.getOperand(1).isReg() ?
RegInfo.getRegClass(
MI.getOperand(1).getReg())
3513 : &Mips::GPR64RegClass);
3514 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3526 BuildMI(*BB,
MI,
DL,
TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3533 MI.eraseFromParent();
3563 MI.getOperand(1).isReg() ?
RegInfo.getRegClass(
MI.getOperand(1).getReg())
3565 : &Mips::GPR64RegClass);
3567 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3571 BuildMI(*BB,
MI,
DL,
TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3583 MI.eraseFromParent();
3639 bool IsFGR64)
const {
3655 Register Wtemp =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3657 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3658 unsigned MFC1Opc = IsFGR64onMips64
3660 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3661 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3667 unsigned WPHI = Wtemp;
3669 if (IsFGR64onMips32) {
3672 Register Wtemp2 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3673 Register Wtemp3 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3686 Register Wtemp2 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3695 MI.eraseFromParent();
3744 bool IsFGR64)
const {
3761 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3762 unsigned MTC1Opc = IsFGR64onMips64
3764 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3765 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3767 Register Wtemp =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3772 WPHI =
RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3779 ?
RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3784 if (IsFGR64onMips32) {
3794 MI.eraseFromParent();
3821 .
addReg(
MI.getOperand(1).getReg());
3823 MI.eraseFromParent();
3850 .
addReg(
MI.getOperand(1).getReg());
3852 MI.eraseFromParent();
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue performSETCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements a class to represent arbitrary precision integral constant values and operations...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue truncateVecElts(SDNode *Node, SelectionDAG &DAG)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, const SmallVector< int, 16 > &Indices, SelectionDAG &DAG)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isConstantOrUndef(const SDValue Op)
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
APInt trunc(unsigned width) const
Truncate to new width.
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool isNegative() const
Determine sign of this APInt.
unsigned logBase2() const
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM Basic Block Representation.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getInRegsParamsCount() const
uint64_t getZExtValue() const
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const Triple & getTargetTriple() const
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
uint64_t getSize() const
Return the size in bytes of the memory reference.
Flags
Flags values. These may be or'd together.
Flags getFlags() const
Return the raw flags of the source value,.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
unsigned getIncomingArgSize() const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool useSoftFloat() const