36#include "llvm/IR/IntrinsicsMips.h"
52#define DEBUG_TYPE "mips-isel"
59 cl::desc(
"Expand double precision loads and "
60 "stores to their single precision "
87 for (
const auto &VecTy : VecTys) {
307 if (VT == MVT::Untyped)
308 return Subtarget.
hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
352 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
383 if (Ty != MVT::v8f16) {
410 EVT ResTy =
Op->getValueType(0);
450 switch(
Op.getOpcode()) {
502 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
504 if (Log2IfPositive <= 0)
508 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
510 unsigned Log2 = Log2IfPositive;
513 Log2 == ExtendTySize) {
539 APInt SplatValue, SplatUndef;
540 unsigned SplatBitSize;
543 if (!
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
557 N =
N->getOperand(0);
564 APInt SplatValue, SplatUndef;
565 unsigned SplatBitSize;
570 if (BVN->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
582 return N->getOperand(1) == OfNode;
585 return N->getOperand(0) == OfNode;
602 EVT Ty =
N->getValueType(0);
615 bool IsLittleEndian = !Subtarget.
isLittle();
618 bool IsConstantMask =
false;
625 if (
isVSplat(Op0Op0, Mask, IsLittleEndian)) {
629 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
630 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
632 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
633 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
636 IsConstantMask =
true;
646 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
647 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
649 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
650 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
653 IsConstantMask =
true;
702 if (IsConstantMask) {
703 if (Mask.isAllOnes())
744 unsigned MaxSteps = Subtarget.
isABI_O32() ? 8 : 12;
750 while (!WorkStack.
empty()) {
753 if (Val == 0 || Val == 1)
756 if (Steps >= MaxSteps)
767 if ((Val - Floor).ule(Ceil - Val)) {
815 if ((
C - Floor).ule(Ceil -
C)) {
832 EVT VT =
N->getValueType(0);
836 C->getAPIntValue(), VT, DAG, Subtarget))
848 APInt SplatValue, SplatUndef;
849 unsigned SplatBitSize;
858 !BV->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
860 (SplatBitSize != EltSize) ||
865 return DAG.
getNode(Opc,
DL, Ty,
N->getOperand(0),
872 EVT Ty =
N->getValueType(0);
874 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
895 EVT Ty =
N->getValueType(0);
916 EVT ExtendTy = cast<VTSDNode>(Op0Op0->
getOperand(2))->getVT();
919 if (TotalBits == 32 ||
931 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.
hasDSPR2()))
941 EVT Ty =
N->getValueType(0);
943 if (((Ty != MVT::v2i16) || !Subtarget.
hasDSPR2()) && (Ty != MVT::v4i8))
950 bool IsV216 = (Ty == MVT::v2i16);
963 default:
return false;
968 EVT Ty =
N->getValueType(0);
970 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
977 N->getOperand(1),
N->getOperand(2));
981 EVT Ty =
N->getValueType(0);
983 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
991 N->getOperand(1),
N->getOperand(2), SetCC.
getOperand(2));
999 EVT Ty =
N->getValueType(0);
1029 switch (
N->getOpcode()) {
1057 N->printrWithDepth(
dbgs(), &DAG);
dbgs() <<
"\n=> \n";
1068 switch (
MI.getOpcode()) {
1071 case Mips::BPOSGE32_PSEUDO:
1072 return emitBPOSGE32(
MI, BB);
1073 case Mips::SNZ_B_PSEUDO:
1074 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_B);
1075 case Mips::SNZ_H_PSEUDO:
1076 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_H);
1077 case Mips::SNZ_W_PSEUDO:
1078 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_W);
1079 case Mips::SNZ_D_PSEUDO:
1080 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_D);
1081 case Mips::SNZ_V_PSEUDO:
1082 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_V);
1083 case Mips::SZ_B_PSEUDO:
1084 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_B);
1085 case Mips::SZ_H_PSEUDO:
1086 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_H);
1087 case Mips::SZ_W_PSEUDO:
1088 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_W);
1089 case Mips::SZ_D_PSEUDO:
1090 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_D);
1091 case Mips::SZ_V_PSEUDO:
1092 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_V);
1093 case Mips::COPY_FW_PSEUDO:
1094 return emitCOPY_FW(
MI, BB);
1095 case Mips::COPY_FD_PSEUDO:
1096 return emitCOPY_FD(
MI, BB);
1097 case Mips::INSERT_FW_PSEUDO:
1098 return emitINSERT_FW(
MI, BB);
1099 case Mips::INSERT_FD_PSEUDO:
1100 return emitINSERT_FD(
MI, BB);
1101 case Mips::INSERT_B_VIDX_PSEUDO:
1102 case Mips::INSERT_B_VIDX64_PSEUDO:
1103 return emitINSERT_DF_VIDX(
MI, BB, 1,
false);
1104 case Mips::INSERT_H_VIDX_PSEUDO:
1105 case Mips::INSERT_H_VIDX64_PSEUDO:
1106 return emitINSERT_DF_VIDX(
MI, BB, 2,
false);
1107 case Mips::INSERT_W_VIDX_PSEUDO:
1108 case Mips::INSERT_W_VIDX64_PSEUDO:
1109 return emitINSERT_DF_VIDX(
MI, BB, 4,
false);
1110 case Mips::INSERT_D_VIDX_PSEUDO:
1111 case Mips::INSERT_D_VIDX64_PSEUDO:
1112 return emitINSERT_DF_VIDX(
MI, BB, 8,
false);
1113 case Mips::INSERT_FW_VIDX_PSEUDO:
1114 case Mips::INSERT_FW_VIDX64_PSEUDO:
1115 return emitINSERT_DF_VIDX(
MI, BB, 4,
true);
1116 case Mips::INSERT_FD_VIDX_PSEUDO:
1117 case Mips::INSERT_FD_VIDX64_PSEUDO:
1118 return emitINSERT_DF_VIDX(
MI, BB, 8,
true);
1119 case Mips::FILL_FW_PSEUDO:
1120 return emitFILL_FW(
MI, BB);
1121 case Mips::FILL_FD_PSEUDO:
1122 return emitFILL_FD(
MI, BB);
1123 case Mips::FEXP2_W_1_PSEUDO:
1124 return emitFEXP2_W_1(
MI, BB);
1125 case Mips::FEXP2_D_1_PSEUDO:
1126 return emitFEXP2_D_1(
MI, BB);
1128 return emitST_F16_PSEUDO(
MI, BB);
1130 return emitLD_F16_PSEUDO(
MI, BB);
1131 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1132 return emitFPEXTEND_PSEUDO(
MI, BB,
false);
1133 case Mips::MSA_FP_ROUND_W_PSEUDO:
1134 return emitFPROUND_PSEUDO(
MI, BB,
false);
1135 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1136 return emitFPEXTEND_PSEUDO(
MI, BB,
true);
1137 case Mips::MSA_FP_ROUND_D_PSEUDO:
1138 return emitFPROUND_PSEUDO(
MI, BB,
true);
1142bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1143 const CCState &CCInfo,
unsigned NextStackOffset,
1161void MipsSETargetLowering::
1163 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1164 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
1165 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
1169 InternalLinkage, IsCallReloc, CLI, Callee,
1182 EVT PtrVT =
Ptr.getValueType();
1211 EVT PtrVT =
Ptr.getValueType();
1234 MVT Src =
Op.getOperand(0).getValueType().getSimpleVT();
1235 MVT Dest =
Op.getValueType().getSimpleVT();
1238 if (Src == MVT::i64 && Dest == MVT::f64) {
1246 if (Src == MVT::f64 && Dest == MVT::i64) {
1261 bool HasLo,
bool HasHi,
1266 EVT Ty =
Op.getOperand(0).getValueType();
1269 Op.getOperand(0),
Op.getOperand(1));
1277 if (!HasLo || !HasHi)
1278 return HasLo ?
Lo :
Hi;
1286 std::tie(InLo, InHi) = DAG.
SplitScalar(In,
DL, MVT::i32, MVT::i32);
1310 bool HasChainIn =
Op->getOperand(0).getValueType() == MVT::Other;
1322 SDValue Opnd =
Op->getOperand(++OpNo), In64;
1340 for (
EVT Ty :
Op->values())
1341 ResTys.
push_back((Ty == MVT::i64) ? MVT::Untyped : Ty);
1360 EVT ResTy =
Op->getValueType(0);
1370 EVT ResVecTy =
Op->getValueType(0);
1371 EVT ViaVecTy = ResVecTy;
1381 if (ResVecTy == MVT::v2i64) {
1384 if (isa<ConstantSDNode>(LaneA))
1392 ViaVecTy = MVT::v4i32;
1398 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1399 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1404 if (ViaVecTy != ResVecTy) {
1414 bool IsSigned =
false) {
1415 auto *CImm = cast<ConstantSDNode>(
Op->getOperand(ImmOp));
1417 APInt(
Op->getValueType(0).getScalarType().getSizeInBits(),
1418 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
1424 EVT ViaVecTy = VecTy;
1425 SDValue SplatValueA = SplatValue;
1426 SDValue SplatValueB = SplatValue;
1429 if (VecTy == MVT::v2i64) {
1431 ViaVecTy = MVT::v4i32;
1444 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1445 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1446 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1447 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1452 if (VecTy != ViaVecTy)
1461 EVT VecTy =
Op->getValueType(0);
1467 if (VecTy == MVT::v2i64) {
1469 APInt BitImm =
APInt(64, 1) << CImm->getAPIntValue();
1481 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1490 if (VecTy == MVT::v2i64)
1499 return DAG.
getNode(Opc,
DL, VecTy,
Op->getOperand(1), Exp2Imm);
1504 EVT ResTy =
Op->getValueType(0);
1507 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1516 EVT ResTy =
Op->getValueType(0);
1527 EVT ResTy =
Op->getValueType(0);
1529 <<
Op->getConstantOperandAPInt(2);
1538 unsigned Intrinsic =
Op->getConstantOperandVal(0);
1539 switch (Intrinsic) {
1542 case Intrinsic::mips_shilo:
1544 case Intrinsic::mips_dpau_h_qbl:
1546 case Intrinsic::mips_dpau_h_qbr:
1548 case Intrinsic::mips_dpsu_h_qbl:
1550 case Intrinsic::mips_dpsu_h_qbr:
1552 case Intrinsic::mips_dpa_w_ph:
1554 case Intrinsic::mips_dps_w_ph:
1556 case Intrinsic::mips_dpax_w_ph:
1558 case Intrinsic::mips_dpsx_w_ph:
1560 case Intrinsic::mips_mulsa_w_ph:
1562 case Intrinsic::mips_mult:
1564 case Intrinsic::mips_multu:
1566 case Intrinsic::mips_madd:
1568 case Intrinsic::mips_maddu:
1570 case Intrinsic::mips_msub:
1572 case Intrinsic::mips_msubu:
1574 case Intrinsic::mips_addv_b:
1575 case Intrinsic::mips_addv_h:
1576 case Intrinsic::mips_addv_w:
1577 case Intrinsic::mips_addv_d:
1580 case Intrinsic::mips_addvi_b:
1581 case Intrinsic::mips_addvi_h:
1582 case Intrinsic::mips_addvi_w:
1583 case Intrinsic::mips_addvi_d:
1586 case Intrinsic::mips_and_v:
1589 case Intrinsic::mips_andi_b:
1592 case Intrinsic::mips_bclr_b:
1593 case Intrinsic::mips_bclr_h:
1594 case Intrinsic::mips_bclr_w:
1595 case Intrinsic::mips_bclr_d:
1597 case Intrinsic::mips_bclri_b:
1598 case Intrinsic::mips_bclri_h:
1599 case Intrinsic::mips_bclri_w:
1600 case Intrinsic::mips_bclri_d:
1602 case Intrinsic::mips_binsli_b:
1603 case Intrinsic::mips_binsli_h:
1604 case Intrinsic::mips_binsli_w:
1605 case Intrinsic::mips_binsli_d: {
1607 EVT VecTy =
Op->getValueType(0);
1612 Op->getConstantOperandVal(3) + 1);
1615 Op->getOperand(2),
Op->getOperand(1));
1617 case Intrinsic::mips_binsri_b:
1618 case Intrinsic::mips_binsri_h:
1619 case Intrinsic::mips_binsri_w:
1620 case Intrinsic::mips_binsri_d: {
1622 EVT VecTy =
Op->getValueType(0);
1627 Op->getConstantOperandVal(3) + 1);
1630 Op->getOperand(2),
Op->getOperand(1));
1632 case Intrinsic::mips_bmnz_v:
1634 Op->getOperand(2),
Op->getOperand(1));
1635 case Intrinsic::mips_bmnzi_b:
1639 case Intrinsic::mips_bmz_v:
1641 Op->getOperand(1),
Op->getOperand(2));
1642 case Intrinsic::mips_bmzi_b:
1646 case Intrinsic::mips_bneg_b:
1647 case Intrinsic::mips_bneg_h:
1648 case Intrinsic::mips_bneg_w:
1649 case Intrinsic::mips_bneg_d: {
1650 EVT VecTy =
Op->getValueType(0);
1657 case Intrinsic::mips_bnegi_b:
1658 case Intrinsic::mips_bnegi_h:
1659 case Intrinsic::mips_bnegi_w:
1660 case Intrinsic::mips_bnegi_d:
1663 case Intrinsic::mips_bnz_b:
1664 case Intrinsic::mips_bnz_h:
1665 case Intrinsic::mips_bnz_w:
1666 case Intrinsic::mips_bnz_d:
1669 case Intrinsic::mips_bnz_v:
1672 case Intrinsic::mips_bsel_v:
1675 Op->getOperand(1),
Op->getOperand(3),
1677 case Intrinsic::mips_bseli_b:
1682 case Intrinsic::mips_bset_b:
1683 case Intrinsic::mips_bset_h:
1684 case Intrinsic::mips_bset_w:
1685 case Intrinsic::mips_bset_d: {
1686 EVT VecTy =
Op->getValueType(0);
1693 case Intrinsic::mips_bseti_b:
1694 case Intrinsic::mips_bseti_h:
1695 case Intrinsic::mips_bseti_w:
1696 case Intrinsic::mips_bseti_d:
1699 case Intrinsic::mips_bz_b:
1700 case Intrinsic::mips_bz_h:
1701 case Intrinsic::mips_bz_w:
1702 case Intrinsic::mips_bz_d:
1705 case Intrinsic::mips_bz_v:
1708 case Intrinsic::mips_ceq_b:
1709 case Intrinsic::mips_ceq_h:
1710 case Intrinsic::mips_ceq_w:
1711 case Intrinsic::mips_ceq_d:
1714 case Intrinsic::mips_ceqi_b:
1715 case Intrinsic::mips_ceqi_h:
1716 case Intrinsic::mips_ceqi_w:
1717 case Intrinsic::mips_ceqi_d:
1720 case Intrinsic::mips_cle_s_b:
1721 case Intrinsic::mips_cle_s_h:
1722 case Intrinsic::mips_cle_s_w:
1723 case Intrinsic::mips_cle_s_d:
1726 case Intrinsic::mips_clei_s_b:
1727 case Intrinsic::mips_clei_s_h:
1728 case Intrinsic::mips_clei_s_w:
1729 case Intrinsic::mips_clei_s_d:
1732 case Intrinsic::mips_cle_u_b:
1733 case Intrinsic::mips_cle_u_h:
1734 case Intrinsic::mips_cle_u_w:
1735 case Intrinsic::mips_cle_u_d:
1738 case Intrinsic::mips_clei_u_b:
1739 case Intrinsic::mips_clei_u_h:
1740 case Intrinsic::mips_clei_u_w:
1741 case Intrinsic::mips_clei_u_d:
1744 case Intrinsic::mips_clt_s_b:
1745 case Intrinsic::mips_clt_s_h:
1746 case Intrinsic::mips_clt_s_w:
1747 case Intrinsic::mips_clt_s_d:
1750 case Intrinsic::mips_clti_s_b:
1751 case Intrinsic::mips_clti_s_h:
1752 case Intrinsic::mips_clti_s_w:
1753 case Intrinsic::mips_clti_s_d:
1756 case Intrinsic::mips_clt_u_b:
1757 case Intrinsic::mips_clt_u_h:
1758 case Intrinsic::mips_clt_u_w:
1759 case Intrinsic::mips_clt_u_d:
1762 case Intrinsic::mips_clti_u_b:
1763 case Intrinsic::mips_clti_u_h:
1764 case Intrinsic::mips_clti_u_w:
1765 case Intrinsic::mips_clti_u_d:
1768 case Intrinsic::mips_copy_s_b:
1769 case Intrinsic::mips_copy_s_h:
1770 case Intrinsic::mips_copy_s_w:
1772 case Intrinsic::mips_copy_s_d:
1780 Op->getValueType(0),
Op->getOperand(1),
1783 case Intrinsic::mips_copy_u_b:
1784 case Intrinsic::mips_copy_u_h:
1785 case Intrinsic::mips_copy_u_w:
1787 case Intrinsic::mips_copy_u_d:
1798 Op->getValueType(0),
Op->getOperand(1),
1801 case Intrinsic::mips_div_s_b:
1802 case Intrinsic::mips_div_s_h:
1803 case Intrinsic::mips_div_s_w:
1804 case Intrinsic::mips_div_s_d:
1807 case Intrinsic::mips_div_u_b:
1808 case Intrinsic::mips_div_u_h:
1809 case Intrinsic::mips_div_u_w:
1810 case Intrinsic::mips_div_u_d:
1813 case Intrinsic::mips_fadd_w:
1814 case Intrinsic::mips_fadd_d:
1819 case Intrinsic::mips_fceq_w:
1820 case Intrinsic::mips_fceq_d:
1823 case Intrinsic::mips_fcle_w:
1824 case Intrinsic::mips_fcle_d:
1827 case Intrinsic::mips_fclt_w:
1828 case Intrinsic::mips_fclt_d:
1831 case Intrinsic::mips_fcne_w:
1832 case Intrinsic::mips_fcne_d:
1835 case Intrinsic::mips_fcor_w:
1836 case Intrinsic::mips_fcor_d:
1839 case Intrinsic::mips_fcueq_w:
1840 case Intrinsic::mips_fcueq_d:
1843 case Intrinsic::mips_fcule_w:
1844 case Intrinsic::mips_fcule_d:
1847 case Intrinsic::mips_fcult_w:
1848 case Intrinsic::mips_fcult_d:
1851 case Intrinsic::mips_fcun_w:
1852 case Intrinsic::mips_fcun_d:
1855 case Intrinsic::mips_fcune_w:
1856 case Intrinsic::mips_fcune_d:
1859 case Intrinsic::mips_fdiv_w:
1860 case Intrinsic::mips_fdiv_d:
1864 case Intrinsic::mips_ffint_u_w:
1865 case Intrinsic::mips_ffint_u_d:
1868 case Intrinsic::mips_ffint_s_w:
1869 case Intrinsic::mips_ffint_s_d:
1872 case Intrinsic::mips_fill_b:
1873 case Intrinsic::mips_fill_h:
1874 case Intrinsic::mips_fill_w:
1875 case Intrinsic::mips_fill_d: {
1876 EVT ResTy =
Op->getValueType(0);
1884 case Intrinsic::mips_fexp2_w:
1885 case Intrinsic::mips_fexp2_d: {
1887 EVT ResTy =
Op->getValueType(0);
1892 case Intrinsic::mips_flog2_w:
1893 case Intrinsic::mips_flog2_d:
1895 case Intrinsic::mips_fmadd_w:
1896 case Intrinsic::mips_fmadd_d:
1898 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
1899 case Intrinsic::mips_fmul_w:
1900 case Intrinsic::mips_fmul_d:
1904 case Intrinsic::mips_fmsub_w:
1905 case Intrinsic::mips_fmsub_d: {
1908 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
1910 case Intrinsic::mips_frint_w:
1911 case Intrinsic::mips_frint_d:
1913 case Intrinsic::mips_fsqrt_w:
1914 case Intrinsic::mips_fsqrt_d:
1916 case Intrinsic::mips_fsub_w:
1917 case Intrinsic::mips_fsub_d:
1921 case Intrinsic::mips_ftrunc_u_w:
1922 case Intrinsic::mips_ftrunc_u_d:
1925 case Intrinsic::mips_ftrunc_s_w:
1926 case Intrinsic::mips_ftrunc_s_d:
1929 case Intrinsic::mips_ilvev_b:
1930 case Intrinsic::mips_ilvev_h:
1931 case Intrinsic::mips_ilvev_w:
1932 case Intrinsic::mips_ilvev_d:
1934 Op->getOperand(1),
Op->getOperand(2));
1935 case Intrinsic::mips_ilvl_b:
1936 case Intrinsic::mips_ilvl_h:
1937 case Intrinsic::mips_ilvl_w:
1938 case Intrinsic::mips_ilvl_d:
1940 Op->getOperand(1),
Op->getOperand(2));
1941 case Intrinsic::mips_ilvod_b:
1942 case Intrinsic::mips_ilvod_h:
1943 case Intrinsic::mips_ilvod_w:
1944 case Intrinsic::mips_ilvod_d:
1946 Op->getOperand(1),
Op->getOperand(2));
1947 case Intrinsic::mips_ilvr_b:
1948 case Intrinsic::mips_ilvr_h:
1949 case Intrinsic::mips_ilvr_w:
1950 case Intrinsic::mips_ilvr_d:
1952 Op->getOperand(1),
Op->getOperand(2));
1953 case Intrinsic::mips_insert_b:
1954 case Intrinsic::mips_insert_h:
1955 case Intrinsic::mips_insert_w:
1956 case Intrinsic::mips_insert_d:
1958 Op->getOperand(1),
Op->getOperand(3),
Op->getOperand(2));
1959 case Intrinsic::mips_insve_b:
1960 case Intrinsic::mips_insve_h:
1961 case Intrinsic::mips_insve_w:
1962 case Intrinsic::mips_insve_d: {
1965 switch (Intrinsic) {
1966 case Intrinsic::mips_insve_b:
Max = 15;
break;
1967 case Intrinsic::mips_insve_h:
Max = 7;
break;
1968 case Intrinsic::mips_insve_w:
Max = 3;
break;
1969 case Intrinsic::mips_insve_d:
Max = 1;
break;
1972 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
1973 if (Value < 0 || Value > Max)
1976 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3),
1979 case Intrinsic::mips_ldi_b:
1980 case Intrinsic::mips_ldi_h:
1981 case Intrinsic::mips_ldi_w:
1982 case Intrinsic::mips_ldi_d:
1984 case Intrinsic::mips_lsa:
1985 case Intrinsic::mips_dlsa: {
1986 EVT ResTy =
Op->getValueType(0);
1989 Op->getOperand(2),
Op->getOperand(3)));
1991 case Intrinsic::mips_maddv_b:
1992 case Intrinsic::mips_maddv_h:
1993 case Intrinsic::mips_maddv_w:
1994 case Intrinsic::mips_maddv_d: {
1995 EVT ResTy =
Op->getValueType(0);
1998 Op->getOperand(2),
Op->getOperand(3)));
2000 case Intrinsic::mips_max_s_b:
2001 case Intrinsic::mips_max_s_h:
2002 case Intrinsic::mips_max_s_w:
2003 case Intrinsic::mips_max_s_d:
2005 Op->getOperand(1),
Op->getOperand(2));
2006 case Intrinsic::mips_max_u_b:
2007 case Intrinsic::mips_max_u_h:
2008 case Intrinsic::mips_max_u_w:
2009 case Intrinsic::mips_max_u_d:
2011 Op->getOperand(1),
Op->getOperand(2));
2012 case Intrinsic::mips_maxi_s_b:
2013 case Intrinsic::mips_maxi_s_h:
2014 case Intrinsic::mips_maxi_s_w:
2015 case Intrinsic::mips_maxi_s_d:
2018 case Intrinsic::mips_maxi_u_b:
2019 case Intrinsic::mips_maxi_u_h:
2020 case Intrinsic::mips_maxi_u_w:
2021 case Intrinsic::mips_maxi_u_d:
2024 case Intrinsic::mips_min_s_b:
2025 case Intrinsic::mips_min_s_h:
2026 case Intrinsic::mips_min_s_w:
2027 case Intrinsic::mips_min_s_d:
2029 Op->getOperand(1),
Op->getOperand(2));
2030 case Intrinsic::mips_min_u_b:
2031 case Intrinsic::mips_min_u_h:
2032 case Intrinsic::mips_min_u_w:
2033 case Intrinsic::mips_min_u_d:
2035 Op->getOperand(1),
Op->getOperand(2));
2036 case Intrinsic::mips_mini_s_b:
2037 case Intrinsic::mips_mini_s_h:
2038 case Intrinsic::mips_mini_s_w:
2039 case Intrinsic::mips_mini_s_d:
2042 case Intrinsic::mips_mini_u_b:
2043 case Intrinsic::mips_mini_u_h:
2044 case Intrinsic::mips_mini_u_w:
2045 case Intrinsic::mips_mini_u_d:
2048 case Intrinsic::mips_mod_s_b:
2049 case Intrinsic::mips_mod_s_h:
2050 case Intrinsic::mips_mod_s_w:
2051 case Intrinsic::mips_mod_s_d:
2054 case Intrinsic::mips_mod_u_b:
2055 case Intrinsic::mips_mod_u_h:
2056 case Intrinsic::mips_mod_u_w:
2057 case Intrinsic::mips_mod_u_d:
2060 case Intrinsic::mips_mulv_b:
2061 case Intrinsic::mips_mulv_h:
2062 case Intrinsic::mips_mulv_w:
2063 case Intrinsic::mips_mulv_d:
2066 case Intrinsic::mips_msubv_b:
2067 case Intrinsic::mips_msubv_h:
2068 case Intrinsic::mips_msubv_w:
2069 case Intrinsic::mips_msubv_d: {
2070 EVT ResTy =
Op->getValueType(0);
2073 Op->getOperand(2),
Op->getOperand(3)));
2075 case Intrinsic::mips_nlzc_b:
2076 case Intrinsic::mips_nlzc_h:
2077 case Intrinsic::mips_nlzc_w:
2078 case Intrinsic::mips_nlzc_d:
2080 case Intrinsic::mips_nor_v: {
2082 Op->getOperand(1),
Op->getOperand(2));
2085 case Intrinsic::mips_nori_b: {
2091 case Intrinsic::mips_or_v:
2094 case Intrinsic::mips_ori_b:
2097 case Intrinsic::mips_pckev_b:
2098 case Intrinsic::mips_pckev_h:
2099 case Intrinsic::mips_pckev_w:
2100 case Intrinsic::mips_pckev_d:
2102 Op->getOperand(1),
Op->getOperand(2));
2103 case Intrinsic::mips_pckod_b:
2104 case Intrinsic::mips_pckod_h:
2105 case Intrinsic::mips_pckod_w:
2106 case Intrinsic::mips_pckod_d:
2108 Op->getOperand(1),
Op->getOperand(2));
2109 case Intrinsic::mips_pcnt_b:
2110 case Intrinsic::mips_pcnt_h:
2111 case Intrinsic::mips_pcnt_w:
2112 case Intrinsic::mips_pcnt_d:
2114 case Intrinsic::mips_sat_s_b:
2115 case Intrinsic::mips_sat_s_h:
2116 case Intrinsic::mips_sat_s_w:
2117 case Intrinsic::mips_sat_s_d:
2118 case Intrinsic::mips_sat_u_b:
2119 case Intrinsic::mips_sat_u_h:
2120 case Intrinsic::mips_sat_u_w:
2121 case Intrinsic::mips_sat_u_d: {
2124 switch (Intrinsic) {
2125 case Intrinsic::mips_sat_s_b:
2126 case Intrinsic::mips_sat_u_b:
Max = 7;
break;
2127 case Intrinsic::mips_sat_s_h:
2128 case Intrinsic::mips_sat_u_h:
Max = 15;
break;
2129 case Intrinsic::mips_sat_s_w:
2130 case Intrinsic::mips_sat_u_w:
Max = 31;
break;
2131 case Intrinsic::mips_sat_s_d:
2132 case Intrinsic::mips_sat_u_d:
Max = 63;
break;
2135 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2136 if (Value < 0 || Value > Max)
2140 case Intrinsic::mips_shf_b:
2141 case Intrinsic::mips_shf_h:
2142 case Intrinsic::mips_shf_w: {
2143 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2144 if (Value < 0 || Value > 255)
2147 Op->getOperand(2),
Op->getOperand(1));
2149 case Intrinsic::mips_sldi_b:
2150 case Intrinsic::mips_sldi_h:
2151 case Intrinsic::mips_sldi_w:
2152 case Intrinsic::mips_sldi_d: {
2155 switch (Intrinsic) {
2156 case Intrinsic::mips_sldi_b:
Max = 15;
break;
2157 case Intrinsic::mips_sldi_h:
Max = 7;
break;
2158 case Intrinsic::mips_sldi_w:
Max = 3;
break;
2159 case Intrinsic::mips_sldi_d:
Max = 1;
break;
2162 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(3))->getSExtValue();
2163 if (Value < 0 || Value > Max)
2167 case Intrinsic::mips_sll_b:
2168 case Intrinsic::mips_sll_h:
2169 case Intrinsic::mips_sll_w:
2170 case Intrinsic::mips_sll_d:
2173 case Intrinsic::mips_slli_b:
2174 case Intrinsic::mips_slli_h:
2175 case Intrinsic::mips_slli_w:
2176 case Intrinsic::mips_slli_d:
2179 case Intrinsic::mips_splat_b:
2180 case Intrinsic::mips_splat_h:
2181 case Intrinsic::mips_splat_w:
2182 case Intrinsic::mips_splat_d:
2190 case Intrinsic::mips_splati_b:
2191 case Intrinsic::mips_splati_h:
2192 case Intrinsic::mips_splati_w:
2193 case Intrinsic::mips_splati_d:
2197 case Intrinsic::mips_sra_b:
2198 case Intrinsic::mips_sra_h:
2199 case Intrinsic::mips_sra_w:
2200 case Intrinsic::mips_sra_d:
2203 case Intrinsic::mips_srai_b:
2204 case Intrinsic::mips_srai_h:
2205 case Intrinsic::mips_srai_w:
2206 case Intrinsic::mips_srai_d:
2209 case Intrinsic::mips_srari_b:
2210 case Intrinsic::mips_srari_h:
2211 case Intrinsic::mips_srari_w:
2212 case Intrinsic::mips_srari_d: {
2215 switch (Intrinsic) {
2216 case Intrinsic::mips_srari_b:
Max = 7;
break;
2217 case Intrinsic::mips_srari_h:
Max = 15;
break;
2218 case Intrinsic::mips_srari_w:
Max = 31;
break;
2219 case Intrinsic::mips_srari_d:
Max = 63;
break;
2222 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2223 if (Value < 0 || Value > Max)
2227 case Intrinsic::mips_srl_b:
2228 case Intrinsic::mips_srl_h:
2229 case Intrinsic::mips_srl_w:
2230 case Intrinsic::mips_srl_d:
2233 case Intrinsic::mips_srli_b:
2234 case Intrinsic::mips_srli_h:
2235 case Intrinsic::mips_srli_w:
2236 case Intrinsic::mips_srli_d:
2239 case Intrinsic::mips_srlri_b:
2240 case Intrinsic::mips_srlri_h:
2241 case Intrinsic::mips_srlri_w:
2242 case Intrinsic::mips_srlri_d: {
2245 switch (Intrinsic) {
2246 case Intrinsic::mips_srlri_b:
Max = 7;
break;
2247 case Intrinsic::mips_srlri_h:
Max = 15;
break;
2248 case Intrinsic::mips_srlri_w:
Max = 31;
break;
2249 case Intrinsic::mips_srlri_d:
Max = 63;
break;
2252 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2253 if (Value < 0 || Value > Max)
2257 case Intrinsic::mips_subv_b:
2258 case Intrinsic::mips_subv_h:
2259 case Intrinsic::mips_subv_w:
2260 case Intrinsic::mips_subv_d:
2263 case Intrinsic::mips_subvi_b:
2264 case Intrinsic::mips_subvi_h:
2265 case Intrinsic::mips_subvi_w:
2266 case Intrinsic::mips_subvi_d:
2269 case Intrinsic::mips_vshf_b:
2270 case Intrinsic::mips_vshf_h:
2271 case Intrinsic::mips_vshf_w:
2272 case Intrinsic::mips_vshf_d:
2274 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
2275 case Intrinsic::mips_xor_v:
2278 case Intrinsic::mips_xori_b:
2281 case Intrinsic::thread_pointer: {
2294 EVT ResTy =
Op->getValueType(0);
2310 unsigned Intr =
Op->getConstantOperandVal(1);
2314 case Intrinsic::mips_extp:
2316 case Intrinsic::mips_extpdp:
2318 case Intrinsic::mips_extr_w:
2320 case Intrinsic::mips_extr_r_w:
2322 case Intrinsic::mips_extr_rs_w:
2324 case Intrinsic::mips_extr_s_h:
2326 case Intrinsic::mips_mthlip:
2328 case Intrinsic::mips_mulsaq_s_w_ph:
2330 case Intrinsic::mips_maq_s_w_phl:
2332 case Intrinsic::mips_maq_s_w_phr:
2334 case Intrinsic::mips_maq_sa_w_phl:
2336 case Intrinsic::mips_maq_sa_w_phr:
2338 case Intrinsic::mips_dpaq_s_w_ph:
2340 case Intrinsic::mips_dpsq_s_w_ph:
2342 case Intrinsic::mips_dpaq_sa_l_w:
2344 case Intrinsic::mips_dpsq_sa_l_w:
2346 case Intrinsic::mips_dpaqx_s_w_ph:
2348 case Intrinsic::mips_dpaqx_sa_w_ph:
2350 case Intrinsic::mips_dpsqx_s_w_ph:
2352 case Intrinsic::mips_dpsqx_sa_w_ph:
2354 case Intrinsic::mips_ld_b:
2355 case Intrinsic::mips_ld_h:
2356 case Intrinsic::mips_ld_w:
2357 case Intrinsic::mips_ld_d:
2385 unsigned Intr =
Op->getConstantOperandVal(1);
2389 case Intrinsic::mips_st_b:
2390 case Intrinsic::mips_st_h:
2391 case Intrinsic::mips_st_w:
2392 case Intrinsic::mips_st_d:
2407 EVT ResTy =
Op->getValueType(0);
2427 if (isa<ConstantSDNode>(
Op))
2429 if (isa<ConstantFPSDNode>(
Op))
2457 EVT ResTy =
Op->getValueType(0);
2459 APInt SplatValue, SplatUndef;
2460 unsigned SplatBitSize;
2466 if (
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2470 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2482 switch (SplatBitSize) {
2486 ViaVecTy = MVT::v16i8;
2489 ViaVecTy = MVT::v8i16;
2492 ViaVecTy = MVT::v4i32;
2503 if (ViaVecTy != ResTy)
2513 EVT ResTy =
Node->getValueType(0);
2519 for (
unsigned i = 0; i < NumElts; ++i) {
2521 Node->getOperand(i),
2551 int SHFIndices[4] = { -1, -1, -1, -1 };
2553 if (Indices.
size() < 4)
2556 for (
unsigned i = 0; i < 4; ++i) {
2557 for (
unsigned j = i; j < Indices.
size(); j += 4) {
2558 int Idx = Indices[j];
2564 if (Idx < 0 || Idx >= 4)
2570 if (SHFIndices[i] == -1)
2571 SHFIndices[i] =
Idx;
2575 if (!(
Idx == -1 ||
Idx == SHFIndices[i]))
2582 for (
int i = 3; i >= 0; --i) {
2583 int Idx = SHFIndices[i];
2600template <
typename ValType>
2603 unsigned CheckStride,
2605 ValType ExpectedIndex,
unsigned ExpectedIndexStride) {
2609 if (*
I != -1 && *
I != ExpectedIndex)
2611 ExpectedIndex += ExpectedIndexStride;
2615 for (
unsigned n = 0; n < CheckStride &&
I !=
End; ++n, ++
I)
2634 int SplatIndex = -1;
2635 for (
const auto &V : Indices) {
2642 return fitsRegularPattern<int>(Indices.
begin(), 1, Indices.
end(), SplatIndex,
2668 const auto &Begin = Indices.
begin();
2669 const auto &
End = Indices.
end();
2673 if (fitsRegularPattern<int>(Begin, 2,
End, 0, 2))
2674 Wt =
Op->getOperand(0);
2675 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size(), 2))
2676 Wt =
Op->getOperand(1);
2682 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 0, 2))
2683 Ws =
Op->getOperand(0);
2684 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size(), 2))
2685 Ws =
Op->getOperand(1);
2714 const auto &Begin = Indices.
begin();
2715 const auto &
End = Indices.
end();
2719 if (fitsRegularPattern<int>(Begin, 2,
End, 1, 2))
2720 Wt =
Op->getOperand(0);
2721 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size() + 1, 2))
2722 Wt =
Op->getOperand(1);
2728 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 1, 2))
2729 Ws =
Op->getOperand(0);
2730 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size() + 1, 2))
2731 Ws =
Op->getOperand(1);
2761 const auto &Begin = Indices.
begin();
2762 const auto &
End = Indices.
end();
2766 if (fitsRegularPattern<int>(Begin, 2,
End, 0, 1))
2767 Wt =
Op->getOperand(0);
2768 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size(), 1))
2769 Wt =
Op->getOperand(1);
2775 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 0, 1))
2776 Ws =
Op->getOperand(0);
2777 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size(), 1))
2778 Ws =
Op->getOperand(1);
2806 unsigned HalfSize = Indices.
size() / 2;
2809 const auto &Begin = Indices.
begin();
2810 const auto &
End = Indices.
end();
2814 if (fitsRegularPattern<int>(Begin, 2,
End, HalfSize, 1))
2815 Wt =
Op->getOperand(0);
2816 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size() + HalfSize, 1))
2817 Wt =
Op->getOperand(1);
2823 if (fitsRegularPattern<int>(Begin + 1, 2,
End, HalfSize, 1))
2824 Ws =
Op->getOperand(0);
2825 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size() + HalfSize,
2827 Ws =
Op->getOperand(1);
2856 const auto &Begin = Indices.
begin();
2857 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2858 const auto &
End = Indices.
end();
2860 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2861 Wt =
Op->getOperand(0);
2862 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size(), 2))
2863 Wt =
Op->getOperand(1);
2867 if (fitsRegularPattern<int>(Mid, 1,
End, 0, 2))
2868 Ws =
Op->getOperand(0);
2869 else if (fitsRegularPattern<int>(Mid, 1,
End, Indices.
size(), 2))
2870 Ws =
Op->getOperand(1);
2899 const auto &Begin = Indices.
begin();
2900 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2901 const auto &
End = Indices.
end();
2903 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2904 Wt =
Op->getOperand(0);
2905 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size() + 1, 2))
2906 Wt =
Op->getOperand(1);
2910 if (fitsRegularPattern<int>(Mid, 1,
End, 1, 2))
2911 Ws =
Op->getOperand(0);
2912 else if (fitsRegularPattern<int>(Mid, 1,
End, Indices.
size() + 1, 2))
2913 Ws =
Op->getOperand(1);
2936 bool Using1stVec =
false;
2937 bool Using2ndVec =
false;
2941 for (
int i = 0; i < ResTyNumElts; ++i) {
2943 int Idx = Indices[i];
2945 if (0 <=
Idx &&
Idx < ResTyNumElts)
2947 if (ResTyNumElts <=
Idx &&
Idx < ResTyNumElts * 2)
2951 for (
int Idx : Indices)
2956 if (Using1stVec && Using2ndVec) {
2957 Op0 =
Op->getOperand(0);
2958 Op1 =
Op->getOperand(1);
2959 }
else if (Using1stVec)
2960 Op0 = Op1 =
Op->getOperand(0);
2961 else if (Using2ndVec)
2962 Op0 = Op1 =
Op->getOperand(1);
2964 llvm_unreachable(
"shuffle vector mask references neither vector operand?");
2981 EVT ResTy =
Op->getValueType(0);
2989 for (
int i = 0; i < ResTyNumElts; ++i)
3042 F->insert(It, Sink);
3047 Sink->transferSuccessorsAndUpdatePHIs(BB);
3073 MI.getOperand(0).getReg())
3079 MI.eraseFromParent();
3111 F->insert(It, Sink);
3116 Sink->transferSuccessorsAndUpdatePHIs(BB);
3142 MI.getOperand(0).getReg())
3148 MI.eraseFromParent();
3170 unsigned Lane =
MI.getOperand(2).getImm();
3177 Wt =
RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3186 : &Mips::MSA128WEvensRegClass);
3192 MI.eraseFromParent();
3215 unsigned Lane =
MI.getOperand(2).getImm() * 2;
3227 MI.eraseFromParent();
3245 unsigned Lane =
MI.getOperand(2).getImm();
3249 : &Mips::MSA128WEvensRegClass);
3261 MI.eraseFromParent();
3281 unsigned Lane =
MI.getOperand(2).getImm();
3295 MI.eraseFromParent();
3326 Register SrcVecReg =
MI.getOperand(1).getReg();
3327 Register LaneReg =
MI.getOperand(2).getReg();
3328 Register SrcValReg =
MI.getOperand(3).getReg();
3336 unsigned EltLog2Size;
3337 unsigned InsertOp = 0;
3338 unsigned InsveOp = 0;
3339 switch (EltSizeInBytes) {
3344 InsertOp = Mips::INSERT_B;
3345 InsveOp = Mips::INSVE_B;
3346 VecRC = &Mips::MSA128BRegClass;
3350 InsertOp = Mips::INSERT_H;
3351 InsveOp = Mips::INSVE_H;
3352 VecRC = &Mips::MSA128HRegClass;
3356 InsertOp = Mips::INSERT_W;
3357 InsveOp = Mips::INSVE_W;
3358 VecRC = &Mips::MSA128WRegClass;
3362 InsertOp = Mips::INSERT_D;
3363 InsveOp = Mips::INSVE_D;
3364 VecRC = &Mips::MSA128DRegClass;
3373 .
addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3378 if (EltSizeInBytes != 1) {
3391 .
addReg(LaneReg, 0, SubRegIdx);
3420 .
addReg(LaneTmp2, 0, SubRegIdx);
3422 MI.eraseFromParent();
3443 : &Mips::MSA128WEvensRegClass);
3446 : &Mips::MSA128WEvensRegClass);
3455 MI.eraseFromParent();
3486 MI.eraseFromParent();
3517 MI.getOperand(1).isReg() ?
RegInfo.getRegClass(
MI.getOperand(1).getReg())
3519 : &Mips::GPR64RegClass);
3520 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3532 BuildMI(*BB,
MI,
DL,
TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3539 MI.eraseFromParent();
3569 MI.getOperand(1).isReg() ?
RegInfo.getRegClass(
MI.getOperand(1).getReg())
3571 : &Mips::GPR64RegClass);
3573 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3577 BuildMI(*BB,
MI,
DL,
TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3589 MI.eraseFromParent();
3645 bool IsFGR64)
const {
3661 Register Wtemp =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3663 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3664 unsigned MFC1Opc = IsFGR64onMips64
3666 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3667 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3673 unsigned WPHI = Wtemp;
3675 if (IsFGR64onMips32) {
3678 Register Wtemp2 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3679 Register Wtemp3 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3692 Register Wtemp2 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3701 MI.eraseFromParent();
3750 bool IsFGR64)
const {
3767 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3768 unsigned MTC1Opc = IsFGR64onMips64
3770 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3771 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3773 Register Wtemp =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3778 WPHI =
RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3785 ?
RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3790 if (IsFGR64onMips32) {
3800 MI.eraseFromParent();
3827 .
addReg(
MI.getOperand(1).getReg());
3829 MI.eraseFromParent();
3856 .
addReg(
MI.getOperand(1).getReg());
3858 MI.eraseFromParent();
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue performSETCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue truncateVecElts(SDNode *Node, SelectionDAG &DAG)
static bool isConstantOrUndef(const SDValue Op)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, const SmallVector< int, 16 > &Indices, SelectionDAG &DAG)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
support::ulittle32_t & Wd
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
APInt trunc(unsigned width) const
Truncate to new width.
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool isNegative() const
Determine sign of this APInt.
unsigned logBase2() const
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM Basic Block Representation.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getInRegsParamsCount() const
uint64_t getZExtValue() const
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const Triple & getTargetTriple() const
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
Flags
Flags values. These may be or'd together.
Flags getFlags() const
Return the raw flags of the source value,.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
unsigned getIncomingArgSize() const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.