36#include "llvm/IR/IntrinsicsMips.h"
53#define DEBUG_TYPE "mips-isel"
60 cl::desc(
"Expand double precision loads and "
61 "stores to their single precision "
88 for (
const auto &VecTy : VecTys) {
304 return Subtarget.
hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
406 EVT ResTy = Op->getValueType(0);
444 switch(Op.getOpcode()) {
445 case ISD::LOAD:
return lowerLOAD(Op, DAG);
496 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
498 if (Log2IfPositive <= 0)
502 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
504 unsigned Log2 = Log2IfPositive;
507 Log2 == ExtendTySize) {
533 APInt SplatValue, SplatUndef;
534 unsigned SplatBitSize;
537 if (!
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
551 N =
N->getOperand(0);
558 APInt SplatValue, SplatUndef;
559 unsigned SplatBitSize;
564 if (BVN->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
576 return N->getOperand(1) == OfNode;
579 return N->getOperand(0) == OfNode;
596 EVT Ty =
N->getValueType(0);
609 bool IsLittleEndian = !Subtarget.
isLittle();
612 bool IsConstantMask =
false;
619 if (
isVSplat(Op0Op0, Mask, IsLittleEndian)) {
623 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
624 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
626 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
627 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
630 IsConstantMask =
true;
640 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
641 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
643 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
644 Mask.getBitWidth() == InvMask.
getBitWidth() && Mask == ~InvMask)
647 IsConstantMask =
true;
696 if (IsConstantMask) {
697 if (Mask.isAllOnes())
738 unsigned MaxSteps = Subtarget.
isABI_O32() ? 8 : 12;
744 while (!WorkStack.
empty()) {
747 if (Val == 0 || Val == 1)
750 if (Steps >= MaxSteps)
761 if ((Val - Floor).ule(Ceil - Val)) {
809 if ((
C - Floor).ule(Ceil -
C)) {
826 EVT VT =
N->getValueType(0);
830 C->getAPIntValue(), VT, DAG, Subtarget))
842 APInt SplatValue, SplatUndef;
843 unsigned SplatBitSize;
852 !BV->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
854 (SplatBitSize != EltSize) ||
859 return DAG.
getNode(Opc,
DL, Ty,
N->getOperand(0),
866 EVT Ty =
N->getValueType(0);
889 EVT Ty =
N->getValueType(0);
910 EVT ExtendTy = cast<VTSDNode>(Op0Op0->
getOperand(2))->getVT();
913 if (TotalBits == 32 ||
935 EVT Ty =
N->getValueType(0);
957 default:
return false;
962 EVT Ty =
N->getValueType(0);
971 N->getOperand(1),
N->getOperand(2));
975 EVT Ty =
N->getValueType(0);
985 N->getOperand(1),
N->getOperand(2), SetCC.
getOperand(2));
993 EVT Ty =
N->getValueType(0);
1023 switch (
N->getOpcode()) {
1051 N->printrWithDepth(
dbgs(), &DAG);
dbgs() <<
"\n=> \n";
1062 switch (
MI.getOpcode()) {
1065 case Mips::BPOSGE32_PSEUDO:
1066 return emitBPOSGE32(
MI, BB);
1067 case Mips::SNZ_B_PSEUDO:
1068 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_B);
1069 case Mips::SNZ_H_PSEUDO:
1070 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_H);
1071 case Mips::SNZ_W_PSEUDO:
1072 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_W);
1073 case Mips::SNZ_D_PSEUDO:
1074 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_D);
1075 case Mips::SNZ_V_PSEUDO:
1076 return emitMSACBranchPseudo(
MI, BB, Mips::BNZ_V);
1077 case Mips::SZ_B_PSEUDO:
1078 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_B);
1079 case Mips::SZ_H_PSEUDO:
1080 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_H);
1081 case Mips::SZ_W_PSEUDO:
1082 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_W);
1083 case Mips::SZ_D_PSEUDO:
1084 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_D);
1085 case Mips::SZ_V_PSEUDO:
1086 return emitMSACBranchPseudo(
MI, BB, Mips::BZ_V);
1087 case Mips::COPY_FW_PSEUDO:
1088 return emitCOPY_FW(
MI, BB);
1089 case Mips::COPY_FD_PSEUDO:
1090 return emitCOPY_FD(
MI, BB);
1091 case Mips::INSERT_FW_PSEUDO:
1092 return emitINSERT_FW(
MI, BB);
1093 case Mips::INSERT_FD_PSEUDO:
1094 return emitINSERT_FD(
MI, BB);
1095 case Mips::INSERT_B_VIDX_PSEUDO:
1096 case Mips::INSERT_B_VIDX64_PSEUDO:
1097 return emitINSERT_DF_VIDX(
MI, BB, 1,
false);
1098 case Mips::INSERT_H_VIDX_PSEUDO:
1099 case Mips::INSERT_H_VIDX64_PSEUDO:
1100 return emitINSERT_DF_VIDX(
MI, BB, 2,
false);
1101 case Mips::INSERT_W_VIDX_PSEUDO:
1102 case Mips::INSERT_W_VIDX64_PSEUDO:
1103 return emitINSERT_DF_VIDX(
MI, BB, 4,
false);
1104 case Mips::INSERT_D_VIDX_PSEUDO:
1105 case Mips::INSERT_D_VIDX64_PSEUDO:
1106 return emitINSERT_DF_VIDX(
MI, BB, 8,
false);
1107 case Mips::INSERT_FW_VIDX_PSEUDO:
1108 case Mips::INSERT_FW_VIDX64_PSEUDO:
1109 return emitINSERT_DF_VIDX(
MI, BB, 4,
true);
1110 case Mips::INSERT_FD_VIDX_PSEUDO:
1111 case Mips::INSERT_FD_VIDX64_PSEUDO:
1112 return emitINSERT_DF_VIDX(
MI, BB, 8,
true);
1113 case Mips::FILL_FW_PSEUDO:
1114 return emitFILL_FW(
MI, BB);
1115 case Mips::FILL_FD_PSEUDO:
1116 return emitFILL_FD(
MI, BB);
1117 case Mips::FEXP2_W_1_PSEUDO:
1118 return emitFEXP2_W_1(
MI, BB);
1119 case Mips::FEXP2_D_1_PSEUDO:
1120 return emitFEXP2_D_1(
MI, BB);
1122 return emitST_F16_PSEUDO(
MI, BB);
1124 return emitLD_F16_PSEUDO(
MI, BB);
1125 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1126 return emitFPEXTEND_PSEUDO(
MI, BB,
false);
1127 case Mips::MSA_FP_ROUND_W_PSEUDO:
1128 return emitFPROUND_PSEUDO(
MI, BB,
false);
1129 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1130 return emitFPEXTEND_PSEUDO(
MI, BB,
true);
1131 case Mips::MSA_FP_ROUND_D_PSEUDO:
1132 return emitFPROUND_PSEUDO(
MI, BB,
true);
1136bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1137 const CCState &CCInfo,
unsigned NextStackOffset,
1155void MipsSETargetLowering::
1157 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1158 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
1163 InternalLinkage, IsCallReloc, CLI,
Callee,
1176 EVT PtrVT =
Ptr.getValueType();
1205 EVT PtrVT =
Ptr.getValueType();
1228 MVT Src =
Op.getOperand(0).getValueType().getSimpleVT();
1229 MVT Dest =
Op.getValueType().getSimpleVT();
1255SDValue MipsSETargetLowering::lowerMulDiv(
SDValue Op,
unsigned NewOpc,
1256 bool HasLo,
bool HasHi,
1261 EVT Ty =
Op.getOperand(0).getValueType();
1264 Op.getOperand(0),
Op.getOperand(1));
1272 if (!HasLo || !HasHi)
1273 return HasLo ?
Lo :
Hi;
1307 bool HasChainIn = Op->getOperand(0).getValueType() ==
MVT::Other;
1319 SDValue Opnd = Op->getOperand(++OpNo), In64;
1327 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1337 for (
EVT Ty : Op->values())
1355 SDValue Vec = Op->getOperand(1);
1357 EVT ResTy = Op->getValueType(0);
1367 EVT ResVecTy = Op->getValueType(0);
1368 EVT ViaVecTy = ResVecTy;
1375 SDValue LaneA = Op->getOperand(OpNr);
1381 if (isa<ConstantSDNode>(LaneA))
1395 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1396 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1401 if (ViaVecTy != ResVecTy) {
1411 bool IsSigned =
false) {
1412 auto *CImm = cast<ConstantSDNode>(Op->getOperand(ImmOp));
1414 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),
1415 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
1416 SDLoc(Op), Op->getValueType(0));
1421 EVT ViaVecTy = VecTy;
1422 SDValue SplatValueA = SplatValue;
1423 SDValue SplatValueB = SplatValue;
1441 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1442 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1443 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1444 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1449 if (VecTy != ViaVecTy)
1458 EVT VecTy = Op->getValueType(0);
1466 APInt BitImm =
APInt(64, 1) << CImm->getAPIntValue();
1478 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1496 return DAG.
getNode(Opc,
DL, VecTy, Op->getOperand(1), Exp2Imm);
1501 EVT ResTy = Op->getValueType(0);
1502 SDValue Vec = Op->getOperand(2);
1513 EVT ResTy = Op->getValueType(0);
1524 EVT ResTy = Op->getValueType(0);
1526 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1535 unsigned Intrinsic = cast<ConstantSDNode>(
Op->getOperand(0))->getZExtValue();
1536 switch (Intrinsic) {
1539 case Intrinsic::mips_shilo:
1541 case Intrinsic::mips_dpau_h_qbl:
1543 case Intrinsic::mips_dpau_h_qbr:
1545 case Intrinsic::mips_dpsu_h_qbl:
1547 case Intrinsic::mips_dpsu_h_qbr:
1549 case Intrinsic::mips_dpa_w_ph:
1551 case Intrinsic::mips_dps_w_ph:
1553 case Intrinsic::mips_dpax_w_ph:
1555 case Intrinsic::mips_dpsx_w_ph:
1557 case Intrinsic::mips_mulsa_w_ph:
1559 case Intrinsic::mips_mult:
1561 case Intrinsic::mips_multu:
1563 case Intrinsic::mips_madd:
1565 case Intrinsic::mips_maddu:
1567 case Intrinsic::mips_msub:
1569 case Intrinsic::mips_msubu:
1571 case Intrinsic::mips_addv_b:
1572 case Intrinsic::mips_addv_h:
1573 case Intrinsic::mips_addv_w:
1574 case Intrinsic::mips_addv_d:
1577 case Intrinsic::mips_addvi_b:
1578 case Intrinsic::mips_addvi_h:
1579 case Intrinsic::mips_addvi_w:
1580 case Intrinsic::mips_addvi_d:
1583 case Intrinsic::mips_and_v:
1586 case Intrinsic::mips_andi_b:
1589 case Intrinsic::mips_bclr_b:
1590 case Intrinsic::mips_bclr_h:
1591 case Intrinsic::mips_bclr_w:
1592 case Intrinsic::mips_bclr_d:
1594 case Intrinsic::mips_bclri_b:
1595 case Intrinsic::mips_bclri_h:
1596 case Intrinsic::mips_bclri_w:
1597 case Intrinsic::mips_bclri_d:
1599 case Intrinsic::mips_binsli_b:
1600 case Intrinsic::mips_binsli_h:
1601 case Intrinsic::mips_binsli_w:
1602 case Intrinsic::mips_binsli_d: {
1604 EVT VecTy =
Op->getValueType(0);
1609 Op->getConstantOperandVal(3) + 1);
1612 Op->getOperand(2),
Op->getOperand(1));
1614 case Intrinsic::mips_binsri_b:
1615 case Intrinsic::mips_binsri_h:
1616 case Intrinsic::mips_binsri_w:
1617 case Intrinsic::mips_binsri_d: {
1619 EVT VecTy =
Op->getValueType(0);
1624 Op->getConstantOperandVal(3) + 1);
1627 Op->getOperand(2),
Op->getOperand(1));
1629 case Intrinsic::mips_bmnz_v:
1631 Op->getOperand(2),
Op->getOperand(1));
1632 case Intrinsic::mips_bmnzi_b:
1636 case Intrinsic::mips_bmz_v:
1638 Op->getOperand(1),
Op->getOperand(2));
1639 case Intrinsic::mips_bmzi_b:
1643 case Intrinsic::mips_bneg_b:
1644 case Intrinsic::mips_bneg_h:
1645 case Intrinsic::mips_bneg_w:
1646 case Intrinsic::mips_bneg_d: {
1647 EVT VecTy =
Op->getValueType(0);
1654 case Intrinsic::mips_bnegi_b:
1655 case Intrinsic::mips_bnegi_h:
1656 case Intrinsic::mips_bnegi_w:
1657 case Intrinsic::mips_bnegi_d:
1660 case Intrinsic::mips_bnz_b:
1661 case Intrinsic::mips_bnz_h:
1662 case Intrinsic::mips_bnz_w:
1663 case Intrinsic::mips_bnz_d:
1666 case Intrinsic::mips_bnz_v:
1669 case Intrinsic::mips_bsel_v:
1672 Op->getOperand(1),
Op->getOperand(3),
1674 case Intrinsic::mips_bseli_b:
1679 case Intrinsic::mips_bset_b:
1680 case Intrinsic::mips_bset_h:
1681 case Intrinsic::mips_bset_w:
1682 case Intrinsic::mips_bset_d: {
1683 EVT VecTy =
Op->getValueType(0);
1690 case Intrinsic::mips_bseti_b:
1691 case Intrinsic::mips_bseti_h:
1692 case Intrinsic::mips_bseti_w:
1693 case Intrinsic::mips_bseti_d:
1696 case Intrinsic::mips_bz_b:
1697 case Intrinsic::mips_bz_h:
1698 case Intrinsic::mips_bz_w:
1699 case Intrinsic::mips_bz_d:
1702 case Intrinsic::mips_bz_v:
1705 case Intrinsic::mips_ceq_b:
1706 case Intrinsic::mips_ceq_h:
1707 case Intrinsic::mips_ceq_w:
1708 case Intrinsic::mips_ceq_d:
1711 case Intrinsic::mips_ceqi_b:
1712 case Intrinsic::mips_ceqi_h:
1713 case Intrinsic::mips_ceqi_w:
1714 case Intrinsic::mips_ceqi_d:
1717 case Intrinsic::mips_cle_s_b:
1718 case Intrinsic::mips_cle_s_h:
1719 case Intrinsic::mips_cle_s_w:
1720 case Intrinsic::mips_cle_s_d:
1723 case Intrinsic::mips_clei_s_b:
1724 case Intrinsic::mips_clei_s_h:
1725 case Intrinsic::mips_clei_s_w:
1726 case Intrinsic::mips_clei_s_d:
1729 case Intrinsic::mips_cle_u_b:
1730 case Intrinsic::mips_cle_u_h:
1731 case Intrinsic::mips_cle_u_w:
1732 case Intrinsic::mips_cle_u_d:
1735 case Intrinsic::mips_clei_u_b:
1736 case Intrinsic::mips_clei_u_h:
1737 case Intrinsic::mips_clei_u_w:
1738 case Intrinsic::mips_clei_u_d:
1741 case Intrinsic::mips_clt_s_b:
1742 case Intrinsic::mips_clt_s_h:
1743 case Intrinsic::mips_clt_s_w:
1744 case Intrinsic::mips_clt_s_d:
1747 case Intrinsic::mips_clti_s_b:
1748 case Intrinsic::mips_clti_s_h:
1749 case Intrinsic::mips_clti_s_w:
1750 case Intrinsic::mips_clti_s_d:
1753 case Intrinsic::mips_clt_u_b:
1754 case Intrinsic::mips_clt_u_h:
1755 case Intrinsic::mips_clt_u_w:
1756 case Intrinsic::mips_clt_u_d:
1759 case Intrinsic::mips_clti_u_b:
1760 case Intrinsic::mips_clti_u_h:
1761 case Intrinsic::mips_clti_u_w:
1762 case Intrinsic::mips_clti_u_d:
1765 case Intrinsic::mips_copy_s_b:
1766 case Intrinsic::mips_copy_s_h:
1767 case Intrinsic::mips_copy_s_w:
1769 case Intrinsic::mips_copy_s_d:
1777 Op->getValueType(0),
Op->getOperand(1),
1780 case Intrinsic::mips_copy_u_b:
1781 case Intrinsic::mips_copy_u_h:
1782 case Intrinsic::mips_copy_u_w:
1784 case Intrinsic::mips_copy_u_d:
1795 Op->getValueType(0),
Op->getOperand(1),
1798 case Intrinsic::mips_div_s_b:
1799 case Intrinsic::mips_div_s_h:
1800 case Intrinsic::mips_div_s_w:
1801 case Intrinsic::mips_div_s_d:
1804 case Intrinsic::mips_div_u_b:
1805 case Intrinsic::mips_div_u_h:
1806 case Intrinsic::mips_div_u_w:
1807 case Intrinsic::mips_div_u_d:
1810 case Intrinsic::mips_fadd_w:
1811 case Intrinsic::mips_fadd_d:
1816 case Intrinsic::mips_fceq_w:
1817 case Intrinsic::mips_fceq_d:
1820 case Intrinsic::mips_fcle_w:
1821 case Intrinsic::mips_fcle_d:
1824 case Intrinsic::mips_fclt_w:
1825 case Intrinsic::mips_fclt_d:
1828 case Intrinsic::mips_fcne_w:
1829 case Intrinsic::mips_fcne_d:
1832 case Intrinsic::mips_fcor_w:
1833 case Intrinsic::mips_fcor_d:
1836 case Intrinsic::mips_fcueq_w:
1837 case Intrinsic::mips_fcueq_d:
1840 case Intrinsic::mips_fcule_w:
1841 case Intrinsic::mips_fcule_d:
1844 case Intrinsic::mips_fcult_w:
1845 case Intrinsic::mips_fcult_d:
1848 case Intrinsic::mips_fcun_w:
1849 case Intrinsic::mips_fcun_d:
1852 case Intrinsic::mips_fcune_w:
1853 case Intrinsic::mips_fcune_d:
1856 case Intrinsic::mips_fdiv_w:
1857 case Intrinsic::mips_fdiv_d:
1861 case Intrinsic::mips_ffint_u_w:
1862 case Intrinsic::mips_ffint_u_d:
1865 case Intrinsic::mips_ffint_s_w:
1866 case Intrinsic::mips_ffint_s_d:
1869 case Intrinsic::mips_fill_b:
1870 case Intrinsic::mips_fill_h:
1871 case Intrinsic::mips_fill_w:
1872 case Intrinsic::mips_fill_d: {
1873 EVT ResTy =
Op->getValueType(0);
1881 case Intrinsic::mips_fexp2_w:
1882 case Intrinsic::mips_fexp2_d: {
1884 EVT ResTy =
Op->getValueType(0);
1889 case Intrinsic::mips_flog2_w:
1890 case Intrinsic::mips_flog2_d:
1892 case Intrinsic::mips_fmadd_w:
1893 case Intrinsic::mips_fmadd_d:
1895 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
1896 case Intrinsic::mips_fmul_w:
1897 case Intrinsic::mips_fmul_d:
1901 case Intrinsic::mips_fmsub_w:
1902 case Intrinsic::mips_fmsub_d: {
1905 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
1907 case Intrinsic::mips_frint_w:
1908 case Intrinsic::mips_frint_d:
1910 case Intrinsic::mips_fsqrt_w:
1911 case Intrinsic::mips_fsqrt_d:
1913 case Intrinsic::mips_fsub_w:
1914 case Intrinsic::mips_fsub_d:
1918 case Intrinsic::mips_ftrunc_u_w:
1919 case Intrinsic::mips_ftrunc_u_d:
1922 case Intrinsic::mips_ftrunc_s_w:
1923 case Intrinsic::mips_ftrunc_s_d:
1926 case Intrinsic::mips_ilvev_b:
1927 case Intrinsic::mips_ilvev_h:
1928 case Intrinsic::mips_ilvev_w:
1929 case Intrinsic::mips_ilvev_d:
1931 Op->getOperand(1),
Op->getOperand(2));
1932 case Intrinsic::mips_ilvl_b:
1933 case Intrinsic::mips_ilvl_h:
1934 case Intrinsic::mips_ilvl_w:
1935 case Intrinsic::mips_ilvl_d:
1937 Op->getOperand(1),
Op->getOperand(2));
1938 case Intrinsic::mips_ilvod_b:
1939 case Intrinsic::mips_ilvod_h:
1940 case Intrinsic::mips_ilvod_w:
1941 case Intrinsic::mips_ilvod_d:
1943 Op->getOperand(1),
Op->getOperand(2));
1944 case Intrinsic::mips_ilvr_b:
1945 case Intrinsic::mips_ilvr_h:
1946 case Intrinsic::mips_ilvr_w:
1947 case Intrinsic::mips_ilvr_d:
1949 Op->getOperand(1),
Op->getOperand(2));
1950 case Intrinsic::mips_insert_b:
1951 case Intrinsic::mips_insert_h:
1952 case Intrinsic::mips_insert_w:
1953 case Intrinsic::mips_insert_d:
1955 Op->getOperand(1),
Op->getOperand(3),
Op->getOperand(2));
1956 case Intrinsic::mips_insve_b:
1957 case Intrinsic::mips_insve_h:
1958 case Intrinsic::mips_insve_w:
1959 case Intrinsic::mips_insve_d: {
1962 switch (Intrinsic) {
1963 case Intrinsic::mips_insve_b:
Max = 15;
break;
1964 case Intrinsic::mips_insve_h:
Max = 7;
break;
1965 case Intrinsic::mips_insve_w:
Max = 3;
break;
1966 case Intrinsic::mips_insve_d:
Max = 1;
break;
1969 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
1970 if (Value < 0 || Value > Max)
1973 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3),
1976 case Intrinsic::mips_ldi_b:
1977 case Intrinsic::mips_ldi_h:
1978 case Intrinsic::mips_ldi_w:
1979 case Intrinsic::mips_ldi_d:
1981 case Intrinsic::mips_lsa:
1982 case Intrinsic::mips_dlsa: {
1983 EVT ResTy =
Op->getValueType(0);
1986 Op->getOperand(2),
Op->getOperand(3)));
1988 case Intrinsic::mips_maddv_b:
1989 case Intrinsic::mips_maddv_h:
1990 case Intrinsic::mips_maddv_w:
1991 case Intrinsic::mips_maddv_d: {
1992 EVT ResTy =
Op->getValueType(0);
1995 Op->getOperand(2),
Op->getOperand(3)));
1997 case Intrinsic::mips_max_s_b:
1998 case Intrinsic::mips_max_s_h:
1999 case Intrinsic::mips_max_s_w:
2000 case Intrinsic::mips_max_s_d:
2002 Op->getOperand(1),
Op->getOperand(2));
2003 case Intrinsic::mips_max_u_b:
2004 case Intrinsic::mips_max_u_h:
2005 case Intrinsic::mips_max_u_w:
2006 case Intrinsic::mips_max_u_d:
2008 Op->getOperand(1),
Op->getOperand(2));
2009 case Intrinsic::mips_maxi_s_b:
2010 case Intrinsic::mips_maxi_s_h:
2011 case Intrinsic::mips_maxi_s_w:
2012 case Intrinsic::mips_maxi_s_d:
2015 case Intrinsic::mips_maxi_u_b:
2016 case Intrinsic::mips_maxi_u_h:
2017 case Intrinsic::mips_maxi_u_w:
2018 case Intrinsic::mips_maxi_u_d:
2021 case Intrinsic::mips_min_s_b:
2022 case Intrinsic::mips_min_s_h:
2023 case Intrinsic::mips_min_s_w:
2024 case Intrinsic::mips_min_s_d:
2026 Op->getOperand(1),
Op->getOperand(2));
2027 case Intrinsic::mips_min_u_b:
2028 case Intrinsic::mips_min_u_h:
2029 case Intrinsic::mips_min_u_w:
2030 case Intrinsic::mips_min_u_d:
2032 Op->getOperand(1),
Op->getOperand(2));
2033 case Intrinsic::mips_mini_s_b:
2034 case Intrinsic::mips_mini_s_h:
2035 case Intrinsic::mips_mini_s_w:
2036 case Intrinsic::mips_mini_s_d:
2039 case Intrinsic::mips_mini_u_b:
2040 case Intrinsic::mips_mini_u_h:
2041 case Intrinsic::mips_mini_u_w:
2042 case Intrinsic::mips_mini_u_d:
2045 case Intrinsic::mips_mod_s_b:
2046 case Intrinsic::mips_mod_s_h:
2047 case Intrinsic::mips_mod_s_w:
2048 case Intrinsic::mips_mod_s_d:
2051 case Intrinsic::mips_mod_u_b:
2052 case Intrinsic::mips_mod_u_h:
2053 case Intrinsic::mips_mod_u_w:
2054 case Intrinsic::mips_mod_u_d:
2057 case Intrinsic::mips_mulv_b:
2058 case Intrinsic::mips_mulv_h:
2059 case Intrinsic::mips_mulv_w:
2060 case Intrinsic::mips_mulv_d:
2063 case Intrinsic::mips_msubv_b:
2064 case Intrinsic::mips_msubv_h:
2065 case Intrinsic::mips_msubv_w:
2066 case Intrinsic::mips_msubv_d: {
2067 EVT ResTy =
Op->getValueType(0);
2070 Op->getOperand(2),
Op->getOperand(3)));
2072 case Intrinsic::mips_nlzc_b:
2073 case Intrinsic::mips_nlzc_h:
2074 case Intrinsic::mips_nlzc_w:
2075 case Intrinsic::mips_nlzc_d:
2077 case Intrinsic::mips_nor_v: {
2079 Op->getOperand(1),
Op->getOperand(2));
2082 case Intrinsic::mips_nori_b: {
2088 case Intrinsic::mips_or_v:
2091 case Intrinsic::mips_ori_b:
2094 case Intrinsic::mips_pckev_b:
2095 case Intrinsic::mips_pckev_h:
2096 case Intrinsic::mips_pckev_w:
2097 case Intrinsic::mips_pckev_d:
2099 Op->getOperand(1),
Op->getOperand(2));
2100 case Intrinsic::mips_pckod_b:
2101 case Intrinsic::mips_pckod_h:
2102 case Intrinsic::mips_pckod_w:
2103 case Intrinsic::mips_pckod_d:
2105 Op->getOperand(1),
Op->getOperand(2));
2106 case Intrinsic::mips_pcnt_b:
2107 case Intrinsic::mips_pcnt_h:
2108 case Intrinsic::mips_pcnt_w:
2109 case Intrinsic::mips_pcnt_d:
2111 case Intrinsic::mips_sat_s_b:
2112 case Intrinsic::mips_sat_s_h:
2113 case Intrinsic::mips_sat_s_w:
2114 case Intrinsic::mips_sat_s_d:
2115 case Intrinsic::mips_sat_u_b:
2116 case Intrinsic::mips_sat_u_h:
2117 case Intrinsic::mips_sat_u_w:
2118 case Intrinsic::mips_sat_u_d: {
2121 switch (Intrinsic) {
2122 case Intrinsic::mips_sat_s_b:
2123 case Intrinsic::mips_sat_u_b:
Max = 7;
break;
2124 case Intrinsic::mips_sat_s_h:
2125 case Intrinsic::mips_sat_u_h:
Max = 15;
break;
2126 case Intrinsic::mips_sat_s_w:
2127 case Intrinsic::mips_sat_u_w:
Max = 31;
break;
2128 case Intrinsic::mips_sat_s_d:
2129 case Intrinsic::mips_sat_u_d:
Max = 63;
break;
2132 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2133 if (Value < 0 || Value > Max)
2137 case Intrinsic::mips_shf_b:
2138 case Intrinsic::mips_shf_h:
2139 case Intrinsic::mips_shf_w: {
2140 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2141 if (Value < 0 || Value > 255)
2144 Op->getOperand(2),
Op->getOperand(1));
2146 case Intrinsic::mips_sldi_b:
2147 case Intrinsic::mips_sldi_h:
2148 case Intrinsic::mips_sldi_w:
2149 case Intrinsic::mips_sldi_d: {
2152 switch (Intrinsic) {
2153 case Intrinsic::mips_sldi_b:
Max = 15;
break;
2154 case Intrinsic::mips_sldi_h:
Max = 7;
break;
2155 case Intrinsic::mips_sldi_w:
Max = 3;
break;
2156 case Intrinsic::mips_sldi_d:
Max = 1;
break;
2159 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(3))->getSExtValue();
2160 if (Value < 0 || Value > Max)
2164 case Intrinsic::mips_sll_b:
2165 case Intrinsic::mips_sll_h:
2166 case Intrinsic::mips_sll_w:
2167 case Intrinsic::mips_sll_d:
2170 case Intrinsic::mips_slli_b:
2171 case Intrinsic::mips_slli_h:
2172 case Intrinsic::mips_slli_w:
2173 case Intrinsic::mips_slli_d:
2176 case Intrinsic::mips_splat_b:
2177 case Intrinsic::mips_splat_h:
2178 case Intrinsic::mips_splat_w:
2179 case Intrinsic::mips_splat_d:
2187 case Intrinsic::mips_splati_b:
2188 case Intrinsic::mips_splati_h:
2189 case Intrinsic::mips_splati_w:
2190 case Intrinsic::mips_splati_d:
2194 case Intrinsic::mips_sra_b:
2195 case Intrinsic::mips_sra_h:
2196 case Intrinsic::mips_sra_w:
2197 case Intrinsic::mips_sra_d:
2200 case Intrinsic::mips_srai_b:
2201 case Intrinsic::mips_srai_h:
2202 case Intrinsic::mips_srai_w:
2203 case Intrinsic::mips_srai_d:
2206 case Intrinsic::mips_srari_b:
2207 case Intrinsic::mips_srari_h:
2208 case Intrinsic::mips_srari_w:
2209 case Intrinsic::mips_srari_d: {
2212 switch (Intrinsic) {
2213 case Intrinsic::mips_srari_b:
Max = 7;
break;
2214 case Intrinsic::mips_srari_h:
Max = 15;
break;
2215 case Intrinsic::mips_srari_w:
Max = 31;
break;
2216 case Intrinsic::mips_srari_d:
Max = 63;
break;
2219 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2220 if (Value < 0 || Value > Max)
2224 case Intrinsic::mips_srl_b:
2225 case Intrinsic::mips_srl_h:
2226 case Intrinsic::mips_srl_w:
2227 case Intrinsic::mips_srl_d:
2230 case Intrinsic::mips_srli_b:
2231 case Intrinsic::mips_srli_h:
2232 case Intrinsic::mips_srli_w:
2233 case Intrinsic::mips_srli_d:
2236 case Intrinsic::mips_srlri_b:
2237 case Intrinsic::mips_srlri_h:
2238 case Intrinsic::mips_srlri_w:
2239 case Intrinsic::mips_srlri_d: {
2242 switch (Intrinsic) {
2243 case Intrinsic::mips_srlri_b:
Max = 7;
break;
2244 case Intrinsic::mips_srlri_h:
Max = 15;
break;
2245 case Intrinsic::mips_srlri_w:
Max = 31;
break;
2246 case Intrinsic::mips_srlri_d:
Max = 63;
break;
2249 int64_t
Value = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
2250 if (Value < 0 || Value > Max)
2254 case Intrinsic::mips_subv_b:
2255 case Intrinsic::mips_subv_h:
2256 case Intrinsic::mips_subv_w:
2257 case Intrinsic::mips_subv_d:
2260 case Intrinsic::mips_subvi_b:
2261 case Intrinsic::mips_subvi_h:
2262 case Intrinsic::mips_subvi_w:
2263 case Intrinsic::mips_subvi_d:
2266 case Intrinsic::mips_vshf_b:
2267 case Intrinsic::mips_vshf_h:
2268 case Intrinsic::mips_vshf_w:
2269 case Intrinsic::mips_vshf_d:
2271 Op->getOperand(1),
Op->getOperand(2),
Op->getOperand(3));
2272 case Intrinsic::mips_xor_v:
2275 case Intrinsic::mips_xori_b:
2278 case Intrinsic::thread_pointer: {
2288 SDValue ChainIn = Op->getOperand(0);
2291 EVT ResTy = Op->getValueType(0);
2307 unsigned Intr = cast<ConstantSDNode>(
Op->getOperand(1))->getZExtValue();
2311 case Intrinsic::mips_extp:
2313 case Intrinsic::mips_extpdp:
2315 case Intrinsic::mips_extr_w:
2317 case Intrinsic::mips_extr_r_w:
2319 case Intrinsic::mips_extr_rs_w:
2321 case Intrinsic::mips_extr_s_h:
2323 case Intrinsic::mips_mthlip:
2325 case Intrinsic::mips_mulsaq_s_w_ph:
2327 case Intrinsic::mips_maq_s_w_phl:
2329 case Intrinsic::mips_maq_s_w_phr:
2331 case Intrinsic::mips_maq_sa_w_phl:
2333 case Intrinsic::mips_maq_sa_w_phr:
2335 case Intrinsic::mips_dpaq_s_w_ph:
2337 case Intrinsic::mips_dpsq_s_w_ph:
2339 case Intrinsic::mips_dpaq_sa_l_w:
2341 case Intrinsic::mips_dpsq_sa_l_w:
2343 case Intrinsic::mips_dpaqx_s_w_ph:
2345 case Intrinsic::mips_dpaqx_sa_w_ph:
2347 case Intrinsic::mips_dpsqx_s_w_ph:
2349 case Intrinsic::mips_dpsqx_sa_w_ph:
2351 case Intrinsic::mips_ld_b:
2352 case Intrinsic::mips_ld_h:
2353 case Intrinsic::mips_ld_w:
2354 case Intrinsic::mips_ld_d:
2362 SDValue ChainIn = Op->getOperand(0);
2382 unsigned Intr = cast<ConstantSDNode>(
Op->getOperand(1))->getZExtValue();
2386 case Intrinsic::mips_st_b:
2387 case Intrinsic::mips_st_h:
2388 case Intrinsic::mips_st_w:
2389 case Intrinsic::mips_st_d:
2404 EVT ResTy =
Op->getValueType(0);
2424 if (isa<ConstantSDNode>(Op))
2426 if (isa<ConstantFPSDNode>(Op))
2432 for (
unsigned i = 0; i < Op->getNumOperands(); ++i)
2454 EVT ResTy =
Op->getValueType(0);
2456 APInt SplatValue, SplatUndef;
2457 unsigned SplatBitSize;
2463 if (
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2467 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2479 switch (SplatBitSize) {
2500 if (ViaVecTy != ResTy)
2510 EVT ResTy =
Node->getValueType(0);
2516 for (
unsigned i = 0; i < NumElts; ++i) {
2518 Node->getOperand(i),
2548 int SHFIndices[4] = { -1, -1, -1, -1 };
2550 if (Indices.
size() < 4)
2553 for (
unsigned i = 0; i < 4; ++i) {
2554 for (
unsigned j = i; j < Indices.
size(); j += 4) {
2555 int Idx = Indices[j];
2561 if (Idx < 0 || Idx >= 4)
2567 if (SHFIndices[i] == -1)
2568 SHFIndices[i] =
Idx;
2572 if (!(
Idx == -1 ||
Idx == SHFIndices[i]))
2579 for (
int i = 3; i >= 0; --i) {
2580 int Idx = SHFIndices[i];
2597template <
typename ValType>
2600 unsigned CheckStride,
2602 ValType ExpectedIndex,
unsigned ExpectedIndexStride) {
2606 if (*
I != -1 && *
I != ExpectedIndex)
2608 ExpectedIndex += ExpectedIndexStride;
2612 for (
unsigned n = 0; n < CheckStride &&
I != End; ++n, ++
I)
2631 int SplatIndex = -1;
2632 for (
const auto &V : Indices) {
2639 return fitsRegularPattern<int>(Indices.
begin(), 1, Indices.
end(), SplatIndex,
2665 const auto &Begin = Indices.
begin();
2666 const auto &End = Indices.
end();
2670 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2671 Wt = Op->getOperand(0);
2672 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size(), 2))
2673 Wt = Op->getOperand(1);
2679 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2680 Ws = Op->getOperand(0);
2681 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size(), 2))
2682 Ws = Op->getOperand(1);
2711 const auto &Begin = Indices.
begin();
2712 const auto &End = Indices.
end();
2716 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2717 Wt = Op->getOperand(0);
2718 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size() + 1, 2))
2719 Wt = Op->getOperand(1);
2725 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2726 Ws = Op->getOperand(0);
2727 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size() + 1, 2))
2728 Ws = Op->getOperand(1);
2758 const auto &Begin = Indices.
begin();
2759 const auto &End = Indices.
end();
2763 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2764 Wt = Op->getOperand(0);
2765 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size(), 1))
2766 Wt = Op->getOperand(1);
2772 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2773 Ws = Op->getOperand(0);
2774 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size(), 1))
2775 Ws = Op->getOperand(1);
2803 unsigned HalfSize = Indices.
size() / 2;
2806 const auto &Begin = Indices.
begin();
2807 const auto &End = Indices.
end();
2811 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2812 Wt = Op->getOperand(0);
2813 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.
size() + HalfSize, 1))
2814 Wt = Op->getOperand(1);
2820 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2821 Ws = Op->getOperand(0);
2822 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.
size() + HalfSize,
2824 Ws = Op->getOperand(1);
2853 const auto &Begin = Indices.
begin();
2854 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2855 const auto &End = Indices.
end();
2857 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2858 Wt = Op->getOperand(0);
2859 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size(), 2))
2860 Wt = Op->getOperand(1);
2864 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2865 Ws = Op->getOperand(0);
2866 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.
size(), 2))
2867 Ws = Op->getOperand(1);
2896 const auto &Begin = Indices.
begin();
2897 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2898 const auto &End = Indices.
end();
2900 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2901 Wt = Op->getOperand(0);
2902 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size() + 1, 2))
2903 Wt = Op->getOperand(1);
2907 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2908 Ws = Op->getOperand(0);
2909 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.
size() + 1, 2))
2910 Ws = Op->getOperand(1);
2933 bool Using1stVec =
false;
2934 bool Using2ndVec =
false;
2938 for (
int i = 0; i < ResTyNumElts; ++i) {
2940 int Idx = Indices[i];
2942 if (0 <=
Idx &&
Idx < ResTyNumElts)
2944 if (ResTyNumElts <=
Idx &&
Idx < ResTyNumElts * 2)
2948 for (
int Idx : Indices)
2953 if (Using1stVec && Using2ndVec) {
2954 Op0 = Op->getOperand(0);
2955 Op1 = Op->getOperand(1);
2956 }
else if (Using1stVec)
2957 Op0 = Op1 = Op->getOperand(0);
2958 else if (Using2ndVec)
2959 Op0 = Op1 = Op->getOperand(1);
2961 llvm_unreachable(
"shuffle vector mask references neither vector operand?");
2978 EVT ResTy =
Op->getValueType(0);
2986 for (
int i = 0; i < ResTyNumElts; ++i)
3039 F->insert(It, Sink);
3044 Sink->transferSuccessorsAndUpdatePHIs(BB);
3070 MI.getOperand(0).getReg())
3076 MI.eraseFromParent();
3108 F->insert(It, Sink);
3113 Sink->transferSuccessorsAndUpdatePHIs(BB);
3139 MI.getOperand(0).getReg())
3145 MI.eraseFromParent();
3167 unsigned Lane =
MI.getOperand(2).getImm();
3174 Wt =
RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3183 : &Mips::MSA128WEvensRegClass);
3189 MI.eraseFromParent();
3212 unsigned Lane =
MI.getOperand(2).getImm() * 2;
3224 MI.eraseFromParent();
3242 unsigned Lane =
MI.getOperand(2).getImm();
3246 : &Mips::MSA128WEvensRegClass);
3258 MI.eraseFromParent();
3278 unsigned Lane =
MI.getOperand(2).getImm();
3292 MI.eraseFromParent();
3323 Register SrcVecReg =
MI.getOperand(1).getReg();
3324 Register LaneReg =
MI.getOperand(2).getReg();
3325 Register SrcValReg =
MI.getOperand(3).getReg();
3333 unsigned EltLog2Size;
3334 unsigned InsertOp = 0;
3335 unsigned InsveOp = 0;
3336 switch (EltSizeInBytes) {
3341 InsertOp = Mips::INSERT_B;
3342 InsveOp = Mips::INSVE_B;
3343 VecRC = &Mips::MSA128BRegClass;
3347 InsertOp = Mips::INSERT_H;
3348 InsveOp = Mips::INSVE_H;
3349 VecRC = &Mips::MSA128HRegClass;
3353 InsertOp = Mips::INSERT_W;
3354 InsveOp = Mips::INSVE_W;
3355 VecRC = &Mips::MSA128WRegClass;
3359 InsertOp = Mips::INSERT_D;
3360 InsveOp = Mips::INSVE_D;
3361 VecRC = &Mips::MSA128DRegClass;
3370 .
addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3375 if (EltSizeInBytes != 1) {
3388 .
addReg(LaneReg, 0, SubRegIdx);
3417 .
addReg(LaneTmp2, 0, SubRegIdx);
3419 MI.eraseFromParent();
3440 : &Mips::MSA128WEvensRegClass);
3443 : &Mips::MSA128WEvensRegClass);
3452 MI.eraseFromParent();
3483 MI.eraseFromParent();
3514 MI.getOperand(1).isReg() ?
RegInfo.getRegClass(
MI.getOperand(1).getReg())
3516 : &Mips::GPR64RegClass);
3517 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3529 BuildMI(*BB,
MI,
DL,
TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3536 MI.eraseFromParent();
3566 MI.getOperand(1).isReg() ?
RegInfo.getRegClass(
MI.getOperand(1).getReg())
3568 : &Mips::GPR64RegClass);
3570 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3574 BuildMI(*BB,
MI,
DL,
TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3586 MI.eraseFromParent();
3642 bool IsFGR64)
const {
3658 Register Wtemp =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3660 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3661 unsigned MFC1Opc = IsFGR64onMips64
3663 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3664 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3670 unsigned WPHI = Wtemp;
3672 if (IsFGR64onMips32) {
3675 Register Wtemp2 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3676 Register Wtemp3 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3689 Register Wtemp2 =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3698 MI.eraseFromParent();
3747 bool IsFGR64)
const {
3764 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3765 unsigned MTC1Opc = IsFGR64onMips64
3767 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3768 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3770 Register Wtemp =
RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3775 WPHI =
RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3782 ?
RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3787 if (IsFGR64onMips32) {
3797 MI.eraseFromParent();
3824 .
addReg(
MI.getOperand(1).getReg());
3826 MI.eraseFromParent();
3853 .
addReg(
MI.getOperand(1).getReg());
3855 MI.eraseFromParent();
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue performSETCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
This file implements a class to represent arbitrary precision integral constant values and operations...
SmallVector< MachineOperand, 4 > Cond
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, const SmallVector< int, 16 > &Indices, SelectionDAG &DAG)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG)
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isConstantOrUndef(const SDValue Op)
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
APInt trunc(unsigned width) const
Truncate to new width.
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool isNegative() const
Determine sign of this APInt.
unsigned logBase2() const
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM Basic Block Representation.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getInRegsParamsCount() const
uint64_t getZExtValue() const
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const Triple & getTargetTriple() const
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.