30#define DEBUG_TYPE "mips-subtarget"
32#define GET_SUBTARGETINFO_TARGET_DESC
33#define GET_SUBTARGETINFO_CTOR
34#include "MipsGenSubtargetInfo.inc"
40 cl::desc(
"Allow for a mixture of Mips16 "
41 "and Mips32 code in a single output file"),
45 cl::desc(
"Compile all functions that don't use "
46 "floating point as Mips 16"),
50 cl::desc(
"Enable mips16 hard float."),
55 cl::desc(
"Enable mips16 constant islands."),
60 cl::desc(
"Enable gp-relative addressing of mips small data items"));
62bool MipsSubtarget::DspWarningPrinted =
false;
63bool MipsSubtarget::MSAWarningPrinted =
false;
64bool MipsSubtarget::VirtWarningPrinted =
false;
65bool MipsSubtarget::CRCWarningPrinted =
false;
66bool MipsSubtarget::GINVWarningPrinted =
false;
67bool MipsSubtarget::MIPS1WarningPrinted =
false;
69void MipsSubtarget::anchor() {}
75 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(
false),
86 StackAlignOverride(StackAlignOverride),
TM(
TM), TargetTriple(TT),
88 initializeSubtargetDependencies(CPU, FS,
TM))),
92 if (MipsArchVersion == MipsDefault)
93 MipsArchVersion = Mips32;
96 if (MipsArchVersion == Mips1 && !MIPS1WarningPrinted) {
97 errs() <<
"warning: MIPS-I support is experimental\n";
98 MIPS1WarningPrinted =
true;
103 if (MipsArchVersion == Mips5)
109 "Invalid Arch & ABI pair.");
118 "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "
119 "Use -mcpu=mips32r2 or greater.",
false);
133 if (UseIndirectJumpsHazard) {
136 "cannot combine indirect jumps with hazard barriers and microMIPS");
139 "indirect jumps with hazard barriers requires MIPS32R2 or later");
157 if (NoABICalls &&
TM.isPositionIndependent())
164 UseSmallSection =
GPOpt;
165 if (!NoABICalls &&
GPOpt) {
166 errs() <<
"warning: cannot use small-data accesses for '-mabicalls'"
168 UseSmallSection =
false;
171 if (
hasDSPR2() && !DspWarningPrinted) {
173 errs() <<
"warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
175 DspWarningPrinted =
true;
177 errs() <<
"warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
179 DspWarningPrinted =
true;
181 }
else if (
hasDSP() && !DspWarningPrinted) {
183 errs() <<
"warning: the 'dsp' ASE requires MIPS64 revision 2 or "
185 DspWarningPrinted =
true;
187 errs() <<
"warning: the 'dsp' ASE requires MIPS32 revision 2 or "
189 DspWarningPrinted =
true;
196 errs() <<
"warning: the 'msa' ASE requires " << ArchName
197 <<
" revision 5 or greater\n";
198 MSAWarningPrinted =
true;
201 errs() <<
"warning: the 'virt' ASE requires " << ArchName
202 <<
" revision 5 or greater\n";
203 VirtWarningPrinted =
true;
206 errs() <<
"warning: the 'crc' ASE requires " << ArchName
207 <<
" revision 6 or greater\n";
208 CRCWarningPrinted =
true;
211 errs() <<
"warning: the 'ginv' ASE requires " << ArchName
212 <<
" revision 6 or greater\n";
213 GINVWarningPrinted =
true;
233 CriticalPathRCs.clear();
234 CriticalPathRCs.push_back(
isGP64bit() ? &Mips::GPR64RegClass
235 : &Mips::GPR32RegClass);
250 InstrItins = getInstrItineraryForCPU(CPUName);
252 if (InMips16Mode && !IsSoftFloat)
253 InMips16HardFloat =
true;
255 if (StackAlignOverride)
256 stackAlignment = *StackAlignOverride;
258 stackAlignment =
Align(16);
261 stackAlignment =
Align(8);
This file contains the simple types necessary to represent the attributes associated with functions a...
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for Mips.
This file declares the targeting of the RegisterBankInfo class for Mips.
static cl::opt< bool > Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden, cl::desc("Enable mips16 constant islands."), cl::init(true))
static cl::opt< bool > Mixed16_32("mips-mixed-16-32", cl::init(false), cl::desc("Allow for a mixture of Mips16 " "and Mips32 code in a single output file"), cl::Hidden)
static cl::opt< bool > Mips16HardFloat("mips16-hard-float", cl::NotHidden, cl::desc("Enable mips16 hard float."), cl::init(false))
static cl::opt< bool > Mips_Os16("mips-os16", cl::init(false), cl::desc("Compile all functions that don't use " "floating point as Mips 16"), cl::Hidden)
static cl::opt< bool > GPOpt("mgpopt", cl::Hidden, cl::desc("Enable gp-relative addressing of mips small data items"))
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Provides the logic to select generic machine instructions.
This class provides legalization strategies.
This class provides the information for the target register banks.
const LegalizerInfo * getLegalizerInfo() const override
static bool useConstantIslands()
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
std::unique_ptr< InstructionSelector > InstSelector
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
const CallLowering * getCallLowering() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool inAbs2008Mode() const
std::unique_ptr< CallLowering > CallLoweringInfo
const MipsRegisterInfo * getRegisterInfo() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const RegisterBankInfo * getRegBankInfo() const override
bool isPositionIndependent() const
InstructionSelector * getInstructionSelector() const override
const MipsTargetLowering * getTargetLowering() const override
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
Reloc::Model getRelocationModel() const
const MipsABIInfo & getABI() const
const MipsABIInfo & getABI() const
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
bool isPositionIndependent() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Triple - Helper class for working with autoconf configuration names.
Level
Code generation optimization level.
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
InstructionSelector * createMipsInstructionSelector(const MipsTargetMachine &, MipsSubtarget &, MipsRegisterBankInfo &)
This struct is a compact representation of a valid (non-zero power of two) alignment.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.