13#ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERBANKINFO_H
18#define GET_REGBANK_DECLARATIONS
19#include "MipsGenRegisterBank.inc"
23class TargetRegisterInfo;
26#define GET_TARGET_REGBANK_CLASS
27#include "MipsGenRegisterBank.inc"
72 AmbiguousWithMergeOrUnmerge
75 bool isAmbiguous_64(InstType InstTy,
unsigned OpSize)
const {
76 if (InstTy == InstType::Ambiguous && OpSize == 64)
81 bool isAmbiguous_32(InstType InstTy,
unsigned OpSize)
const {
82 if (InstTy == InstType::Ambiguous && OpSize == 32)
87 bool isAmbiguous_32or64(InstType InstTy,
unsigned OpSize)
const {
88 if (InstTy == InstType::Ambiguous && (OpSize == 32 || OpSize == 64))
93 bool isAmbiguousWithMergeOrUnmerge_64(InstType InstTy,
94 unsigned OpSize)
const {
95 if (InstTy == InstType::AmbiguousWithMergeOrUnmerge && OpSize == 64)
100 bool isFloatingPoint_32or64(InstType InstTy,
unsigned OpSize)
const {
101 if (InstTy == InstType::FloatingPoint && (OpSize == 32 || OpSize == 64))
106 bool isFloatingPoint_64(InstType InstTy,
unsigned OpSize)
const {
107 if (InstTy == InstType::FloatingPoint && OpSize == 64)
112 bool isInteger_32(InstType InstTy,
unsigned OpSize)
const {
113 if (InstTy == InstType::Integer && OpSize == 32)
124 class AmbiguousRegDefUseContainer {
151 class TypeInfoForMF {
163 InstType &AmbiguousTy);
168 bool isDefUse, InstType &AmbiguousTy);
182 Types.try_emplace(
MI, InstType::NotDetermined);
191 const InstType &getRecordedTypeForInstr(
const MachineInstr *
MI)
const {
192 assert(wasVisited(
MI) &&
"Instruction was not visited!");
193 return Types.find(
MI)->getSecond();
197 void changeRecordedTypeForInstr(
const MachineInstr *
MI, InstType InstTy) {
198 assert(wasVisited(
MI) &&
"Instruction was not visited!");
199 Types.find(
MI)->getSecond() = InstTy;
205 assert(WaitingQueues.
count(
MI) &&
"Instruction was not visited!");
206 return WaitingQueues.
find(
MI)->getSecond();
212 assert(WaitingQueues.
count(
MI) &&
"Instruction was not visited!");
213 WaitingQueues.
find(
MI)->getSecond().push_back(WaitingForMI);
unsigned const MachineRegisterInfo * MRI
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
iterator find(const_arg_type_t< KeyT > Val)
std::pair< iterator, bool > try_emplace(KeyT &&Key, Ts &&... Args)
bool erase(const KeyT &Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This class provides the information for the target register banks.
void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const
RegBankSelect determined that s64 operand is better to be split into two s32 operands in gprb.
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
Here we have to narrowScalar s64 operands to s32, combine away G_MERGE or G_UNMERGE and erase instruc...
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Holds all the information related to register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.