LLVM  16.0.0git
MipsInstrInfo.h
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1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips implementation of the TargetInstrInfo class.
10 //
11 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
12 // order for MipsLongBranch pass to work correctly when the code has inline
13 // assembly. The returned value doesn't have to be the asm instruction's exact
14 // size in bytes; MipsLongBranch only expects it to be the correct upper bound.
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
18 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19 
21 #include "Mips.h"
22 #include "MipsRegisterInfo.h"
23 #include "llvm/ADT/ArrayRef.h"
28 #include <cstdint>
29 
30 #define GET_INSTRINFO_HEADER
31 #include "MipsGenInstrInfo.inc"
32 
33 namespace llvm {
34 
35 class MachineInstr;
36 class MachineOperand;
37 class MipsSubtarget;
38 class TargetRegisterClass;
39 class TargetRegisterInfo;
40 
42  virtual void anchor();
43 
44 protected:
46  unsigned UncondBrOpc;
47 
48 public:
49  enum BranchType {
50  BT_None, // Couldn't analyze branch.
51  BT_NoBranch, // No branches found.
52  BT_Uncond, // One unconditional branch.
53  BT_Cond, // One conditional branch.
54  BT_CondUncond, // A conditional branch followed by an unconditional branch.
55  BT_Indirect // One indirct branch.
56  };
57 
58  explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
59 
60  static const MipsInstrInfo *create(MipsSubtarget &STI);
61 
62  /// Branch Analysis
64  MachineBasicBlock *&FBB,
66  bool AllowModify) const override;
67 
69  int *BytesRemoved = nullptr) const override;
70 
73  const DebugLoc &DL,
74  int *BytesAdded = nullptr) const override;
75 
76  bool
78 
80  MachineBasicBlock *&FBB,
82  bool AllowModify,
83  SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
84 
85  /// Determine the opcode of a non-delay slot form for a branch if one exists.
87 
88  /// Determine if the branch target is in range.
89  bool isBranchOffsetInRange(unsigned BranchOpc,
90  int64_t BrOffset) const override;
91 
92  /// Predicate to determine if an instruction can go in a forbidden slot.
93  bool SafeInForbiddenSlot(const MachineInstr &MI) const;
94 
95  /// Predicate to determine if an instruction can go in an FPU delay slot.
96  bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
97  const MachineInstr &FPUMI) const;
98 
99  /// Predicate to determine if an instruction can go in a load delay slot.
100  bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
101  const MachineInstr &LoadMI) const;
102 
103  /// Predicate to determine if an instruction has a forbidden slot.
104  bool HasForbiddenSlot(const MachineInstr &MI) const;
105 
106  /// Predicate to determine if an instruction has an FPU delay slot.
107  bool HasFPUDelaySlot(const MachineInstr &MI) const;
108 
109  /// Predicate to determine if an instruction has a load delay slot.
110  bool HasLoadDelaySlot(const MachineInstr &MI) const;
111 
112  /// Insert nop instruction when hazard condition is found
114  MachineBasicBlock::iterator MI) const override;
115 
116  /// Insert an ISA appropriate `nop`.
117  // FIXME: Add support for MIPS16e.
120  DebugLoc DL) const;
121 
122  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
123  /// such, whenever a client has an instance of instruction info, it should
124  /// always be able to get register info as well (through this method).
125  virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
126 
127  virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
128 
129  virtual bool isBranchWithImm(unsigned Opc) const {
130  return false;
131  }
132 
133  /// Return the number of bytes of code the specified instruction may be.
134  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
135 
138  Register SrcReg, bool isKill, int FrameIndex,
139  const TargetRegisterClass *RC,
140  const TargetRegisterInfo *TRI) const override {
141  storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
142  }
143 
146  Register DestReg, int FrameIndex,
147  const TargetRegisterClass *RC,
148  const TargetRegisterInfo *TRI) const override {
149  loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
150  }
151 
152  virtual void storeRegToStack(MachineBasicBlock &MBB,
154  Register SrcReg, bool isKill, int FrameIndex,
155  const TargetRegisterClass *RC,
156  const TargetRegisterInfo *TRI,
157  int64_t Offset) const = 0;
158 
159  virtual void loadRegFromStack(MachineBasicBlock &MBB,
161  Register DestReg, int FrameIndex,
162  const TargetRegisterClass *RC,
163  const TargetRegisterInfo *TRI,
164  int64_t Offset) const = 0;
165 
166  virtual void adjustStackPtr(unsigned SP, int64_t Amount,
168  MachineBasicBlock::iterator I) const = 0;
169 
170  /// Create an instruction which has the same operands and memory operands
171  /// as MI but has a new opcode.
172  MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
174 
175  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
176  unsigned &SrcOpIdx2) const override;
177 
178  /// Perform target specific instruction verification.
179  bool verifyInstruction(const MachineInstr &MI,
180  StringRef &ErrInfo) const override;
181 
182  std::pair<unsigned, unsigned>
183  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
184 
187 
188  std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
189  Register Reg) const override;
190 
191  std::optional<ParamLoadedValue>
192  describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
193 
194 protected:
195  bool isZeroImm(const MachineOperand &op) const;
196 
198  MachineMemOperand::Flags Flags) const;
199 
200 private:
201  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
202 
203  void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
206 
207  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
208  const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
209 };
210 
211 /// Create MipsInstrInfo objects.
212 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
213 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
214 
215 } // end namespace llvm
216 
217 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
llvm::MipsInstrInfo::create
static const MipsInstrInfo * create(MipsSubtarget &STI)
Definition: MipsInstrInfo.cpp:44
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MipsInstrInfo::insertNop
MachineInstrBuilder insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
Insert an ISA appropriate nop.
Definition: MipsInstrInfo.cpp:64
llvm::createMipsSEInstrInfo
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
Definition: MipsSEInstrInfo.cpp:913
llvm::MipsInstrInfo::storeRegToStack
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
llvm::MipsInstrInfo::adjustStackPtr
virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
op
#define op(i)
llvm::MipsInstrInfo::BT_Indirect
@ BT_Indirect
Definition: MipsInstrInfo.h:55
llvm::MipsInstrInfo::SafeInLoadDelaySlot
bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
Predicate to determine if an instruction can go in a load delay slot.
Definition: MipsInstrInfo.cpp:616
llvm::MipsInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
Definition: MipsInstrInfo.cpp:108
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::MipsInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: MipsInstrInfo.cpp:168
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::createMips16InstrInfo
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
Definition: Mips16InstrInfo.cpp:468
llvm::MipsInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: MipsInstrInfo.cpp:771
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MipsInstrInfo::isBranchWithImm
virtual bool isBranchWithImm(unsigned Opc) const
Definition: MipsInstrInfo.h:129
llvm::MipsInstrInfo::BT_CondUncond
@ BT_CondUncond
Definition: MipsInstrInfo.h:54
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
Mips.h
llvm::MipsInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: MipsInstrInfo.cpp:134
llvm::MipsInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
Definition: MipsInstrInfo.cpp:667
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MipsInstrInfo
Definition: MipsInstrInfo.h:41
MipsRegisterInfo.h
llvm::MipsInstrInfo::getEquivalentCompactForm
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
Definition: MipsInstrInfo.cpp:452
llvm::MipsInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: MipsInstrInfo.cpp:899
llvm::MipsInstrInfo::isAddImmediate
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: MipsInstrInfo.cpp:965
llvm::MipsInstrInfo::isZeroImm
bool isZeroImm(const MachineOperand &op) const
Definition: MipsInstrInfo.cpp:51
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MipsInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
Definition: MipsInstrInfo.cpp:58
llvm::MipsInstrInfo::describeLoadedValue
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: MipsInstrInfo.cpp:937
llvm::MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: MipsInstrInfo.cpp:904
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MipsInstrInfo::SafeInFPUDelaySlot
bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
Predicate to determine if an instruction can go in an FPU delay slot.
Definition: MipsInstrInfo.cpp:584
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MipsRegisterInfo
Definition: MipsRegisterInfo.h:27
llvm::MipsInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: MipsInstrInfo.h:136
ArrayRef.h
llvm::MipsInstrInfo::genInstrWithNewOpc
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode.
Definition: MipsInstrInfo.cpp:685
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
MipsMCTargetDesc.h
llvm::MipsInstrInfo::MipsInstrInfo
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
Definition: MipsInstrInfo.cpp:40
llvm::MipsInstrInfo::BranchType
BranchType
Definition: MipsInstrInfo.h:49
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MipsInstrInfo::loadRegFromStack
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
llvm::MipsInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
Definition: MipsInstrInfo.cpp:292
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MipsInstrInfo::getOppositeBranchOpc
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
llvm::MipsInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
Definition: MipsInstrInfo.cpp:850
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsInstrInfo::HasForbiddenSlot
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
Definition: MipsInstrInfo.cpp:627
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MipsInstrInfo::HasLoadDelaySlot
bool HasLoadDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a load delay slot.
Definition: MipsInstrInfo.cpp:651
llvm::MipsInstrInfo::getRegisterInfo
virtual const MipsRegisterInfo & getRegisterInfo() const =0
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
llvm::MipsInstrInfo::BT_None
@ BT_None
Definition: MipsInstrInfo.h:50
llvm::MipsInstrInfo::SafeInForbiddenSlot
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
Definition: MipsInstrInfo.cpp:577
llvm::MipsInstrInfo::GetMemOperand
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Definition: MipsInstrInfo.cpp:79
llvm::MipsInstrInfo::BT_NoBranch
@ BT_NoBranch
Definition: MipsInstrInfo.h:51
llvm::MipsInstrInfo::BT_Uncond
@ BT_Uncond
Definition: MipsInstrInfo.h:52
llvm::MipsInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: MipsInstrInfo.h:144
MachineInstrBuilder.h
llvm::MipsInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
Definition: MipsInstrInfo.cpp:196
llvm::MipsInstrInfo::UncondBrOpc
unsigned UncondBrOpc
Definition: MipsInstrInfo.h:46
llvm::MipsInstrInfo::BT_Cond
@ BT_Cond
Definition: MipsInstrInfo.h:53
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MipsInstrInfo::HasFPUDelaySlot
bool HasFPUDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has an FPU delay slot.
Definition: MipsInstrInfo.cpp:632
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
MipsGenInstrInfo
llvm::MipsInstrInfo::Subtarget
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:45