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PPCISelLowering.h
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1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that PPC uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 
17 #include "PPCInstrInfo.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Type.h"
32 #include <utility>
33 
34 namespace llvm {
35 
36  namespace PPCISD {
37 
38  // When adding a NEW PPCISD node please add it to the correct position in
39  // the enum. The order of elements in this enum matters!
40  // Values that are added after this entry:
41  // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
42  // are considered memory opcodes and are treated differently than entries
43  // that come before it. For example, ADD or MUL should be placed before
44  // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
45  // after it.
46  enum NodeType : unsigned {
47  // Start the numbering where the builtin ops and target ops leave off.
49 
50  /// FSEL - Traditional three-operand fsel node.
51  ///
53 
54  /// XSMAXCDP, XSMINCDP - C-type min/max instructions.
57 
58  /// FCFID - The FCFID instruction, taking an f64 operand and producing
59  /// and f64 value containing the FP representation of the integer that
60  /// was temporarily in the f64 operand.
62 
63  /// Newer FCFID[US] integer-to-floating-point conversion instructions for
64  /// unsigned integers and single-precision outputs.
68 
69  /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
70  /// operand, producing an f64 value containing the integer representation
71  /// of that FP value.
74 
75  /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
76  /// unsigned integers with round toward zero.
79 
80  /// Floating-point-to-interger conversion instructions
83 
84  /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
85  /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
87 
88  /// Reciprocal estimate instructions (unary FP ops).
89  FRE,
91 
92  /// Test instruction for software square root.
94 
95  /// Square root instruction.
97 
98  /// VPERM - The PPC VPERM Instruction.
99  ///
101 
102  /// XXSPLT - The PPC VSX splat instructions
103  ///
105 
106  /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
107  /// converting immediate single precision numbers to double precision
108  /// vector or scalar.
110 
111  /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
112  ///
114 
115  /// VECINSERT - The PPC vector insert instruction
116  ///
118 
119  /// VECSHL - The PPC vector shift left instruction
120  ///
122 
123  /// XXPERMDI - The PPC XXPERMDI instruction
124  ///
126 
127  /// The CMPB instruction (takes two operands of i32 or i64).
129 
130  /// Hi/Lo - These represent the high and low 16-bit parts of a global
131  /// address respectively. These nodes have two operands, the first of
132  /// which must be a TargetGlobalAddress, and the second of which must be a
133  /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
134  /// though these are usually folded into other nodes.
135  Hi,
136  Lo,
137 
138  /// The following two target-specific nodes are used for calls through
139  /// function pointers in the 64-bit SVR4 ABI.
140 
141  /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
142  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
143  /// compute an allocation on the stack.
145 
146  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
147  /// compute an offset from native SP to the address of the most recent
148  /// dynamic alloca.
150 
151  /// To avoid stack clash, allocation is performed by block and each block is
152  /// probed.
154 
155  /// The result of the mflr at function entry, used for PIC code.
157 
158  /// These nodes represent PPC shifts.
159  ///
160  /// For scalar types, only the last `n + 1` bits of the shift amounts
161  /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
162  /// for exact behaviors.
163  ///
164  /// For vector types, only the last n bits are used. See vsld.
168 
169  /// FNMSUB - Negated multiply-subtract instruction.
171 
172  /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
173  /// word and shift left immediate.
175 
176  /// The combination of sra[wd]i and addze used to implemented signed
177  /// integer division by a power of 2. The first operand is the dividend,
178  /// and the second is the constant shift amount (representing the
179  /// divisor).
181 
182  /// CALL - A direct function call.
183  /// CALL_NOP is a call with the special NOP which follows 64-bit
184  /// CALL_NOTOC the caller does not use the TOC.
185  /// SVR4 calls and 32-bit/64-bit AIX calls.
189 
190  /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
191  /// MTCTR instruction.
193 
194  /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
195  /// BCTRL instruction.
197 
198  /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
199  /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
200  /// and 64-bit AIX.
202 
203  /// Return with a flag operand, matched by 'blr'
205 
206  /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
207  /// This copies the bits corresponding to the specified CRREG into the
208  /// resultant GPR. Bits corresponding to other CR regs are undefined.
210 
211  /// Direct move from a VSX register to a GPR
213 
214  /// Direct move from a GPR to a VSX register (algebraic)
216 
217  /// Direct move from a GPR to a VSX register (zero)
219 
220  /// Direct move of 2 consecutive GPR to a VSX register.
222 
223  /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
224  /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
225  /// unsupported for this target.
226  /// Merge 2 GPRs to a single SPE register.
228 
229  /// Extract SPE register component, second argument is high or low.
231 
232  /// Extract a subvector from signed integer vector and convert to FP.
233  /// It is primarily used to convert a (widened) illegal integer vector
234  /// type to a legal floating point vector type.
235  /// For example v2i32 -> widened to v4i32 -> v2f64
237 
238  /// Extract a subvector from unsigned integer vector and convert to FP.
239  /// As with SINT_VEC_TO_FP, used for converting illegal types.
241 
242  /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to
243  /// place the value into the least significant element of the most
244  /// significant doubleword in the vector. This is not element zero for
245  /// anything smaller than a doubleword on either endianness. This node has
246  /// the same semantics as SCALAR_TO_VECTOR except that the value remains in
247  /// the aforementioned location in the vector register.
249 
250  // FIXME: Remove these once the ANDI glue bug is fixed:
251  /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
252  /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
253  /// implement truncation of i32 or i64 to i1.
256 
257  // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
258  // target (returns (Lo, Hi)). It takes a chain operand.
260 
261  // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
263 
264  // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
266 
267  /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
268  /// instructions. For lack of better number, we use the opcode number
269  /// encoding for the OPC field to identify the compare. For example, 838
270  /// is VCMPGTSH.
272 
273  /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
274  /// altivec VCMP*_rec instructions. For lack of better number, we use the
275  /// opcode number encoding for the OPC field to identify the compare. For
276  /// example, 838 is VCMPGTSH.
278 
279  /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
280  /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
281  /// condition register to branch on, OPC is the branch opcode to use (e.g.
282  /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
283  /// an optional input flag argument.
285 
286  /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
287  /// loops.
290 
291  /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
292  /// towards zero. Used only as part of the long double-to-int
293  /// conversion sequence.
295 
296  /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
298 
299  /// TC_RETURN - A tail call return.
300  /// operand #0 chain
301  /// operand #1 callee (register or absolute)
302  /// operand #2 stack adjustment
303  /// operand #3 optional in flag
305 
306  /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
309 
310  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
311  /// for non-position independent code on PPC32.
313 
314  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
315  /// local dynamic TLS and position indendepent code on PPC32.
317 
318  /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
319  /// TLS model, produces an ADDIS8 instruction that adds the GOT
320  /// base to sym\@got\@tprel\@ha.
322 
323  /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
324  /// TLS model, produces a LD instruction with base register G8RReg
325  /// and offset sym\@got\@tprel\@l. This completes the addition that
326  /// finds the offset of "sym" relative to the thread pointer.
328 
329  /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
330  /// model, produces an ADD instruction that adds the contents of
331  /// G8RReg to the thread pointer. Symbol contains a relocation
332  /// sym\@tls which is to be replaced by the thread pointer and
333  /// identifies to the linker that the instruction is part of a
334  /// TLS sequence.
336 
337  /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
338  /// model, produces an ADDIS8 instruction that adds the GOT base
339  /// register to sym\@got\@tlsgd\@ha.
341 
342  /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
343  /// model, produces an ADDI8 instruction that adds G8RReg to
344  /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
345  /// ADDIS_TLSGD_L_ADDR until after register assignment.
347 
348  /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
349  /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
350  /// ADDIS_TLSGD_L_ADDR until after register assignment.
352 
353  /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
354  /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
355  /// register assignment.
357 
358  /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
359  /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
360  /// Op that combines two register copies of TOC entries
361  /// (region handle into R3 and variable offset into R4) followed by a
362  /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr.
363  /// This node is used in 64-bit mode as well (in which case the result is
364  /// G8RC and inputs are X3/X4).
366 
367  /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
368  /// model, produces an ADDIS8 instruction that adds the GOT base
369  /// register to sym\@got\@tlsld\@ha.
371 
372  /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
373  /// model, produces an ADDI8 instruction that adds G8RReg to
374  /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
375  /// ADDIS_TLSLD_L_ADDR until after register assignment.
377 
378  /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
379  /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
380  /// ADDIS_TLSLD_L_ADDR until after register assignment.
382 
383  /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
384  /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
385  /// following register assignment.
387 
388  /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
389  /// model, produces an ADDIS8 instruction that adds X3 to
390  /// sym\@dtprel\@ha.
392 
393  /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
394  /// model, produces an ADDI8 instruction that adds G8RReg to
395  /// sym\@got\@dtprel\@l.
397 
398  /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
399  /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.
401 
402  /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
403  /// during instruction selection to optimize a BUILD_VECTOR into
404  /// operations on splats. This is necessary to avoid losing these
405  /// optimizations due to constant folding.
407 
408  /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
409  /// operand identifies the operating system entry point.
410  SC,
411 
412  /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
414 
415  /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
416  /// history rolling buffer entry.
418 
419  /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
421 
422  /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
423  /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
424  /// or stxvd2x instruction. The chain is necessary because the
425  /// sequence replaces a load and needs to provide the same number
426  /// of outputs.
428 
429  /// An SDNode for swaps that are not associated with any loads/stores
430  /// and thereby have no chain.
432 
433  /// An SDNode for Power9 vector absolute value difference.
434  /// operand #0 vector
435  /// operand #1 vector
436  /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
437  /// the most significant bit for signed i32
438  ///
439  /// Power9 VABSD* instructions are designed to support unsigned integer
440  /// vectors (byte/halfword/word), if we want to make use of them for signed
441  /// integer vectors, we have to flip their sign bits first. To flip sign bit
442  /// for byte/halfword integer vector would become inefficient, but for word
443  /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
444  /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
445  /// => VABSDUW((XVNEGSP a), (XVNEGSP b))
447 
448  /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
449  /// lower (IDX=1) half of v4f32 to v2f64.
451 
452  /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
453  /// either through an add like PADDI or through a PC Relative load like
454  /// PLD.
456 
457  /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for
458  /// TLS global address when using dynamic access models. This can be done
459  /// through an add like PADDI.
461 
462  /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address
463  /// when using local exec access models, and when prefixed instructions are
464  /// available. This is used with ADD_TLS to produce an add like PADDI.
466 
467  /// ACC_BUILD = Build an accumulator register from 4 VSX registers.
469 
470  /// PAIR_BUILD = Build a vector pair register from 2 VSX registers.
472 
473  /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of
474  /// an accumulator or pair register. This node is needed because
475  /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same
476  /// element type.
478 
479  /// XXMFACC = This corresponds to the xxmfacc instruction.
481 
482  // Constrained conversion from floating point to int
487 
488  /// Constrained integer-to-floating-point conversion instructions.
493 
494  /// Constrained floating point add in round-to-zero mode.
496 
497  // NOTE: The nodes below may require PC-Rel specific patterns if the
498  // address could be PC-Relative. When adding new nodes below, consider
499  // whether or not the address can be PC-Relative and add the corresponding
500  // PC-relative patterns and tests.
501 
502  /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
503  /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
504  /// the GPRC input, then stores it through Ptr. Type can be either i16 or
505  /// i32.
507 
508  /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
509  /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
510  /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
511  /// or i32.
513 
514  /// STFIWX - The STFIWX instruction. The first operand is an input token
515  /// chain, then an f64 value to store, then an address to store it to.
517 
518  /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
519  /// load which sign-extends from a 32-bit integer value into the
520  /// destination 64-bit register.
522 
523  /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
524  /// load which zero-extends from a 32-bit integer value into the
525  /// destination 64-bit register.
527 
528  /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
529  /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
530  /// This can be used for converting loaded integers to floating point.
532 
533  /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
534  /// chain, then an f64 value to store, then an address to store it to,
535  /// followed by a byte-width for the store.
537 
538  /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
539  /// Maps directly to an lxvd2x instruction that will be followed by
540  /// an xxswapd.
542 
543  /// LXVRZX - Load VSX Vector Rightmost and Zero Extend
544  /// This node represents v1i128 BUILD_VECTOR of a zero extending load
545  /// instruction from <byte, halfword, word, or doubleword> to i128.
546  /// Allows utilization of the Load VSX Vector Rightmost Instructions.
548 
549  /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
550  /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
551  /// the vector type to load vector in big-endian element order.
553 
554  /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
555  /// v2f32 value into the lower half of a VSR register.
557 
558  /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
559  /// instructions such as LXVDSX, LXVWSX.
561 
562  /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
563  /// Maps directly to an stxvd2x instruction that will be preceded by
564  /// an xxswapd.
566 
567  /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
568  /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
569  /// the vector type to store vector in big-endian element order.
571 
572  /// Store scalar integers from VSR.
574 
575  /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
576  /// except they ensure that the compare input is zero-extended for
577  /// sub-word versions because the atomic loads zero-extend.
580 
581  /// GPRC = TOC_ENTRY GA, TOC
582  /// Loads the entry for GA from the TOC, where the TOC base is given by
583  /// the last operand.
585  };
586 
587  } // end namespace PPCISD
588 
589  /// Define some predicates that are used for node matching.
590  namespace PPC {
591 
592  /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
593  /// VPKUHUM instruction.
594  bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
595  SelectionDAG &DAG);
596 
597  /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
598  /// VPKUWUM instruction.
599  bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
600  SelectionDAG &DAG);
601 
602  /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
603  /// VPKUDUM instruction.
604  bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
605  SelectionDAG &DAG);
606 
607  /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
608  /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
609  bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
610  unsigned ShuffleKind, SelectionDAG &DAG);
611 
612  /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
613  /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
614  bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
615  unsigned ShuffleKind, SelectionDAG &DAG);
616 
617  /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
618  /// a VMRGEW or VMRGOW instruction
619  bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
620  unsigned ShuffleKind, SelectionDAG &DAG);
621  /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
622  /// for a XXSLDWI instruction.
623  bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
624  bool &Swap, bool IsLE);
625 
626  /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
627  /// for a XXBRH instruction.
628  bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
629 
630  /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
631  /// for a XXBRW instruction.
632  bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
633 
634  /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
635  /// for a XXBRD instruction.
636  bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
637 
638  /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
639  /// for a XXBRQ instruction.
640  bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
641 
642  /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
643  /// for a XXPERMDI instruction.
644  bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
645  bool &Swap, bool IsLE);
646 
647  /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
648  /// shift amount, otherwise return -1.
649  int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
650  SelectionDAG &DAG);
651 
652  /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
653  /// specifies a splat of a single element that is suitable for input to
654  /// VSPLTB/VSPLTH/VSPLTW.
655  bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
656 
657  /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
658  /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
659  /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
660  /// vector into the other. This function will also set a couple of
661  /// output parameters for how much the source vector needs to be shifted and
662  /// what byte number needs to be specified for the instruction to put the
663  /// element in the desired location of the target vector.
664  bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
665  unsigned &InsertAtByte, bool &Swap, bool IsLE);
666 
667  /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
668  /// appropriate for PPC mnemonics (which have a big endian bias - namely
669  /// elements are counted from the left of the vector register).
670  unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
671  SelectionDAG &DAG);
672 
673  /// get_VSPLTI_elt - If this is a build_vector of constants which can be
674  /// formed by using a vspltis[bhw] instruction of the specified element
675  /// size, return the constant being splatted. The ByteSize field indicates
676  /// the number of bytes of each element [124] -> [bhw].
677  SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
678 
679  // Flags for computing the optimal addressing mode for loads and stores.
680  enum MemOpFlags {
681  MOF_None = 0,
682 
683  // Extension mode for integer loads.
684  MOF_SExt = 1,
685  MOF_ZExt = 1 << 1,
686  MOF_NoExt = 1 << 2,
687 
688  // Address computation flags.
689  MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar.
690  MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant.
691  MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation
692  MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4.
693  MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16.
694  MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant.
695  MOF_RPlusR = 1 << 11, // Sum of two variables.
696  MOF_PCRel = 1 << 12, // PC-Relative relocation.
697  MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant.
698 
699  // The in-memory type.
700  MOF_SubWordInt = 1 << 15,
701  MOF_WordInt = 1 << 16,
702  MOF_DoubleWordInt = 1 << 17,
703  MOF_ScalarFloat = 1 << 18, // Scalar single or double precision.
704  MOF_Vector = 1 << 19, // Vector types and quad precision scalars.
705  MOF_Vector256 = 1 << 20,
706 
707  // Subtarget features.
709  MOF_SubtargetP9 = 1 << 23,
710  MOF_SubtargetP10 = 1 << 24,
712  };
713 
714  // The addressing modes for loads and stores.
715  enum AddrMode {
723  };
724  } // end namespace PPC
725 
727  const PPCSubtarget &Subtarget;
728 
729  public:
730  explicit PPCTargetLowering(const PPCTargetMachine &TM,
731  const PPCSubtarget &STI);
732 
733  /// getTargetNodeName() - This method returns the name of a target specific
734  /// DAG node.
735  const char *getTargetNodeName(unsigned Opcode) const override;
736 
737  bool isSelectSupported(SelectSupportKind Kind) const override {
738  // PowerPC does not support scalar condition selects on vectors.
739  return (Kind != SelectSupportKind::ScalarCondVectorVal);
740  }
741 
742  /// getPreferredVectorAction - The code we generate when vector types are
743  /// legalized by promoting the integer element type is often much worse
744  /// than code we generate if we widen the type for applicable vector types.
745  /// The issue with promoting is that the vector is scalaraized, individual
746  /// elements promoted and then the vector is rebuilt. So say we load a pair
747  /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
748  /// loads, moves back into VSR's (or memory ops if we don't have moves) and
749  /// then the VPERM for the shuffle. All in all a very slow sequence.
751  const override {
752  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
753  VT.getScalarSizeInBits() % 8 == 0)
754  return TypeWidenVector;
756  }
757 
758  bool useSoftFloat() const override;
759 
760  bool hasSPE() const;
761 
762  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
763  return MVT::i32;
764  }
765 
766  bool isCheapToSpeculateCttz() const override {
767  return true;
768  }
769 
770  bool isCheapToSpeculateCtlz() const override {
771  return true;
772  }
773 
774  bool isCtlzFast() const override {
775  return true;
776  }
777 
778  bool isEqualityCmpFoldedWithSignedCmp() const override {
779  return false;
780  }
781 
782  bool hasAndNotCompare(SDValue) const override {
783  return true;
784  }
785 
786  bool preferIncOfAddToSubOfNot(EVT VT) const override;
787 
788  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
789  return VT.isScalarInteger();
790  }
791 
792  SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
793  bool OptForSize, NegatibleCost &Cost,
794  unsigned Depth = 0) const override;
795 
796  /// getSetCCResultType - Return the ISD::SETCC ValueType
798  EVT VT) const override;
799 
800  /// Return true if target always benefits from combining into FMA for a
801  /// given value type. This must typically return false on targets where FMA
802  /// takes more cycles to execute than FADD.
803  bool enableAggressiveFMAFusion(EVT VT) const override;
804 
805  /// getPreIndexedAddressParts - returns true by value, base pointer and
806  /// offset pointer and addressing mode by reference if the node's address
807  /// can be legally represented as pre-indexed load / store address.
809  SDValue &Offset,
811  SelectionDAG &DAG) const override;
812 
813  /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
814  /// it can be more efficiently represented as [r+imm].
816  SelectionDAG &DAG) const;
817 
818  /// SelectAddressRegReg - Given the specified addressed, check to see if it
819  /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
820  /// is non-zero, only accept displacement which is not suitable for [r+imm].
821  /// Returns false if it can be represented by [r+imm], which are preferred.
823  SelectionDAG &DAG,
824  MaybeAlign EncodingAlignment = None) const;
825 
826  /// SelectAddressRegImm - Returns true if the address N can be represented
827  /// by a base register plus a signed 16-bit displacement [r+imm], and if it
828  /// is not better represented as reg+reg. If \p EncodingAlignment is
829  /// non-zero, only accept displacements suitable for instruction encoding
830  /// requirement, i.e. multiples of 4 for DS form.
832  SelectionDAG &DAG,
833  MaybeAlign EncodingAlignment) const;
835  SelectionDAG &DAG) const;
836 
837  /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
838  /// represented as an indexed [r+r] operation.
840  SelectionDAG &DAG) const;
841 
842  /// SelectAddressPCRel - Represent the specified address as pc relative to
843  /// be represented as [pc+imm]
844  bool SelectAddressPCRel(SDValue N, SDValue &Base) const;
845 
847 
848  /// LowerOperation - Provide custom lowering hooks for some operations.
849  ///
850  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
851 
852  /// ReplaceNodeResults - Replace the results of node with an illegal result
853  /// type with new values built out of custom code.
854  ///
856  SelectionDAG &DAG) const override;
857 
858  SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
859  SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
860 
861  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
862 
863  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
864  SmallVectorImpl<SDNode *> &Created) const override;
865 
866  Register getRegisterByName(const char* RegName, LLT VT,
867  const MachineFunction &MF) const override;
868 
870  KnownBits &Known,
871  const APInt &DemandedElts,
872  const SelectionDAG &DAG,
873  unsigned Depth = 0) const override;
874 
875  Align getPrefLoopAlignment(MachineLoop *ML) const override;
876 
877  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
878  return true;
879  }
880 
882  AtomicOrdering Ord) const override;
884  AtomicOrdering Ord) const override;
885 
887  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
888 
891 
893  AtomicRMWInst *AI, Value *AlignedAddr,
894  Value *Incr, Value *Mask,
895  Value *ShiftAmt,
896  AtomicOrdering Ord) const override;
898  AtomicCmpXchgInst *CI,
899  Value *AlignedAddr, Value *CmpVal,
900  Value *NewVal, Value *Mask,
901  AtomicOrdering Ord) const override;
902 
905  MachineBasicBlock *MBB) const override;
908  unsigned AtomicSize,
909  unsigned BinOpcode,
910  unsigned CmpOpcode = 0,
911  unsigned CmpPred = 0) const;
914  bool is8bit,
915  unsigned Opcode,
916  unsigned CmpOpcode = 0,
917  unsigned CmpPred = 0) const;
918 
920  MachineBasicBlock *MBB) const;
921 
923  MachineBasicBlock *MBB) const;
924 
926  MachineBasicBlock *MBB) const;
927 
928  bool hasInlineStackProbe(MachineFunction &MF) const override;
929 
930  unsigned getStackProbeSize(MachineFunction &MF) const;
931 
932  ConstraintType getConstraintType(StringRef Constraint) const override;
933 
934  /// Examine constraint string and operand type and determine a weight value.
935  /// The operand object must already have been set up with the operand type.
937  AsmOperandInfo &info, const char *constraint) const override;
938 
939  std::pair<unsigned, const TargetRegisterClass *>
941  StringRef Constraint, MVT VT) const override;
942 
943  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
944  /// function arguments in the caller parameter area. This is the actual
945  /// alignment, not its logarithm.
947  const DataLayout &DL) const override;
948 
949  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
950  /// vector. If it is invalid, don't add anything to Ops.
952  std::string &Constraint,
953  std::vector<SDValue> &Ops,
954  SelectionDAG &DAG) const override;
955 
956  unsigned
957  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
958  if (ConstraintCode == "es")
960  else if (ConstraintCode == "Q")
962  else if (ConstraintCode == "Z")
964  else if (ConstraintCode == "Zy")
966  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
967  }
968 
969  /// isLegalAddressingMode - Return true if the addressing mode represented
970  /// by AM is legal for this target, for a load/store of the specified type.
971  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
972  Type *Ty, unsigned AS,
973  Instruction *I = nullptr) const override;
974 
975  /// isLegalICmpImmediate - Return true if the specified immediate is legal
976  /// icmp immediate, that is the target has icmp instructions which can
977  /// compare a register against the immediate without having to materialize
978  /// the immediate into a register.
979  bool isLegalICmpImmediate(int64_t Imm) const override;
980 
981  /// isLegalAddImmediate - Return true if the specified immediate is legal
982  /// add immediate, that is the target has add instructions which can
983  /// add a register and the immediate without having to materialize
984  /// the immediate into a register.
985  bool isLegalAddImmediate(int64_t Imm) const override;
986 
987  /// isTruncateFree - Return true if it's free to truncate a value of
988  /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
989  /// register X1 to i32 by referencing its sub-register R1.
990  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
991  bool isTruncateFree(EVT VT1, EVT VT2) const override;
992 
993  bool isZExtFree(SDValue Val, EVT VT2) const override;
994 
995  bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
996 
997  /// Returns true if it is beneficial to convert a load of a constant
998  /// to just the constant itself.
1000  Type *Ty) const override;
1001 
1002  bool convertSelectOfConstantsToMath(EVT VT) const override {
1003  return true;
1004  }
1005 
1007  SDValue C) const override;
1008 
1010  EVT VT) const override {
1011  // Only handle float load/store pair because float(fpr) load/store
1012  // instruction has more cycles than integer(gpr) load/store in PPC.
1013  if (Opc != ISD::LOAD && Opc != ISD::STORE)
1014  return false;
1015  if (VT != MVT::f32 && VT != MVT::f64)
1016  return false;
1017 
1018  return true;
1019  }
1020 
1021  // Returns true if the address of the global is stored in TOC entry.
1022  bool isAccessedAsGotIndirect(SDValue N) const;
1023 
1024  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
1025 
1026  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
1027  const CallInst &I,
1028  MachineFunction &MF,
1029  unsigned Intrinsic) const override;
1030 
1031  /// It returns EVT::Other if the type should be determined using generic
1032  /// target-independent logic.
1034  const AttributeList &FuncAttributes) const override;
1035 
1036  /// Is unaligned memory access allowed for the given type, and is it fast
1037  /// relative to software emulation.
1039  EVT VT, unsigned AddrSpace, Align Alignment = Align(1),
1041  bool *Fast = nullptr) const override;
1042 
1043  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
1044  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
1045  /// expanded to FMAs when this method returns true, otherwise fmuladd is
1046  /// expanded to fmul + fadd.
1048  EVT VT) const override;
1049 
1050  bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
1051 
1052  /// isProfitableToHoist - Check if it is profitable to hoist instruction
1053  /// \p I to its dominator block.
1054  /// For example, it is not profitable if \p I and it's only user can form a
1055  /// FMA instruction, because Powerpc prefers FMADD.
1056  bool isProfitableToHoist(Instruction *I) const override;
1057 
1058  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1059 
1060  // Should we expand the build vector with shuffles?
1061  bool
1063  unsigned DefinedValues) const override;
1064 
1065  // Keep the zero-extensions for arguments to libcalls.
1066  bool shouldKeepZExtForFP16Conv() const override { return true; }
1067 
1068  /// createFastISel - This method returns a target-specific FastISel object,
1069  /// or null if the target does not support "fast" instruction selection.
1071  const TargetLibraryInfo *LibInfo) const override;
1072 
1073  /// Returns true if an argument of type Ty needs to be passed in a
1074  /// contiguous block of registers in calling convention CallConv.
1076  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
1077  const DataLayout &DL) const override {
1078  // We support any array type as "consecutive" block in the parameter
1079  // save area. The element type defines the alignment requirement and
1080  // whether the argument should go in GPRs, FPRs, or VRs if available.
1081  //
1082  // Note that clang uses this capability both to implement the ELFv2
1083  // homogeneous float/vector aggregate ABI, and to avoid having to use
1084  // "byval" when passing aggregates that might fully fit in registers.
1085  return Ty->isArrayTy();
1086  }
1087 
1088  /// If a physical register, this returns the register that receives the
1089  /// exception address on entry to an EH pad.
1090  Register
1091  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1092 
1093  /// If a physical register, this returns the register that receives the
1094  /// exception typeid on entry to a landing pad.
1095  Register
1096  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1097 
1098  /// Override to support customized stack guard loading.
1099  bool useLoadStackGuardNode() const override;
1100  void insertSSPDeclarations(Module &M) const override;
1101  Value *getSDagStackGuard(const Module &M) const override;
1102 
1103  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1104  bool ForCodeSize) const override;
1105 
1106  unsigned getJumpTableEncoding() const override;
1107  bool isJumpTableRelative() const override;
1109  SelectionDAG &DAG) const override;
1111  unsigned JTI,
1112  MCContext &Ctx) const override;
1113 
1114  /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode),
1115  /// compute the address flags of the node, get the optimal address mode
1116  /// based on the flags, and set the Base and Disp based on the address mode.
1118  SDValue &Disp, SDValue &Base,
1119  SelectionDAG &DAG,
1120  MaybeAlign Align) const;
1121  /// SelectForceXFormMode - Given the specified address, force it to be
1122  /// represented as an indexed [r+r] operation (an XForm instruction).
1124  SelectionDAG &DAG) const;
1125 
1126  /// Structure that collects some common arguments that get passed around
1127  /// between the functions for call lowering.
1128  struct CallFlags {
1130  const bool IsTailCall : 1;
1131  const bool IsVarArg : 1;
1132  const bool IsPatchPoint : 1;
1133  const bool IsIndirect : 1;
1134  const bool HasNest : 1;
1135  const bool NoMerge : 1;
1136 
1138  bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
1142  };
1143 
1144  CCAssignFn *ccAssignFnForCall(CallingConv::ID CC, bool Return,
1145  bool IsVarArg) const;
1146 
1147  private:
1148  struct ReuseLoadInfo {
1149  SDValue Ptr;
1150  SDValue Chain;
1151  SDValue ResChain;
1152  MachinePointerInfo MPI;
1153  bool IsDereferenceable = false;
1154  bool IsInvariant = false;
1155  Align Alignment;
1156  AAMDNodes AAInfo;
1157  const MDNode *Ranges = nullptr;
1158 
1159  ReuseLoadInfo() = default;
1160 
1161  MachineMemOperand::Flags MMOFlags() const {
1163  if (IsDereferenceable)
1165  if (IsInvariant)
1167  return F;
1168  }
1169  };
1170 
1171  // Map that relates a set of common address flags to PPC addressing modes.
1172  std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap;
1173  void initializeAddrModeMap();
1174 
1175  bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
1176  SelectionDAG &DAG,
1177  ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
1178  void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
1179  SelectionDAG &DAG) const;
1180 
1181  void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
1182  SelectionDAG &DAG, const SDLoc &dl) const;
1183  SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
1184  const SDLoc &dl) const;
1185 
1186  bool directMoveIsProfitable(const SDValue &Op) const;
1187  SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
1188  const SDLoc &dl) const;
1189 
1190  SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
1191  const SDLoc &dl) const;
1192 
1193  SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
1194 
1195  SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
1196  SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
1197 
1198  bool
1199  IsEligibleForTailCallOptimization(SDValue Callee,
1200  CallingConv::ID CalleeCC,
1201  bool isVarArg,
1202  const SmallVectorImpl<ISD::InputArg> &Ins,
1203  SelectionDAG& DAG) const;
1204 
1205  bool IsEligibleForTailCallOptimization_64SVR4(
1206  SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB,
1207  bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
1208  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1209 
1210  SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
1211  SDValue Chain, SDValue &LROpOut,
1212  SDValue &FPOpOut,
1213  const SDLoc &dl) const;
1214 
1215  SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1216 
1217  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1218  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1219  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1220  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1221  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1222  SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const;
1223  SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
1224  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1225  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1226  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1227  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1228  SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1229  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
1230  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1231  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1232  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1233  SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1234  SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1235  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1236  SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1237  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1238  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1239  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1240  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1241  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1242  const SDLoc &dl) const;
1243  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1244  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1245  SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1246  SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1247  SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1248  SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
1249  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1250  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1251  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1252  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1253  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1254  SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1255  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1256  SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;
1257  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1258  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1259  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1260  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1261  SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
1262 
1263  SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1264  SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1265 
1266  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1267  CallingConv::ID CallConv, bool isVarArg,
1268  const SmallVectorImpl<ISD::InputArg> &Ins,
1269  const SDLoc &dl, SelectionDAG &DAG,
1270  SmallVectorImpl<SDValue> &InVals) const;
1271 
1272  SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
1273  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1274  SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1275  SDValue &Callee, int SPDiff, unsigned NumBytes,
1276  const SmallVectorImpl<ISD::InputArg> &Ins,
1277  SmallVectorImpl<SDValue> &InVals,
1278  const CallBase *CB) const;
1279 
1280  SDValue
1281  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1282  const SmallVectorImpl<ISD::InputArg> &Ins,
1283  const SDLoc &dl, SelectionDAG &DAG,
1284  SmallVectorImpl<SDValue> &InVals) const override;
1285 
1286  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1287  SmallVectorImpl<SDValue> &InVals) const override;
1288 
1289  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1290  bool isVarArg,
1291  const SmallVectorImpl<ISD::OutputArg> &Outs,
1292  LLVMContext &Context) const override;
1293 
1294  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1295  const SmallVectorImpl<ISD::OutputArg> &Outs,
1296  const SmallVectorImpl<SDValue> &OutVals,
1297  const SDLoc &dl, SelectionDAG &DAG) const override;
1298 
1299  SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1300  SelectionDAG &DAG, SDValue ArgVal,
1301  const SDLoc &dl) const;
1302 
1303  SDValue LowerFormalArguments_AIX(
1304  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1305  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1306  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1307  SDValue LowerFormalArguments_64SVR4(
1308  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1309  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1310  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1311  SDValue LowerFormalArguments_32SVR4(
1312  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1313  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1314  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1315 
1316  SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1317  SDValue CallSeqStart,
1318  ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1319  const SDLoc &dl) const;
1320 
1321  SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1322  const SmallVectorImpl<ISD::OutputArg> &Outs,
1323  const SmallVectorImpl<SDValue> &OutVals,
1324  const SmallVectorImpl<ISD::InputArg> &Ins,
1325  const SDLoc &dl, SelectionDAG &DAG,
1326  SmallVectorImpl<SDValue> &InVals,
1327  const CallBase *CB) const;
1328  SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1329  const SmallVectorImpl<ISD::OutputArg> &Outs,
1330  const SmallVectorImpl<SDValue> &OutVals,
1331  const SmallVectorImpl<ISD::InputArg> &Ins,
1332  const SDLoc &dl, SelectionDAG &DAG,
1333  SmallVectorImpl<SDValue> &InVals,
1334  const CallBase *CB) const;
1335  SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags,
1336  const SmallVectorImpl<ISD::OutputArg> &Outs,
1337  const SmallVectorImpl<SDValue> &OutVals,
1338  const SmallVectorImpl<ISD::InputArg> &Ins,
1339  const SDLoc &dl, SelectionDAG &DAG,
1340  SmallVectorImpl<SDValue> &InVals,
1341  const CallBase *CB) const;
1342 
1343  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1344  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1345  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1346 
1347  SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1348  SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1349  SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1350  SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1351  SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1352  SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1353  SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1354  SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1355  SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1356  SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1357  SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
1358  SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1359  SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1360  SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1361  SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1362  SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
1363  SelectionDAG &DAG) const;
1364  SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1365  DAGCombinerInfo &DCI) const;
1366 
1367  /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1368  /// SETCC with integer subtraction when (1) there is a legal way of doing it
1369  /// (2) keeping the result of comparison in GPR has performance benefit.
1370  SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1371 
1372  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1373  int &RefinementSteps, bool &UseOneConstNR,
1374  bool Reciprocal) const override;
1375  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1376  int &RefinementSteps) const override;
1377  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1378  const DenormalMode &Mode) const override;
1379  SDValue getSqrtResultForDenormInput(SDValue Operand,
1380  SelectionDAG &DAG) const override;
1381  unsigned combineRepeatedFPDivisors() const override;
1382 
1383  SDValue
1384  combineElementTruncationToVectorTruncation(SDNode *N,
1385  DAGCombinerInfo &DCI) const;
1386 
1387  /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1388  /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1389  /// essentially any shuffle of v8i16 vectors that just inserts one element
1390  /// from one vector into the other.
1391  SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1392 
1393  /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1394  /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1395  /// essentially v16i8 vector version of VINSERTH.
1396  SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1397 
1398  /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
1399  /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1.
1400  SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1401 
1402  // Return whether the call instruction can potentially be optimized to a
1403  // tail call. This will cause the optimizers to attempt to move, or
1404  // duplicate return instructions to help enable tail call optimizations.
1405  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1406  bool hasBitPreservingFPLogic(EVT VT) const override;
1407  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1408 
1409  /// getAddrModeForFlags - Based on the set of address flags, select the most
1410  /// optimal instruction format to match by.
1411  PPC::AddrMode getAddrModeForFlags(unsigned Flags) const;
1412 
1413  /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute
1414  /// the address flags of the load/store instruction that is to be matched.
1415  /// The address flags are stored in a map, which is then searched
1416  /// through to determine the optimal load/store instruction format.
1417  unsigned computeMOFlags(const SDNode *Parent, SDValue N,
1418  SelectionDAG &DAG) const;
1419  }; // end class PPCTargetLowering
1420 
1421  namespace PPC {
1422 
1423  FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1424  const TargetLibraryInfo *LibInfo);
1425 
1426  } // end namespace PPC
1427 
1428  bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1429  bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1430  bool isIntS34Immediate(SDNode *N, int64_t &Imm);
1431  bool isIntS34Immediate(SDValue Op, int64_t &Imm);
1432 
1433  bool convertToNonDenormSingle(APInt &ArgAPInt);
1434  bool convertToNonDenormSingle(APFloat &ArgAPFloat);
1435  bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat);
1436 
1437 } // end namespace llvm
1438 
1439 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
llvm::PPCISD::READ_TIME_BASE
@ READ_TIME_BASE
Definition: PPCISelLowering.h:259
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:438
llvm::PPCISD::MTCTR
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
Definition: PPCISelLowering.h:192
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:495
ValueTypes.h
llvm::PPC::isXXINSERTWMask
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
Definition: PPCISelLowering.cpp:2173
llvm::InlineAsm::Constraint_Zy
@ Constraint_Zy
Definition: InlineAsm.h:265
llvm::PPCTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: PPCISelLowering.cpp:3134
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1310
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::PPCTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: PPCISelLowering.cpp:3119
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::PPC::isXXSLDWIShuffleMask
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
Definition: PPCISelLowering.cpp:2248
llvm::PPCISD::FCTIDZ
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Definition: PPCISelLowering.h:72
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::PPCISD::FSQRT
@ FSQRT
Square root instruction.
Definition: PPCISelLowering.h:96
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::PPCTargetLowering::CallFlags::NoMerge
const bool NoMerge
Definition: PPCISelLowering.h:1135
llvm::PPCISD::BDNZ
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
Definition: PPCISelLowering.h:288
llvm::PPCISD::RFEBB
@ RFEBB
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
Definition: PPCISelLowering.h:420
Metadata.h
llvm::PPC::isXXBRDShuffleMask
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
Definition: PPCISelLowering.cpp:2331
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4155
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1341
llvm::PPCTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Definition: PPCISelLowering.cpp:2935
llvm::PPCISD::FP_EXTEND_HALF
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
Definition: PPCISelLowering.h:450
llvm::PPC::AM_PrefixDForm
@ AM_PrefixDForm
Definition: PPCISelLowering.h:720
llvm::PPCISD::VABSD
@ VABSD
An SDNode for Power9 vector absolute value difference.
Definition: PPCISelLowering.h:446
llvm::isIntS34Immediate
bool isIntS34Immediate(SDNode *N, int64_t &Imm)
isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...
Definition: PPCISelLowering.cpp:2575
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Function
Definition: Function.h:62
llvm::PPCISD::CLRBHRB
@ CLRBHRB
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
Definition: PPCISelLowering.h:413
llvm::PPCTargetLowering::shouldKeepZExtForFP16Conv
bool shouldKeepZExtForFP16Conv() const override
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
Definition: PPCISelLowering.h:1066
llvm::PPC::AM_DForm
@ AM_DForm
Definition: PPCISelLowering.h:717
llvm::PPC::MOF_SubtargetP9
@ MOF_SubtargetP9
Definition: PPCISelLowering.h:709
llvm::PPCTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
Definition: PPCISelLowering.h:750
llvm::PPCTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: PPCISelLowering.cpp:17721
llvm::PPCTargetLowering::SelectAddressRegReg
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=None) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
Definition: PPCISelLowering.cpp:2592
llvm::InlineAsm::Constraint_Z
@ Constraint_Z
Definition: InlineAsm.h:263
InlineAsm.h
llvm::PPCTargetLowering::isAccessedAsGotIndirect
bool isAccessedAsGotIndirect(SDValue N) const
Definition: PPCISelLowering.cpp:16168
llvm::PPCISD::MTVSRA
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
Definition: PPCISelLowering.h:215
llvm::PPCTargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: PPCISelLowering.h:774
llvm::PPC::AM_None
@ AM_None
Definition: PPCISelLowering.h:716
llvm::PPC::MOF_NotAddNorCst
@ MOF_NotAddNorCst
Definition: PPCISelLowering.h:689
llvm::PPCISD::MAT_PCREL_ADDR
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
Definition: PPCISelLowering.h:455
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::PPCISD::ACC_BUILD
@ ACC_BUILD
ACC_BUILD = Build an accumulator register from 4 VSX registers.
Definition: PPCISelLowering.h:468
llvm::PPCTargetLowering::expandVSXLoadForLE
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: PPCISelLowering.cpp:14327
llvm::PPCISD::VPERM
@ VPERM
VPERM - The PPC VPERM Instruction.
Definition: PPCISelLowering.h:100
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::PPCTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
Definition: PPCISelLowering.cpp:16326
llvm::PPC::MOF_RPlusSImm16Mult16
@ MOF_RPlusSImm16Mult16
Definition: PPCISelLowering.h:693
llvm::PPCISD::STXSIX
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
Definition: PPCISelLowering.h:536
llvm::PPCISD::XSMINCDP
@ XSMINCDP
Definition: PPCISelLowering.h:56
llvm::PPCTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: PPCISelLowering.cpp:16200
llvm::MemOp
Definition: TargetLowering.h:112
llvm::PPCTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: PPCISelLowering.cpp:15774
llvm::PPC::isSplatShuffleMask
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
Definition: PPCISelLowering.cpp:2105
llvm::PPCISD::BUILD_SPE64
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
Definition: PPCISelLowering.h:227
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::PPC::isXXPERMDIShuffleMask
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
Definition: PPCISelLowering.cpp:2347
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::PPCISD::FADDRTZ
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
Definition: PPCISelLowering.h:294
llvm::PPCISD::Lo
@ Lo
Definition: PPCISelLowering.h:136
llvm::PPCTargetLowering::ccAssignFnForCall
CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: PPCISelLowering.cpp:17709
llvm::PPCTargetLowering::getByValTypeAlignment
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
Definition: PPCISelLowering.cpp:1558
llvm::AttributeList
Definition: Attributes.h:399
llvm::PPCISD::XXSPLT
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
Definition: PPCISelLowering.h:104
llvm::PPCISD::LD_GOT_TPREL_L
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
Definition: PPCISelLowering.h:327
llvm::PPCISD::FCFIDU
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
Definition: PPCISelLowering.h:65
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::PPCISD::STRICT_FCTIDZ
@ STRICT_FCTIDZ
Definition: PPCISelLowering.h:483
llvm::PPCISD::FNMSUB
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
Definition: PPCISelLowering.h:170
llvm::InlineAsm::Constraint_es
@ Constraint_es
Definition: InlineAsm.h:245
llvm::PPCTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: PPCISelLowering.cpp:15634
llvm::PPCISD::XXSPLTI32DX
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
Definition: PPCISelLowering.h:113
llvm::PPC::MOF_RPlusSImm34
@ MOF_RPlusSImm34
Definition: PPCISelLowering.h:694
llvm::PPC::AM_DQForm
@ AM_DQForm
Definition: PPCISelLowering.h:719
llvm::PPCTargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: PPCISelLowering.cpp:11523
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::PPC::AM_DSForm
@ AM_DSForm
Definition: PPCISelLowering.h:718
llvm::PPCISD::DYNALLOC
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
Definition: PPCISelLowering.h:144
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::PPCTargetLowering::EmitPartwordAtomicBinary
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Definition: PPCISelLowering.cpp:11308
llvm::PPCISD::MFBHRBE
@ MFBHRBE
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.
Definition: PPCISelLowering.h:417
llvm::PPCTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: PPCISelLowering.cpp:11105
llvm::PPCTargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: PPCISelLowering.h:782
llvm::PPCTargetLowering::CallFlags::IsPatchPoint
const bool IsPatchPoint
Definition: PPCISelLowering.h:1132
llvm::PPC::MOF_SubtargetP10
@ MOF_SubtargetP10
Definition: PPCISelLowering.h:710
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: PPCISelLowering.cpp:16567
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::PPCISD::LBRX
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
Definition: PPCISelLowering.h:512
llvm::PPCISD::FCFID
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
Definition: PPCISelLowering.h:61
llvm::PPCTargetLowering::expandVSXStoreForLE
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: PPCISelLowering.cpp:14395
llvm::PPC::isVPKUHUMShuffleMask
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
Definition: PPCISelLowering.cpp:1781
llvm::convertToNonDenormSingle
bool convertToNonDenormSingle(APInt &ArgAPInt)
Definition: PPCISelLowering.cpp:9042
llvm::PPCISD::BDZ
@ BDZ
Definition: PPCISelLowering.h:289
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::PPCTargetLowering::PPCTargetLowering
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
Definition: PPCISelLowering.cpp:143
llvm::PPCISD::ADDI_TLSLD_L
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
Definition: PPCISelLowering.h:376
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
llvm::PPCTargetLowering::isEqualityCmpFoldedWithSignedCmp
bool isEqualityCmpFoldedWithSignedCmp() const override
Return true if instruction generated for equality comparison is folded with instruction generated for...
Definition: PPCISelLowering.h:778
llvm::PPC::MOF_SubtargetSPE
@ MOF_SubtargetSPE
Definition: PPCISelLowering.h:711
MachineValueType.h
llvm::PPC::isXXBRWShuffleMask
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
Definition: PPCISelLowering.cpp:2327
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::PPCISD::UINT_VEC_TO_FP
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
Definition: PPCISelLowering.h:240
llvm::PPCISD::ANDI_rec_1_GT_BIT
@ ANDI_rec_1_GT_BIT
Definition: PPCISelLowering.h:255
llvm::PPCTargetLowering::CallFlags::HasNest
const bool HasNest
Definition: PPCISelLowering.h:1134
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1341
llvm::PPCISD::STXVD2X
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:565
TargetLowering.h
llvm::Type::isArrayTy
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:214
llvm::PPCISD::STRICT_FCTIDUZ
@ STRICT_FCTIDUZ
Definition: PPCISelLowering.h:485
llvm::PPCTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: PPCISelLowering.cpp:10921
llvm::PPCISD::STFIWX
@ STFIWX
STFIWX - The STFIWX instruction.
Definition: PPCISelLowering.h:516
llvm::PPC::MOF_RPlusLo
@ MOF_RPlusLo
Definition: PPCISelLowering.h:691
llvm::PPCISD::CR6SET
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
Definition: PPCISelLowering.h:307
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1095
llvm::PPCTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: PPCISelLowering.cpp:16346
llvm::PPCISD::TC_RETURN
@ TC_RETURN
TC_RETURN - A tail call return.
Definition: PPCISelLowering.h:304
llvm::PPCISD::STRICT_FCFIDUS
@ STRICT_FCFIDUS
Definition: PPCISelLowering.h:492
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:251
llvm::PPCTargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: PPCISelLowering.cpp:1576
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:410
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::PPCISD::GlobalBaseReg
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
Definition: PPCISelLowering.h:156
llvm::PPCTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: PPCISelLowering.cpp:16695
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCTargetLowering::hasSPE
bool hasSPE() const
Definition: PPCISelLowering.cpp:1572
llvm::PPCTargetLowering::isDesirableToTransformToIntegerOp
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition: PPCISelLowering.h:1009
llvm::PPCISD::LFIWZX
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
Definition: PPCISelLowering.h:526
llvm::PPC::MOF_RPlusR
@ MOF_RPlusR
Definition: PPCISelLowering.h:695
llvm::PPC::MOF_ZExt
@ MOF_ZExt
Definition: PPCISelLowering.h:685
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::PPCISD::XXSPLTI_SP_TO_DP
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
Definition: PPCISelLowering.h:109
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3187
llvm::PPCTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: PPCISelLowering.cpp:11007
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1062
llvm::PPCISD::VCMP_rec
@ VCMP_rec
RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.
Definition: PPCISelLowering.h:277
llvm::PPCTargetLowering::CallFlags::CallConv
const CallingConv::ID CallConv
Definition: PPCISelLowering.h:1129
llvm::PPCTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: PPCISelLowering.cpp:16036
llvm::PPCTargetLowering::CallFlags
Structure that collects some common arguments that get passed around between the functions for call l...
Definition: PPCISelLowering.h:1128
llvm::PPCTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: PPCISelLowering.h:877
llvm::PPCISD::ATOMIC_CMP_SWAP_8
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
Definition: PPCISelLowering.h:578
llvm::PPCISD::VADD_SPLAT
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
Definition: PPCISelLowering.h:406
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::PPC::MOF_Vector
@ MOF_Vector
Definition: PPCISelLowering.h:704
llvm::PPCTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
Definition: PPCISelLowering.cpp:15740
llvm::PPCTargetLowering::getNegatedExpression
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Definition: PPCISelLowering.cpp:16605
llvm::Instruction
Definition: Instruction.h:45
llvm::PPCTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: PPCISelLowering.cpp:17758
llvm::PPCTargetLowering::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
Definition: PPCISelLowering.cpp:16492
llvm::PPCISD::SRA_ADDZE
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
Definition: PPCISelLowering.h:180
llvm::PPCISD::MFVSR
@ MFVSR
Direct move from a VSX register to a GPR.
Definition: PPCISelLowering.h:212
llvm::PPCTargetLowering::SelectAddressPCRel
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
Definition: PPCISelLowering.cpp:2875
llvm::PPCISD::PPC32_GOT
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
Definition: PPCISelLowering.h:312
llvm::PPC::isVSLDOIShuffleMask
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
Definition: PPCISelLowering.cpp:2061
llvm::PPC::MOF_DoubleWordInt
@ MOF_DoubleWordInt
Definition: PPCISelLowering.h:702
llvm::PPCISD::XXSWAPD
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
Definition: PPCISelLowering.h:427
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::PPCTargetLowering::CallFlags::IsIndirect
const bool IsIndirect
Definition: PPCISelLowering.h:1133
llvm::PPCISD::ADDIS_GOT_TPREL_HA
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
Definition: PPCISelLowering.h:321
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:214
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::PPCISD::SRL
@ SRL
These nodes represent PPC shifts.
Definition: PPCISelLowering.h:165
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::PPCISD::MTVSRZ
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
Definition: PPCISelLowering.h:218
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::PPCTargetLowering::SelectOptimalAddrMode
PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const
SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...
Definition: PPCISelLowering.cpp:17574
llvm::PPCISD::LFIWAX
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Definition: PPCISelLowering.h:521
llvm::PPCISD::STORE_VEC_BE
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:570
llvm::PPCTargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: PPCISelLowering.cpp:16689
llvm::PPCISD::FP_TO_SINT_IN_VSR
@ FP_TO_SINT_IN_VSR
Definition: PPCISelLowering.h:82
llvm::PPCTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: PPCISelLowering.cpp:17783
llvm::PPCTargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: PPCISelLowering.cpp:15689
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::PPCISD::XXMFACC
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
Definition: PPCISelLowering.h:480
llvm::PPCISD::FCTIWZ
@ FCTIWZ
Definition: PPCISelLowering.h:73
llvm::PPC::MOF_None
@ MOF_None
Definition: PPCISelLowering.h:681
llvm::PPCTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Definition: PPCISelLowering.cpp:11766
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::PPCTargetLowering::SelectAddressRegRegOnly
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
Definition: PPCISelLowering.cpp:2837
llvm::PPCISD::CALL_NOP
@ CALL_NOP
Definition: PPCISelLowering.h:187
llvm::PPC::isXXBRHShuffleMask
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
Definition: PPCISelLowering.cpp:2323
llvm::PPCISD::ADD_TLS
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
Definition: PPCISelLowering.h:335
llvm::APFloat
Definition: APFloat.h:701
llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: PPCISelLowering.cpp:3150
llvm::PPCTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: PPCISelLowering.cpp:16561
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::PPCTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: PPCISelLowering.h:770
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::PPCISD::LXSIZX
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
Definition: PPCISelLowering.h:531
uint64_t
llvm::PPC::MOF_ScalarFloat
@ MOF_ScalarFloat
Definition: PPCISelLowering.h:703
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1255
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:921
llvm::PPCISD::MFFS
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
Definition: PPCISelLowering.h:297
llvm::PPCISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: PPCISelLowering.h:48
llvm::PPC::isVMRGHShuffleMask
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
Definition: PPCISelLowering.cpp:1942
llvm::PPCTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: PPCISelLowering.cpp:15960
llvm::PPC::MOF_SExt
@ MOF_SExt
Definition: PPCISelLowering.h:684
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::PPCTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: PPCISelLowering.h:762
PPCInstrInfo.h
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::PPC::AddrMode
AddrMode
Definition: PPCISelLowering.h:715
llvm::PPCTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: PPCISelLowering.cpp:16149
llvm::PPCTargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Definition: PPCISelLowering.cpp:1747
llvm::TargetLoweringBase::NegatibleCost
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition: TargetLowering.h:268
llvm::PPCISD::SRA
@ SRA
Definition: PPCISelLowering.h:166
llvm::PPCISD::Hi
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Definition: PPCISelLowering.h:135
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:850
llvm::PPCISD::PROBED_ALLOCA
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
Definition: PPCISelLowering.h:153
llvm::PPCTargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: PPCISelLowering.cpp:11774
llvm::PPCISD::EXTRACT_SPE
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
Definition: PPCISelLowering.h:230
llvm::PPCISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: PPCISelLowering.h:265
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
Definition: PPCISelLowering.cpp:16407
llvm::PPC::MOF_PCRel
@ MOF_PCRel
Definition: PPCISelLowering.h:696
llvm::PPCISD::BUILD_FP128
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
Definition: PPCISelLowering.h:221
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::PPCTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: PPCISelLowering.cpp:1739
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::PPCISD::EXTRACT_VSX_REG
@ EXTRACT_VSX_REG
EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.
Definition: PPCISelLowering.h:477
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::PPCTargetLowering
Definition: PPCISelLowering.h:726
llvm::PPCTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: PPCISelLowering.cpp:16556
llvm::PPC::MemOpFlags
MemOpFlags
Definition: PPCISelLowering.h:680
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::PPCISD::DYNAREAOFFSET
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
Definition: PPCISelLowering.h:149
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::PPCTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: PPCISelLowering.cpp:16195
llvm::PPC::isVMRGEOShuffleMask
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
Definition: PPCISelLowering.cpp:2032
info
lazy value info
Definition: LazyValueInfo.cpp:59
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::isIntS16Immediate
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
Definition: PPCISelLowering.cpp:2525
llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
Definition: PPCISelLowering.h:248
llvm::PPCISD::STRICT_FCFIDU
@ STRICT_FCFIDU
Definition: PPCISelLowering.h:490
llvm::PPCTargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: PPCISelLowering.cpp:11665
llvm::PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
Definition: PPCISelLowering.h:1075
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::PPCISD::VCMP
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
Definition: PPCISelLowering.h:271
llvm::PPCISD::STRICT_FADDRTZ
@ STRICT_FADDRTZ
Constrained floating point add in round-to-zero mode.
Definition: PPCISelLowering.h:495
llvm::PPCISD::STRICT_FCFIDS
@ STRICT_FCFIDS
Definition: PPCISelLowering.h:491
llvm::PPCTargetLowering::SelectAddressEVXRegReg
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
Definition: PPCISelLowering.cpp:2556
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
llvm::PPCTargetLowering::SelectAddressRegImm34
bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...
Definition: PPCISelLowering.cpp:2788
llvm::PPCTargetLowering::CallFlags::IsTailCall
const bool IsTailCall
Definition: PPCISelLowering.h:1130
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCISD::FCFIDUS
@ FCFIDUS
Definition: PPCISelLowering.h:67
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::PPCISD::PPC32_PICGOT
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
Definition: PPCISelLowering.h:316
llvm::PPCISD::LXVRZX
@ LXVRZX
LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero...
Definition: PPCISelLowering.h:547
llvm::PPCISD::LD_VSX_LH
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
Definition: PPCISelLowering.h:556
llvm::PPC::getSplatIdxForPPCMnemonics
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
Definition: PPCISelLowering.cpp:2403
llvm::PPCTargetLowering::isJumpTableRelative
bool isJumpTableRelative() const override
Definition: PPCISelLowering.cpp:3126
llvm::PPCISD::PADDI_DTPREL
@ PADDI_DTPREL
G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 inst...
Definition: PPCISelLowering.h:400
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
llvm::PPCTargetLowering::EmitAtomicBinary
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Definition: PPCISelLowering.cpp:11135
llvm::PPC::AM_XForm
@ AM_XForm
Definition: PPCISelLowering.h:721
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: PPCISelLowering.cpp:16544
llvm::PPCISD::LXVD2X
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:541
llvm::PPCISD::ADDIS_TLSGD_HA
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
Definition: PPCISelLowering.h:340
llvm::PPCISD::ADDI_DTPREL_L
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
Definition: PPCISelLowering.h:396
llvm::PPC::isVPKUDUMShuffleMask
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
Definition: PPCISelLowering.cpp:1849
llvm::PPCISD::FCTIWUZ
@ FCTIWUZ
Definition: PPCISelLowering.h:78
llvm::PPCTargetLowering::isFPExtFree
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
Definition: PPCISelLowering.cpp:16390
CallingConv.h
llvm::PPCISD::ADDI_TLSLD_L_ADDR
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
Definition: PPCISelLowering.h:386
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::PPCISD::FSEL
@ FSEL
FSEL - Traditional three-operand fsel node.
Definition: PPCISelLowering.h:52
llvm::PPCISD::RET_FLAG
@ RET_FLAG
Return with a flag operand, matched by 'blr'.
Definition: PPCISelLowering.h:204
llvm::PPCISD::TOC_ENTRY
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
Definition: PPCISelLowering.h:584
llvm::PPCTargetLowering::CallFlags::IsVarArg
const bool IsVarArg
Definition: PPCISelLowering.h:1131
llvm::PPC::isXXBRQShuffleMask
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
Definition: PPCISelLowering.cpp:2335
llvm::PPCISD::STRICT_FCTIWUZ
@ STRICT_FCTIWUZ
Definition: PPCISelLowering.h:486
llvm::PPC::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Definition: PPCFastISel.cpp:2469
llvm::PPCTargetLowering::SelectAddressRegImm
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
Definition: PPCISelLowering.cpp:2683
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1718
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
uint16_t
llvm::PPCISD::STBRX
@ STBRX
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
Definition: PPCISelLowering.h:506
CallingConvLower.h
llvm::PPCISD::XSMAXCDP
@ XSMAXCDP
XSMAXCDP, XSMINCDP - C-type min/max instructions.
Definition: PPCISelLowering.h:55
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::PPCTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: PPCISelLowering.cpp:16671
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4164
llvm::PPCISD::FCTIDUZ
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
Definition: PPCISelLowering.h:77
llvm::PPCISD::ADDIS_DTPREL_HA
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
Definition: PPCISelLowering.h:391
llvm::PPCISD::ANDI_rec_1_EQ_BIT
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
Definition: PPCISelLowering.h:254
llvm::PPCTargetLowering::BuildSDIVPow2
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
Definition: PPCISelLowering.cpp:15601
Function.h
llvm::PPCTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Definition: PPCISelLowering.cpp:16403
llvm::PPC::MOF_SubWordInt
@ MOF_SubWordInt
Definition: PPCISelLowering.h:700
llvm::PPCISD::SWAP_NO_CHAIN
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
Definition: PPCISelLowering.h:431
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::PPCISD::NodeType
NodeType
Definition: PPCISelLowering.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::PPC::isVPKUWUMShuffleMask
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
Definition: PPCISelLowering.cpp:1812
llvm::PPCISD::CALL
@ CALL
CALL - A direct function call.
Definition: PPCISelLowering.h:186
llvm::PPCISD::CR6UNSET
@ CR6UNSET
Definition: PPCISelLowering.h:308
llvm::PPCTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: PPCISelLowering.cpp:16679
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:839
llvm::PPCISD::BCTRL_LOAD_TOC
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
Definition: PPCISelLowering.h:201
llvm::PPC::MOF_RPlusSImm16Mult4
@ MOF_RPlusSImm16Mult4
Definition: PPCISelLowering.h:692
llvm::PPCTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: PPCISelLowering.h:766
llvm::PPCTargetLowering::CallFlags::CallFlags
CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
Definition: PPCISelLowering.h:1137
llvm::PPCISD::LOAD_VEC_BE
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:552
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:922
llvm::PPCISD::ADDIS_TLSLD_HA
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
Definition: PPCISelLowering.h:370
llvm::PPC::MOF_WordInt
@ MOF_WordInt
Definition: PPCISelLowering.h:701
llvm::PPCISD::ADDI_TLSGD_L
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
Definition: PPCISelLowering.h:346
llvm::checkConvertToNonDenormSingle
bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)
Definition: PPCISelLowering.cpp:9052
llvm::PPCTargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: PPCISelLowering.cpp:16354
llvm::PPCISD::EXTSWSLI
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
Definition: PPCISelLowering.h:174
llvm::PPCISD::TLSGD_AIX
@ TLSGD_AIX
GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two re...
Definition: PPCISelLowering.h:365
llvm::PPC::MOF_RPlusSImm16
@ MOF_RPlusSImm16
Definition: PPCISelLowering.h:690
llvm::PPCISD::MFOCRF
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
Definition: PPCISelLowering.h:209
llvm::PPC::isVMRGLShuffleMask
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
Definition: PPCISelLowering.cpp:1917
llvm::PPCISD::VECINSERT
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
Definition: PPCISelLowering.h:117
llvm::PPCISD::CALL_NOTOC
@ CALL_NOTOC
Definition: PPCISelLowering.h:188
llvm::PPCTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: PPCISelLowering.cpp:11115
llvm::PPCISD::SINT_VEC_TO_FP
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
Definition: PPCISelLowering.h:236
llvm::PPC::AM_PCRel
@ AM_PCRel
Definition: PPCISelLowering.h:722
llvm::PPCISD::LD_SPLAT
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
Definition: PPCISelLowering.h:560
llvm::PPCISD::SHL
@ SHL
Definition: PPCISelLowering.h:167
llvm::PPCISD::VEXTS
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
Definition: PPCISelLowering.h:86
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
N
#define N
llvm::PPCTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: PPCISelLowering.cpp:16445
llvm::PPCTargetLowering::SelectForceXFormMode
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...
Definition: PPCISelLowering.cpp:17526
llvm::PPCTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: PPCISelLowering.cpp:11961
llvm::PPCTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: PPCISelLowering.cpp:16370
llvm::PPCISD::PAIR_BUILD
@ PAIR_BUILD
PAIR_BUILD = Build a vector pair register from 2 VSX registers.
Definition: PPCISelLowering.h:471
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4256
llvm::PPCTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: PPCISelLowering.cpp:1568
llvm::PPCISD::FRE
@ FRE
Reciprocal estimate instructions (unary FP ops).
Definition: PPCISelLowering.h:89
llvm::PPCISD::ST_VSR_SCAL_INT
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
Definition: PPCISelLowering.h:573
llvm::PPCTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: PPCISelLowering.cpp:17729
llvm::PPCISD::XXPERMDI
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
Definition: PPCISelLowering.h:125
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::PPC::MOF_NoExt
@ MOF_NoExt
Definition: PPCISelLowering.h:686
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::PPC::MOF_Vector256
@ MOF_Vector256
Definition: PPCISelLowering.h:705
llvm::PPCISD::GET_TLS_ADDR
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
Definition: PPCISelLowering.h:351
RegName
#define RegName(no)
llvm::PPCISD::BCTRL
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
Definition: PPCISelLowering.h:196
llvm::PPCTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
Definition: PPCISelLowering.cpp:16587
llvm::PPCTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: PPCISelLowering.h:957
llvm::PPC::MOF_AddrIsSImm32
@ MOF_AddrIsSImm32
Definition: PPCISelLowering.h:697
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:491
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::PPCISD::CMPB
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
Definition: PPCISelLowering.h:128
llvm::PPCISD::GET_TLSLD_ADDR
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
Definition: PPCISelLowering.h:381
llvm::PPCTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: PPCISelLowering.h:1002
llvm::PPCISD::ATOMIC_CMP_SWAP_16
@ ATOMIC_CMP_SWAP_16
Definition: PPCISelLowering.h:579
llvm::PPCTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: PPCISelLowering.h:788
llvm::PPCISD::FP_TO_UINT_IN_VSR
@ FP_TO_UINT_IN_VSR
Floating-point-to-interger conversion instructions.
Definition: PPCISelLowering.h:81
llvm::Sched::Preference
Preference
Definition: TargetLowering.h:98
llvm::PPC::get_VSPLTI_elt
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
Definition: PPCISelLowering.cpp:2417
llvm::PPCTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: PPCISelLowering.cpp:15830
llvm::PPC::MOF_SubtargetBeforeP9
@ MOF_SubtargetBeforeP9
Definition: PPCISelLowering.h:708
llvm::PPCISD::STRICT_FCFID
@ STRICT_FCFID
Constrained integer-to-floating-point conversion instructions.
Definition: PPCISelLowering.h:489
llvm::PPCISD::FTSQRT
@ FTSQRT
Test instruction for software square root.
Definition: PPCISelLowering.h:93
llvm::PPCTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
Definition: PPCISelLowering.cpp:1580
MachineFunction.h
llvm::PPCISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: PPCISelLowering.h:262
llvm::PPCTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Definition: PPCISelLowering.cpp:16399
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::PPCTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
Definition: PPCISelLowering.cpp:16472
llvm::PPCTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: PPCISelLowering.cpp:14851
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::PPCTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind Kind) const override
Definition: PPCISelLowering.h:737
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:521
llvm::PPCISD::TLS_LOCAL_EXEC_MAT_ADDR
@ TLS_LOCAL_EXEC_MAT_ADDR
TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access ...
Definition: PPCISelLowering.h:465
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::PPCISD::ADDI_TLSGD_L_ADDR
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
Definition: PPCISelLowering.h:356
llvm::PPCISD::STRICT_FCTIWZ
@ STRICT_FCTIWZ
Definition: PPCISelLowering.h:484
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:238
llvm::PPCISD::COND_BRANCH
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
Definition: PPCISelLowering.h:284
llvm::PPCTargetLowering::emitProbedAlloca
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: PPCISelLowering.cpp:11799
llvm::PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR
@ TLS_DYNAMIC_MAT_PCREL_ADDR
TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dyna...
Definition: PPCISelLowering.h:460
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::PPCISD::FRSQRTE
@ FRSQRTE
Definition: PPCISelLowering.h:90
llvm::PPCISD::VECSHL
@ VECSHL
VECSHL - The PPC vector shift left instruction.
Definition: PPCISelLowering.h:121
llvm::PPCISD::FCFIDS
@ FCFIDS
Definition: PPCISelLowering.h:66
llvm::LLT
Definition: LowLevelTypeImpl.h:40