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PPCISelLowering.h
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1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that PPC uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 
17 #include "PPCInstrInfo.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Type.h"
32 #include <utility>
33 
34 namespace llvm {
35 
36  namespace PPCISD {
37 
38  // When adding a NEW PPCISD node please add it to the correct position in
39  // the enum. The order of elements in this enum matters!
40  // Values that are added after this entry:
41  // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
42  // are considered memory opcodes and are treated differently than entries
43  // that come before it. For example, ADD or MUL should be placed before
44  // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
45  // after it.
46  enum NodeType : unsigned {
47  // Start the numbering where the builtin ops and target ops leave off.
49 
50  /// FSEL - Traditional three-operand fsel node.
51  ///
53 
54  /// XSMAXCDP, XSMINCDP - C-type min/max instructions.
57 
58  /// FCFID - The FCFID instruction, taking an f64 operand and producing
59  /// and f64 value containing the FP representation of the integer that
60  /// was temporarily in the f64 operand.
62 
63  /// Newer FCFID[US] integer-to-floating-point conversion instructions for
64  /// unsigned integers and single-precision outputs.
68 
69  /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
70  /// operand, producing an f64 value containing the integer representation
71  /// of that FP value.
74 
75  /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
76  /// unsigned integers with round toward zero.
79 
80  /// Floating-point-to-interger conversion instructions
83 
84  /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
85  /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
87 
88  /// Reciprocal estimate instructions (unary FP ops).
89  FRE,
91 
92  /// Test instruction for software square root.
94 
95  /// Square root instruction.
97 
98  /// VPERM - The PPC VPERM Instruction.
99  ///
101 
102  /// XXSPLT - The PPC VSX splat instructions
103  ///
105 
106  /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
107  /// converting immediate single precision numbers to double precision
108  /// vector or scalar.
110 
111  /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
112  ///
114 
115  /// VECINSERT - The PPC vector insert instruction
116  ///
118 
119  /// VECSHL - The PPC vector shift left instruction
120  ///
122 
123  /// XXPERMDI - The PPC XXPERMDI instruction
124  ///
126 
127  /// The CMPB instruction (takes two operands of i32 or i64).
129 
130  /// Hi/Lo - These represent the high and low 16-bit parts of a global
131  /// address respectively. These nodes have two operands, the first of
132  /// which must be a TargetGlobalAddress, and the second of which must be a
133  /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
134  /// though these are usually folded into other nodes.
135  Hi,
136  Lo,
137 
138  /// The following two target-specific nodes are used for calls through
139  /// function pointers in the 64-bit SVR4 ABI.
140 
141  /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
142  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
143  /// compute an allocation on the stack.
145 
146  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
147  /// compute an offset from native SP to the address of the most recent
148  /// dynamic alloca.
150 
151  /// To avoid stack clash, allocation is performed by block and each block is
152  /// probed.
154 
155  /// The result of the mflr at function entry, used for PIC code.
157 
158  /// These nodes represent PPC shifts.
159  ///
160  /// For scalar types, only the last `n + 1` bits of the shift amounts
161  /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
162  /// for exact behaviors.
163  ///
164  /// For vector types, only the last n bits are used. See vsld.
168 
169  /// FNMSUB - Negated multiply-subtract instruction.
171 
172  /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
173  /// word and shift left immediate.
175 
176  /// The combination of sra[wd]i and addze used to implemented signed
177  /// integer division by a power of 2. The first operand is the dividend,
178  /// and the second is the constant shift amount (representing the
179  /// divisor).
181 
182  /// CALL - A direct function call.
183  /// CALL_NOP is a call with the special NOP which follows 64-bit
184  /// CALL_NOTOC the caller does not use the TOC.
185  /// SVR4 calls and 32-bit/64-bit AIX calls.
189 
190  /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
191  /// MTCTR instruction.
193 
194  /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
195  /// BCTRL instruction.
197 
198  /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
199  /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
200  /// and 64-bit AIX.
202 
203  /// The variants that implicitly define rounding mode for calls with
204  /// strictfp semantics.
210 
211  /// Return with a flag operand, matched by 'blr'
213 
214  /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
215  /// This copies the bits corresponding to the specified CRREG into the
216  /// resultant GPR. Bits corresponding to other CR regs are undefined.
218 
219  /// Direct move from a VSX register to a GPR
221 
222  /// Direct move from a GPR to a VSX register (algebraic)
224 
225  /// Direct move from a GPR to a VSX register (zero)
227 
228  /// Direct move of 2 consecutive GPR to a VSX register.
230 
231  /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
232  /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
233  /// unsupported for this target.
234  /// Merge 2 GPRs to a single SPE register.
236 
237  /// Extract SPE register component, second argument is high or low.
239 
240  /// Extract a subvector from signed integer vector and convert to FP.
241  /// It is primarily used to convert a (widened) illegal integer vector
242  /// type to a legal floating point vector type.
243  /// For example v2i32 -> widened to v4i32 -> v2f64
245 
246  /// Extract a subvector from unsigned integer vector and convert to FP.
247  /// As with SINT_VEC_TO_FP, used for converting illegal types.
249 
250  /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to
251  /// place the value into the least significant element of the most
252  /// significant doubleword in the vector. This is not element zero for
253  /// anything smaller than a doubleword on either endianness. This node has
254  /// the same semantics as SCALAR_TO_VECTOR except that the value remains in
255  /// the aforementioned location in the vector register.
257 
258  // FIXME: Remove these once the ANDI glue bug is fixed:
259  /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
260  /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
261  /// implement truncation of i32 or i64 to i1.
264 
265  // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
266  // target (returns (Lo, Hi)). It takes a chain operand.
268 
269  // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
271 
272  // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
274 
275  /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
276  /// instructions. For lack of better number, we use the opcode number
277  /// encoding for the OPC field to identify the compare. For example, 838
278  /// is VCMPGTSH.
280 
281  /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
282  /// altivec VCMP*_rec instructions. For lack of better number, we use the
283  /// opcode number encoding for the OPC field to identify the compare. For
284  /// example, 838 is VCMPGTSH.
286 
287  /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
288  /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
289  /// condition register to branch on, OPC is the branch opcode to use (e.g.
290  /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
291  /// an optional input flag argument.
293 
294  /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
295  /// loops.
298 
299  /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
300  /// towards zero. Used only as part of the long double-to-int
301  /// conversion sequence.
303 
304  /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
306 
307  /// TC_RETURN - A tail call return.
308  /// operand #0 chain
309  /// operand #1 callee (register or absolute)
310  /// operand #2 stack adjustment
311  /// operand #3 optional in flag
313 
314  /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
317 
318  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
319  /// for non-position independent code on PPC32.
321 
322  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
323  /// local dynamic TLS and position indendepent code on PPC32.
325 
326  /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
327  /// TLS model, produces an ADDIS8 instruction that adds the GOT
328  /// base to sym\@got\@tprel\@ha.
330 
331  /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
332  /// TLS model, produces a LD instruction with base register G8RReg
333  /// and offset sym\@got\@tprel\@l. This completes the addition that
334  /// finds the offset of "sym" relative to the thread pointer.
336 
337  /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
338  /// model, produces an ADD instruction that adds the contents of
339  /// G8RReg to the thread pointer. Symbol contains a relocation
340  /// sym\@tls which is to be replaced by the thread pointer and
341  /// identifies to the linker that the instruction is part of a
342  /// TLS sequence.
344 
345  /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
346  /// model, produces an ADDIS8 instruction that adds the GOT base
347  /// register to sym\@got\@tlsgd\@ha.
349 
350  /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
351  /// model, produces an ADDI8 instruction that adds G8RReg to
352  /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
353  /// ADDIS_TLSGD_L_ADDR until after register assignment.
355 
356  /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
357  /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
358  /// ADDIS_TLSGD_L_ADDR until after register assignment.
360 
361  /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
362  /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
363  /// register assignment.
365 
366  /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
367  /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
368  /// Op that combines two register copies of TOC entries
369  /// (region handle into R3 and variable offset into R4) followed by a
370  /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr.
371  /// This node is used in 64-bit mode as well (in which case the result is
372  /// G8RC and inputs are X3/X4).
374 
375  /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
376  /// model, produces an ADDIS8 instruction that adds the GOT base
377  /// register to sym\@got\@tlsld\@ha.
379 
380  /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
381  /// model, produces an ADDI8 instruction that adds G8RReg to
382  /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
383  /// ADDIS_TLSLD_L_ADDR until after register assignment.
385 
386  /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
387  /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
388  /// ADDIS_TLSLD_L_ADDR until after register assignment.
390 
391  /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
392  /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
393  /// following register assignment.
395 
396  /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
397  /// model, produces an ADDIS8 instruction that adds X3 to
398  /// sym\@dtprel\@ha.
400 
401  /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
402  /// model, produces an ADDI8 instruction that adds G8RReg to
403  /// sym\@got\@dtprel\@l.
405 
406  /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
407  /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.
409 
410  /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
411  /// during instruction selection to optimize a BUILD_VECTOR into
412  /// operations on splats. This is necessary to avoid losing these
413  /// optimizations due to constant folding.
415 
416  /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
417  /// operand identifies the operating system entry point.
418  SC,
419 
420  /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
422 
423  /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
424  /// history rolling buffer entry.
426 
427  /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
429 
430  /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
431  /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
432  /// or stxvd2x instruction. The chain is necessary because the
433  /// sequence replaces a load and needs to provide the same number
434  /// of outputs.
436 
437  /// An SDNode for swaps that are not associated with any loads/stores
438  /// and thereby have no chain.
440 
441  /// An SDNode for Power9 vector absolute value difference.
442  /// operand #0 vector
443  /// operand #1 vector
444  /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
445  /// the most significant bit for signed i32
446  ///
447  /// Power9 VABSD* instructions are designed to support unsigned integer
448  /// vectors (byte/halfword/word), if we want to make use of them for signed
449  /// integer vectors, we have to flip their sign bits first. To flip sign bit
450  /// for byte/halfword integer vector would become inefficient, but for word
451  /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
452  /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
453  /// => VABSDUW((XVNEGSP a), (XVNEGSP b))
455 
456  /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
457  /// lower (IDX=1) half of v4f32 to v2f64.
459 
460  /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
461  /// either through an add like PADDI or through a PC Relative load like
462  /// PLD.
464 
465  /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for
466  /// TLS global address when using dynamic access models. This can be done
467  /// through an add like PADDI.
469 
470  /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address
471  /// when using local exec access models, and when prefixed instructions are
472  /// available. This is used with ADD_TLS to produce an add like PADDI.
474 
475  /// ACC_BUILD = Build an accumulator register from 4 VSX registers.
477 
478  /// PAIR_BUILD = Build a vector pair register from 2 VSX registers.
480 
481  /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of
482  /// an accumulator or pair register. This node is needed because
483  /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same
484  /// element type.
486 
487  /// XXMFACC = This corresponds to the xxmfacc instruction.
489 
490  // Constrained conversion from floating point to int
495 
496  /// Constrained integer-to-floating-point conversion instructions.
501 
502  /// Constrained floating point add in round-to-zero mode.
504 
505  // NOTE: The nodes below may require PC-Rel specific patterns if the
506  // address could be PC-Relative. When adding new nodes below, consider
507  // whether or not the address can be PC-Relative and add the corresponding
508  // PC-relative patterns and tests.
509 
510  /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
511  /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
512  /// the GPRC input, then stores it through Ptr. Type can be either i16 or
513  /// i32.
515 
516  /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
517  /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
518  /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
519  /// or i32.
521 
522  /// STFIWX - The STFIWX instruction. The first operand is an input token
523  /// chain, then an f64 value to store, then an address to store it to.
525 
526  /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
527  /// load which sign-extends from a 32-bit integer value into the
528  /// destination 64-bit register.
530 
531  /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
532  /// load which zero-extends from a 32-bit integer value into the
533  /// destination 64-bit register.
535 
536  /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
537  /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
538  /// This can be used for converting loaded integers to floating point.
540 
541  /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
542  /// chain, then an f64 value to store, then an address to store it to,
543  /// followed by a byte-width for the store.
545 
546  /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
547  /// Maps directly to an lxvd2x instruction that will be followed by
548  /// an xxswapd.
550 
551  /// LXVRZX - Load VSX Vector Rightmost and Zero Extend
552  /// This node represents v1i128 BUILD_VECTOR of a zero extending load
553  /// instruction from <byte, halfword, word, or doubleword> to i128.
554  /// Allows utilization of the Load VSX Vector Rightmost Instructions.
556 
557  /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
558  /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
559  /// the vector type to load vector in big-endian element order.
561 
562  /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
563  /// v2f32 value into the lower half of a VSR register.
565 
566  /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
567  /// instructions such as LXVDSX, LXVWSX.
569 
570  /// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
571  /// that zero-extends.
573 
574  /// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
575  /// that sign-extends.
577 
578  /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
579  /// Maps directly to an stxvd2x instruction that will be preceded by
580  /// an xxswapd.
582 
583  /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
584  /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
585  /// the vector type to store vector in big-endian element order.
587 
588  /// Store scalar integers from VSR.
590 
591  /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
592  /// except they ensure that the compare input is zero-extended for
593  /// sub-word versions because the atomic loads zero-extend.
596 
597  /// GPRC = TOC_ENTRY GA, TOC
598  /// Loads the entry for GA from the TOC, where the TOC base is given by
599  /// the last operand.
601  };
602 
603  } // end namespace PPCISD
604 
605  /// Define some predicates that are used for node matching.
606  namespace PPC {
607 
608  /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
609  /// VPKUHUM instruction.
610  bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
611  SelectionDAG &DAG);
612 
613  /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
614  /// VPKUWUM instruction.
615  bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
616  SelectionDAG &DAG);
617 
618  /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
619  /// VPKUDUM instruction.
620  bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
621  SelectionDAG &DAG);
622 
623  /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
624  /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
625  bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
626  unsigned ShuffleKind, SelectionDAG &DAG);
627 
628  /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
629  /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
630  bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
631  unsigned ShuffleKind, SelectionDAG &DAG);
632 
633  /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
634  /// a VMRGEW or VMRGOW instruction
635  bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
636  unsigned ShuffleKind, SelectionDAG &DAG);
637  /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
638  /// for a XXSLDWI instruction.
639  bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
640  bool &Swap, bool IsLE);
641 
642  /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
643  /// for a XXBRH instruction.
644  bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
645 
646  /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
647  /// for a XXBRW instruction.
648  bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
649 
650  /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
651  /// for a XXBRD instruction.
652  bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
653 
654  /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
655  /// for a XXBRQ instruction.
656  bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
657 
658  /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
659  /// for a XXPERMDI instruction.
660  bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
661  bool &Swap, bool IsLE);
662 
663  /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
664  /// shift amount, otherwise return -1.
665  int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
666  SelectionDAG &DAG);
667 
668  /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
669  /// specifies a splat of a single element that is suitable for input to
670  /// VSPLTB/VSPLTH/VSPLTW.
671  bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
672 
673  /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
674  /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
675  /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
676  /// vector into the other. This function will also set a couple of
677  /// output parameters for how much the source vector needs to be shifted and
678  /// what byte number needs to be specified for the instruction to put the
679  /// element in the desired location of the target vector.
680  bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
681  unsigned &InsertAtByte, bool &Swap, bool IsLE);
682 
683  /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
684  /// appropriate for PPC mnemonics (which have a big endian bias - namely
685  /// elements are counted from the left of the vector register).
686  unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
687  SelectionDAG &DAG);
688 
689  /// get_VSPLTI_elt - If this is a build_vector of constants which can be
690  /// formed by using a vspltis[bhw] instruction of the specified element
691  /// size, return the constant being splatted. The ByteSize field indicates
692  /// the number of bytes of each element [124] -> [bhw].
693  SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
694 
695  // Flags for computing the optimal addressing mode for loads and stores.
696  enum MemOpFlags {
697  MOF_None = 0,
698 
699  // Extension mode for integer loads.
700  MOF_SExt = 1,
701  MOF_ZExt = 1 << 1,
702  MOF_NoExt = 1 << 2,
703 
704  // Address computation flags.
705  MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar.
706  MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant.
707  MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation
708  MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4.
709  MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16.
710  MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant.
711  MOF_RPlusR = 1 << 11, // Sum of two variables.
712  MOF_PCRel = 1 << 12, // PC-Relative relocation.
713  MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant.
714 
715  // The in-memory type.
716  MOF_SubWordInt = 1 << 15,
717  MOF_WordInt = 1 << 16,
718  MOF_DoubleWordInt = 1 << 17,
719  MOF_ScalarFloat = 1 << 18, // Scalar single or double precision.
720  MOF_Vector = 1 << 19, // Vector types and quad precision scalars.
721  MOF_Vector256 = 1 << 20,
722 
723  // Subtarget features.
725  MOF_SubtargetP9 = 1 << 23,
726  MOF_SubtargetP10 = 1 << 24,
728  };
729 
730  // The addressing modes for loads and stores.
731  enum AddrMode {
739  };
740  } // end namespace PPC
741 
743  const PPCSubtarget &Subtarget;
744 
745  public:
746  explicit PPCTargetLowering(const PPCTargetMachine &TM,
747  const PPCSubtarget &STI);
748 
749  /// getTargetNodeName() - This method returns the name of a target specific
750  /// DAG node.
751  const char *getTargetNodeName(unsigned Opcode) const override;
752 
753  bool isSelectSupported(SelectSupportKind Kind) const override {
754  // PowerPC does not support scalar condition selects on vectors.
755  return (Kind != SelectSupportKind::ScalarCondVectorVal);
756  }
757 
758  /// getPreferredVectorAction - The code we generate when vector types are
759  /// legalized by promoting the integer element type is often much worse
760  /// than code we generate if we widen the type for applicable vector types.
761  /// The issue with promoting is that the vector is scalaraized, individual
762  /// elements promoted and then the vector is rebuilt. So say we load a pair
763  /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
764  /// loads, moves back into VSR's (or memory ops if we don't have moves) and
765  /// then the VPERM for the shuffle. All in all a very slow sequence.
767  const override {
768  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
769  VT.getScalarSizeInBits() % 8 == 0)
770  return TypeWidenVector;
772  }
773 
774  bool useSoftFloat() const override;
775 
776  bool hasSPE() const;
777 
778  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
779  return MVT::i32;
780  }
781 
782  bool isCheapToSpeculateCttz() const override {
783  return true;
784  }
785 
786  bool isCheapToSpeculateCtlz() const override {
787  return true;
788  }
789 
790  bool isCtlzFast() const override {
791  return true;
792  }
793 
794  bool isEqualityCmpFoldedWithSignedCmp() const override {
795  return false;
796  }
797 
798  bool hasAndNotCompare(SDValue) const override {
799  return true;
800  }
801 
802  bool preferIncOfAddToSubOfNot(EVT VT) const override;
803 
804  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
805  return VT.isScalarInteger();
806  }
807 
808  SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
809  bool OptForSize, NegatibleCost &Cost,
810  unsigned Depth = 0) const override;
811 
812  /// getSetCCResultType - Return the ISD::SETCC ValueType
814  EVT VT) const override;
815 
816  /// Return true if target always benefits from combining into FMA for a
817  /// given value type. This must typically return false on targets where FMA
818  /// takes more cycles to execute than FADD.
819  bool enableAggressiveFMAFusion(EVT VT) const override;
820 
821  /// getPreIndexedAddressParts - returns true by value, base pointer and
822  /// offset pointer and addressing mode by reference if the node's address
823  /// can be legally represented as pre-indexed load / store address.
825  SDValue &Offset,
827  SelectionDAG &DAG) const override;
828 
829  /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
830  /// it can be more efficiently represented as [r+imm].
832  SelectionDAG &DAG) const;
833 
834  /// SelectAddressRegReg - Given the specified addressed, check to see if it
835  /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
836  /// is non-zero, only accept displacement which is not suitable for [r+imm].
837  /// Returns false if it can be represented by [r+imm], which are preferred.
839  SelectionDAG &DAG,
840  MaybeAlign EncodingAlignment = None) const;
841 
842  /// SelectAddressRegImm - Returns true if the address N can be represented
843  /// by a base register plus a signed 16-bit displacement [r+imm], and if it
844  /// is not better represented as reg+reg. If \p EncodingAlignment is
845  /// non-zero, only accept displacements suitable for instruction encoding
846  /// requirement, i.e. multiples of 4 for DS form.
848  SelectionDAG &DAG,
849  MaybeAlign EncodingAlignment) const;
851  SelectionDAG &DAG) const;
852 
853  /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
854  /// represented as an indexed [r+r] operation.
856  SelectionDAG &DAG) const;
857 
858  /// SelectAddressPCRel - Represent the specified address as pc relative to
859  /// be represented as [pc+imm]
860  bool SelectAddressPCRel(SDValue N, SDValue &Base) const;
861 
863 
864  /// LowerOperation - Provide custom lowering hooks for some operations.
865  ///
866  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
867 
868  /// ReplaceNodeResults - Replace the results of node with an illegal result
869  /// type with new values built out of custom code.
870  ///
872  SelectionDAG &DAG) const override;
873 
874  SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
875  SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
876 
877  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
878 
879  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
880  SmallVectorImpl<SDNode *> &Created) const override;
881 
882  Register getRegisterByName(const char* RegName, LLT VT,
883  const MachineFunction &MF) const override;
884 
886  KnownBits &Known,
887  const APInt &DemandedElts,
888  const SelectionDAG &DAG,
889  unsigned Depth = 0) const override;
890 
891  Align getPrefLoopAlignment(MachineLoop *ML) const override;
892 
893  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
894  return true;
895  }
896 
898  AtomicOrdering Ord) const override;
900  AtomicOrdering Ord) const override;
901 
903  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
904 
907 
909  AtomicRMWInst *AI, Value *AlignedAddr,
910  Value *Incr, Value *Mask,
911  Value *ShiftAmt,
912  AtomicOrdering Ord) const override;
914  AtomicCmpXchgInst *CI,
915  Value *AlignedAddr, Value *CmpVal,
916  Value *NewVal, Value *Mask,
917  AtomicOrdering Ord) const override;
918 
921  MachineBasicBlock *MBB) const override;
924  unsigned AtomicSize,
925  unsigned BinOpcode,
926  unsigned CmpOpcode = 0,
927  unsigned CmpPred = 0) const;
930  bool is8bit,
931  unsigned Opcode,
932  unsigned CmpOpcode = 0,
933  unsigned CmpPred = 0) const;
934 
936  MachineBasicBlock *MBB) const;
937 
939  MachineBasicBlock *MBB) const;
940 
942  MachineBasicBlock *MBB) const;
943 
944  bool hasInlineStackProbe(MachineFunction &MF) const override;
945 
946  unsigned getStackProbeSize(MachineFunction &MF) const;
947 
948  ConstraintType getConstraintType(StringRef Constraint) const override;
949 
950  /// Examine constraint string and operand type and determine a weight value.
951  /// The operand object must already have been set up with the operand type.
953  AsmOperandInfo &info, const char *constraint) const override;
954 
955  std::pair<unsigned, const TargetRegisterClass *>
957  StringRef Constraint, MVT VT) const override;
958 
959  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
960  /// function arguments in the caller parameter area. This is the actual
961  /// alignment, not its logarithm.
963  const DataLayout &DL) const override;
964 
965  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
966  /// vector. If it is invalid, don't add anything to Ops.
968  std::string &Constraint,
969  std::vector<SDValue> &Ops,
970  SelectionDAG &DAG) const override;
971 
972  unsigned
973  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
974  if (ConstraintCode == "es")
976  else if (ConstraintCode == "Q")
978  else if (ConstraintCode == "Z")
980  else if (ConstraintCode == "Zy")
982  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
983  }
984 
985  /// isLegalAddressingMode - Return true if the addressing mode represented
986  /// by AM is legal for this target, for a load/store of the specified type.
987  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
988  Type *Ty, unsigned AS,
989  Instruction *I = nullptr) const override;
990 
991  /// isLegalICmpImmediate - Return true if the specified immediate is legal
992  /// icmp immediate, that is the target has icmp instructions which can
993  /// compare a register against the immediate without having to materialize
994  /// the immediate into a register.
995  bool isLegalICmpImmediate(int64_t Imm) const override;
996 
997  /// isLegalAddImmediate - Return true if the specified immediate is legal
998  /// add immediate, that is the target has add instructions which can
999  /// add a register and the immediate without having to materialize
1000  /// the immediate into a register.
1001  bool isLegalAddImmediate(int64_t Imm) const override;
1002 
1003  /// isTruncateFree - Return true if it's free to truncate a value of
1004  /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
1005  /// register X1 to i32 by referencing its sub-register R1.
1006  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1007  bool isTruncateFree(EVT VT1, EVT VT2) const override;
1008 
1009  bool isZExtFree(SDValue Val, EVT VT2) const override;
1010 
1011  bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
1012 
1013  /// Returns true if it is beneficial to convert a load of a constant
1014  /// to just the constant itself.
1015  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1016  Type *Ty) const override;
1017 
1018  bool convertSelectOfConstantsToMath(EVT VT) const override {
1019  return true;
1020  }
1021 
1023  SDValue C) const override;
1024 
1026  EVT VT) const override {
1027  // Only handle float load/store pair because float(fpr) load/store
1028  // instruction has more cycles than integer(gpr) load/store in PPC.
1029  if (Opc != ISD::LOAD && Opc != ISD::STORE)
1030  return false;
1031  if (VT != MVT::f32 && VT != MVT::f64)
1032  return false;
1033 
1034  return true;
1035  }
1036 
1037  // Returns true if the address of the global is stored in TOC entry.
1038  bool isAccessedAsGotIndirect(SDValue N) const;
1039 
1040  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
1041 
1042  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
1043  const CallInst &I,
1044  MachineFunction &MF,
1045  unsigned Intrinsic) const override;
1046 
1047  /// It returns EVT::Other if the type should be determined using generic
1048  /// target-independent logic.
1050  const AttributeList &FuncAttributes) const override;
1051 
1052  /// Is unaligned memory access allowed for the given type, and is it fast
1053  /// relative to software emulation.
1055  EVT VT, unsigned AddrSpace, Align Alignment = Align(1),
1057  bool *Fast = nullptr) const override;
1058 
1059  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
1060  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
1061  /// expanded to FMAs when this method returns true, otherwise fmuladd is
1062  /// expanded to fmul + fadd.
1064  EVT VT) const override;
1065 
1066  bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
1067 
1068  /// isProfitableToHoist - Check if it is profitable to hoist instruction
1069  /// \p I to its dominator block.
1070  /// For example, it is not profitable if \p I and it's only user can form a
1071  /// FMA instruction, because Powerpc prefers FMADD.
1072  bool isProfitableToHoist(Instruction *I) const override;
1073 
1074  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1075 
1076  // Should we expand the build vector with shuffles?
1077  bool
1079  unsigned DefinedValues) const override;
1080 
1081  // Keep the zero-extensions for arguments to libcalls.
1082  bool shouldKeepZExtForFP16Conv() const override { return true; }
1083 
1084  /// createFastISel - This method returns a target-specific FastISel object,
1085  /// or null if the target does not support "fast" instruction selection.
1087  const TargetLibraryInfo *LibInfo) const override;
1088 
1089  /// Returns true if an argument of type Ty needs to be passed in a
1090  /// contiguous block of registers in calling convention CallConv.
1092  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
1093  const DataLayout &DL) const override {
1094  // We support any array type as "consecutive" block in the parameter
1095  // save area. The element type defines the alignment requirement and
1096  // whether the argument should go in GPRs, FPRs, or VRs if available.
1097  //
1098  // Note that clang uses this capability both to implement the ELFv2
1099  // homogeneous float/vector aggregate ABI, and to avoid having to use
1100  // "byval" when passing aggregates that might fully fit in registers.
1101  return Ty->isArrayTy();
1102  }
1103 
1104  /// If a physical register, this returns the register that receives the
1105  /// exception address on entry to an EH pad.
1106  Register
1107  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1108 
1109  /// If a physical register, this returns the register that receives the
1110  /// exception typeid on entry to a landing pad.
1111  Register
1112  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1113 
1114  /// Override to support customized stack guard loading.
1115  bool useLoadStackGuardNode() const override;
1116  void insertSSPDeclarations(Module &M) const override;
1117  Value *getSDagStackGuard(const Module &M) const override;
1118 
1119  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1120  bool ForCodeSize) const override;
1121 
1122  unsigned getJumpTableEncoding() const override;
1123  bool isJumpTableRelative() const override;
1125  SelectionDAG &DAG) const override;
1127  unsigned JTI,
1128  MCContext &Ctx) const override;
1129 
1130  /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode),
1131  /// compute the address flags of the node, get the optimal address mode
1132  /// based on the flags, and set the Base and Disp based on the address mode.
1134  SDValue &Disp, SDValue &Base,
1135  SelectionDAG &DAG,
1136  MaybeAlign Align) const;
1137  /// SelectForceXFormMode - Given the specified address, force it to be
1138  /// represented as an indexed [r+r] operation (an XForm instruction).
1140  SelectionDAG &DAG) const;
1141 
1142  bool
1144  SDValue *Parts, unsigned NumParts, MVT PartVT,
1145  Optional<CallingConv::ID> CC) const override;
1146  /// Structure that collects some common arguments that get passed around
1147  /// between the functions for call lowering.
1148  struct CallFlags {
1150  const bool IsTailCall : 1;
1151  const bool IsVarArg : 1;
1152  const bool IsPatchPoint : 1;
1153  const bool IsIndirect : 1;
1154  const bool HasNest : 1;
1155  const bool NoMerge : 1;
1156 
1158  bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
1162  };
1163 
1164  CCAssignFn *ccAssignFnForCall(CallingConv::ID CC, bool Return,
1165  bool IsVarArg) const;
1166 
1167  private:
1168  struct ReuseLoadInfo {
1169  SDValue Ptr;
1170  SDValue Chain;
1171  SDValue ResChain;
1172  MachinePointerInfo MPI;
1173  bool IsDereferenceable = false;
1174  bool IsInvariant = false;
1175  Align Alignment;
1176  AAMDNodes AAInfo;
1177  const MDNode *Ranges = nullptr;
1178 
1179  ReuseLoadInfo() = default;
1180 
1181  MachineMemOperand::Flags MMOFlags() const {
1183  if (IsDereferenceable)
1185  if (IsInvariant)
1187  return F;
1188  }
1189  };
1190 
1191  // Map that relates a set of common address flags to PPC addressing modes.
1192  std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap;
1193  void initializeAddrModeMap();
1194 
1195  bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
1196  SelectionDAG &DAG,
1197  ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
1198  void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
1199  SelectionDAG &DAG) const;
1200 
1201  void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
1202  SelectionDAG &DAG, const SDLoc &dl) const;
1203  SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
1204  const SDLoc &dl) const;
1205 
1206  bool directMoveIsProfitable(const SDValue &Op) const;
1207  SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
1208  const SDLoc &dl) const;
1209 
1210  SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
1211  const SDLoc &dl) const;
1212 
1213  SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
1214 
1215  SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
1216  SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
1217 
1218  bool
1219  IsEligibleForTailCallOptimization(SDValue Callee,
1220  CallingConv::ID CalleeCC,
1221  bool isVarArg,
1222  const SmallVectorImpl<ISD::InputArg> &Ins,
1223  SelectionDAG& DAG) const;
1224 
1225  bool IsEligibleForTailCallOptimization_64SVR4(
1226  SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB,
1227  bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
1228  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1229 
1230  SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
1231  SDValue Chain, SDValue &LROpOut,
1232  SDValue &FPOpOut,
1233  const SDLoc &dl) const;
1234 
1235  SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1236 
1237  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1238  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1239  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1240  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1241  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1242  SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const;
1243  SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
1244  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1245  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1246  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1247  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1248  SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1249  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
1250  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1251  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1252  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1253  SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1254  SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1255  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1256  SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1257  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1258  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1259  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1260  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1261  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1262  const SDLoc &dl) const;
1263  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1264  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1265  SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1266  SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1267  SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1268  SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
1269  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1270  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1271  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1272  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1273  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1274  SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1275  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1276  SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;
1277  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1278  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1279  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1280  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1281  SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
1282 
1283  SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1284  SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1285 
1286  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1287  CallingConv::ID CallConv, bool isVarArg,
1288  const SmallVectorImpl<ISD::InputArg> &Ins,
1289  const SDLoc &dl, SelectionDAG &DAG,
1290  SmallVectorImpl<SDValue> &InVals) const;
1291 
1292  SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
1293  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1294  SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1295  SDValue &Callee, int SPDiff, unsigned NumBytes,
1296  const SmallVectorImpl<ISD::InputArg> &Ins,
1297  SmallVectorImpl<SDValue> &InVals,
1298  const CallBase *CB) const;
1299 
1300  SDValue
1301  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1302  const SmallVectorImpl<ISD::InputArg> &Ins,
1303  const SDLoc &dl, SelectionDAG &DAG,
1304  SmallVectorImpl<SDValue> &InVals) const override;
1305 
1306  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1307  SmallVectorImpl<SDValue> &InVals) const override;
1308 
1309  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1310  bool isVarArg,
1311  const SmallVectorImpl<ISD::OutputArg> &Outs,
1312  LLVMContext &Context) const override;
1313 
1314  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1315  const SmallVectorImpl<ISD::OutputArg> &Outs,
1316  const SmallVectorImpl<SDValue> &OutVals,
1317  const SDLoc &dl, SelectionDAG &DAG) const override;
1318 
1319  SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1320  SelectionDAG &DAG, SDValue ArgVal,
1321  const SDLoc &dl) const;
1322 
1323  SDValue LowerFormalArguments_AIX(
1324  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1325  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1326  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1327  SDValue LowerFormalArguments_64SVR4(
1328  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1329  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1330  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1331  SDValue LowerFormalArguments_32SVR4(
1332  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1333  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1334  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1335 
1336  SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1337  SDValue CallSeqStart,
1338  ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1339  const SDLoc &dl) const;
1340 
1341  SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1342  const SmallVectorImpl<ISD::OutputArg> &Outs,
1343  const SmallVectorImpl<SDValue> &OutVals,
1344  const SmallVectorImpl<ISD::InputArg> &Ins,
1345  const SDLoc &dl, SelectionDAG &DAG,
1346  SmallVectorImpl<SDValue> &InVals,
1347  const CallBase *CB) const;
1348  SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1349  const SmallVectorImpl<ISD::OutputArg> &Outs,
1350  const SmallVectorImpl<SDValue> &OutVals,
1351  const SmallVectorImpl<ISD::InputArg> &Ins,
1352  const SDLoc &dl, SelectionDAG &DAG,
1353  SmallVectorImpl<SDValue> &InVals,
1354  const CallBase *CB) const;
1355  SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags,
1356  const SmallVectorImpl<ISD::OutputArg> &Outs,
1357  const SmallVectorImpl<SDValue> &OutVals,
1358  const SmallVectorImpl<ISD::InputArg> &Ins,
1359  const SDLoc &dl, SelectionDAG &DAG,
1360  SmallVectorImpl<SDValue> &InVals,
1361  const CallBase *CB) const;
1362 
1363  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1364  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1365  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1366 
1367  SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1368  SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1369  SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1370  SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1371  SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1372  SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1373  SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1374  SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1375  SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1376  SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1377  SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
1378  SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1379  SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1380  SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1381  SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1382  SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
1383  SelectionDAG &DAG) const;
1384  SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1385  DAGCombinerInfo &DCI) const;
1386 
1387  /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1388  /// SETCC with integer subtraction when (1) there is a legal way of doing it
1389  /// (2) keeping the result of comparison in GPR has performance benefit.
1390  SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1391 
1392  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1393  int &RefinementSteps, bool &UseOneConstNR,
1394  bool Reciprocal) const override;
1395  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1396  int &RefinementSteps) const override;
1397  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1398  const DenormalMode &Mode) const override;
1399  SDValue getSqrtResultForDenormInput(SDValue Operand,
1400  SelectionDAG &DAG) const override;
1401  unsigned combineRepeatedFPDivisors() const override;
1402 
1403  SDValue
1404  combineElementTruncationToVectorTruncation(SDNode *N,
1405  DAGCombinerInfo &DCI) const;
1406 
1407  /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1408  /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1409  /// essentially any shuffle of v8i16 vectors that just inserts one element
1410  /// from one vector into the other.
1411  SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1412 
1413  /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1414  /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1415  /// essentially v16i8 vector version of VINSERTH.
1416  SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1417 
1418  /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
1419  /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1.
1420  SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1421 
1422  // Return whether the call instruction can potentially be optimized to a
1423  // tail call. This will cause the optimizers to attempt to move, or
1424  // duplicate return instructions to help enable tail call optimizations.
1425  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1426  bool hasBitPreservingFPLogic(EVT VT) const override;
1427  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1428 
1429  /// getAddrModeForFlags - Based on the set of address flags, select the most
1430  /// optimal instruction format to match by.
1431  PPC::AddrMode getAddrModeForFlags(unsigned Flags) const;
1432 
1433  /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute
1434  /// the address flags of the load/store instruction that is to be matched.
1435  /// The address flags are stored in a map, which is then searched
1436  /// through to determine the optimal load/store instruction format.
1437  unsigned computeMOFlags(const SDNode *Parent, SDValue N,
1438  SelectionDAG &DAG) const;
1439  }; // end class PPCTargetLowering
1440 
1441  namespace PPC {
1442 
1443  FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1444  const TargetLibraryInfo *LibInfo);
1445 
1446  } // end namespace PPC
1447 
1448  bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1449  bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1450  bool isIntS34Immediate(SDNode *N, int64_t &Imm);
1451  bool isIntS34Immediate(SDValue Op, int64_t &Imm);
1452 
1453  bool convertToNonDenormSingle(APInt &ArgAPInt);
1454  bool convertToNonDenormSingle(APFloat &ArgAPFloat);
1455  bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat);
1456 
1457 } // end namespace llvm
1458 
1459 #endif // LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
llvm::PPCISD::READ_TIME_BASE
@ READ_TIME_BASE
Definition: PPCISelLowering.h:267
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:451
llvm::PPCISD::MTCTR
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
Definition: PPCISelLowering.h:192
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:497
ValueTypes.h
llvm::PPC::isXXINSERTWMask
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
Definition: PPCISelLowering.cpp:2191
llvm::PPCTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: PPCISelLowering.cpp:3151
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1319
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::PPCTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: PPCISelLowering.cpp:3136
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::PPC::isXXSLDWIShuffleMask
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
Definition: PPCISelLowering.cpp:2266
llvm::PPCISD::FCTIDZ
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Definition: PPCISelLowering.h:72
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::PPCISD::FSQRT
@ FSQRT
Square root instruction.
Definition: PPCISelLowering.h:96
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1088
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::PPCTargetLowering::CallFlags::NoMerge
const bool NoMerge
Definition: PPCISelLowering.h:1155
llvm::PPCISD::BDNZ
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
Definition: PPCISelLowering.h:296
llvm::PPCISD::RFEBB
@ RFEBB
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
Definition: PPCISelLowering.h:428
Metadata.h
llvm::PPC::isXXBRDShuffleMask
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
Definition: PPCISelLowering.cpp:2349
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4252
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1350
llvm::PPCTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Definition: PPCISelLowering.cpp:2952
llvm::PPCISD::FP_EXTEND_HALF
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
Definition: PPCISelLowering.h:458
llvm::PPC::AM_PrefixDForm
@ AM_PrefixDForm
Definition: PPCISelLowering.h:736
llvm::PPCISD::VABSD
@ VABSD
An SDNode for Power9 vector absolute value difference.
Definition: PPCISelLowering.h:454
llvm::isIntS34Immediate
bool isIntS34Immediate(SDNode *N, int64_t &Imm)
isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...
Definition: PPCISelLowering.cpp:2592
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Function
Definition: Function.h:62
llvm::PPCISD::CLRBHRB
@ CLRBHRB
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
Definition: PPCISelLowering.h:421
llvm::PPCTargetLowering::shouldKeepZExtForFP16Conv
bool shouldKeepZExtForFP16Conv() const override
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
Definition: PPCISelLowering.h:1082
llvm::PPC::AM_DForm
@ AM_DForm
Definition: PPCISelLowering.h:733
llvm::PPC::MOF_SubtargetP9
@ MOF_SubtargetP9
Definition: PPCISelLowering.h:725
llvm::PPCTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
Definition: PPCISelLowering.h:766
llvm::PPCTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: PPCISelLowering.cpp:17850
llvm::PPCTargetLowering::SelectAddressRegReg
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=None) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
Definition: PPCISelLowering.cpp:2609
InlineAsm.h
llvm::PPCTargetLowering::isAccessedAsGotIndirect
bool isAccessedAsGotIndirect(SDValue N) const
Definition: PPCISelLowering.cpp:16279
llvm::PPCISD::MTVSRA
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
Definition: PPCISelLowering.h:223
llvm::PPCISD::SEXT_LD_SPLAT
@ SEXT_LD_SPLAT
VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that sign-extends.
Definition: PPCISelLowering.h:576
llvm::PPCTargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: PPCISelLowering.h:790
llvm::PPC::AM_None
@ AM_None
Definition: PPCISelLowering.h:732
llvm::PPC::MOF_NotAddNorCst
@ MOF_NotAddNorCst
Definition: PPCISelLowering.h:705
llvm::PPCISD::MAT_PCREL_ADDR
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
Definition: PPCISelLowering.h:463
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::PPCISD::ACC_BUILD
@ ACC_BUILD
ACC_BUILD = Build an accumulator register from 4 VSX registers.
Definition: PPCISelLowering.h:476
llvm::PPCTargetLowering::expandVSXLoadForLE
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: PPCISelLowering.cpp:14438
llvm::PPCISD::VPERM
@ VPERM
VPERM - The PPC VPERM Instruction.
Definition: PPCISelLowering.h:100
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::PPCTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
Definition: PPCISelLowering.cpp:16437
llvm::PPC::MOF_RPlusSImm16Mult16
@ MOF_RPlusSImm16Mult16
Definition: PPCISelLowering.h:709
llvm::PPCISD::STXSIX
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
Definition: PPCISelLowering.h:544
llvm::PPCISD::XSMINCDP
@ XSMINCDP
Definition: PPCISelLowering.h:56
llvm::PPCTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: PPCISelLowering.cpp:16311
llvm::MemOp
Definition: TargetLowering.h:111
llvm::PPCTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: PPCISelLowering.cpp:15882
llvm::PPC::isSplatShuffleMask
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
Definition: PPCISelLowering.cpp:2123
llvm::PPCISD::BUILD_SPE64
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
Definition: PPCISelLowering.h:235
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::PPC::isXXPERMDIShuffleMask
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
Definition: PPCISelLowering.cpp:2365
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::PPCISD::FADDRTZ
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
Definition: PPCISelLowering.h:302
llvm::PPCISD::Lo
@ Lo
Definition: PPCISelLowering.h:136
llvm::PPCTargetLowering::ccAssignFnForCall
CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: PPCISelLowering.cpp:17838
llvm::PPCTargetLowering::getByValTypeAlignment
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
Definition: PPCISelLowering.cpp:1564
llvm::AttributeList
Definition: Attributes.h:404
llvm::PPCISD::XXSPLT
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
Definition: PPCISelLowering.h:104
llvm::PPCISD::LD_GOT_TPREL_L
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
Definition: PPCISelLowering.h:335
llvm::PPCISD::FCFIDU
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
Definition: PPCISelLowering.h:65
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::PPCISD::STRICT_FCTIDZ
@ STRICT_FCTIDZ
Definition: PPCISelLowering.h:491
llvm::PPCISD::FNMSUB
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
Definition: PPCISelLowering.h:170
llvm::PPCTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: PPCISelLowering.cpp:15742
llvm::PPCISD::XXSPLTI32DX
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
Definition: PPCISelLowering.h:113
llvm::PPC::MOF_RPlusSImm34
@ MOF_RPlusSImm34
Definition: PPCISelLowering.h:710
llvm::PPC::AM_DQForm
@ AM_DQForm
Definition: PPCISelLowering.h:735
llvm::PPCTargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: PPCISelLowering.cpp:11641
llvm::Optional< CallingConv::ID >
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::PPC::AM_DSForm
@ AM_DSForm
Definition: PPCISelLowering.h:734
llvm::PPCISD::DYNALLOC
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
Definition: PPCISelLowering.h:144
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::PPCTargetLowering::EmitPartwordAtomicBinary
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Definition: PPCISelLowering.cpp:11426
llvm::PPCISD::MFBHRBE
@ MFBHRBE
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.
Definition: PPCISelLowering.h:425
llvm::PPCTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: PPCISelLowering.cpp:17671
llvm::PPCTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: PPCISelLowering.cpp:11223
llvm::PPCTargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: PPCISelLowering.h:798
llvm::PPCTargetLowering::CallFlags::IsPatchPoint
const bool IsPatchPoint
Definition: PPCISelLowering.h:1152
llvm::PPCISD::ZEXT_LD_SPLAT
@ ZEXT_LD_SPLAT
VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that zero-extends.
Definition: PPCISelLowering.h:572
llvm::PPC::MOF_SubtargetP10
@ MOF_SubtargetP10
Definition: PPCISelLowering.h:726
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: PPCISelLowering.cpp:16678
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::PPCISD::LBRX
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
Definition: PPCISelLowering.h:520
llvm::PPCISD::FCFID
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
Definition: PPCISelLowering.h:61
llvm::PPCTargetLowering::expandVSXStoreForLE
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: PPCISelLowering.cpp:14506
llvm::PPC::isVPKUHUMShuffleMask
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
Definition: PPCISelLowering.cpp:1799
llvm::convertToNonDenormSingle
bool convertToNonDenormSingle(APInt &ArgAPInt)
Definition: PPCISelLowering.cpp:9072
llvm::PPCISD::BDZ
@ BDZ
Definition: PPCISelLowering.h:297
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::PPCTargetLowering::PPCTargetLowering
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
Definition: PPCISelLowering.cpp:143
llvm::PPCISD::ADDI_TLSLD_L
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
Definition: PPCISelLowering.h:384
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
llvm::PPCTargetLowering::isEqualityCmpFoldedWithSignedCmp
bool isEqualityCmpFoldedWithSignedCmp() const override
Return true if instruction generated for equality comparison is folded with instruction generated for...
Definition: PPCISelLowering.h:794
llvm::PPC::MOF_SubtargetSPE
@ MOF_SubtargetSPE
Definition: PPCISelLowering.h:727
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
MachineValueType.h
llvm::PPC::isXXBRWShuffleMask
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
Definition: PPCISelLowering.cpp:2345
llvm::PPCISD::UINT_VEC_TO_FP
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
Definition: PPCISelLowering.h:248
llvm::PPCISD::ANDI_rec_1_GT_BIT
@ ANDI_rec_1_GT_BIT
Definition: PPCISelLowering.h:263
llvm::PPCTargetLowering::CallFlags::HasNest
const bool HasNest
Definition: PPCISelLowering.h:1154
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:185
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1350
llvm::PPCISD::STXVD2X
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:581
TargetLowering.h
llvm::Type::isArrayTy
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:214
llvm::PPCISD::STRICT_FCTIDUZ
@ STRICT_FCTIDUZ
Definition: PPCISelLowering.h:493
llvm::PPCTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: PPCISelLowering.cpp:11027
llvm::PPCISD::STFIWX
@ STFIWX
STFIWX - The STFIWX instruction.
Definition: PPCISelLowering.h:524
llvm::PPC::MOF_RPlusLo
@ MOF_RPlusLo
Definition: PPCISelLowering.h:707
llvm::PPCISD::CR6SET
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
Definition: PPCISelLowering.h:315
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1104
llvm::PPCTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: PPCISelLowering.cpp:16457
llvm::PPCISD::TC_RETURN
@ TC_RETURN
TC_RETURN - A tail call return.
Definition: PPCISelLowering.h:312
llvm::PPCISD::STRICT_FCFIDUS
@ STRICT_FCFIDUS
Definition: PPCISelLowering.h:500
llvm::PPCTargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: PPCISelLowering.cpp:1582
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:418
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::PPCISD::GlobalBaseReg
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
Definition: PPCISelLowering.h:156
llvm::PPCTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: PPCISelLowering.cpp:16806
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCTargetLowering::hasSPE
bool hasSPE() const
Definition: PPCISelLowering.cpp:1578
llvm::PPCTargetLowering::isDesirableToTransformToIntegerOp
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition: PPCISelLowering.h:1025
llvm::PPCISD::LFIWZX
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
Definition: PPCISelLowering.h:534
llvm::PPC::MOF_RPlusR
@ MOF_RPlusR
Definition: PPCISelLowering.h:711
llvm::PPC::MOF_ZExt
@ MOF_ZExt
Definition: PPCISelLowering.h:701
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::PPCISD::XXSPLTI_SP_TO_DP
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
Definition: PPCISelLowering.h:109
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3277
llvm::PPCTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: PPCISelLowering.cpp:11113
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1066
llvm::PPCISD::VCMP_rec
@ VCMP_rec
RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.
Definition: PPCISelLowering.h:285
llvm::PPCTargetLowering::CallFlags::CallConv
const CallingConv::ID CallConv
Definition: PPCISelLowering.h:1149
llvm::PPCTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: PPCISelLowering.cpp:16147
llvm::PPCTargetLowering::CallFlags
Structure that collects some common arguments that get passed around between the functions for call l...
Definition: PPCISelLowering.h:1148
llvm::PPCTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: PPCISelLowering.h:893
llvm::PPCISD::ATOMIC_CMP_SWAP_8
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
Definition: PPCISelLowering.h:594
llvm::PPCISD::VADD_SPLAT
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
Definition: PPCISelLowering.h:414
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::InlineAsm::Constraint_es
@ Constraint_es
Definition: InlineAsm.h:250
llvm::PPC::MOF_Vector
@ MOF_Vector
Definition: PPCISelLowering.h:720
llvm::PPCTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
Definition: PPCISelLowering.cpp:15848
llvm::PPCTargetLowering::getNegatedExpression
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Definition: PPCISelLowering.cpp:16716
llvm::Instruction
Definition: Instruction.h:45
llvm::PPCTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: PPCISelLowering.cpp:17887
llvm::PPCTargetLowering::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
Definition: PPCISelLowering.cpp:16603
llvm::PPCISD::SRA_ADDZE
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
Definition: PPCISelLowering.h:180
llvm::PPCISD::MFVSR
@ MFVSR
Direct move from a VSX register to a GPR.
Definition: PPCISelLowering.h:220
llvm::InlineAsm::Constraint_Zy
@ Constraint_Zy
Definition: InlineAsm.h:270
llvm::PPCTargetLowering::SelectAddressPCRel
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
Definition: PPCISelLowering.cpp:2892
llvm::PPCISD::PPC32_GOT
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
Definition: PPCISelLowering.h:320
llvm::PPC::isVSLDOIShuffleMask
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
Definition: PPCISelLowering.cpp:2079
llvm::PPC::MOF_DoubleWordInt
@ MOF_DoubleWordInt
Definition: PPCISelLowering.h:718
llvm::PPCISD::XXSWAPD
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
Definition: PPCISelLowering.h:435
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::PPCTargetLowering::CallFlags::IsIndirect
const bool IsIndirect
Definition: PPCISelLowering.h:1153
llvm::PPCISD::ADDIS_GOT_TPREL_HA
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
Definition: PPCISelLowering.h:329
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::PPCISD::SRL
@ SRL
These nodes represent PPC shifts.
Definition: PPCISelLowering.h:165
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::PPCISD::MTVSRZ
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
Definition: PPCISelLowering.h:226
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::PPCTargetLowering::SelectOptimalAddrMode
PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const
SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...
Definition: PPCISelLowering.cpp:17703
llvm::PPCISD::LFIWAX
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Definition: PPCISelLowering.h:529
llvm::PPCISD::STORE_VEC_BE
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:586
llvm::PPCTargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: PPCISelLowering.cpp:16800
llvm::PPCISD::FP_TO_SINT_IN_VSR
@ FP_TO_SINT_IN_VSR
Definition: PPCISelLowering.h:82
llvm::PPCTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: PPCISelLowering.cpp:17912
llvm::PPCTargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: PPCISelLowering.cpp:15797
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::PPCISD::XXMFACC
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
Definition: PPCISelLowering.h:488
llvm::PPCISD::FCTIWZ
@ FCTIWZ
Definition: PPCISelLowering.h:73
llvm::PPC::MOF_None
@ MOF_None
Definition: PPCISelLowering.h:697
llvm::PPCTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Definition: PPCISelLowering.cpp:11884
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::PPCTargetLowering::SelectAddressRegRegOnly
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
Definition: PPCISelLowering.cpp:2854
llvm::PPCISD::CALL_NOP
@ CALL_NOP
Definition: PPCISelLowering.h:187
llvm::PPC::isXXBRHShuffleMask
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
Definition: PPCISelLowering.cpp:2341
llvm::PPCISD::ADD_TLS
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
Definition: PPCISelLowering.h:343
llvm::APFloat
Definition: APFloat.h:701
llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: PPCISelLowering.cpp:3167
llvm::PPCTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: PPCISelLowering.cpp:16672
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::PPCTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: PPCISelLowering.h:786
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::PPCISD::LXSIZX
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
Definition: PPCISelLowering.h:539
uint64_t
llvm::PPC::MOF_ScalarFloat
@ MOF_ScalarFloat
Definition: PPCISelLowering.h:719
llvm::PPCISD::CALL_RM
@ CALL_RM
The variants that implicitly define rounding mode for calls with strictfp semantics.
Definition: PPCISelLowering.h:205
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1259
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:925
llvm::PPCISD::MFFS
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
Definition: PPCISelLowering.h:305
llvm::PPCISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: PPCISelLowering.h:48
llvm::PPC::isVMRGHShuffleMask
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
Definition: PPCISelLowering.cpp:1960
llvm::PPCTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: PPCISelLowering.cpp:16071
llvm::PPC::MOF_SExt
@ MOF_SExt
Definition: PPCISelLowering.h:700
llvm::PPCISD::CALL_NOTOC_RM
@ CALL_NOTOC_RM
Definition: PPCISelLowering.h:207
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::PPCTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: PPCISelLowering.h:778
PPCInstrInfo.h
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::PPC::AddrMode
AddrMode
Definition: PPCISelLowering.h:731
llvm::PPCTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: PPCISelLowering.cpp:16260
llvm::PPCTargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Definition: PPCISelLowering.cpp:1765
llvm::TargetLoweringBase::NegatibleCost
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition: TargetLowering.h:267
llvm::PPCISD::SRA
@ SRA
Definition: PPCISelLowering.h:166
llvm::PPCISD::Hi
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Definition: PPCISelLowering.h:135
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:850
llvm::PPCISD::PROBED_ALLOCA
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
Definition: PPCISelLowering.h:153
llvm::PPCTargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: PPCISelLowering.cpp:11892
llvm::PPCISD::EXTRACT_SPE
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
Definition: PPCISelLowering.h:238
llvm::PPCISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: PPCISelLowering.h:273
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
Definition: PPCISelLowering.cpp:16518
llvm::PPC::MOF_PCRel
@ MOF_PCRel
Definition: PPCISelLowering.h:712
llvm::PPCISD::BUILD_FP128
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
Definition: PPCISelLowering.h:229
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::PPCTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: PPCISelLowering.cpp:1757
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::PPCISD::EXTRACT_VSX_REG
@ EXTRACT_VSX_REG
EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.
Definition: PPCISelLowering.h:485
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::PPCTargetLowering
Definition: PPCISelLowering.h:742
llvm::PPCTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: PPCISelLowering.cpp:16667
llvm::PPC::MemOpFlags
MemOpFlags
Definition: PPCISelLowering.h:696
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::PPCISD::DYNAREAOFFSET
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
Definition: PPCISelLowering.h:149
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::PPCTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: PPCISelLowering.cpp:16306
llvm::PPC::isVMRGEOShuffleMask
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
Definition: PPCISelLowering.cpp:2050
info
lazy value info
Definition: LazyValueInfo.cpp:59
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::isIntS16Immediate
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
Definition: PPCISelLowering.cpp:2543
llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
Definition: PPCISelLowering.h:256
llvm::PPCISD::STRICT_FCFIDU
@ STRICT_FCFIDU
Definition: PPCISelLowering.h:498
llvm::PPCTargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: PPCISelLowering.cpp:11783
llvm::PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
Definition: PPCISelLowering.h:1091
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::PPCISD::VCMP
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
Definition: PPCISelLowering.h:279
llvm::PPCISD::STRICT_FADDRTZ
@ STRICT_FADDRTZ
Constrained floating point add in round-to-zero mode.
Definition: PPCISelLowering.h:503
llvm::PPCISD::STRICT_FCFIDS
@ STRICT_FCFIDS
Definition: PPCISelLowering.h:499
llvm::PPCTargetLowering::SelectAddressEVXRegReg
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
Definition: PPCISelLowering.cpp:2574
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
llvm::PPCTargetLowering::SelectAddressRegImm34
bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...
Definition: PPCISelLowering.cpp:2805
llvm::PPCTargetLowering::CallFlags::IsTailCall
const bool IsTailCall
Definition: PPCISelLowering.h:1150
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCISD::FCFIDUS
@ FCFIDUS
Definition: PPCISelLowering.h:67
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1253
llvm::PPCISD::PPC32_PICGOT
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
Definition: PPCISelLowering.h:324
llvm::PPCISD::LXVRZX
@ LXVRZX
LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero...
Definition: PPCISelLowering.h:555
llvm::PPCISD::LD_VSX_LH
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
Definition: PPCISelLowering.h:564
llvm::PPC::getSplatIdxForPPCMnemonics
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
Definition: PPCISelLowering.cpp:2421
llvm::PPCTargetLowering::isJumpTableRelative
bool isJumpTableRelative() const override
Definition: PPCISelLowering.cpp:3143
llvm::PPCISD::PADDI_DTPREL
@ PADDI_DTPREL
G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 inst...
Definition: PPCISelLowering.h:408
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:731
llvm::PPCTargetLowering::EmitAtomicBinary
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Definition: PPCISelLowering.cpp:11253
llvm::PPC::AM_XForm
@ AM_XForm
Definition: PPCISelLowering.h:737
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: PPCISelLowering.cpp:16655
llvm::PPCISD::LXVD2X
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:549
llvm::PPCISD::ADDIS_TLSGD_HA
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
Definition: PPCISelLowering.h:348
llvm::PPCISD::CALL_NOP_RM
@ CALL_NOP_RM
Definition: PPCISelLowering.h:206
llvm::PPCISD::ADDI_DTPREL_L
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
Definition: PPCISelLowering.h:404
llvm::PPC::isVPKUDUMShuffleMask
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
Definition: PPCISelLowering.cpp:1867
llvm::PPCISD::FCTIWUZ
@ FCTIWUZ
Definition: PPCISelLowering.h:78
llvm::PPCTargetLowering::isFPExtFree
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
Definition: PPCISelLowering.cpp:16501
CallingConv.h
llvm::PPCISD::ADDI_TLSLD_L_ADDR
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
Definition: PPCISelLowering.h:394
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::PPCISD::FSEL
@ FSEL
FSEL - Traditional three-operand fsel node.
Definition: PPCISelLowering.h:52
llvm::PPCISD::RET_FLAG
@ RET_FLAG
Return with a flag operand, matched by 'blr'.
Definition: PPCISelLowering.h:212
llvm::PPCISD::TOC_ENTRY
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
Definition: PPCISelLowering.h:600
llvm::PPCTargetLowering::CallFlags::IsVarArg
const bool IsVarArg
Definition: PPCISelLowering.h:1151
llvm::PPC::isXXBRQShuffleMask
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
Definition: PPCISelLowering.cpp:2353
llvm::PPCISD::STRICT_FCTIWUZ
@ STRICT_FCTIWUZ
Definition: PPCISelLowering.h:494
llvm::PPC::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Definition: PPCFastISel.cpp:2466
llvm::PPCTargetLowering::SelectAddressRegImm
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
Definition: PPCISelLowering.cpp:2700
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1720
llvm::KnownBits
Definition: KnownBits.h:23
llvm::PPCISD::BCTRL_LOAD_TOC_RM
@ BCTRL_LOAD_TOC_RM
Definition: PPCISelLowering.h:209
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
uint16_t
llvm::PPCISD::STBRX
@ STBRX
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
Definition: PPCISelLowering.h:514
CallingConvLower.h
llvm::PPCISD::XSMAXCDP
@ XSMAXCDP
XSMAXCDP, XSMINCDP - C-type min/max instructions.
Definition: PPCISelLowering.h:55
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::PPCTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: PPCISelLowering.cpp:16782
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4261
llvm::PPCISD::FCTIDUZ
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
Definition: PPCISelLowering.h:77
llvm::PPCISD::ADDIS_DTPREL_HA
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
Definition: PPCISelLowering.h:399
llvm::PPCISD::ANDI_rec_1_EQ_BIT
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
Definition: PPCISelLowering.h:262
llvm::PPCTargetLowering::BuildSDIVPow2
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
Definition: PPCISelLowering.cpp:15709
Function.h
llvm::PPCTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Definition: PPCISelLowering.cpp:16514
llvm::PPC::MOF_SubWordInt
@ MOF_SubWordInt
Definition: PPCISelLowering.h:716
llvm::PPCISD::SWAP_NO_CHAIN
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
Definition: PPCISelLowering.h:439
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::PPCISD::NodeType
NodeType
Definition: PPCISelLowering.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::PPC::isVPKUWUMShuffleMask
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
Definition: PPCISelLowering.cpp:1830
llvm::PPCISD::CALL
@ CALL
CALL - A direct function call.
Definition: PPCISelLowering.h:186
llvm::PPCISD::CR6UNSET
@ CR6UNSET
Definition: PPCISelLowering.h:316
llvm::PPCTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: PPCISelLowering.cpp:16790
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:869
llvm::PPCISD::BCTRL_LOAD_TOC
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
Definition: PPCISelLowering.h:201
llvm::PPC::MOF_RPlusSImm16Mult4
@ MOF_RPlusSImm16Mult4
Definition: PPCISelLowering.h:708
llvm::PPCTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: PPCISelLowering.h:782
llvm::PPCTargetLowering::CallFlags::CallFlags
CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
Definition: PPCISelLowering.h:1157
llvm::PPCISD::BCTRL_RM
@ BCTRL_RM
Definition: PPCISelLowering.h:208
llvm::PPCISD::LOAD_VEC_BE
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
Definition: PPCISelLowering.h:560
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:926
llvm::PPCISD::ADDIS_TLSLD_HA
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
Definition: PPCISelLowering.h:378
llvm::PPC::MOF_WordInt
@ MOF_WordInt
Definition: PPCISelLowering.h:717
llvm::PPCISD::ADDI_TLSGD_L
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
Definition: PPCISelLowering.h:354
llvm::checkConvertToNonDenormSingle
bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)
Definition: PPCISelLowering.cpp:9082
llvm::PPCTargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: PPCISelLowering.cpp:16465
llvm::PPCISD::EXTSWSLI
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
Definition: PPCISelLowering.h:174
llvm::PPCISD::TLSGD_AIX
@ TLSGD_AIX
GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two re...
Definition: PPCISelLowering.h:373
llvm::PPC::MOF_RPlusSImm16
@ MOF_RPlusSImm16
Definition: PPCISelLowering.h:706
llvm::PPCISD::MFOCRF
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
Definition: PPCISelLowering.h:217
llvm::PPC::isVMRGLShuffleMask
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
Definition: PPCISelLowering.cpp:1935
llvm::PPCISD::VECINSERT
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
Definition: PPCISelLowering.h:117
llvm::PPCISD::CALL_NOTOC
@ CALL_NOTOC
Definition: PPCISelLowering.h:188
llvm::PPCTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: PPCISelLowering.cpp:11233
llvm::PPCISD::SINT_VEC_TO_FP
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
Definition: PPCISelLowering.h:244
llvm::PPC::AM_PCRel
@ AM_PCRel
Definition: PPCISelLowering.h:738
llvm::PPCISD::LD_SPLAT
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
Definition: PPCISelLowering.h:568
llvm::PPCISD::SHL
@ SHL
Definition: PPCISelLowering.h:167
llvm::PPCISD::VEXTS
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
Definition: PPCISelLowering.h:86
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1265
N
#define N
llvm::PPCTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: PPCISelLowering.cpp:16556
llvm::PPCTargetLowering::SelectForceXFormMode
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...
Definition: PPCISelLowering.cpp:17637
llvm::PPCTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: PPCISelLowering.cpp:12079
llvm::PPCTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: PPCISelLowering.cpp:16481
llvm::PPCISD::PAIR_BUILD
@ PAIR_BUILD
PAIR_BUILD = Build a vector pair register from 2 VSX registers.
Definition: PPCISelLowering.h:479
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4353
llvm::PPCTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: PPCISelLowering.cpp:1574
llvm::PPCISD::FRE
@ FRE
Reciprocal estimate instructions (unary FP ops).
Definition: PPCISelLowering.h:89
llvm::PPCISD::ST_VSR_SCAL_INT
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
Definition: PPCISelLowering.h:589
llvm::PPCTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: PPCISelLowering.cpp:17858
llvm::PPCISD::XXPERMDI
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
Definition: PPCISelLowering.h:125
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::PPC::MOF_NoExt
@ MOF_NoExt
Definition: PPCISelLowering.h:702
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::PPC::MOF_Vector256
@ MOF_Vector256
Definition: PPCISelLowering.h:721
llvm::PPCISD::GET_TLS_ADDR
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
Definition: PPCISelLowering.h:359
RegName
#define RegName(no)
llvm::PPCISD::BCTRL
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
Definition: PPCISelLowering.h:196
llvm::PPCTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
Definition: PPCISelLowering.cpp:16698
llvm::PPCTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: PPCISelLowering.h:973
llvm::PPC::MOF_AddrIsSImm32
@ MOF_AddrIsSImm32
Definition: PPCISelLowering.h:713
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:504
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1478
llvm::PPCISD::CMPB
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
Definition: PPCISelLowering.h:128
llvm::PPCISD::GET_TLSLD_ADDR
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
Definition: PPCISelLowering.h:389
llvm::PPCTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: PPCISelLowering.h:1018
llvm::PPCISD::ATOMIC_CMP_SWAP_16
@ ATOMIC_CMP_SWAP_16
Definition: PPCISelLowering.h:595
llvm::PPCTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: PPCISelLowering.h:804
llvm::PPCISD::FP_TO_UINT_IN_VSR
@ FP_TO_UINT_IN_VSR
Floating-point-to-interger conversion instructions.
Definition: PPCISelLowering.h:81
llvm::Sched::Preference
Preference
Definition: TargetLowering.h:97
llvm::PPC::get_VSPLTI_elt
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
Definition: PPCISelLowering.cpp:2435
llvm::PPCTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: PPCISelLowering.cpp:15938
llvm::PPC::MOF_SubtargetBeforeP9
@ MOF_SubtargetBeforeP9
Definition: PPCISelLowering.h:724
llvm::PPCISD::STRICT_FCFID
@ STRICT_FCFID
Constrained integer-to-floating-point conversion instructions.
Definition: PPCISelLowering.h:497
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:256
llvm::PPCISD::FTSQRT
@ FTSQRT
Test instruction for software square root.
Definition: PPCISelLowering.h:93
llvm::PPCTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
Definition: PPCISelLowering.cpp:1586
MachineFunction.h
llvm::PPCISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: PPCISelLowering.h:270
llvm::PPCTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Definition: PPCISelLowering.cpp:16510
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::PPCTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
Definition: PPCISelLowering.cpp:16583
llvm::PPCTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: PPCISelLowering.cpp:14962
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::PPCTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind Kind) const override
Definition: PPCISelLowering.h:753
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:526
llvm::PPCISD::TLS_LOCAL_EXEC_MAT_ADDR
@ TLS_LOCAL_EXEC_MAT_ADDR
TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access ...
Definition: PPCISelLowering.h:473
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::PPCISD::ADDI_TLSGD_L_ADDR
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
Definition: PPCISelLowering.h:364
llvm::PPCISD::STRICT_FCTIWZ
@ STRICT_FCTIWZ
Definition: PPCISelLowering.h:492
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:237
llvm::PPCISD::COND_BRANCH
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
Definition: PPCISelLowering.h:292
llvm::InlineAsm::Constraint_Z
@ Constraint_Z
Definition: InlineAsm.h:268
llvm::PPCTargetLowering::emitProbedAlloca
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: PPCISelLowering.cpp:11917
llvm::PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR
@ TLS_DYNAMIC_MAT_PCREL_ADDR
TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dyna...
Definition: PPCISelLowering.h:468
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::PPCISD::FRSQRTE
@ FRSQRTE
Definition: PPCISelLowering.h:90
llvm::PPCISD::VECSHL
@ VECSHL
VECSHL - The PPC vector shift left instruction.
Definition: PPCISelLowering.h:121
llvm::PPCISD::FCFIDS
@ FCFIDS
Definition: PPCISelLowering.h:66
llvm::LLT
Definition: LowLevelTypeImpl.h:39