LLVM  16.0.0git
PPCInstrInfo.h
Go to the documentation of this file.
1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 
16 #include "PPCRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "PPCGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 /// PPCII - This namespace holds all of the PowerPC target-specific
25 /// per-instruction flags. These must match the corresponding definitions in
26 /// PPC.td and PPCInstrFormats.td.
27 namespace PPCII {
28 enum {
29  // PPC970 Instruction Flags. These flags describe the characteristics of the
30  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
31  // raw machine instructions.
32 
33  /// PPC970_First - This instruction starts a new dispatch group, so it will
34  /// always be the first one in the group.
35  PPC970_First = 0x1,
36 
37  /// PPC970_Single - This instruction starts a new dispatch group and
38  /// terminates it, so it will be the sole instruction in the group.
40 
41  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
42  /// two dispatch pipes to be available to issue.
44 
45  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
46  /// an instruction is issued to.
49 };
51  /// These are the various PPC970 execution unit pipelines. Each instruction
52  /// is one of these.
53  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
54  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
55  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
56  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
57  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
58  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
59  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
60  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
61 };
62 
63 enum {
64  /// Shift count to bypass PPC970 flags
66 
67  /// This instruction is an X-Form memory operation.
69  /// This instruction is prefixed.
70  Prefixed = 0x1 << (NewDef_Shift + 1),
71  /// This instruction produced a sign extended result.
72  SExt32To64 = 0x1 << (NewDef_Shift + 2),
73  /// This instruction produced a zero extended result.
74  ZExt32To64 = 0x1 << (NewDef_Shift + 3)
75 };
76 } // end namespace PPCII
77 
78 // Instructions that have an immediate form might be convertible to that
79 // form if the correct input is a result of a load immediate. In order to
80 // know whether the transformation is special, we might need to know some
81 // of the details of the two forms.
82 struct ImmInstrInfo {
83  // Is the immediate field in the immediate form signed or unsigned?
85  // Does the immediate need to be a multiple of some value?
87  // Is R0/X0 treated specially by the original r+r instruction?
88  // If so, in which operand?
90  // Is R0/X0 treated specially by the new r+i instruction?
91  // If so, in which operand?
93  // Is the operation commutative?
95  // The operand number to check for add-immediate def.
97  // The operand number for the immediate.
99  // The opcode of the new instruction.
101  // The size of the immediate.
103  // The immediate should be truncated to N bits.
105  // Is the instruction summing the operand
107 };
108 
109 // Information required to convert an instruction to just a materialized
110 // immediate.
112  unsigned Imm : 16;
113  unsigned Is64Bit : 1;
114  unsigned SetCR : 1;
115 };
116 
117 // Index into the OpcodesForSpill array.
136  SOK_LastOpcodeSpill // This must be last on the enum.
137 };
138 
139 // Define list of load and store spill opcodes.
140 #define NoInstr PPC::INSTRUCTION_LIST_END
141 #define Pwr8LoadOpcodes \
142  { \
143  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
144  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
145  PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
146  PPC::RESTORE_QUADWORD \
147  }
148 
149 #define Pwr9LoadOpcodes \
150  { \
151  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
152  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
153  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
154  NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
155  }
156 
157 #define Pwr10LoadOpcodes \
158  { \
159  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
160  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
161  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
162  PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
163  }
164 
165 #define FutureLoadOpcodes \
166  { \
167  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
168  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
169  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
170  PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD \
171  }
172 
173 #define Pwr8StoreOpcodes \
174  { \
175  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
176  PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
177  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
178  PPC::SPILL_QUADWORD \
179  }
180 
181 #define Pwr9StoreOpcodes \
182  { \
183  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
184  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
185  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
186  PPC::SPILL_QUADWORD \
187  }
188 
189 #define Pwr10StoreOpcodes \
190  { \
191  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
192  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
193  PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
194  NoInstr, NoInstr, PPC::SPILL_QUADWORD \
195  }
196 
197 #define FutureStoreOpcodes \
198  { \
199  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
200  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
201  PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
202  PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD \
203  }
204 
205 // Initialize arrays for load and store spill opcodes on supported subtargets.
206 #define StoreOpcodesForSpill \
207  { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
208 #define LoadOpcodesForSpill \
209  { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
210 
211 class PPCSubtarget;
213  PPCSubtarget &Subtarget;
214  const PPCRegisterInfo RI;
215  const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
217  const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
219 
220  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
221  int FrameIdx, const TargetRegisterClass *RC,
222  SmallVectorImpl<MachineInstr *> &NewMIs) const;
223  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
224  unsigned DestReg, int FrameIdx,
225  const TargetRegisterClass *RC,
226  SmallVectorImpl<MachineInstr *> &NewMIs) const;
227 
228  // Replace the instruction with single LI if possible. \p DefMI must be LI or
229  // LI8.
230  bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
231  unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
232  // If the inst is imm-form and its register operand is produced by a ADDI, put
233  // the imm into the inst directly and remove the ADDI if possible.
234  bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
235  unsigned OpNoForForwarding) const;
236  // If the inst is x-form and has imm-form and one of its operand is produced
237  // by a LI, put the imm into the inst directly and remove the LI if possible.
238  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
239  unsigned ConstantOpNo,
240  MachineInstr &DefMI) const;
241  // If the inst is x-form and has imm-form and one of its operand is produced
242  // by an add-immediate, try to transform it when possible.
243  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
244  unsigned ConstantOpNo, MachineInstr &DefMI,
245  bool KillDefMI) const;
246  // Try to find that, if the instruction 'MI' contains any operand that
247  // could be forwarded from some inst that feeds it. If yes, return the
248  // Def of that operand. And OpNoForForwarding is the operand index in
249  // the 'MI' for that 'Def'. If we see another use of this Def between
250  // the Def and the MI, SeenIntermediateUse becomes 'true'.
251  MachineInstr *getForwardingDefMI(MachineInstr &MI,
252  unsigned &OpNoForForwarding,
253  bool &SeenIntermediateUse) const;
254 
255  // Can the user MI have it's source at index \p OpNoForForwarding
256  // forwarded from an add-immediate that feeds it?
257  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
258  unsigned OpNoForForwarding) const;
259  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
260  const ImmInstrInfo &III,
261  MachineOperand *&ImmMO,
262  MachineOperand *&RegMO) const;
263  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
264  const MachineInstr &DefMI,
265  const ImmInstrInfo &III,
266  int64_t &Imm,
267  int64_t BaseImm = 0) const;
268  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
269  const MachineInstr &DefMI,
270  const MachineInstr &MI, bool KillDefMI,
271  bool &IsFwdFeederRegKilled,
272  bool &SeenIntermediateUse) const;
273  unsigned getSpillTarget() const;
274  ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
275  ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
276  unsigned getSpillIndex(const TargetRegisterClass *RC) const;
277  int16_t getFMAOpIdxInfo(unsigned Opcode) const;
278  void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
281  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
282  bool isLoadFromConstantPool(MachineInstr *I) const;
283  Register
284  generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
285  SmallVectorImpl<MachineInstr *> &InsInstrs) const;
286  const Constant *getConstantFromConstantPool(MachineInstr *I) const;
287  virtual void anchor();
288 
289 protected:
290  /// Commutes the operands in the given instruction.
291  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
292  ///
293  /// Do not call this method for a non-commutable instruction or for
294  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
295  /// Even though the instruction is commutable, the method may still
296  /// fail to commute the operands, null pointer is returned in such cases.
297  ///
298  /// For example, we can commute rlwimi instructions, but only if the
299  /// rotate amt is zero. We also have to munge the immediates a bit.
301  unsigned OpIdx1,
302  unsigned OpIdx2) const override;
303 
304 public:
305  explicit PPCInstrInfo(PPCSubtarget &STI);
306 
307  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
308  /// such, whenever a client has an instance of instruction info, it should
309  /// always be able to get register info as well (through this method).
310  ///
311  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
312 
313  bool isXFormMemOp(unsigned Opcode) const {
314  return get(Opcode).TSFlags & PPCII::XFormMemOp;
315  }
316  bool isPrefixed(unsigned Opcode) const {
317  return get(Opcode).TSFlags & PPCII::Prefixed;
318  }
319  bool isSExt32To64(unsigned Opcode) const {
320  return get(Opcode).TSFlags & PPCII::SExt32To64;
321  }
322  bool isZExt32To64(unsigned Opcode) const {
323  return get(Opcode).TSFlags & PPCII::ZExt32To64;
324  }
325 
326  /// Check if Opcode corresponds to a call instruction that should be marked
327  /// with the NOTOC relocation.
328  bool isNoTOCCallInstr(unsigned Opcode) const {
329  if (!get(Opcode).isCall())
330  return false;
331 
332  switch (Opcode) {
333  default:
334 #ifndef NDEBUG
335  llvm_unreachable("Unknown call opcode");
336 #endif
337  return false;
338  case PPC::BL8_NOTOC:
339  case PPC::BL8_NOTOC_TLS:
340  case PPC::BL8_NOTOC_RM:
341  return true;
342 #ifndef NDEBUG
343  case PPC::BL8:
344  case PPC::BL:
345  case PPC::BL8_TLS:
346  case PPC::BL_TLS:
347  case PPC::BLA8:
348  case PPC::BLA:
349  case PPC::BCCL:
350  case PPC::BCCLA:
351  case PPC::BCL:
352  case PPC::BCLn:
353  case PPC::BL8_NOP:
354  case PPC::BL_NOP:
355  case PPC::BL8_NOP_TLS:
356  case PPC::BLA8_NOP:
357  case PPC::BCTRL8:
358  case PPC::BCTRL:
359  case PPC::BCCCTRL8:
360  case PPC::BCCCTRL:
361  case PPC::BCCTRL8:
362  case PPC::BCCTRL:
363  case PPC::BCCTRL8n:
364  case PPC::BCCTRLn:
365  case PPC::BL8_RM:
366  case PPC::BLA8_RM:
367  case PPC::BL8_NOP_RM:
368  case PPC::BLA8_NOP_RM:
369  case PPC::BCTRL8_RM:
370  case PPC::BCTRL8_LDinto_toc:
371  case PPC::BCTRL8_LDinto_toc_RM:
372  case PPC::BL8_TLS_:
373  case PPC::TCRETURNdi8:
374  case PPC::TCRETURNai8:
375  case PPC::TCRETURNri8:
376  case PPC::TAILBCTR8:
377  case PPC::TAILB8:
378  case PPC::TAILBA8:
379  case PPC::BCLalways:
380  case PPC::BLRL:
381  case PPC::BCCLRL:
382  case PPC::BCLRL:
383  case PPC::BCLRLn:
384  case PPC::BDZL:
385  case PPC::BDNZL:
386  case PPC::BDZLA:
387  case PPC::BDNZLA:
388  case PPC::BDZLp:
389  case PPC::BDNZLp:
390  case PPC::BDZLAp:
391  case PPC::BDNZLAp:
392  case PPC::BDZLm:
393  case PPC::BDNZLm:
394  case PPC::BDZLAm:
395  case PPC::BDNZLAm:
396  case PPC::BDZLRL:
397  case PPC::BDNZLRL:
398  case PPC::BDZLRLp:
399  case PPC::BDNZLRLp:
400  case PPC::BDZLRLm:
401  case PPC::BDNZLRLm:
402  case PPC::BL_RM:
403  case PPC::BLA_RM:
404  case PPC::BL_NOP_RM:
405  case PPC::BCTRL_RM:
406  case PPC::TCRETURNdi:
407  case PPC::TCRETURNai:
408  case PPC::TCRETURNri:
409  case PPC::BCTRL_LWZinto_toc:
410  case PPC::BCTRL_LWZinto_toc_RM:
411  case PPC::TAILBCTR:
412  case PPC::TAILB:
413  case PPC::TAILBA:
414  return false;
415 #endif
416  }
417  }
418 
419  static bool isSameClassPhysRegCopy(unsigned Opcode) {
420  unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
421  PPC::VOR, PPC::XXLOR, PPC::XXLORf,
422  PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
423  PPC::EVOR, -1U};
424  for (int i = 0; CopyOpcodes[i] != -1U; i++)
425  if (Opcode == CopyOpcodes[i])
426  return true;
427  return false;
428  }
429 
432  const ScheduleDAG *DAG) const override;
435  const ScheduleDAG *DAG) const override;
436 
437  unsigned getInstrLatency(const InstrItineraryData *ItinData,
438  const MachineInstr &MI,
439  unsigned *PredCost = nullptr) const override;
440 
441  int getOperandLatency(const InstrItineraryData *ItinData,
442  const MachineInstr &DefMI, unsigned DefIdx,
443  const MachineInstr &UseMI,
444  unsigned UseIdx) const override;
446  SDNode *DefNode, unsigned DefIdx,
447  SDNode *UseNode, unsigned UseIdx) const override {
448  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
449  UseNode, UseIdx);
450  }
451 
452  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
453  const MachineInstr &DefMI,
454  unsigned DefIdx) const override {
455  // Machine LICM should hoist all instructions in low-register-pressure
456  // situations; none are sufficiently free to justify leaving in a loop
457  // body.
458  return false;
459  }
460 
461  bool useMachineCombiner() const override {
462  return true;
463  }
464 
465  /// When getMachineCombinerPatterns() finds patterns, this function generates
466  /// the instructions that could replace the original code sequence
471  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
472 
473  /// Return true when there is potentially a faster code sequence for a fma
474  /// chain ending in \p Root. All potential patterns are output in the \p
475  /// P array.
476  bool getFMAPatterns(MachineInstr &Root,
478  bool DoRegPressureReduce) const;
479 
480  /// Return true when there is potentially a faster code sequence
481  /// for an instruction chain ending in <Root>. All potential patterns are
482  /// output in the <Pattern> array.
485  bool DoRegPressureReduce) const override;
486 
487  /// On PowerPC, we leverage machine combiner pass to reduce register pressure
488  /// when the register pressure is high for one BB.
489  /// Return true if register pressure for \p MBB is high and ABI is supported
490  /// to reduce register pressure. Otherwise return false.
492  const MachineBasicBlock *MBB,
493  const RegisterClassInfo *RegClassInfo) const override;
494 
495  /// Fixup the placeholders we put in genAlternativeCodeSequence() for
496  /// MachineCombiner.
497  void
499  SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
500 
501  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
502 
503  /// On PowerPC, we try to reassociate FMA chain which will increase
504  /// instruction size. Set extension resource length limit to 1 for edge case.
505  /// Resource Length is calculated by scaled resource usage in getCycles().
506  /// Because of the division in getCycles(), it returns different cycles due to
507  /// legacy scaled resource usage. So new resource length may be same with
508  /// legacy or 1 bigger than legacy.
509  /// We need to execlude the 1 bigger case even the resource length is not
510  /// perserved for more FMA chain reassociations on PowerPC.
511  int getExtendResourceLenLimit() const override { return 1; }
512 
513  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
514  MachineInstr &NewMI1,
515  MachineInstr &NewMI2) const override;
516 
517  // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
518  // and clears nuw, nsw, and exact flags.
519  void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const;
520 
522  Register &SrcReg, Register &DstReg,
523  unsigned &SubIdx) const override;
524  unsigned isLoadFromStackSlot(const MachineInstr &MI,
525  int &FrameIndex) const override;
526  bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
527  unsigned isStoreToStackSlot(const MachineInstr &MI,
528  int &FrameIndex) const override;
529 
530  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
531  unsigned &SrcOpIdx2) const override;
532 
534  MachineBasicBlock::iterator MI) const override;
535 
536 
537  // Branch analysis.
539  MachineBasicBlock *&FBB,
541  bool AllowModify) const override;
543  int *BytesRemoved = nullptr) const override;
546  const DebugLoc &DL,
547  int *BytesAdded = nullptr) const override;
548 
549  // Select analysis.
551  Register, Register, Register, int &, int &,
552  int &) const override;
554  const DebugLoc &DL, Register DstReg,
556  Register FalseReg) const override;
557 
559  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
560  bool KillSrc) const override;
561 
564  Register SrcReg, bool isKill, int FrameIndex,
565  const TargetRegisterClass *RC,
566  const TargetRegisterInfo *TRI) const override;
567 
568  // Emits a register spill without updating the register class for vector
569  // registers. This ensures that when we spill a vector register the
570  // element order in the register is the same as it was in memory.
573  unsigned SrcReg, bool isKill, int FrameIndex,
574  const TargetRegisterClass *RC,
575  const TargetRegisterInfo *TRI) const;
576 
579  Register DestReg, int FrameIndex,
580  const TargetRegisterClass *RC,
581  const TargetRegisterInfo *TRI) const override;
582 
583  // Emits a register reload without updating the register class for vector
584  // registers. This ensures that when we reload a vector register the
585  // element order in the register is the same as it was in memory.
588  unsigned DestReg, int FrameIndex,
589  const TargetRegisterClass *RC,
590  const TargetRegisterInfo *TRI) const;
591 
592  unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
593 
594  unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
595 
596  bool
598 
600  MachineRegisterInfo *MRI) const override;
601 
603  Register Reg) const;
604 
605  // If conversion by predication (only supported by some branch instructions).
606  // All of the profitability checks always return true; it is always
607  // profitable to use the predicated branches.
609  unsigned NumCycles, unsigned ExtraPredCycles,
610  BranchProbability Probability) const override {
611  return true;
612  }
613 
615  unsigned NumT, unsigned ExtraT,
616  MachineBasicBlock &FMBB,
617  unsigned NumF, unsigned ExtraF,
618  BranchProbability Probability) const override;
619 
621  BranchProbability Probability) const override {
622  return true;
623  }
624 
626  MachineBasicBlock &FMBB) const override {
627  return false;
628  }
629 
630  // Predication support.
631  bool isPredicated(const MachineInstr &MI) const override;
632 
634  const MachineBasicBlock *MBB,
635  const MachineFunction &MF) const override;
636 
638  ArrayRef<MachineOperand> Pred) const override;
639 
641  ArrayRef<MachineOperand> Pred2) const override;
642 
643  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
644  bool SkipDead) const override;
645 
646  // Comparison optimization.
647 
648  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
649  Register &SrcReg2, int64_t &Mask,
650  int64_t &Value) const override;
651 
652  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
653  Register SrcReg2, int64_t Mask, int64_t Value,
654  const MachineRegisterInfo *MRI) const override;
655 
656 
657  /// Return true if get the base operand, byte offset of an instruction and
658  /// the memory width. Width is the size of memory that is being
659  /// loaded/stored (e.g. 1, 2, 4, 8).
661  const MachineOperand *&BaseOp,
662  int64_t &Offset, unsigned &Width,
663  const TargetRegisterInfo *TRI) const;
664 
665  bool optimizeCmpPostRA(MachineInstr &MI) const;
666 
667  /// Get the base operand and byte offset of an instruction that reads/writes
668  /// memory.
670  const MachineInstr &LdSt,
671  SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
672  bool &OffsetIsScalable, unsigned &Width,
673  const TargetRegisterInfo *TRI) const override;
674 
675  /// Returns true if the two given memory operations should be scheduled
676  /// adjacent.
679  unsigned NumLoads, unsigned NumBytes) const override;
680 
681  /// Return true if two MIs access different memory addresses and false
682  /// otherwise
683  bool
685  const MachineInstr &MIb) const override;
686 
687  /// GetInstSize - Return the number of bytes of code the specified
688  /// instruction may be. This returns the maximum number of bytes.
689  ///
690  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
691 
692  MCInst getNop() const override;
693 
694  std::pair<unsigned, unsigned>
695  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
696 
699 
702 
703  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
704  bool expandVSXMemPseudo(MachineInstr &MI) const;
705 
706  // Lower pseudo instructions after register allocation.
707  bool expandPostRAPseudo(MachineInstr &MI) const override;
708 
709  static bool isVFRegister(unsigned Reg) {
710  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
711  }
712  static bool isVRRegister(unsigned Reg) {
713  return Reg >= PPC::V0 && Reg <= PPC::V31;
714  }
715  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
716  static int getRecordFormOpcode(unsigned Opcode);
717 
718  bool isTOCSaveMI(const MachineInstr &MI) const;
719 
720  std::pair<bool, bool>
721  isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
722  const MachineRegisterInfo *MRI) const;
723 
724  // Return true if the register is sign-extended from 32 to 64 bits.
725  bool isSignExtended(const unsigned Reg,
726  const MachineRegisterInfo *MRI) const {
727  return isSignOrZeroExtended(Reg, 0, MRI).first;
728  }
729 
730  // Return true if the register is zero-extended from 32 to 64 bits.
731  bool isZeroExtended(const unsigned Reg,
732  const MachineRegisterInfo *MRI) const {
733  return isSignOrZeroExtended(Reg, 0, MRI).second;
734  }
735 
737  MachineInstr **KilledDef = nullptr) const;
738  bool foldFrameOffset(MachineInstr &MI) const;
739  bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
740  bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
741  bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
742  bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
743  unsigned &XFormOpcode,
744  int64_t &OffsetOfImmInstr,
745  ImmInstrInfo &III) const;
746  bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
747  MachineInstr *&ADDIMI, int64_t &OffsetAddi,
748  int64_t OffsetImm) const;
749 
750  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
751  /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
752  /// register killed/dead flags semantics, this function can be called to fix
753  /// up. Before calling this function,
754  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
755  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
756  /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
757  /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
758  /// will be adjust to true definition.
759  /// 3. We can do accurate fixup for the case when all instructions between
760  /// [\p StartMI, \p EndMI] are in same basic block.
761  /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
762  /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
763  /// and for post-RA, we give an assertion as without reaching definition
764  /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
765  void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
766  unsigned RegNo) const;
767  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
768  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
769  int64_t Imm) const;
770 
771  bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
772  bool PostRA) const;
773 
774  // In PostRA phase, try to find instruction defines \p Reg before \p MI.
775  // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
777  bool &SeenIntermediateUse) const;
778 
779  // Materialize immediate after RA.
782  const DebugLoc &DL, Register Reg,
783  int64_t Imm) const;
784 
785  /// getRegNumForOperand - some operands use different numbering schemes
786  /// for the same registers. For example, a VSX instruction may have any of
787  /// vs0-vs63 allocated whereas an Altivec instruction could only have
788  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
789  /// register number needed for the opcode/operand number combination.
790  /// The operand number argument will be useful when we need to extend this
791  /// to instructions that use both Altivec and VSX numbering (for different
792  /// operands).
793  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
794  unsigned OpNo) {
795  int16_t regClass = Desc.OpInfo[OpNo].RegClass;
796  switch (regClass) {
797  // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
798  // VSX32-VSX63 during encoding/disassembling
799  case PPC::VSSRCRegClassID:
800  case PPC::VSFRCRegClassID:
801  if (isVFRegister(Reg))
802  return PPC::VSX32 + (Reg - PPC::VF0);
803  break;
804  // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
805  // VSX32-VSX63 during encoding/disassembling
806  case PPC::VSRCRegClassID:
807  if (isVRRegister(Reg))
808  return PPC::VSX32 + (Reg - PPC::V0);
809  break;
810  // Other RegClass doesn't need mapping
811  default:
812  break;
813  }
814  return Reg;
815  }
816 
817  /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
818  bool isBDNZ(unsigned Opcode) const;
819 
820  /// Find the hardware loop instruction used to set-up the specified loop.
821  /// On PPC, we have two instructions used to set-up the hardware loop
822  /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
823  /// instructions to indicate the end of a loop.
824  MachineInstr *
825  findLoopInstr(MachineBasicBlock &PreHeader,
826  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
827 
828  /// Analyze loop L, which must be a single-basic-block loop, and if the
829  /// conditions can be understood enough produce a PipelinerLoopInfo object.
830  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
831  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
832 };
833 
834 }
835 
836 #endif
llvm::PPCII::PPC970_First
@ PPC970_First
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:35
llvm::PPCII::PPC970_Unit
PPC970_Unit
Definition: PPCInstrInfo.h:50
llvm::PPCInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1125
i
i
Definition: README.txt:29
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
llvm::PPCInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:1971
llvm::PPCInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: PPCInstrInfo.cpp:2973
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::PPCInstrInfo::fixupIsDeadOrKill
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
Definition: PPCInstrInfo.cpp:3463
llvm::PPCII::ZExt32To64
@ ZExt32To64
This instruction produced a zero extended result.
Definition: PPCInstrInfo.h:74
llvm::PPCInstrInfo::isZExt32To64
bool isZExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:322
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::PPCInstrInfo::replaceInstrOperandWithImm
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
Definition: PPCInstrInfo.cpp:3247
PPCRegisterInfo.h
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::PPCInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:3084
llvm::PPCInstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:625
llvm::SOK_SpillToVSR
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:129
llvm::SOK_PairedVecSpill
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:130
llvm::PPCInstrInfo::isPrefixed
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:316
llvm::ImmInstrInfo::OpNoForForwarding
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:96
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::LoadImmediateInfo::SetCR
unsigned SetCR
Definition: PPCInstrInfo.h:114
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::PPCII::PPC970_VALU
@ PPC970_VALU
Definition: PPCInstrInfo.h:58
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:445
llvm::PPCInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2381
llvm::PPCInstrInfo::isVFRegister
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:709
llvm::PPCInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: PPCInstrInfo.cpp:1681
llvm::PPCInstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Definition: PPCInstrInfo.cpp:254
llvm::PPCInstrInfo::getDefMIPostRA
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Definition: PPCInstrInfo.cpp:3301
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SOK_VRVectorSpill
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:125
llvm::PPCInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: PPCInstrInfo.cpp:2049
llvm::PPCInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: PPCInstrInfo.cpp:2351
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:212
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::PPCInstrInfo::isADDInstrEligibleForFolding
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
Definition: PPCInstrInfo.cpp:3696
llvm::PPCII::PPC970_FPU
@ PPC970_FPU
Definition: PPCInstrInfo.h:56
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::PPCInstrInfo::getStoreOpcodeForSpill
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1918
llvm::ImmInstrInfo::ZeroIsSpecialNew
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:92
llvm::SOK_PairedG8Spill
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:135
llvm::PPCInstrInfo::getExtendResourceLenLimit
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:511
llvm::LoadImmediateInfo::Is64Bit
unsigned Is64Bit
Definition: PPCInstrInfo.h:113
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::PPCInstrInfo::isBDNZ
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
Definition: PPCInstrInfo.cpp:5516
llvm::PPCInstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
Definition: PPCInstrInfo.cpp:223
llvm::PPCInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: PPCInstrInfo.cpp:138
llvm::PPCInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: PPCInstrInfo.cpp:1569
llvm::SOK_LastOpcodeSpill
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:136
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::PPCInstrInfo::onlyFoldImmediate
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
Definition: PPCInstrInfo.cpp:2062
llvm::PPCInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
Definition: PPCInstrInfo.cpp:118
llvm::PPCII::PPC970_Shift
@ PPC970_Shift
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:47
llvm::PPCInstrInfo::shouldReduceRegisterPressure
bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
Definition: PPCInstrInfo.cpp:615
llvm::PPCInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
Definition: PPCInstrInfo.cpp:2896
llvm::ImmInstrInfo::IsSummingOperands
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:106
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::PPCInstrInfo::materializeImmPostRA
void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
Definition: PPCInstrInfo.cpp:3318
llvm::PPCInstrInfo::replaceInstrWithLI
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
Definition: PPCInstrInfo.cpp:3278
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::LoadImmediateInfo
Definition: PPCInstrInfo.h:111
llvm::SOK_Float8Spill
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:121
llvm::PPCII::Prefixed
@ Prefixed
This instruction is prefixed.
Definition: PPCInstrInfo.h:70
llvm::PPCInstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: PPCInstrInfo.cpp:1054
llvm::PPCInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:2031
llvm::PPCInstrInfo::isNoTOCCallInstr
bool isNoTOCCallInstr(unsigned Opcode) const
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
Definition: PPCInstrInfo.h:328
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCII::PPC970_VPERM
@ PPC970_VPERM
Definition: PPCInstrInfo.h:59
llvm::PPCInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: PPCInstrInfo.cpp:2954
llvm::SOK_SPESpill
@ SOK_SPESpill
Definition: PPCInstrInfo.h:134
llvm::PPCInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: PPCInstrInfo.cpp:1237
llvm::ImmInstrInfo::SignedImm
uint64_t SignedImm
Definition: PPCInstrInfo.h:84
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCInstrInfo::isXFormMemOp
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:313
llvm::PPCII::NewDef_Shift
@ NewDef_Shift
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::PPCInstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: PPCInstrInfo.cpp:1257
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::SOK_WAccumulatorSpill
@ SOK_WAccumulatorSpill
Definition: PPCInstrInfo.h:133
LoadOpcodesForSpill
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:208
llvm::PPCInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2129
llvm::PPCInstrInfo::isImmInstrEligibleForFolding
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
Definition: PPCInstrInfo.cpp:3703
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SOK_UAccumulatorSpill
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:132
llvm::SOK_Int4Spill
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:119
llvm::PPCInstrInfo::updatedRC
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:5207
llvm::PPCInstrInfo::findLoopInstr
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
Definition: PPCInstrInfo.cpp:5610
llvm::LoadImmediateInfo::Imm
unsigned Imm
Definition: PPCInstrInfo.h:112
llvm::PPCInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: PPCInstrInfo.cpp:2181
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::PPCInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: PPCInstrInfo.cpp:1221
llvm::PPCInstrInfo::analyzeLoopForPipelining
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: PPCInstrInfo.cpp:5590
llvm::PPCII::PPC970_Cracked
@ PPC970_Cracked
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:43
llvm::PPCInstrInfo::optimizeCmpPostRA
bool optimizeCmpPostRA(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:2766
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::PPCInstrInfo::isADDIInstrEligibleForFolding
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
Definition: PPCInstrInfo.cpp:3679
llvm::PPCInstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: PPCInstrInfo.cpp:774
llvm::SOK_CRSpill
@ SOK_CRSpill
Definition: PPCInstrInfo.h:123
llvm::PPCInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: PPCInstrInfo.cpp:2316
llvm::PPCInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: PPCInstrInfo.cpp:2170
llvm::PPCInstrInfo::isSameClassPhysRegCopy
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:419
llvm::SOK_VectorFloat8Spill
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:127
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::PPCII::PPC970_CRU
@ PPC970_CRU
Definition: PPCInstrInfo.h:57
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::PPCInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: PPCInstrInfo.cpp:1526
uint64_t
llvm::PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2994
llvm::PPCInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:1085
llvm::ImmInstrInfo
Definition: PPCInstrInfo.h:82
llvm::PPCII::PPC970_Single
@ PPC970_Single
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:39
llvm::ImmInstrInfo::IsCommutative
uint64_t IsCommutative
Definition: PPCInstrInfo.h:94
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ImmInstrInfo::TruncateImmTo
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:104
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: PPCInstrInfo.cpp:168
llvm::SpillOpcodeKey
SpillOpcodeKey
Definition: PPCInstrInfo.h:118
llvm::SOK_Int8Spill
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:120
llvm::PPCInstrInfo::hasLowDefLatency
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:452
llvm::PPCInstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:461
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::PPCInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1069
llvm::PPCII::PPC970_Mask
@ PPC970_Mask
Definition: PPCInstrInfo.h:48
llvm::SOK_VectorFloat4Spill
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:128
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::PPCInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: PPCInstrInfo.cpp:1266
llvm::PPCInstrInfo::getFMAPatterns
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
Definition: PPCInstrInfo.cpp:369
llvm::SOK_AccumulatorSpill
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:131
llvm::PPCInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Definition: PPCInstrInfo.cpp:2285
llvm::PPCInstrInfo::loadRegFromStackSlotNoUpd
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:2006
llvm::ImmInstrInfo::ZeroIsSpecialOrig
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:89
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ScheduleDAG
Definition: ScheduleDAG.h:554
llvm::ArrayRef< unsigned >
llvm::PPCInstrInfo::convertToImmediateForm
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
Definition: PPCInstrInfo.cpp:3791
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::PPCInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:2159
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCInstrInfo::instrHasImmForm
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
Definition: PPCInstrInfo.cpp:3980
llvm::PPCII::SExt32To64
@ SExt32To64
This instruction produced a sign extended result.
Definition: PPCInstrInfo.h:72
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCInstrInfo::isSExt32To64
bool isSExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:319
llvm::PPCInstrInfo::isTOCSaveMI
bool isTOCSaveMI(const MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:5326
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::ImmInstrInfo::ImmMustBeMultipleOf
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:86
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
PPCGenInstrInfo
llvm::PPCInstrInfo::getRegisterInfo
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:311
llvm::PPCInstrInfo::getRegNumForOperand
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:793
uint16_t
llvm::PPCInstrInfo::combineRLWINM
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
Definition: PPCInstrInfo.cpp:3843
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::PPCInstrInfo::isSignOrZeroExtended
std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.cpp:5348
llvm::PPCInstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
Definition: PPCInstrInfo.cpp:759
llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
Definition: PPCInstrInfo.cpp:5648
llvm::PPCII::PPC970_FXU
@ PPC970_FXU
Definition: PPCInstrInfo.h:54
llvm::PPCISD::BCTRL_RM
@ BCTRL_RM
Definition: PPCISelLowering.h:209
llvm::PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2979
llvm::PPCInstrInfo::getLoadOpcodeForSpill
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1924
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
StoreOpcodesForSpill
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:206
llvm::PPCInstrInfo::getRecordFormOpcode
static int getRecordFormOpcode(unsigned Opcode)
Definition: PPCInstrInfo.cpp:5213
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::PPCInstrInfo::isValidToBeChangedReg
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
Definition: PPCInstrInfo.cpp:3746
llvm::SOK_Float4Spill
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:122
llvm::PPCInstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
Definition: PPCInstrInfo.cpp:5625
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::PPCInstrInfo::isZeroExtended
bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:731
llvm::PPCInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: PPCInstrInfo.cpp:2845
llvm::PPCInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: PPCInstrInfo.cpp:1137
llvm::PPCInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: PPCInstrInfo.cpp:1473
llvm::SOK_VSXVectorSpill
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:126
llvm::SmallVectorImpl< MachineInstr * >
llvm::PPCISD::BCTRL
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
Definition: PPCISelLowering.h:197
llvm::PPCInstrInfo::expandVSXMemPseudo
bool expandVSXMemPseudo(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:3018
llvm::PPCII::PPC970_LSU
@ PPC970_LSU
Definition: PPCInstrInfo.h:55
llvm::PPCII::PPC970_BRU
@ PPC970_BRU
Definition: PPCInstrInfo.h:60
llvm::PPCInstrInfo::CreateTargetHazardRecognizer
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
Definition: PPCInstrInfo.cpp:101
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SOK_CRBitSpill
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:124
llvm::PPCInstrInfo::foldFrameOffset
bool foldFrameOffset(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:3582
llvm::PPCInstrInfo::storeRegToStackSlotNoUpd
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:1951
llvm::PPCInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:620
llvm::PPCInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:608
llvm::PPCInstrInfo::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)
Definition: PPCInstrInfo.cpp:92
llvm::PPCInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: PPCInstrInfo.cpp:1441
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::PPCInstrInfo::isSignExtended
bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:725
llvm::PPCII::XFormMemOp
@ XFormMemOp
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:68
llvm::ImmInstrInfo::ImmOpcode
uint64_t ImmOpcode
Definition: PPCInstrInfo.h:100
llvm::ImmInstrInfo::ImmOpNo
uint64_t ImmOpNo
Definition: PPCInstrInfo.h:98
llvm::PPCInstrInfo::finalizeInsInstrs
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
Definition: PPCInstrInfo.cpp:545
llvm::ImmInstrInfo::ImmWidth
uint64_t ImmWidth
Definition: PPCInstrInfo.h:102
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::PPCII::PPC970_Pseudo
@ PPC970_Pseudo
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:53
llvm::PPCInstrInfo::isVRRegister
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:712
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20