LLVM 19.0.0git
PPCInstrInfo.h
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1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/ADT/SmallSet.h"
21
22#define GET_INSTRINFO_HEADER
23#include "PPCGenInstrInfo.inc"
24
25namespace llvm {
26
27// Instructions that have an immediate form might be convertible to that
28// form if the correct input is a result of a load immediate. In order to
29// know whether the transformation is special, we might need to know some
30// of the details of the two forms.
32 // Is the immediate field in the immediate form signed or unsigned?
34 // Does the immediate need to be a multiple of some value?
36 // Is R0/X0 treated specially by the original r+r instruction?
37 // If so, in which operand?
39 // Is R0/X0 treated specially by the new r+i instruction?
40 // If so, in which operand?
42 // Is the operation commutative?
44 // The operand number to check for add-immediate def.
46 // The operand number for the immediate.
48 // The opcode of the new instruction.
50 // The size of the immediate.
52 // The immediate should be truncated to N bits.
54 // Is the instruction summing the operand
56};
57
58// Information required to convert an instruction to just a materialized
59// immediate.
61 unsigned Imm : 16;
62 unsigned Is64Bit : 1;
63 unsigned SetCR : 1;
64};
65
66// Index into the OpcodesForSpill array.
85 SOK_LastOpcodeSpill // This must be last on the enum.
86};
87
88// PPC MachineCombiner patterns
90 // These are patterns matched by the PowerPC to reassociate FMA chains.
93
94 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
95 // reduce register pressure.
98
99};
100
101// Define list of load and store spill opcodes.
102#define NoInstr PPC::INSTRUCTION_LIST_END
103#define Pwr8LoadOpcodes \
104 { \
105 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
106 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
107 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
108 PPC::RESTORE_QUADWORD \
109 }
110
111#define Pwr9LoadOpcodes \
112 { \
113 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
114 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
115 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
116 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
117 }
118
119#define Pwr10LoadOpcodes \
120 { \
121 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
122 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
123 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
124 PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
125 }
126
127#define FutureLoadOpcodes \
128 { \
129 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
130 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
131 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
132 PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD \
133 }
134
135#define Pwr8StoreOpcodes \
136 { \
137 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
138 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
139 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
140 PPC::SPILL_QUADWORD \
141 }
142
143#define Pwr9StoreOpcodes \
144 { \
145 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
146 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
147 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
148 PPC::SPILL_QUADWORD \
149 }
150
151#define Pwr10StoreOpcodes \
152 { \
153 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
154 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
155 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
156 NoInstr, NoInstr, PPC::SPILL_QUADWORD \
157 }
158
159#define FutureStoreOpcodes \
160 { \
161 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
162 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
163 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
164 PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD \
165 }
166
167// Initialize arrays for load and store spill opcodes on supported subtargets.
168#define StoreOpcodesForSpill \
169 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
170#define LoadOpcodesForSpill \
171 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
172
173class PPCSubtarget;
175 PPCSubtarget &Subtarget;
176 const PPCRegisterInfo RI;
177 const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
179 const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
181
182 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
183 int FrameIdx, const TargetRegisterClass *RC,
184 SmallVectorImpl<MachineInstr *> &NewMIs) const;
185 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
186 unsigned DestReg, int FrameIdx,
187 const TargetRegisterClass *RC,
188 SmallVectorImpl<MachineInstr *> &NewMIs) const;
189
190 // Replace the instruction with single LI if possible. \p DefMI must be LI or
191 // LI8.
192 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
193 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
194 // If the inst is imm-form and its register operand is produced by a ADDI, put
195 // the imm into the inst directly and remove the ADDI if possible.
196 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
197 unsigned OpNoForForwarding) const;
198 // If the inst is x-form and has imm-form and one of its operand is produced
199 // by a LI, put the imm into the inst directly and remove the LI if possible.
200 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
201 unsigned ConstantOpNo,
202 MachineInstr &DefMI) const;
203 // If the inst is x-form and has imm-form and one of its operand is produced
204 // by an add-immediate, try to transform it when possible.
205 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
206 unsigned ConstantOpNo, MachineInstr &DefMI,
207 bool KillDefMI) const;
208 // Try to find that, if the instruction 'MI' contains any operand that
209 // could be forwarded from some inst that feeds it. If yes, return the
210 // Def of that operand. And OpNoForForwarding is the operand index in
211 // the 'MI' for that 'Def'. If we see another use of this Def between
212 // the Def and the MI, SeenIntermediateUse becomes 'true'.
213 MachineInstr *getForwardingDefMI(MachineInstr &MI,
214 unsigned &OpNoForForwarding,
215 bool &SeenIntermediateUse) const;
216
217 // Can the user MI have it's source at index \p OpNoForForwarding
218 // forwarded from an add-immediate that feeds it?
219 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
220 unsigned OpNoForForwarding) const;
221 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
222 const ImmInstrInfo &III,
223 MachineOperand *&ImmMO,
224 MachineOperand *&RegMO) const;
225 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
226 const MachineInstr &DefMI,
227 const ImmInstrInfo &III,
228 int64_t &Imm,
229 int64_t BaseImm = 0) const;
230 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
231 const MachineInstr &DefMI,
232 const MachineInstr &MI, bool KillDefMI,
233 bool &IsFwdFeederRegKilled,
234 bool &SeenIntermediateUse) const;
235 unsigned getSpillTarget() const;
236 ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
237 ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
238 unsigned getSpillIndex(const TargetRegisterClass *RC) const;
239 int16_t getFMAOpIdxInfo(unsigned Opcode) const;
240 void reassociateFMA(MachineInstr &Root, unsigned Pattern,
243 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
245 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
246 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
247 virtual void anchor();
248
249protected:
250 /// Commutes the operands in the given instruction.
251 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
252 ///
253 /// Do not call this method for a non-commutable instruction or for
254 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
255 /// Even though the instruction is commutable, the method may still
256 /// fail to commute the operands, null pointer is returned in such cases.
257 ///
258 /// For example, we can commute rlwimi instructions, but only if the
259 /// rotate amt is zero. We also have to munge the immediates a bit.
261 unsigned OpIdx1,
262 unsigned OpIdx2) const override;
263
264public:
265 explicit PPCInstrInfo(PPCSubtarget &STI);
266
269
270 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
271 /// such, whenever a client has an instance of instruction info, it should
272 /// always be able to get register info as well (through this method).
273 ///
274 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
275
276 bool isXFormMemOp(unsigned Opcode) const {
277 return get(Opcode).TSFlags & PPCII::XFormMemOp;
278 }
279 bool isPrefixed(unsigned Opcode) const {
280 return get(Opcode).TSFlags & PPCII::Prefixed;
281 }
282 bool isSExt32To64(unsigned Opcode) const {
283 return get(Opcode).TSFlags & PPCII::SExt32To64;
284 }
285 bool isZExt32To64(unsigned Opcode) const {
286 return get(Opcode).TSFlags & PPCII::ZExt32To64;
287 }
288
289 static bool isSameClassPhysRegCopy(unsigned Opcode) {
290 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
291 PPC::VOR, PPC::XXLOR, PPC::XXLORf,
292 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
293 PPC::EVOR, -1U};
294 for (int i = 0; CopyOpcodes[i] != -1U; i++)
295 if (Opcode == CopyOpcodes[i])
296 return true;
297 return false;
298 }
299
300 static bool hasPCRelFlag(unsigned TF) {
306 }
307
308 static bool hasGOTFlag(unsigned TF) {
313 }
314
315 static bool hasTLSFlag(unsigned TF) {
316 return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG ||
322 TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS ||
324 }
325
328 const ScheduleDAG *DAG) const override;
331 const ScheduleDAG *DAG) const override;
332
333 unsigned getInstrLatency(const InstrItineraryData *ItinData,
334 const MachineInstr &MI,
335 unsigned *PredCost = nullptr) const override;
336
337 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
338 const MachineInstr &DefMI,
339 unsigned DefIdx,
340 const MachineInstr &UseMI,
341 unsigned UseIdx) const override;
342 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
343 SDNode *DefNode, unsigned DefIdx,
344 SDNode *UseNode,
345 unsigned UseIdx) const override {
346 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
347 UseNode, UseIdx);
348 }
349
350 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
351 const MachineInstr &DefMI,
352 unsigned DefIdx) const override {
353 // Machine LICM should hoist all instructions in low-register-pressure
354 // situations; none are sufficiently free to justify leaving in a loop
355 // body.
356 return false;
357 }
358
359 bool useMachineCombiner() const override {
360 return true;
361 }
362
363 /// When getMachineCombinerPatterns() finds patterns, this function generates
364 /// the instructions that could replace the original code sequence
366 MachineInstr &Root, unsigned Pattern,
369 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
370
371 /// Return true when there is potentially a faster code sequence for a fma
372 /// chain ending in \p Root. All potential patterns are output in the \p
373 /// P array.
375 bool DoRegPressureReduce) const;
376
377 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
378
379 /// Return true when there is potentially a faster code sequence
380 /// for an instruction chain ending in <Root>. All potential patterns are
381 /// output in the <Pattern> array.
384 bool DoRegPressureReduce) const override;
385
386 /// On PowerPC, we leverage machine combiner pass to reduce register pressure
387 /// when the register pressure is high for one BB.
388 /// Return true if register pressure for \p MBB is high and ABI is supported
389 /// to reduce register pressure. Otherwise return false.
391 const MachineBasicBlock *MBB,
392 const RegisterClassInfo *RegClassInfo) const override;
393
394 /// Fixup the placeholders we put in genAlternativeCodeSequence() for
395 /// MachineCombiner.
396 void
397 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
398 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
399
401 bool Invert) const override;
402
403 /// On PowerPC, we try to reassociate FMA chain which will increase
404 /// instruction size. Set extension resource length limit to 1 for edge case.
405 /// Resource Length is calculated by scaled resource usage in getCycles().
406 /// Because of the division in getCycles(), it returns different cycles due to
407 /// legacy scaled resource usage. So new resource length may be same with
408 /// legacy or 1 bigger than legacy.
409 /// We need to execlude the 1 bigger case even the resource length is not
410 /// perserved for more FMA chain reassociations on PowerPC.
411 int getExtendResourceLenLimit() const override { return 1; }
412
413 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
414 // and clears nuw, nsw, and exact flags.
416 void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
417
419 Register &SrcReg, Register &DstReg,
420 unsigned &SubIdx) const override;
422 int &FrameIndex) const override;
423 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
425 int &FrameIndex) const override;
426
427 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
428 unsigned &SrcOpIdx2) const override;
429
431 MachineBasicBlock::iterator MI) const override;
432
433
434 // Branch analysis.
436 MachineBasicBlock *&FBB,
438 bool AllowModify) const override;
440 int *BytesRemoved = nullptr) const override;
443 const DebugLoc &DL,
444 int *BytesAdded = nullptr) const override;
445
446 // Select analysis.
448 Register, Register, Register, int &, int &,
449 int &) const override;
451 const DebugLoc &DL, Register DstReg,
453 Register FalseReg) const override;
454
456 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
457 bool KillSrc) const override;
458
461 bool isKill, int FrameIndex,
462 const TargetRegisterClass *RC,
463 const TargetRegisterInfo *TRI,
464 Register VReg) const override;
465
466 // Emits a register spill without updating the register class for vector
467 // registers. This ensures that when we spill a vector register the
468 // element order in the register is the same as it was in memory.
471 unsigned SrcReg, bool isKill, int FrameIndex,
472 const TargetRegisterClass *RC,
473 const TargetRegisterInfo *TRI) const;
474
477 int FrameIndex, const TargetRegisterClass *RC,
478 const TargetRegisterInfo *TRI,
479 Register VReg) const override;
480
481 // Emits a register reload without updating the register class for vector
482 // registers. This ensures that when we reload a vector register the
483 // element order in the register is the same as it was in memory.
486 unsigned DestReg, int FrameIndex,
487 const TargetRegisterClass *RC,
488 const TargetRegisterInfo *TRI) const;
489
490 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
491
492 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
493
494 bool
496
498 MachineRegisterInfo *MRI) const override;
499
501 Register Reg) const;
502
503 // If conversion by predication (only supported by some branch instructions).
504 // All of the profitability checks always return true; it is always
505 // profitable to use the predicated branches.
507 unsigned NumCycles, unsigned ExtraPredCycles,
508 BranchProbability Probability) const override {
509 return true;
510 }
511
513 unsigned NumT, unsigned ExtraT,
514 MachineBasicBlock &FMBB,
515 unsigned NumF, unsigned ExtraF,
516 BranchProbability Probability) const override;
517
519 BranchProbability Probability) const override {
520 return true;
521 }
522
524 MachineBasicBlock &FMBB) const override {
525 return false;
526 }
527
528 // Predication support.
529 bool isPredicated(const MachineInstr &MI) const override;
530
532 const MachineBasicBlock *MBB,
533 const MachineFunction &MF) const override;
534
536 ArrayRef<MachineOperand> Pred) const override;
537
539 ArrayRef<MachineOperand> Pred2) const override;
540
541 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
542 bool SkipDead) const override;
543
544 // Comparison optimization.
545
546 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
547 Register &SrcReg2, int64_t &Mask,
548 int64_t &Value) const override;
549
550 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
551 Register SrcReg2, int64_t Mask, int64_t Value,
552 const MachineRegisterInfo *MRI) const override;
553
554
555 /// Return true if get the base operand, byte offset of an instruction and
556 /// the memory width. Width is the size of memory that is being
557 /// loaded/stored (e.g. 1, 2, 4, 8).
559 const MachineOperand *&BaseOp,
560 int64_t &Offset, LocationSize &Width,
561 const TargetRegisterInfo *TRI) const;
562
563 bool optimizeCmpPostRA(MachineInstr &MI) const;
564
565 /// Get the base operand and byte offset of an instruction that reads/writes
566 /// memory.
568 const MachineInstr &LdSt,
570 bool &OffsetIsScalable, LocationSize &Width,
571 const TargetRegisterInfo *TRI) const override;
572
573 /// Returns true if the two given memory operations should be scheduled
574 /// adjacent.
576 int64_t Offset1, bool OffsetIsScalable1,
578 int64_t Offset2, bool OffsetIsScalable2,
579 unsigned ClusterSize,
580 unsigned NumBytes) const override;
581
582 /// Return true if two MIs access different memory addresses and false
583 /// otherwise
584 bool
586 const MachineInstr &MIb) const override;
587
588 /// GetInstSize - Return the number of bytes of code the specified
589 /// instruction may be. This returns the maximum number of bytes.
590 ///
591 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
592
593 MCInst getNop() const override;
594
595 std::pair<unsigned, unsigned>
596 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
597
600
601 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
603
604 // Lower pseudo instructions after register allocation.
605 bool expandPostRAPseudo(MachineInstr &MI) const override;
606
607 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
608 static int getRecordFormOpcode(unsigned Opcode);
609
610 bool isTOCSaveMI(const MachineInstr &MI) const;
611
612 std::pair<bool, bool>
613 isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
614 const MachineRegisterInfo *MRI) const;
615
616 // Return true if the register is sign-extended from 32 to 64 bits.
617 bool isSignExtended(const unsigned Reg,
618 const MachineRegisterInfo *MRI) const {
619 return isSignOrZeroExtended(Reg, 0, MRI).first;
620 }
621
622 // Return true if the register is zero-extended from 32 to 64 bits.
623 bool isZeroExtended(const unsigned Reg,
624 const MachineRegisterInfo *MRI) const {
625 return isSignOrZeroExtended(Reg, 0, MRI).second;
626 }
627
629 SmallSet<Register, 4> &RegsToUpdate,
630 MachineInstr **KilledDef = nullptr) const;
631 bool foldFrameOffset(MachineInstr &MI) const;
632 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
633 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
635 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
636 unsigned &XFormOpcode,
637 int64_t &OffsetOfImmInstr,
638 ImmInstrInfo &III) const;
639 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
640 MachineInstr *&ADDIMI, int64_t &OffsetAddi,
641 int64_t OffsetImm) const;
642
643 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
644 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
645 int64_t Imm) const;
646
647 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
648 bool PostRA) const;
649
650 // In PostRA phase, try to find instruction defines \p Reg before \p MI.
651 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
653 bool &SeenIntermediateUse) const;
654
655 // Materialize immediate after RA.
658 const DebugLoc &DL, Register Reg,
659 int64_t Imm) const;
660
661 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
662 bool isBDNZ(unsigned Opcode) const;
663
664 /// Find the hardware loop instruction used to set-up the specified loop.
665 /// On PPC, we have two instructions used to set-up the hardware loop
666 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
667 /// instructions to indicate the end of a loop.
671
672 /// Analyze loop L, which must be a single-basic-block loop, and if the
673 /// conditions can be understood enough produce a PipelinerLoopInfo object.
674 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
675 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
676};
677
678}
679
680#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
uint64_t IntrinsicInst * II
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:170
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:168
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file defines the SmallSet class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This is an important base class in LLVM.
Definition: Constant.h:42
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isPredicated(const MachineInstr &MI) const override
bool expandVSXMemPseudo(MachineInstr &MI) const
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:411
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:279
void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
MCInst getNop() const override
Return the noop instruction to use for a noop.
static int getRecordFormOpcode(unsigned Opcode)
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:276
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:274
CombinerObjective getCombinerObjective(unsigned Pattern) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
bool isTOCSaveMI(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool isSExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:282
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:342
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:623
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:506
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
bool isZExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:285
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:289
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:359
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bool foldFrameOffset(MachineInstr &MI) const
bool isLoadFromConstantPool(MachineInstr *I) const
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:523
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool convertToImmediateForm(MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:350
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:518
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
static bool hasTLSFlag(unsigned TF)
Definition: PPCInstrInfo.h:315
bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:617
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
static bool hasPCRelFlag(unsigned TF)
Definition: PPCInstrInfo.h:300
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool optimizeCmpPostRA(MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const Constant * getConstantFromConstantPool(MachineInstr *I) const
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
static bool hasGOTFlag(unsigned TF)
Definition: PPCInstrInfo.h:308
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:479
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ ZExt32To64
This instruction produced a zero extended result.
@ SExt32To64
This instruction produced a sign extended result.
@ Prefixed
This instruction is prefixed.
@ XFormMemOp
This instruction is an X-Form memory operation.
@ MO_TLSLD_LO
Definition: PPC.h:184
@ MO_TPREL_PCREL_FLAG
MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TPREL_FLAG.
Definition: PPC.h:197
@ MO_GOT_TPREL_PCREL_FLAG
MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:172
@ MO_GOT_PCREL_FLAG
MO_GOT_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG.
Definition: PPC.h:203
@ MO_TLSGDM_FLAG
MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative to the region handle of TLS Gene...
Definition: PPC.h:154
@ MO_PCREL_FLAG
MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to the current instruction addre...
Definition: PPC.h:121
@ MO_TLSLD_FLAG
MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to TLS Local Dynamic model.
Definition: PPC.h:150
@ MO_TLS_PCREL_FLAG
MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TLS.
Definition: PPC.h:200
@ MO_GOT_FLAG
MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.
Definition: PPC.h:126
@ MO_TPREL_HA
Definition: PPC.h:179
@ MO_DTPREL_LO
These values identify relocations on immediates folded into memory operations.
Definition: PPC.h:183
@ MO_TLS
Symbol for VK_PPC_TLS fixup attached to an ADD instruction.
Definition: PPC.h:188
@ MO_TPREL_FLAG
MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to the thread pointer and the sy...
Definition: PPC.h:140
@ MO_TPREL_LO
Definition: PPC.h:178
@ MO_GOT_TLSLD_PCREL_FLAG
MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:166
@ MO_TLSGD_FLAG
MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to TLS General Dynamic model for ...
Definition: PPC.h:135
@ MO_GOT_TLSGD_PCREL_FLAG
MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:160
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
CombinerObjective
The combiner's goal may differ based on which pattern it is attempting to optimize.
PPCMachineCombinerPattern
Definition: PPCInstrInfo.h:89
@ REASSOC_XY_BCA
Definition: PPCInstrInfo.h:96
@ REASSOC_XY_BAC
Definition: PPCInstrInfo.h:97
@ REASSOC_XY_AMM_BMM
Definition: PPCInstrInfo.h:91
@ REASSOC_XMM_AMM_BMM
Definition: PPCInstrInfo.h:92
SpillOpcodeKey
Definition: PPCInstrInfo.h:67
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:73
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:75
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:78
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:68
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:79
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:76
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:81
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:84
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:77
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:70
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:71
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:74
@ SOK_WAccumulatorSpill
Definition: PPCInstrInfo.h:82
@ SOK_SPESpill
Definition: PPCInstrInfo.h:83
@ SOK_CRSpill
Definition: PPCInstrInfo.h:72
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:80
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:69
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:85
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:55
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:45
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:35
uint64_t IsCommutative
Definition: PPCInstrInfo.h:43
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:41
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:53
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:38