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PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 
16 #include "PPCRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "PPCGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 /// PPCII - This namespace holds all of the PowerPC target-specific
25 /// per-instruction flags. These must match the corresponding definitions in
26 /// PPC.td and PPCInstrFormats.td.
27 namespace PPCII {
28 enum {
29  // PPC970 Instruction Flags. These flags describe the characteristics of the
30  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
31  // raw machine instructions.
32 
33  /// PPC970_First - This instruction starts a new dispatch group, so it will
34  /// always be the first one in the group.
35  PPC970_First = 0x1,
36 
37  /// PPC970_Single - This instruction starts a new dispatch group and
38  /// terminates it, so it will be the sole instruction in the group.
40 
41  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
42  /// two dispatch pipes to be available to issue.
44 
45  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
46  /// an instruction is issued to.
49 };
51  /// These are the various PPC970 execution unit pipelines. Each instruction
52  /// is one of these.
53  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
54  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
55  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
56  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
57  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
58  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
59  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
60  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
61 };
62 
63 enum {
64  /// Shift count to bypass PPC970 flags
66 
67  /// This instruction is an X-Form memory operation.
69  /// This instruction is prefixed.
70  Prefixed = 0x1 << (NewDef_Shift+1)
71 };
72 } // end namespace PPCII
73 
74 // Instructions that have an immediate form might be convertible to that
75 // form if the correct input is a result of a load immediate. In order to
76 // know whether the transformation is special, we might need to know some
77 // of the details of the two forms.
78 struct ImmInstrInfo {
79  // Is the immediate field in the immediate form signed or unsigned?
81  // Does the immediate need to be a multiple of some value?
83  // Is R0/X0 treated specially by the original r+r instruction?
84  // If so, in which operand?
86  // Is R0/X0 treated specially by the new r+i instruction?
87  // If so, in which operand?
89  // Is the operation commutative?
91  // The operand number to check for add-immediate def.
93  // The operand number for the immediate.
95  // The opcode of the new instruction.
97  // The size of the immediate.
99  // The immediate should be truncated to N bits.
101  // Is the instruction summing the operand
103 };
104 
105 // Information required to convert an instruction to just a materialized
106 // immediate.
108  unsigned Imm : 16;
109  unsigned Is64Bit : 1;
110  unsigned SetCR : 1;
111 };
112 
113 // Index into the OpcodesForSpill array.
131  SOK_LastOpcodeSpill // This must be last on the enum.
132 };
133 
134 // Define list of load and store spill opcodes.
135 #define NoInstr PPC::INSTRUCTION_LIST_END
136 #define Pwr8LoadOpcodes \
137  { \
138  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
139  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
140  PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
141  PPC::RESTORE_QUADWORD \
142  }
143 
144 #define Pwr9LoadOpcodes \
145  { \
146  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
147  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
148  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
149  NoInstr, PPC::RESTORE_QUADWORD \
150  }
151 
152 #define Pwr10LoadOpcodes \
153  { \
154  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
155  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
156  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
157  PPC::RESTORE_UACC, NoInstr, PPC::RESTORE_QUADWORD \
158  }
159 
160 #define Pwr8StoreOpcodes \
161  { \
162  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
163  PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
164  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
165  PPC::SPILL_QUADWORD \
166  }
167 
168 #define Pwr9StoreOpcodes \
169  { \
170  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
171  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
172  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, \
173  PPC::SPILL_QUADWORD \
174  }
175 
176 #define Pwr10StoreOpcodes \
177  { \
178  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
179  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
180  PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
181  NoInstr, PPC::SPILL_QUADWORD \
182  }
183 
184 // Initialize arrays for load and store spill opcodes on supported subtargets.
185 #define StoreOpcodesForSpill \
186  { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes }
187 #define LoadOpcodesForSpill \
188  { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes }
189 
190 class PPCSubtarget;
192  PPCSubtarget &Subtarget;
193  const PPCRegisterInfo RI;
194  const unsigned StoreSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
196  const unsigned LoadSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
198 
199  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
200  int FrameIdx, const TargetRegisterClass *RC,
201  SmallVectorImpl<MachineInstr *> &NewMIs) const;
202  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
203  unsigned DestReg, int FrameIdx,
204  const TargetRegisterClass *RC,
205  SmallVectorImpl<MachineInstr *> &NewMIs) const;
206 
207  // Replace the instruction with single LI if possible. \p DefMI must be LI or
208  // LI8.
209  bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
210  unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
211  // If the inst is imm-form and its register operand is produced by a ADDI, put
212  // the imm into the inst directly and remove the ADDI if possible.
213  bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
214  unsigned OpNoForForwarding) const;
215  // If the inst is x-form and has imm-form and one of its operand is produced
216  // by a LI, put the imm into the inst directly and remove the LI if possible.
217  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
218  unsigned ConstantOpNo,
219  MachineInstr &DefMI) const;
220  // If the inst is x-form and has imm-form and one of its operand is produced
221  // by an add-immediate, try to transform it when possible.
222  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
223  unsigned ConstantOpNo, MachineInstr &DefMI,
224  bool KillDefMI) const;
225  // Try to find that, if the instruction 'MI' contains any operand that
226  // could be forwarded from some inst that feeds it. If yes, return the
227  // Def of that operand. And OpNoForForwarding is the operand index in
228  // the 'MI' for that 'Def'. If we see another use of this Def between
229  // the Def and the MI, SeenIntermediateUse becomes 'true'.
230  MachineInstr *getForwardingDefMI(MachineInstr &MI,
231  unsigned &OpNoForForwarding,
232  bool &SeenIntermediateUse) const;
233 
234  // Can the user MI have it's source at index \p OpNoForForwarding
235  // forwarded from an add-immediate that feeds it?
236  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
237  unsigned OpNoForForwarding) const;
238  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
239  const ImmInstrInfo &III,
240  MachineOperand *&ImmMO,
241  MachineOperand *&RegMO) const;
242  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
243  const MachineInstr &DefMI,
244  const ImmInstrInfo &III,
245  int64_t &Imm,
246  int64_t BaseImm = 0) const;
247  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
248  const MachineInstr &DefMI,
249  const MachineInstr &MI, bool KillDefMI,
250  bool &IsFwdFeederRegKilled) const;
251  unsigned getSpillTarget() const;
252  const unsigned *getStoreOpcodesForSpillArray() const;
253  const unsigned *getLoadOpcodesForSpillArray() const;
254  unsigned getSpillIndex(const TargetRegisterClass *RC) const;
255  int16_t getFMAOpIdxInfo(unsigned Opcode) const;
256  void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
259  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
260  bool isLoadFromConstantPool(MachineInstr *I) const;
261  Register
262  generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
263  SmallVectorImpl<MachineInstr *> &InsInstrs) const;
264  const Constant *getConstantFromConstantPool(MachineInstr *I) const;
265  virtual void anchor();
266 
267 protected:
268  /// Commutes the operands in the given instruction.
269  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
270  ///
271  /// Do not call this method for a non-commutable instruction or for
272  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
273  /// Even though the instruction is commutable, the method may still
274  /// fail to commute the operands, null pointer is returned in such cases.
275  ///
276  /// For example, we can commute rlwimi instructions, but only if the
277  /// rotate amt is zero. We also have to munge the immediates a bit.
279  unsigned OpIdx1,
280  unsigned OpIdx2) const override;
281 
282 public:
283  explicit PPCInstrInfo(PPCSubtarget &STI);
284 
285  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
286  /// such, whenever a client has an instance of instruction info, it should
287  /// always be able to get register info as well (through this method).
288  ///
289  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
290 
291  bool isXFormMemOp(unsigned Opcode) const {
292  return get(Opcode).TSFlags & PPCII::XFormMemOp;
293  }
294  bool isPrefixed(unsigned Opcode) const {
295  return get(Opcode).TSFlags & PPCII::Prefixed;
296  }
297 
298  /// Check if Opcode corresponds to a call instruction that should be marked
299  /// with the NOTOC relocation.
300  bool isNoTOCCallInstr(unsigned Opcode) const {
301  if (!get(Opcode).isCall())
302  return false;
303 
304  switch (Opcode) {
305  default:
306 #ifndef NDEBUG
307  llvm_unreachable("Unknown call opcode");
308 #endif
309  return false;
310  case PPC::BL8_NOTOC:
311  case PPC::BL8_NOTOC_TLS:
312  case PPC::BL8_NOTOC_RM:
313  return true;
314 #ifndef NDEBUG
315  case PPC::BL8:
316  case PPC::BL:
317  case PPC::BL8_TLS:
318  case PPC::BL_TLS:
319  case PPC::BLA8:
320  case PPC::BLA:
321  case PPC::BCCL:
322  case PPC::BCCLA:
323  case PPC::BCL:
324  case PPC::BCLn:
325  case PPC::BL8_NOP:
326  case PPC::BL_NOP:
327  case PPC::BL8_NOP_TLS:
328  case PPC::BLA8_NOP:
329  case PPC::BCTRL8:
330  case PPC::BCTRL:
331  case PPC::BCCCTRL8:
332  case PPC::BCCCTRL:
333  case PPC::BCCTRL8:
334  case PPC::BCCTRL:
335  case PPC::BCCTRL8n:
336  case PPC::BCCTRLn:
337  case PPC::BL8_RM:
338  case PPC::BLA8_RM:
339  case PPC::BL8_NOP_RM:
340  case PPC::BLA8_NOP_RM:
341  case PPC::BCTRL8_RM:
342  case PPC::BCTRL8_LDinto_toc:
343  case PPC::BCTRL8_LDinto_toc_RM:
344  case PPC::BL8_TLS_:
345  case PPC::TCRETURNdi8:
346  case PPC::TCRETURNai8:
347  case PPC::TCRETURNri8:
348  case PPC::TAILBCTR8:
349  case PPC::TAILB8:
350  case PPC::TAILBA8:
351  case PPC::BCLalways:
352  case PPC::BLRL:
353  case PPC::BCCLRL:
354  case PPC::BCLRL:
355  case PPC::BCLRLn:
356  case PPC::BDZL:
357  case PPC::BDNZL:
358  case PPC::BDZLA:
359  case PPC::BDNZLA:
360  case PPC::BDZLp:
361  case PPC::BDNZLp:
362  case PPC::BDZLAp:
363  case PPC::BDNZLAp:
364  case PPC::BDZLm:
365  case PPC::BDNZLm:
366  case PPC::BDZLAm:
367  case PPC::BDNZLAm:
368  case PPC::BDZLRL:
369  case PPC::BDNZLRL:
370  case PPC::BDZLRLp:
371  case PPC::BDNZLRLp:
372  case PPC::BDZLRLm:
373  case PPC::BDNZLRLm:
374  case PPC::BL_RM:
375  case PPC::BLA_RM:
376  case PPC::BL_NOP_RM:
377  case PPC::BCTRL_RM:
378  case PPC::TCRETURNdi:
379  case PPC::TCRETURNai:
380  case PPC::TCRETURNri:
381  case PPC::BCTRL_LWZinto_toc:
382  case PPC::BCTRL_LWZinto_toc_RM:
383  case PPC::TAILBCTR:
384  case PPC::TAILB:
385  case PPC::TAILBA:
386  return false;
387 #endif
388  }
389  }
390 
391  static bool isSameClassPhysRegCopy(unsigned Opcode) {
392  unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
393  PPC::VOR, PPC::XXLOR, PPC::XXLORf,
394  PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
395  PPC::EVOR, -1U};
396  for (int i = 0; CopyOpcodes[i] != -1U; i++)
397  if (Opcode == CopyOpcodes[i])
398  return true;
399  return false;
400  }
401 
404  const ScheduleDAG *DAG) const override;
407  const ScheduleDAG *DAG) const override;
408 
409  unsigned getInstrLatency(const InstrItineraryData *ItinData,
410  const MachineInstr &MI,
411  unsigned *PredCost = nullptr) const override;
412 
413  int getOperandLatency(const InstrItineraryData *ItinData,
414  const MachineInstr &DefMI, unsigned DefIdx,
415  const MachineInstr &UseMI,
416  unsigned UseIdx) const override;
418  SDNode *DefNode, unsigned DefIdx,
419  SDNode *UseNode, unsigned UseIdx) const override {
420  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
421  UseNode, UseIdx);
422  }
423 
424  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
425  const MachineInstr &DefMI,
426  unsigned DefIdx) const override {
427  // Machine LICM should hoist all instructions in low-register-pressure
428  // situations; none are sufficiently free to justify leaving in a loop
429  // body.
430  return false;
431  }
432 
433  bool useMachineCombiner() const override {
434  return true;
435  }
436 
437  /// When getMachineCombinerPatterns() finds patterns, this function generates
438  /// the instructions that could replace the original code sequence
443  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
444 
445  /// Return true when there is potentially a faster code sequence for a fma
446  /// chain ending in \p Root. All potential patterns are output in the \p
447  /// P array.
448  bool getFMAPatterns(MachineInstr &Root,
450  bool DoRegPressureReduce) const;
451 
452  /// Return true when there is potentially a faster code sequence
453  /// for an instruction chain ending in <Root>. All potential patterns are
454  /// output in the <Pattern> array.
457  bool DoRegPressureReduce) const override;
458 
459  /// On PowerPC, we leverage machine combiner pass to reduce register pressure
460  /// when the register pressure is high for one BB.
461  /// Return true if register pressure for \p MBB is high and ABI is supported
462  /// to reduce register pressure. Otherwise return false.
463  bool
465  RegisterClassInfo *RegClassInfo) const override;
466 
467  /// Fixup the placeholders we put in genAlternativeCodeSequence() for
468  /// MachineCombiner.
469  void
471  SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
472 
473  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
474 
475  /// On PowerPC, we try to reassociate FMA chain which will increase
476  /// instruction size. Set extension resource length limit to 1 for edge case.
477  /// Resource Length is calculated by scaled resource usage in getCycles().
478  /// Because of the division in getCycles(), it returns different cycles due to
479  /// legacy scaled resource usage. So new resource length may be same with
480  /// legacy or 1 bigger than legacy.
481  /// We need to execlude the 1 bigger case even the resource length is not
482  /// perserved for more FMA chain reassociations on PowerPC.
483  int getExtendResourceLenLimit() const override { return 1; }
484 
485  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
486  MachineInstr &NewMI1,
487  MachineInstr &NewMI2) const override;
488 
489  // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
490  // and clears nuw, nsw, and exact flags.
491  void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const;
492 
494  Register &SrcReg, Register &DstReg,
495  unsigned &SubIdx) const override;
496  unsigned isLoadFromStackSlot(const MachineInstr &MI,
497  int &FrameIndex) const override;
499  AAResults *AA) const override;
500  unsigned isStoreToStackSlot(const MachineInstr &MI,
501  int &FrameIndex) const override;
502 
503  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
504  unsigned &SrcOpIdx2) const override;
505 
507  MachineBasicBlock::iterator MI) const override;
508 
509 
510  // Branch analysis.
512  MachineBasicBlock *&FBB,
514  bool AllowModify) const override;
516  int *BytesRemoved = nullptr) const override;
519  const DebugLoc &DL,
520  int *BytesAdded = nullptr) const override;
521 
522  // Select analysis.
524  Register, Register, Register, int &, int &,
525  int &) const override;
527  const DebugLoc &DL, Register DstReg,
529  Register FalseReg) const override;
530 
532  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
533  bool KillSrc) const override;
534 
537  Register SrcReg, bool isKill, int FrameIndex,
538  const TargetRegisterClass *RC,
539  const TargetRegisterInfo *TRI) const override;
540 
541  // Emits a register spill without updating the register class for vector
542  // registers. This ensures that when we spill a vector register the
543  // element order in the register is the same as it was in memory.
546  unsigned SrcReg, bool isKill, int FrameIndex,
547  const TargetRegisterClass *RC,
548  const TargetRegisterInfo *TRI) const;
549 
552  Register DestReg, int FrameIndex,
553  const TargetRegisterClass *RC,
554  const TargetRegisterInfo *TRI) const override;
555 
556  // Emits a register reload without updating the register class for vector
557  // registers. This ensures that when we reload a vector register the
558  // element order in the register is the same as it was in memory.
561  unsigned DestReg, int FrameIndex,
562  const TargetRegisterClass *RC,
563  const TargetRegisterInfo *TRI) const;
564 
565  unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
566 
567  unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
568 
569  bool
571 
573  MachineRegisterInfo *MRI) const override;
574 
576  Register Reg) const;
577 
578  // If conversion by predication (only supported by some branch instructions).
579  // All of the profitability checks always return true; it is always
580  // profitable to use the predicated branches.
582  unsigned NumCycles, unsigned ExtraPredCycles,
583  BranchProbability Probability) const override {
584  return true;
585  }
586 
588  unsigned NumT, unsigned ExtraT,
589  MachineBasicBlock &FMBB,
590  unsigned NumF, unsigned ExtraF,
591  BranchProbability Probability) const override;
592 
594  BranchProbability Probability) const override {
595  return true;
596  }
597 
599  MachineBasicBlock &FMBB) const override {
600  return false;
601  }
602 
603  // Predication support.
604  bool isPredicated(const MachineInstr &MI) const override;
605 
607  const MachineBasicBlock *MBB,
608  const MachineFunction &MF) const override;
609 
611  ArrayRef<MachineOperand> Pred) const override;
612 
614  ArrayRef<MachineOperand> Pred2) const override;
615 
616  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
617  bool SkipDead) const override;
618 
619  // Comparison optimization.
620 
621  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
622  Register &SrcReg2, int64_t &Mask,
623  int64_t &Value) const override;
624 
625  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
626  Register SrcReg2, int64_t Mask, int64_t Value,
627  const MachineRegisterInfo *MRI) const override;
628 
629 
630  /// Return true if get the base operand, byte offset of an instruction and
631  /// the memory width. Width is the size of memory that is being
632  /// loaded/stored (e.g. 1, 2, 4, 8).
634  const MachineOperand *&BaseOp,
635  int64_t &Offset, unsigned &Width,
636  const TargetRegisterInfo *TRI) const;
637 
638  /// Get the base operand and byte offset of an instruction that reads/writes
639  /// memory.
641  const MachineInstr &LdSt,
642  SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
643  bool &OffsetIsScalable, unsigned &Width,
644  const TargetRegisterInfo *TRI) const override;
645 
646  /// Returns true if the two given memory operations should be scheduled
647  /// adjacent.
650  unsigned NumLoads, unsigned NumBytes) const override;
651 
652  /// Return true if two MIs access different memory addresses and false
653  /// otherwise
654  bool
656  const MachineInstr &MIb) const override;
657 
658  /// GetInstSize - Return the number of bytes of code the specified
659  /// instruction may be. This returns the maximum number of bytes.
660  ///
661  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
662 
663  MCInst getNop() const override;
664 
665  std::pair<unsigned, unsigned>
666  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
667 
670 
673 
674  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
675  bool expandVSXMemPseudo(MachineInstr &MI) const;
676 
677  // Lower pseudo instructions after register allocation.
678  bool expandPostRAPseudo(MachineInstr &MI) const override;
679 
680  static bool isVFRegister(unsigned Reg) {
681  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
682  }
683  static bool isVRRegister(unsigned Reg) {
684  return Reg >= PPC::V0 && Reg <= PPC::V31;
685  }
686  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
687  static int getRecordFormOpcode(unsigned Opcode);
688 
689  bool isTOCSaveMI(const MachineInstr &MI) const;
690 
691  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
692  const unsigned PhiDepth) const;
693 
694  /// Return true if the output of the instruction is always a sign-extended,
695  /// i.e. 0 to 31-th bits are same as 32-th bit.
696  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
697  return isSignOrZeroExtended(MI, true, depth);
698  }
699 
700  /// Return true if the output of the instruction is always zero-extended,
701  /// i.e. 0 to 31-th bits are all zeros
702  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
703  return isSignOrZeroExtended(MI, false, depth);
704  }
705 
707  MachineInstr **KilledDef = nullptr) const;
708  bool foldFrameOffset(MachineInstr &MI) const;
709  bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
710  bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
711  bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
712  bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
713  unsigned &XFormOpcode,
714  int64_t &OffsetOfImmInstr,
715  ImmInstrInfo &III) const;
716  bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
717  MachineInstr *&ADDIMI, int64_t &OffsetAddi,
718  int64_t OffsetImm) const;
719 
720  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
721  /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
722  /// register killed/dead flags semantics, this function can be called to fix
723  /// up. Before calling this function,
724  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
725  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
726  /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
727  /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
728  /// will be adjust to true definition.
729  /// 3. We can do accurate fixup for the case when all instructions between
730  /// [\p StartMI, \p EndMI] are in same basic block.
731  /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
732  /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
733  /// and for post-RA, we give an assertion as without reaching definition
734  /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
735  void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
736  unsigned RegNo) const;
737  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
738  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
739  int64_t Imm) const;
740 
741  bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
742  bool PostRA) const;
743 
744  // In PostRA phase, try to find instruction defines \p Reg before \p MI.
745  // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
747  bool &SeenIntermediateUse) const;
748 
749  /// getRegNumForOperand - some operands use different numbering schemes
750  /// for the same registers. For example, a VSX instruction may have any of
751  /// vs0-vs63 allocated whereas an Altivec instruction could only have
752  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
753  /// register number needed for the opcode/operand number combination.
754  /// The operand number argument will be useful when we need to extend this
755  /// to instructions that use both Altivec and VSX numbering (for different
756  /// operands).
757  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
758  unsigned OpNo) {
759  int16_t regClass = Desc.OpInfo[OpNo].RegClass;
760  switch (regClass) {
761  // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
762  // VSX32-VSX63 during encoding/disassembling
763  case PPC::VSSRCRegClassID:
764  case PPC::VSFRCRegClassID:
765  if (isVFRegister(Reg))
766  return PPC::VSX32 + (Reg - PPC::VF0);
767  break;
768  // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
769  // VSX32-VSX63 during encoding/disassembling
770  case PPC::VSRCRegClassID:
771  if (isVRRegister(Reg))
772  return PPC::VSX32 + (Reg - PPC::V0);
773  break;
774  // Other RegClass doesn't need mapping
775  default:
776  break;
777  }
778  return Reg;
779  }
780 
781  /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
782  bool isBDNZ(unsigned Opcode) const;
783 
784  /// Find the hardware loop instruction used to set-up the specified loop.
785  /// On PPC, we have two instructions used to set-up the hardware loop
786  /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
787  /// instructions to indicate the end of a loop.
788  MachineInstr *
789  findLoopInstr(MachineBasicBlock &PreHeader,
790  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
791 
792  /// Analyze loop L, which must be a single-basic-block loop, and if the
793  /// conditions can be understood enough produce a PipelinerLoopInfo object.
794  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
795  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
796 };
797 
798 }
799 
800 #endif
llvm::PPCII::PPC970_Unit
PPC970_Unit
Definition: PPCInstrInfo.h:50
llvm::PPCInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1128
i
i
Definition: README.txt:29
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
llvm::PPCInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:1974
llvm::PPCInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: PPCInstrInfo.cpp:2892
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::PPCInstrInfo::fixupIsDeadOrKill
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
Definition: PPCInstrInfo.cpp:3339
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::PPCInstrInfo::replaceInstrOperandWithImm
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
Definition: PPCInstrInfo.cpp:3166
PPCRegisterInfo.h
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::PPCInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:3003
llvm::PPCInstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:598
llvm::SOK_SpillToVSR
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:125
llvm::SOK_PairedVecSpill
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:126
llvm::PPCInstrInfo::isPrefixed
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:294
llvm::ImmInstrInfo::OpNoForForwarding
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:92
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::LoadImmediateInfo::SetCR
unsigned SetCR
Definition: PPCInstrInfo.h:110
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::PPCII::PPC970_VALU
@ PPC970_VALU
Definition: PPCInstrInfo.h:58
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:417
llvm::PPCInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2384
llvm::PPCInstrInfo::isSignExtended
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:696
llvm::PPCInstrInfo::isVFRegister
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:680
llvm::PPCInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: PPCInstrInfo.cpp:1688
llvm::PPCInstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Definition: PPCInstrInfo.cpp:252
llvm::PPCInstrInfo::getDefMIPostRA
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Definition: PPCInstrInfo.cpp:3220
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SOK_VRVectorSpill
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:121
llvm::PPCInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: PPCInstrInfo.cpp:2052
llvm::PPCII::NewDef_Shift
@ NewDef_Shift
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:65
llvm::PPCInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: PPCInstrInfo.cpp:2354
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::PPCInstrInfo::isADDInstrEligibleForFolding
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
Definition: PPCInstrInfo.cpp:3572
llvm::PPCII::PPC970_FPU
@ PPC970_FPU
Definition: PPCInstrInfo.h:56
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::PPCInstrInfo::getStoreOpcodeForSpill
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1921
llvm::ImmInstrInfo::ZeroIsSpecialNew
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:88
llvm::SOK_PairedG8Spill
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:130
llvm::PPCInstrInfo::getExtendResourceLenLimit
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:483
llvm::LoadImmediateInfo::Is64Bit
unsigned Is64Bit
Definition: PPCInstrInfo.h:109
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::PPCInstrInfo::isBDNZ
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
Definition: PPCInstrInfo.cpp:5367
llvm::PPCInstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
Definition: PPCInstrInfo.cpp:221
llvm::PPCInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: PPCInstrInfo.cpp:136
llvm::PPCInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: PPCInstrInfo.cpp:1576
llvm::SOK_LastOpcodeSpill
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:131
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::PPCInstrInfo::onlyFoldImmediate
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
Definition: PPCInstrInfo.cpp:2065
llvm::PPCInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
Definition: PPCInstrInfo.cpp:116
llvm::PPCInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
Definition: PPCInstrInfo.cpp:2815
llvm::ImmInstrInfo::IsSummingOperands
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:102
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::PPCInstrInfo::replaceInstrWithLI
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
Definition: PPCInstrInfo.cpp:3197
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::LoadImmediateInfo
Definition: PPCInstrInfo.h:107
llvm::SOK_Float8Spill
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:117
llvm::PPCInstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: PPCInstrInfo.cpp:1054
llvm::PPCInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:2034
llvm::PPCInstrInfo::isNoTOCCallInstr
bool isNoTOCCallInstr(unsigned Opcode) const
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
Definition: PPCInstrInfo.h:300
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCII::PPC970_VPERM
@ PPC970_VPERM
Definition: PPCInstrInfo.h:59
llvm::PPCInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: PPCInstrInfo.cpp:2873
llvm::SOK_SPESpill
@ SOK_SPESpill
Definition: PPCInstrInfo.h:129
llvm::PPCInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: PPCInstrInfo.cpp:1244
llvm::ImmInstrInfo::SignedImm
uint64_t SignedImm
Definition: PPCInstrInfo.h:80
llvm::PPCII::PPC970_First
@ PPC970_First
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:35
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::PPCII::PPC970_Shift
@ PPC970_Shift
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:47
llvm::PPCInstrInfo::isXFormMemOp
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:291
llvm::PPCInstrInfo::shouldReduceRegisterPressure
bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
Definition: PPCInstrInfo.cpp:613
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::PPCInstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: PPCInstrInfo.cpp:1264
LoadOpcodesForSpill
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:187
llvm::PPCInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2132
llvm::PPCInstrInfo::isImmInstrEligibleForFolding
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
Definition: PPCInstrInfo.cpp:3579
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SOK_UAccumulatorSpill
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:128
llvm::SOK_Int4Spill
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:115
llvm::PPCInstrInfo::updatedRC
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:5080
llvm::PPCInstrInfo::findLoopInstr
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
Definition: PPCInstrInfo.cpp:5461
llvm::LoadImmediateInfo::Imm
unsigned Imm
Definition: PPCInstrInfo.h:108
llvm::PPCInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: PPCInstrInfo.cpp:2184
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::PPCInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: PPCInstrInfo.cpp:1228
llvm::PPCInstrInfo::analyzeLoopForPipelining
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: PPCInstrInfo.cpp:5441
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::PPCInstrInfo::isADDIInstrEligibleForFolding
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
Definition: PPCInstrInfo.cpp:3555
llvm::PPCInstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: PPCInstrInfo.cpp:774
llvm::SOK_CRSpill
@ SOK_CRSpill
Definition: PPCInstrInfo.h:119
llvm::PPCInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: PPCInstrInfo.cpp:2319
llvm::PPCInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: PPCInstrInfo.cpp:2173
llvm::PPCInstrInfo::isSameClassPhysRegCopy
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:391
llvm::SOK_VectorFloat8Spill
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:123
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::PPCII::PPC970_CRU
@ PPC970_CRU
Definition: PPCInstrInfo.h:57
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::PPCInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: PPCInstrInfo.cpp:1533
uint64_t
llvm::PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2913
llvm::ImmInstrInfo
Definition: PPCInstrInfo.h:78
llvm::ImmInstrInfo::IsCommutative
uint64_t IsCommutative
Definition: PPCInstrInfo.h:90
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ImmInstrInfo::TruncateImmTo
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:100
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: PPCInstrInfo.cpp:166
llvm::SpillOpcodeKey
SpillOpcodeKey
Definition: PPCInstrInfo.h:114
llvm::PPCInstrInfo::isSignOrZeroExtended
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Definition: PPCInstrInfo.cpp:5207
llvm::SOK_Int8Spill
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:116
llvm::PPCInstrInfo::hasLowDefLatency
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:424
llvm::PPCInstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:433
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::PPCInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1069
llvm::SOK_VectorFloat4Spill
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:124
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::PPCInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: PPCInstrInfo.cpp:1273
llvm::PPCInstrInfo::getFMAPatterns
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
Definition: PPCInstrInfo.cpp:367
llvm::SOK_AccumulatorSpill
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:127
llvm::PPCInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Definition: PPCInstrInfo.cpp:2288
llvm::PPCInstrInfo::loadRegFromStackSlotNoUpd
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:2009
llvm::ImmInstrInfo::ZeroIsSpecialOrig
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:85
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::PPCInstrInfo::convertToImmediateForm
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
Definition: PPCInstrInfo.cpp:3667
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::PPCInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:2162
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::PPCII::PPC970_Mask
@ PPC970_Mask
Definition: PPCInstrInfo.h:48
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::BranchProbability
Definition: BranchProbability.h:29
llvm::PPCInstrInfo::isZeroExtended
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:702
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCInstrInfo::instrHasImmForm
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
Definition: PPCInstrInfo.cpp:3856
llvm::PPCII::Prefixed
@ Prefixed
This instruction is prefixed.
Definition: PPCInstrInfo.h:70
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCInstrInfo::isTOCSaveMI
bool isTOCSaveMI(const MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:5189
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::ImmInstrInfo::ImmMustBeMultipleOf
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:82
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
PPCGenInstrInfo
llvm::PPCInstrInfo::getRegisterInfo
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:289
llvm::PPCInstrInfo::getRegNumForOperand
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:757
llvm::PPCII::XFormMemOp
@ XFormMemOp
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:68
uint16_t
llvm::PPCInstrInfo::combineRLWINM
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
Definition: PPCInstrInfo.cpp:3719
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::PPCInstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
Definition: PPCInstrInfo.cpp:759
llvm::PPCII::PPC970_Cracked
@ PPC970_Cracked
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:43
llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
Definition: PPCInstrInfo.cpp:5499
llvm::PPCII::PPC970_FXU
@ PPC970_FXU
Definition: PPCInstrInfo.h:54
llvm::PPCISD::BCTRL_RM
@ BCTRL_RM
Definition: PPCISelLowering.h:208
llvm::PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2898
llvm::PPCInstrInfo::getLoadOpcodeForSpill
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1927
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:432
StoreOpcodesForSpill
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:185
llvm::PPCInstrInfo::getRecordFormOpcode
static int getRecordFormOpcode(unsigned Opcode)
Definition: PPCInstrInfo.cpp:5086
llvm::PPCII::PPC970_Single
@ PPC970_Single
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:39
AA
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::PPCInstrInfo::isValidToBeChangedReg
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
Definition: PPCInstrInfo.cpp:3622
llvm::SOK_Float4Spill
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:118
llvm::PPCInstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
Definition: PPCInstrInfo.cpp:5476
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::PPCInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: PPCInstrInfo.cpp:2764
llvm::PPCInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: PPCInstrInfo.cpp:1144
llvm::PPCInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: PPCInstrInfo.cpp:1480
llvm::SOK_VSXVectorSpill
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:122
llvm::SmallVectorImpl< MachineInstr * >
llvm::PPCISD::BCTRL
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
Definition: PPCISelLowering.h:196
llvm::PPCInstrInfo::expandVSXMemPseudo
bool expandVSXMemPseudo(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:2937
llvm::PPCII::PPC970_LSU
@ PPC970_LSU
Definition: PPCInstrInfo.h:55
llvm::PPCII::PPC970_BRU
@ PPC970_BRU
Definition: PPCInstrInfo.h:60
llvm::PPCInstrInfo::CreateTargetHazardRecognizer
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
Definition: PPCInstrInfo.cpp:99
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SOK_CRBitSpill
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:120
llvm::PPCInstrInfo::foldFrameOffset
bool foldFrameOffset(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:3458
llvm::PPCInstrInfo::storeRegToStackSlotNoUpd
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:1954
llvm::PPCInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:593
llvm::PPCInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:581
llvm::PPCInstrInfo::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)
Definition: PPCInstrInfo.cpp:90
llvm::PPCInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: PPCInstrInfo.cpp:1448
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::PPCInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: PPCInstrInfo.cpp:1089
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ImmInstrInfo::ImmOpcode
uint64_t ImmOpcode
Definition: PPCInstrInfo.h:96
llvm::ImmInstrInfo::ImmOpNo
uint64_t ImmOpNo
Definition: PPCInstrInfo.h:94
llvm::PPCInstrInfo::finalizeInsInstrs
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
Definition: PPCInstrInfo.cpp:543
llvm::ImmInstrInfo::ImmWidth
uint64_t ImmWidth
Definition: PPCInstrInfo.h:98
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::PPCII::PPC970_Pseudo
@ PPC970_Pseudo
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:53
llvm::PPCInstrInfo::isVRRegister
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:683
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20