LLVM 19.0.0git
PPCInstrInfo.h
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1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/ADT/SmallSet.h"
21
22#define GET_INSTRINFO_HEADER
23#include "PPCGenInstrInfo.inc"
24
25namespace llvm {
26
27// Instructions that have an immediate form might be convertible to that
28// form if the correct input is a result of a load immediate. In order to
29// know whether the transformation is special, we might need to know some
30// of the details of the two forms.
32 // Is the immediate field in the immediate form signed or unsigned?
34 // Does the immediate need to be a multiple of some value?
36 // Is R0/X0 treated specially by the original r+r instruction?
37 // If so, in which operand?
39 // Is R0/X0 treated specially by the new r+i instruction?
40 // If so, in which operand?
42 // Is the operation commutative?
44 // The operand number to check for add-immediate def.
46 // The operand number for the immediate.
48 // The opcode of the new instruction.
50 // The size of the immediate.
52 // The immediate should be truncated to N bits.
54 // Is the instruction summing the operand
56};
57
58// Information required to convert an instruction to just a materialized
59// immediate.
61 unsigned Imm : 16;
62 unsigned Is64Bit : 1;
63 unsigned SetCR : 1;
64};
65
66// Index into the OpcodesForSpill array.
85 SOK_LastOpcodeSpill // This must be last on the enum.
86};
87
88// Define list of load and store spill opcodes.
89#define NoInstr PPC::INSTRUCTION_LIST_END
90#define Pwr8LoadOpcodes \
91 { \
92 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
93 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
94 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
95 PPC::RESTORE_QUADWORD \
96 }
97
98#define Pwr9LoadOpcodes \
99 { \
100 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
101 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
102 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
103 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
104 }
105
106#define Pwr10LoadOpcodes \
107 { \
108 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
109 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
110 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
111 PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
112 }
113
114#define FutureLoadOpcodes \
115 { \
116 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
117 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
118 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
119 PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD \
120 }
121
122#define Pwr8StoreOpcodes \
123 { \
124 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
125 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
126 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
127 PPC::SPILL_QUADWORD \
128 }
129
130#define Pwr9StoreOpcodes \
131 { \
132 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
133 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
134 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
135 PPC::SPILL_QUADWORD \
136 }
137
138#define Pwr10StoreOpcodes \
139 { \
140 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
141 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
142 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
143 NoInstr, NoInstr, PPC::SPILL_QUADWORD \
144 }
145
146#define FutureStoreOpcodes \
147 { \
148 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
149 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
150 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
151 PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD \
152 }
153
154// Initialize arrays for load and store spill opcodes on supported subtargets.
155#define StoreOpcodesForSpill \
156 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
157#define LoadOpcodesForSpill \
158 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
159
160class PPCSubtarget;
162 PPCSubtarget &Subtarget;
163 const PPCRegisterInfo RI;
164 const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
166 const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
168
169 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
170 int FrameIdx, const TargetRegisterClass *RC,
171 SmallVectorImpl<MachineInstr *> &NewMIs) const;
172 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
173 unsigned DestReg, int FrameIdx,
174 const TargetRegisterClass *RC,
175 SmallVectorImpl<MachineInstr *> &NewMIs) const;
176
177 // Replace the instruction with single LI if possible. \p DefMI must be LI or
178 // LI8.
179 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
180 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
181 // If the inst is imm-form and its register operand is produced by a ADDI, put
182 // the imm into the inst directly and remove the ADDI if possible.
183 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
184 unsigned OpNoForForwarding) const;
185 // If the inst is x-form and has imm-form and one of its operand is produced
186 // by a LI, put the imm into the inst directly and remove the LI if possible.
187 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
188 unsigned ConstantOpNo,
189 MachineInstr &DefMI) const;
190 // If the inst is x-form and has imm-form and one of its operand is produced
191 // by an add-immediate, try to transform it when possible.
192 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
193 unsigned ConstantOpNo, MachineInstr &DefMI,
194 bool KillDefMI) const;
195 // Try to find that, if the instruction 'MI' contains any operand that
196 // could be forwarded from some inst that feeds it. If yes, return the
197 // Def of that operand. And OpNoForForwarding is the operand index in
198 // the 'MI' for that 'Def'. If we see another use of this Def between
199 // the Def and the MI, SeenIntermediateUse becomes 'true'.
200 MachineInstr *getForwardingDefMI(MachineInstr &MI,
201 unsigned &OpNoForForwarding,
202 bool &SeenIntermediateUse) const;
203
204 // Can the user MI have it's source at index \p OpNoForForwarding
205 // forwarded from an add-immediate that feeds it?
206 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
207 unsigned OpNoForForwarding) const;
208 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
209 const ImmInstrInfo &III,
210 MachineOperand *&ImmMO,
211 MachineOperand *&RegMO) const;
212 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
213 const MachineInstr &DefMI,
214 const ImmInstrInfo &III,
215 int64_t &Imm,
216 int64_t BaseImm = 0) const;
217 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
218 const MachineInstr &DefMI,
219 const MachineInstr &MI, bool KillDefMI,
220 bool &IsFwdFeederRegKilled,
221 bool &SeenIntermediateUse) const;
222 unsigned getSpillTarget() const;
223 ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
224 ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
225 unsigned getSpillIndex(const TargetRegisterClass *RC) const;
226 int16_t getFMAOpIdxInfo(unsigned Opcode) const;
227 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
230 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
232 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
233 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
234 virtual void anchor();
235
236protected:
237 /// Commutes the operands in the given instruction.
238 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
239 ///
240 /// Do not call this method for a non-commutable instruction or for
241 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
242 /// Even though the instruction is commutable, the method may still
243 /// fail to commute the operands, null pointer is returned in such cases.
244 ///
245 /// For example, we can commute rlwimi instructions, but only if the
246 /// rotate amt is zero. We also have to munge the immediates a bit.
248 unsigned OpIdx1,
249 unsigned OpIdx2) const override;
250
251public:
252 explicit PPCInstrInfo(PPCSubtarget &STI);
253
256
257 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
258 /// such, whenever a client has an instance of instruction info, it should
259 /// always be able to get register info as well (through this method).
260 ///
261 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
262
263 bool isXFormMemOp(unsigned Opcode) const {
264 return get(Opcode).TSFlags & PPCII::XFormMemOp;
265 }
266 bool isPrefixed(unsigned Opcode) const {
267 return get(Opcode).TSFlags & PPCII::Prefixed;
268 }
269 bool isSExt32To64(unsigned Opcode) const {
270 return get(Opcode).TSFlags & PPCII::SExt32To64;
271 }
272 bool isZExt32To64(unsigned Opcode) const {
273 return get(Opcode).TSFlags & PPCII::ZExt32To64;
274 }
275
276 static bool isSameClassPhysRegCopy(unsigned Opcode) {
277 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
278 PPC::VOR, PPC::XXLOR, PPC::XXLORf,
279 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
280 PPC::EVOR, -1U};
281 for (int i = 0; CopyOpcodes[i] != -1U; i++)
282 if (Opcode == CopyOpcodes[i])
283 return true;
284 return false;
285 }
286
287 static bool hasPCRelFlag(unsigned TF) {
293 }
294
295 static bool hasGOTFlag(unsigned TF) {
300 }
301
302 static bool hasTLSFlag(unsigned TF) {
303 return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG ||
309 TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS ||
311 }
312
315 const ScheduleDAG *DAG) const override;
318 const ScheduleDAG *DAG) const override;
319
320 unsigned getInstrLatency(const InstrItineraryData *ItinData,
321 const MachineInstr &MI,
322 unsigned *PredCost = nullptr) const override;
323
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
325 const MachineInstr &DefMI,
326 unsigned DefIdx,
327 const MachineInstr &UseMI,
328 unsigned UseIdx) const override;
329 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
330 SDNode *DefNode, unsigned DefIdx,
331 SDNode *UseNode,
332 unsigned UseIdx) const override {
333 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
334 UseNode, UseIdx);
335 }
336
337 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
338 const MachineInstr &DefMI,
339 unsigned DefIdx) const override {
340 // Machine LICM should hoist all instructions in low-register-pressure
341 // situations; none are sufficiently free to justify leaving in a loop
342 // body.
343 return false;
344 }
345
346 bool useMachineCombiner() const override {
347 return true;
348 }
349
350 /// When getMachineCombinerPatterns() finds patterns, this function generates
351 /// the instructions that could replace the original code sequence
356 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
357
358 /// Return true when there is potentially a faster code sequence for a fma
359 /// chain ending in \p Root. All potential patterns are output in the \p
360 /// P array.
361 bool getFMAPatterns(MachineInstr &Root,
363 bool DoRegPressureReduce) const;
364
365 /// Return true when there is potentially a faster code sequence
366 /// for an instruction chain ending in <Root>. All potential patterns are
367 /// output in the <Pattern> array.
370 bool DoRegPressureReduce) const override;
371
372 /// On PowerPC, we leverage machine combiner pass to reduce register pressure
373 /// when the register pressure is high for one BB.
374 /// Return true if register pressure for \p MBB is high and ABI is supported
375 /// to reduce register pressure. Otherwise return false.
377 const MachineBasicBlock *MBB,
378 const RegisterClassInfo *RegClassInfo) const override;
379
380 /// Fixup the placeholders we put in genAlternativeCodeSequence() for
381 /// MachineCombiner.
382 void
384 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
385
387 bool Invert) const override;
388
389 /// On PowerPC, we try to reassociate FMA chain which will increase
390 /// instruction size. Set extension resource length limit to 1 for edge case.
391 /// Resource Length is calculated by scaled resource usage in getCycles().
392 /// Because of the division in getCycles(), it returns different cycles due to
393 /// legacy scaled resource usage. So new resource length may be same with
394 /// legacy or 1 bigger than legacy.
395 /// We need to execlude the 1 bigger case even the resource length is not
396 /// perserved for more FMA chain reassociations on PowerPC.
397 int getExtendResourceLenLimit() const override { return 1; }
398
399 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
400 // and clears nuw, nsw, and exact flags.
402 void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
403
405 Register &SrcReg, Register &DstReg,
406 unsigned &SubIdx) const override;
408 int &FrameIndex) const override;
409 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
411 int &FrameIndex) const override;
412
413 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
414 unsigned &SrcOpIdx2) const override;
415
417 MachineBasicBlock::iterator MI) const override;
418
419
420 // Branch analysis.
422 MachineBasicBlock *&FBB,
424 bool AllowModify) const override;
426 int *BytesRemoved = nullptr) const override;
429 const DebugLoc &DL,
430 int *BytesAdded = nullptr) const override;
431
432 // Select analysis.
434 Register, Register, Register, int &, int &,
435 int &) const override;
437 const DebugLoc &DL, Register DstReg,
439 Register FalseReg) const override;
440
442 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
443 bool KillSrc) const override;
444
447 bool isKill, int FrameIndex,
448 const TargetRegisterClass *RC,
449 const TargetRegisterInfo *TRI,
450 Register VReg) const override;
451
452 // Emits a register spill without updating the register class for vector
453 // registers. This ensures that when we spill a vector register the
454 // element order in the register is the same as it was in memory.
457 unsigned SrcReg, bool isKill, int FrameIndex,
458 const TargetRegisterClass *RC,
459 const TargetRegisterInfo *TRI) const;
460
463 int FrameIndex, const TargetRegisterClass *RC,
464 const TargetRegisterInfo *TRI,
465 Register VReg) const override;
466
467 // Emits a register reload without updating the register class for vector
468 // registers. This ensures that when we reload a vector register the
469 // element order in the register is the same as it was in memory.
472 unsigned DestReg, int FrameIndex,
473 const TargetRegisterClass *RC,
474 const TargetRegisterInfo *TRI) const;
475
476 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
477
478 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
479
480 bool
482
484 MachineRegisterInfo *MRI) const override;
485
487 Register Reg) const;
488
489 // If conversion by predication (only supported by some branch instructions).
490 // All of the profitability checks always return true; it is always
491 // profitable to use the predicated branches.
493 unsigned NumCycles, unsigned ExtraPredCycles,
494 BranchProbability Probability) const override {
495 return true;
496 }
497
499 unsigned NumT, unsigned ExtraT,
500 MachineBasicBlock &FMBB,
501 unsigned NumF, unsigned ExtraF,
502 BranchProbability Probability) const override;
503
505 BranchProbability Probability) const override {
506 return true;
507 }
508
510 MachineBasicBlock &FMBB) const override {
511 return false;
512 }
513
514 // Predication support.
515 bool isPredicated(const MachineInstr &MI) const override;
516
518 const MachineBasicBlock *MBB,
519 const MachineFunction &MF) const override;
520
522 ArrayRef<MachineOperand> Pred) const override;
523
525 ArrayRef<MachineOperand> Pred2) const override;
526
527 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
528 bool SkipDead) const override;
529
530 // Comparison optimization.
531
532 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
533 Register &SrcReg2, int64_t &Mask,
534 int64_t &Value) const override;
535
536 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
537 Register SrcReg2, int64_t Mask, int64_t Value,
538 const MachineRegisterInfo *MRI) const override;
539
540
541 /// Return true if get the base operand, byte offset of an instruction and
542 /// the memory width. Width is the size of memory that is being
543 /// loaded/stored (e.g. 1, 2, 4, 8).
545 const MachineOperand *&BaseOp,
546 int64_t &Offset, unsigned &Width,
547 const TargetRegisterInfo *TRI) const;
548
549 bool optimizeCmpPostRA(MachineInstr &MI) const;
550
551 /// Get the base operand and byte offset of an instruction that reads/writes
552 /// memory.
554 const MachineInstr &LdSt,
556 bool &OffsetIsScalable, unsigned &Width,
557 const TargetRegisterInfo *TRI) const override;
558
559 /// Returns true if the two given memory operations should be scheduled
560 /// adjacent.
562 int64_t Offset1, bool OffsetIsScalable1,
564 int64_t Offset2, bool OffsetIsScalable2,
565 unsigned ClusterSize,
566 unsigned NumBytes) const override;
567
568 /// Return true if two MIs access different memory addresses and false
569 /// otherwise
570 bool
572 const MachineInstr &MIb) const override;
573
574 /// GetInstSize - Return the number of bytes of code the specified
575 /// instruction may be. This returns the maximum number of bytes.
576 ///
577 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
578
579 MCInst getNop() const override;
580
581 std::pair<unsigned, unsigned>
582 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
583
586
587 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
589
590 // Lower pseudo instructions after register allocation.
591 bool expandPostRAPseudo(MachineInstr &MI) const override;
592
593 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
594 static int getRecordFormOpcode(unsigned Opcode);
595
596 bool isTOCSaveMI(const MachineInstr &MI) const;
597
598 std::pair<bool, bool>
599 isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
600 const MachineRegisterInfo *MRI) const;
601
602 // Return true if the register is sign-extended from 32 to 64 bits.
603 bool isSignExtended(const unsigned Reg,
604 const MachineRegisterInfo *MRI) const {
605 return isSignOrZeroExtended(Reg, 0, MRI).first;
606 }
607
608 // Return true if the register is zero-extended from 32 to 64 bits.
609 bool isZeroExtended(const unsigned Reg,
610 const MachineRegisterInfo *MRI) const {
611 return isSignOrZeroExtended(Reg, 0, MRI).second;
612 }
613
615 SmallSet<Register, 4> &RegsToUpdate,
616 MachineInstr **KilledDef = nullptr) const;
617 bool foldFrameOffset(MachineInstr &MI) const;
618 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
619 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
621 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
622 unsigned &XFormOpcode,
623 int64_t &OffsetOfImmInstr,
624 ImmInstrInfo &III) const;
625 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
626 MachineInstr *&ADDIMI, int64_t &OffsetAddi,
627 int64_t OffsetImm) const;
628
629 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
630 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
631 int64_t Imm) const;
632
633 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
634 bool PostRA) const;
635
636 // In PostRA phase, try to find instruction defines \p Reg before \p MI.
637 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
639 bool &SeenIntermediateUse) const;
640
641 // Materialize immediate after RA.
644 const DebugLoc &DL, Register Reg,
645 int64_t Imm) const;
646
647 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
648 bool isBDNZ(unsigned Opcode) const;
649
650 /// Find the hardware loop instruction used to set-up the specified loop.
651 /// On PPC, we have two instructions used to set-up the hardware loop
652 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
653 /// instructions to indicate the end of a loop.
657
658 /// Analyze loop L, which must be a single-basic-block loop, and if the
659 /// conditions can be understood enough produce a PipelinerLoopInfo object.
660 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
661 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
662};
663
664}
665
666#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:157
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:155
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file defines the SmallSet class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This is an important base class in LLVM.
Definition: Constant.h:41
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isPredicated(const MachineInstr &MI) const override
bool expandVSXMemPseudo(MachineInstr &MI) const
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:397
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:266
MCInst getNop() const override
Return the noop instruction to use for a noop.
static int getRecordFormOpcode(unsigned Opcode)
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:263
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:261
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
bool isTOCSaveMI(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool isSExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:269
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:329
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:609
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:492
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
bool isZExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:272
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:276
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:346
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bool foldFrameOffset(MachineInstr &MI) const
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool isLoadFromConstantPool(MachineInstr *I) const
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:509
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool convertToImmediateForm(MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:337
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:504
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
static bool hasTLSFlag(unsigned TF)
Definition: PPCInstrInfo.h:302
bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:603
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
static bool hasPCRelFlag(unsigned TF)
Definition: PPCInstrInfo.h:287
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool optimizeCmpPostRA(MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const Constant * getConstantFromConstantPool(MachineInstr *I) const
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
static bool hasGOTFlag(unsigned TF)
Definition: PPCInstrInfo.h:295
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ ZExt32To64
This instruction produced a zero extended result.
@ SExt32To64
This instruction produced a sign extended result.
@ Prefixed
This instruction is prefixed.
@ XFormMemOp
This instruction is an X-Form memory operation.
@ MO_TLSLD_LO
Definition: PPC.h:178
@ MO_TPREL_PCREL_FLAG
MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TPREL_FLAG.
Definition: PPC.h:191
@ MO_GOT_TPREL_PCREL_FLAG
MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:166
@ MO_GOT_PCREL_FLAG
MO_GOT_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG.
Definition: PPC.h:197
@ MO_TLSGDM_FLAG
MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative to the region handle of TLS Gene...
Definition: PPC.h:148
@ MO_PCREL_FLAG
MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to the current instruction addre...
Definition: PPC.h:121
@ MO_TLSLD_FLAG
MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to TLS Local Dynamic model.
Definition: PPC.h:144
@ MO_TLS_PCREL_FLAG
MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TLS.
Definition: PPC.h:194
@ MO_GOT_FLAG
MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.
Definition: PPC.h:126
@ MO_TPREL_HA
Definition: PPC.h:173
@ MO_DTPREL_LO
These values identify relocations on immediates folded into memory operations.
Definition: PPC.h:177
@ MO_TLS
Symbol for VK_PPC_TLS fixup attached to an ADD instruction.
Definition: PPC.h:182
@ MO_TPREL_FLAG
MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to the thread pointer and the sy...
Definition: PPC.h:140
@ MO_TPREL_LO
Definition: PPC.h:172
@ MO_GOT_TLSLD_PCREL_FLAG
MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:160
@ MO_TLSGD_FLAG
MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to TLS General Dynamic model for ...
Definition: PPC.h:135
@ MO_GOT_TLSGD_PCREL_FLAG
MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:154
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
SpillOpcodeKey
Definition: PPCInstrInfo.h:67
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:73
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:75
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:78
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:68
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:79
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:76
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:81
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:84
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:77
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:70
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:71
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:74
@ SOK_WAccumulatorSpill
Definition: PPCInstrInfo.h:82
@ SOK_SPESpill
Definition: PPCInstrInfo.h:83
@ SOK_CRSpill
Definition: PPCInstrInfo.h:72
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:80
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:69
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:85
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:55
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:45
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:35
uint64_t IsCommutative
Definition: PPCInstrInfo.h:43
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:41
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:53
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:38