LLVM 18.0.0git
PPCInstrInfo.h
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1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15
17#include "PPCRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "PPCGenInstrInfo.inc"
22
23namespace llvm {
24
25// Instructions that have an immediate form might be convertible to that
26// form if the correct input is a result of a load immediate. In order to
27// know whether the transformation is special, we might need to know some
28// of the details of the two forms.
30 // Is the immediate field in the immediate form signed or unsigned?
32 // Does the immediate need to be a multiple of some value?
34 // Is R0/X0 treated specially by the original r+r instruction?
35 // If so, in which operand?
37 // Is R0/X0 treated specially by the new r+i instruction?
38 // If so, in which operand?
40 // Is the operation commutative?
42 // The operand number to check for add-immediate def.
44 // The operand number for the immediate.
46 // The opcode of the new instruction.
48 // The size of the immediate.
50 // The immediate should be truncated to N bits.
52 // Is the instruction summing the operand
54};
55
56// Information required to convert an instruction to just a materialized
57// immediate.
59 unsigned Imm : 16;
60 unsigned Is64Bit : 1;
61 unsigned SetCR : 1;
62};
63
64// Index into the OpcodesForSpill array.
83 SOK_LastOpcodeSpill // This must be last on the enum.
84};
85
86// Define list of load and store spill opcodes.
87#define NoInstr PPC::INSTRUCTION_LIST_END
88#define Pwr8LoadOpcodes \
89 { \
90 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
91 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
92 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
93 PPC::RESTORE_QUADWORD \
94 }
95
96#define Pwr9LoadOpcodes \
97 { \
98 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
99 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
100 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
101 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
102 }
103
104#define Pwr10LoadOpcodes \
105 { \
106 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
107 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
108 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
109 PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
110 }
111
112#define FutureLoadOpcodes \
113 { \
114 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
115 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
116 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
117 PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD \
118 }
119
120#define Pwr8StoreOpcodes \
121 { \
122 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
123 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
124 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
125 PPC::SPILL_QUADWORD \
126 }
127
128#define Pwr9StoreOpcodes \
129 { \
130 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
131 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
132 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
133 PPC::SPILL_QUADWORD \
134 }
135
136#define Pwr10StoreOpcodes \
137 { \
138 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
139 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
140 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
141 NoInstr, NoInstr, PPC::SPILL_QUADWORD \
142 }
143
144#define FutureStoreOpcodes \
145 { \
146 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
147 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
148 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
149 PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD \
150 }
151
152// Initialize arrays for load and store spill opcodes on supported subtargets.
153#define StoreOpcodesForSpill \
154 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
155#define LoadOpcodesForSpill \
156 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
157
158class PPCSubtarget;
160 PPCSubtarget &Subtarget;
161 const PPCRegisterInfo RI;
162 const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
164 const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
166
167 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
168 int FrameIdx, const TargetRegisterClass *RC,
169 SmallVectorImpl<MachineInstr *> &NewMIs) const;
170 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
171 unsigned DestReg, int FrameIdx,
172 const TargetRegisterClass *RC,
173 SmallVectorImpl<MachineInstr *> &NewMIs) const;
174
175 // Replace the instruction with single LI if possible. \p DefMI must be LI or
176 // LI8.
177 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
178 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
179 // If the inst is imm-form and its register operand is produced by a ADDI, put
180 // the imm into the inst directly and remove the ADDI if possible.
181 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
182 unsigned OpNoForForwarding) const;
183 // If the inst is x-form and has imm-form and one of its operand is produced
184 // by a LI, put the imm into the inst directly and remove the LI if possible.
185 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
186 unsigned ConstantOpNo,
187 MachineInstr &DefMI) const;
188 // If the inst is x-form and has imm-form and one of its operand is produced
189 // by an add-immediate, try to transform it when possible.
190 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
191 unsigned ConstantOpNo, MachineInstr &DefMI,
192 bool KillDefMI) const;
193 // Try to find that, if the instruction 'MI' contains any operand that
194 // could be forwarded from some inst that feeds it. If yes, return the
195 // Def of that operand. And OpNoForForwarding is the operand index in
196 // the 'MI' for that 'Def'. If we see another use of this Def between
197 // the Def and the MI, SeenIntermediateUse becomes 'true'.
198 MachineInstr *getForwardingDefMI(MachineInstr &MI,
199 unsigned &OpNoForForwarding,
200 bool &SeenIntermediateUse) const;
201
202 // Can the user MI have it's source at index \p OpNoForForwarding
203 // forwarded from an add-immediate that feeds it?
204 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
205 unsigned OpNoForForwarding) const;
206 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
207 const ImmInstrInfo &III,
208 MachineOperand *&ImmMO,
209 MachineOperand *&RegMO) const;
210 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
211 const MachineInstr &DefMI,
212 const ImmInstrInfo &III,
213 int64_t &Imm,
214 int64_t BaseImm = 0) const;
215 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
216 const MachineInstr &DefMI,
217 const MachineInstr &MI, bool KillDefMI,
218 bool &IsFwdFeederRegKilled,
219 bool &SeenIntermediateUse) const;
220 unsigned getSpillTarget() const;
221 ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
222 ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
223 unsigned getSpillIndex(const TargetRegisterClass *RC) const;
224 int16_t getFMAOpIdxInfo(unsigned Opcode) const;
225 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
228 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
230 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
231 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
232 virtual void anchor();
233
234protected:
235 /// Commutes the operands in the given instruction.
236 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
237 ///
238 /// Do not call this method for a non-commutable instruction or for
239 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
240 /// Even though the instruction is commutable, the method may still
241 /// fail to commute the operands, null pointer is returned in such cases.
242 ///
243 /// For example, we can commute rlwimi instructions, but only if the
244 /// rotate amt is zero. We also have to munge the immediates a bit.
246 unsigned OpIdx1,
247 unsigned OpIdx2) const override;
248
249public:
250 explicit PPCInstrInfo(PPCSubtarget &STI);
251
254
255 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
256 /// such, whenever a client has an instance of instruction info, it should
257 /// always be able to get register info as well (through this method).
258 ///
259 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
260
261 bool isXFormMemOp(unsigned Opcode) const {
262 return get(Opcode).TSFlags & PPCII::XFormMemOp;
263 }
264 bool isPrefixed(unsigned Opcode) const {
265 return get(Opcode).TSFlags & PPCII::Prefixed;
266 }
267 bool isSExt32To64(unsigned Opcode) const {
268 return get(Opcode).TSFlags & PPCII::SExt32To64;
269 }
270 bool isZExt32To64(unsigned Opcode) const {
271 return get(Opcode).TSFlags & PPCII::ZExt32To64;
272 }
273
274 static bool isSameClassPhysRegCopy(unsigned Opcode) {
275 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
276 PPC::VOR, PPC::XXLOR, PPC::XXLORf,
277 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
278 PPC::EVOR, -1U};
279 for (int i = 0; CopyOpcodes[i] != -1U; i++)
280 if (Opcode == CopyOpcodes[i])
281 return true;
282 return false;
283 }
284
287 const ScheduleDAG *DAG) const override;
290 const ScheduleDAG *DAG) const override;
291
292 unsigned getInstrLatency(const InstrItineraryData *ItinData,
293 const MachineInstr &MI,
294 unsigned *PredCost = nullptr) const override;
295
296 int getOperandLatency(const InstrItineraryData *ItinData,
297 const MachineInstr &DefMI, unsigned DefIdx,
298 const MachineInstr &UseMI,
299 unsigned UseIdx) const override;
301 SDNode *DefNode, unsigned DefIdx,
302 SDNode *UseNode, unsigned UseIdx) const override {
303 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
304 UseNode, UseIdx);
305 }
306
307 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
308 const MachineInstr &DefMI,
309 unsigned DefIdx) const override {
310 // Machine LICM should hoist all instructions in low-register-pressure
311 // situations; none are sufficiently free to justify leaving in a loop
312 // body.
313 return false;
314 }
315
316 bool useMachineCombiner() const override {
317 return true;
318 }
319
320 /// When getMachineCombinerPatterns() finds patterns, this function generates
321 /// the instructions that could replace the original code sequence
326 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
327
328 /// Return true when there is potentially a faster code sequence for a fma
329 /// chain ending in \p Root. All potential patterns are output in the \p
330 /// P array.
331 bool getFMAPatterns(MachineInstr &Root,
333 bool DoRegPressureReduce) const;
334
335 /// Return true when there is potentially a faster code sequence
336 /// for an instruction chain ending in <Root>. All potential patterns are
337 /// output in the <Pattern> array.
340 bool DoRegPressureReduce) const override;
341
342 /// On PowerPC, we leverage machine combiner pass to reduce register pressure
343 /// when the register pressure is high for one BB.
344 /// Return true if register pressure for \p MBB is high and ABI is supported
345 /// to reduce register pressure. Otherwise return false.
347 const MachineBasicBlock *MBB,
348 const RegisterClassInfo *RegClassInfo) const override;
349
350 /// Fixup the placeholders we put in genAlternativeCodeSequence() for
351 /// MachineCombiner.
352 void
354 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
355
357 bool Invert) const override;
358
359 /// On PowerPC, we try to reassociate FMA chain which will increase
360 /// instruction size. Set extension resource length limit to 1 for edge case.
361 /// Resource Length is calculated by scaled resource usage in getCycles().
362 /// Because of the division in getCycles(), it returns different cycles due to
363 /// legacy scaled resource usage. So new resource length may be same with
364 /// legacy or 1 bigger than legacy.
365 /// We need to execlude the 1 bigger case even the resource length is not
366 /// perserved for more FMA chain reassociations on PowerPC.
367 int getExtendResourceLenLimit() const override { return 1; }
368
369 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
370 MachineInstr &NewMI1,
371 MachineInstr &NewMI2) const override;
372
373 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
374 // and clears nuw, nsw, and exact flags.
375 void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
376
378 Register &SrcReg, Register &DstReg,
379 unsigned &SubIdx) const override;
380 unsigned isLoadFromStackSlot(const MachineInstr &MI,
381 int &FrameIndex) const override;
382 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
383 unsigned isStoreToStackSlot(const MachineInstr &MI,
384 int &FrameIndex) const override;
385
386 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
387 unsigned &SrcOpIdx2) const override;
388
390 MachineBasicBlock::iterator MI) const override;
391
392
393 // Branch analysis.
395 MachineBasicBlock *&FBB,
397 bool AllowModify) const override;
399 int *BytesRemoved = nullptr) const override;
402 const DebugLoc &DL,
403 int *BytesAdded = nullptr) const override;
404
405 // Select analysis.
407 Register, Register, Register, int &, int &,
408 int &) const override;
410 const DebugLoc &DL, Register DstReg,
412 Register FalseReg) const override;
413
415 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
416 bool KillSrc) const override;
417
420 bool isKill, int FrameIndex,
421 const TargetRegisterClass *RC,
422 const TargetRegisterInfo *TRI,
423 Register VReg) const override;
424
425 // Emits a register spill without updating the register class for vector
426 // registers. This ensures that when we spill a vector register the
427 // element order in the register is the same as it was in memory.
430 unsigned SrcReg, bool isKill, int FrameIndex,
431 const TargetRegisterClass *RC,
432 const TargetRegisterInfo *TRI) const;
433
436 int FrameIndex, const TargetRegisterClass *RC,
437 const TargetRegisterInfo *TRI,
438 Register VReg) const override;
439
440 // Emits a register reload without updating the register class for vector
441 // registers. This ensures that when we reload a vector register the
442 // element order in the register is the same as it was in memory.
445 unsigned DestReg, int FrameIndex,
446 const TargetRegisterClass *RC,
447 const TargetRegisterInfo *TRI) const;
448
449 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
450
451 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
452
453 bool
455
457 MachineRegisterInfo *MRI) const override;
458
460 Register Reg) const;
461
462 // If conversion by predication (only supported by some branch instructions).
463 // All of the profitability checks always return true; it is always
464 // profitable to use the predicated branches.
466 unsigned NumCycles, unsigned ExtraPredCycles,
467 BranchProbability Probability) const override {
468 return true;
469 }
470
472 unsigned NumT, unsigned ExtraT,
473 MachineBasicBlock &FMBB,
474 unsigned NumF, unsigned ExtraF,
475 BranchProbability Probability) const override;
476
478 BranchProbability Probability) const override {
479 return true;
480 }
481
483 MachineBasicBlock &FMBB) const override {
484 return false;
485 }
486
487 // Predication support.
488 bool isPredicated(const MachineInstr &MI) const override;
489
491 const MachineBasicBlock *MBB,
492 const MachineFunction &MF) const override;
493
495 ArrayRef<MachineOperand> Pred) const override;
496
498 ArrayRef<MachineOperand> Pred2) const override;
499
500 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
501 bool SkipDead) const override;
502
503 // Comparison optimization.
504
505 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
506 Register &SrcReg2, int64_t &Mask,
507 int64_t &Value) const override;
508
509 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
510 Register SrcReg2, int64_t Mask, int64_t Value,
511 const MachineRegisterInfo *MRI) const override;
512
513
514 /// Return true if get the base operand, byte offset of an instruction and
515 /// the memory width. Width is the size of memory that is being
516 /// loaded/stored (e.g. 1, 2, 4, 8).
518 const MachineOperand *&BaseOp,
519 int64_t &Offset, unsigned &Width,
520 const TargetRegisterInfo *TRI) const;
521
522 bool optimizeCmpPostRA(MachineInstr &MI) const;
523
524 /// Get the base operand and byte offset of an instruction that reads/writes
525 /// memory.
527 const MachineInstr &LdSt,
529 bool &OffsetIsScalable, unsigned &Width,
530 const TargetRegisterInfo *TRI) const override;
531
532 /// Returns true if the two given memory operations should be scheduled
533 /// adjacent.
536 unsigned NumLoads, unsigned NumBytes) const override;
537
538 /// Return true if two MIs access different memory addresses and false
539 /// otherwise
540 bool
542 const MachineInstr &MIb) const override;
543
544 /// GetInstSize - Return the number of bytes of code the specified
545 /// instruction may be. This returns the maximum number of bytes.
546 ///
547 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
548
549 MCInst getNop() const override;
550
551 std::pair<unsigned, unsigned>
552 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
553
556
559
560 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
562
563 // Lower pseudo instructions after register allocation.
564 bool expandPostRAPseudo(MachineInstr &MI) const override;
565
566 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
567 static int getRecordFormOpcode(unsigned Opcode);
568
569 bool isTOCSaveMI(const MachineInstr &MI) const;
570
571 std::pair<bool, bool>
572 isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
573 const MachineRegisterInfo *MRI) const;
574
575 // Return true if the register is sign-extended from 32 to 64 bits.
576 bool isSignExtended(const unsigned Reg,
577 const MachineRegisterInfo *MRI) const {
578 return isSignOrZeroExtended(Reg, 0, MRI).first;
579 }
580
581 // Return true if the register is zero-extended from 32 to 64 bits.
582 bool isZeroExtended(const unsigned Reg,
583 const MachineRegisterInfo *MRI) const {
584 return isSignOrZeroExtended(Reg, 0, MRI).second;
585 }
586
588 MachineInstr **KilledDef = nullptr) const;
589 bool foldFrameOffset(MachineInstr &MI) const;
590 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
591 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
593 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
594 unsigned &XFormOpcode,
595 int64_t &OffsetOfImmInstr,
596 ImmInstrInfo &III) const;
597 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
598 MachineInstr *&ADDIMI, int64_t &OffsetAddi,
599 int64_t OffsetImm) const;
600
601 /// Fixup killed/dead flag for register \p RegNo between instructions [\p
602 /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
603 /// register killed/dead flags semantics, this function can be called to fix
604 /// up. Before calling this function,
605 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
606 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
607 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
608 /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
609 /// will be adjust to true definition.
610 /// 3. We can do accurate fixup for the case when all instructions between
611 /// [\p StartMI, \p EndMI] are in same basic block.
612 /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
613 /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
614 /// and for post-RA, we give an assertion as without reaching definition
615 /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
616 void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
617 unsigned RegNo) const;
618 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
619 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
620 int64_t Imm) const;
621
622 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
623 bool PostRA) const;
624
625 // In PostRA phase, try to find instruction defines \p Reg before \p MI.
626 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
628 bool &SeenIntermediateUse) const;
629
630 // Materialize immediate after RA.
633 const DebugLoc &DL, Register Reg,
634 int64_t Imm) const;
635
636 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
637 bool isBDNZ(unsigned Opcode) const;
638
639 /// Find the hardware loop instruction used to set-up the specified loop.
640 /// On PPC, we have two instructions used to set-up the hardware loop
641 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
642 /// instructions to indicate the end of a loop.
646
647 /// Analyze loop L, which must be a single-basic-block loop, and if the
648 /// conditions can be understood enough produce a PipelinerLoopInfo object.
649 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
650 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
651};
652
653}
654
655#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:155
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:153
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This is an important base class in LLVM.
Definition: Constant.h:41
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isPredicated(const MachineInstr &MI) const override
bool expandVSXMemPseudo(MachineInstr &MI) const
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:367
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:264
MCInst getNop() const override
Return the noop instruction to use for a noop.
static int getRecordFormOpcode(unsigned Opcode)
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:261
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:259
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool isTOCSaveMI(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool isSExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:267
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:582
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:465
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
bool isZExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:270
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:274
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:316
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bool foldFrameOffset(MachineInstr &MI) const
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool isLoadFromConstantPool(MachineInstr *I) const
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:482
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:307
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:477
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:576
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool optimizeCmpPostRA(MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const Constant * getConstantFromConstantPool(MachineInstr *I) const
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:300
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:451
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ ZExt32To64
This instruction produced a zero extended result.
@ SExt32To64
This instruction produced a sign extended result.
@ Prefixed
This instruction is prefixed.
@ XFormMemOp
This instruction is an X-Form memory operation.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
SpillOpcodeKey
Definition: PPCInstrInfo.h:65
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:71
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:73
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:76
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:66
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:77
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:74
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:79
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:82
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:75
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:68
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:69
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:72
@ SOK_WAccumulatorSpill
Definition: PPCInstrInfo.h:80
@ SOK_SPESpill
Definition: PPCInstrInfo.h:81
@ SOK_CRSpill
Definition: PPCInstrInfo.h:70
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:78
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:67
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:83
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:53
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:43
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:33
uint64_t IsCommutative
Definition: PPCInstrInfo.h:41
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:39
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:51
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:36